Silicon-on-insulator LDMOS device and manufacturing method thereof

Abstract

The invention provides a silicon-on-insulator LDMOS device which comprises an SOI substrate, and the SOI is composed of a substrate, a buried oxide layer and a thin silicon layer which are sequentially stacked from bottom to top. A P-type buried layer with linear doping concentration is formed on the thin silicon layer; the epitaxial layer is formed on the thin silicon layer, the P-type body region and the N-type drift region are located on the epitaxial layer, a transverse distance is formed between the body region and the drift region, and a P-type buried layer with linear doping concentration is located at the lower corner, close to the body region, in the drift region; and the residual LDMOS device structure is formed on the epitaxial layer. The P-type buried layer with linear doping concentration can increase the electric field intensity of the junction position of the thin silicon layer and the buried oxide layer. The linear doping can improve the withstand voltage of the junction, thereby improving the electric field intensity in the buried oxide layer, and achieving the improvement of the overall longitudinal withstand voltage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon-on-insulator LDMOS device and a manufacturing method thereof. Background Art

[0002] The SOI LDMOS device has a different pressure-bearing method from the bulk SI LDMOS. Its pressure-bearing method consists of two parts:

[0003] Laterally: the PN junction depletion region formed by N-drift (N-type drift region) and P-body (P-type body region) is under pressure;

[0004] Vertically: The N-drift depletion region and BOX (buried oxide layer) are under pressure, where the electric field strength in the buried oxide layer is three times that of the silicon at the junction of the thin silicon layer and the buried oxide layer.

[0005] For the traditional SOI LDMOS device structure, the vertical breakdown of the device generally occurs on the SOI layer side at the interface between the SOI layer and the buried oxide layer below the drain. That is, when the breakdown occurs, the electric field length E1 at this point reaches the critical field strength Ec.

[0006] In order to solve the above problems, it is necessary to propose a novel silicon-on-insulator LDMOS device and a manufacturing method thereof. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a silicon-on-insulator LDMOS device and a manufacturing method thereof, which is used to solve the problem in the prior art that the vertical breakdown of the device is prone to occur on the side of the SOI layer at the interface between the SOI layer and the buried oxide layer below the drain.

[0008] To achieve the above objectives and other related objectives, the present invention provides a silicon-on-insulator LDMOS device, comprising:

[0009] An SOI substrate, wherein the SOI is composed of a substrate, a buried oxide layer and a thin silicon layer stacked in sequence from bottom to top;

[0010] forming a P-type buried layer having a linear doping concentration on the thin silicon layer;

[0011] An epitaxial layer is formed on the thin silicon layer, and a remaining LDMOS device structure is formed on the epitaxial layer.

[0012] Preferably, the remaining LDMOS device structure includes: a P-type body region and an N-type drift region formed by ion implantation, wherein the body region and the drift region have a lateral spacing therebetween; a gate dielectric layer and a gate polysilicon layer located on the gate dielectric layer, and a side wall located on the gate dielectric layer and the gate polysilicon layer, wherein one end of the gate dielectric layer and the gate polysilicon layer extends to the body region, and the other end thereof extends to the adjacent drift region; a heavily doped region located on the body region and the drift region formed by ion implantation; wherein the heavily doped region on the drift region serves as a drain terminal, and the heavily doped region on the body region serves as a source terminal.

[0013] Preferably, the remaining LDMOS device structure further includes a body region lead-out region located on the body region, and a shallow trench isolation is formed between the body region lead-out region and the source terminal.

[0014] The present invention also provides a method for manufacturing the above-mentioned silicon-on-insulator LDMOS device, comprising:

[0015] Step 1, providing an SOI substrate, wherein the SOI substrate is composed of a substrate, a buried oxide layer and a thin silicon layer stacked in sequence from bottom to top;

[0016] Step 2: forming a mask layer for P-type buried layer ion implantation on the thin silicon layer, and patterning the mask layer to form a plurality of open areas, wherein the critical dimensions of the open areas gradually increase from one side to the other side;

[0017] Step 3: using the patterned mask layer as an ion implantation mask, and forming a P-type buried layer with a linear doping concentration on the thin silicon layer by ion implantation;

[0018] Step 4: remove the mask layer, form an epitaxial layer on the thin silicon layer, and form the remaining LDMOS device structure on the epitaxial layer.

[0019] Preferably, the mask layer in step 2 is a photoresist layer.

[0020] Preferably, in step three, the photoresist layer is opened by photolithography to form the open area.

[0021] Preferably, the open area in step three is a plurality of linear grooves.

[0022] Preferably, in step four, the photoresist layer is removed by using an ashing process and a wet cleaning method.

[0023] Preferably, the remaining LDMOS device structure in step four includes: a P-type body region and an N-type drift region formed by ion implantation, wherein the body region and the drift region have a lateral spacing therebetween; a gate dielectric layer and a gate polysilicon layer located on the gate dielectric layer, and a side wall located on the gate dielectric layer and the gate polysilicon layer, wherein one end of the gate dielectric layer and the gate polysilicon layer extends to the body region, and the other end thereof extends to the adjacent drift region; a heavily doped region located on the body region and the drift region formed by ion implantation; wherein the heavily doped region on the drift region serves as a drain terminal, and the heavily doped region on the body region serves as a source terminal.

[0024] Preferably, the remaining LDMOS device structure in step 4 further includes a body region lead-out region located on the body region, and a shallow trench isolation is formed between the body region lead-out region and the source terminal.

[0025] As described above, the silicon-on-insulator LDMOS device and the manufacturing method thereof of the present invention have the following beneficial effects:

[0026] The linear doping concentration of the P-type buried layer of the present invention can increase the electric field strength at the junction of the thin silicon layer and the buried oxide layer. The linear doping can increase the withstand voltage at the junction, and further increase the electric field strength in the buried oxide layer, thereby achieving an increase in the overall longitudinal withstand voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a schematic diagram of SOI-LDMOS potential distribution in the prior art;

[0028] Figure 2 Shown is a schematic diagram of the longitudinal electric field distribution of SOI-LDMOS in the prior art;

[0029] Figure 3 Shown is a schematic diagram of the process flow of the present invention;

[0030] Figure 4 Shown is a schematic diagram of the SOI substrate of the present invention;

[0031] Figure 5 Shown is a schematic diagram of an ion implantation mask of the present invention;

[0032] Figure 6 It is a schematic diagram showing a P-type buried layer forming a linear doping concentration according to the present invention;

[0033] Figure 7 Shown is a schematic diagram of the epitaxial layer of the present invention;

[0034] Figure 8 Shown is a schematic diagram of the LDMOS device structure of the present invention;

[0035] Fig. 9 It is a schematic diagram of the longitudinal electric field distribution of the SOI-LDMOS of the present invention. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] See also Figure 8 The present invention provides a silicon-on-insulator LDMOS device, comprising:

[0038] SOI substrate, SOI is composed of a substrate 101, a buried oxide layer 102 and a thin silicon layer 103 stacked in sequence from bottom to top;

[0039] A P-type buried layer 105 with a linear doping concentration is formed on the thin silicon layer 103, that is, the doping concentration of the P-type buried layer 105 increases linearly from one side to the other side;

[0040] An epitaxial layer 106 is formed on the thin silicon layer 103, a P-type body region and an N-type drift region 107 are located on the epitaxial layer 106, a lateral spacing is provided between the body region and the drift region 107, and a P-type buried layer 105 with a linear doping concentration is located in a lower corner of the drift region 107 close to the body region;

[0041] See also Fig. 9 The linear doping concentration of the P-type buried layer 105 can increase the electric field strength at the interface between the thin silicon layer 103 and the buried oxide layer 102. Linear doping can increase the withstand voltage at the interface, and further increase the electric field strength in the buried oxide layer 102, thereby increasing the overall longitudinal withstand voltage.

[0042] The remaining LDMOS device structure is formed on the epitaxial layer 106 .

[0043] In some embodiments, the remaining LDMOS device structure includes: a gate dielectric layer 108 and a gate polysilicon layer 109 located on the gate dielectric layer 108, and a side wall located on the gate dielectric layer 108 and the gate polysilicon layer 109, one end of the gate dielectric layer 108 and the gate polysilicon layer 109 extends to the body region, and the other end thereof extends to the adjacent drift region 107; a heavily doped region located on the body region and the drift region 107 formed by ion implantation; wherein the heavily doped region on the drift region 107 serves as a drain terminal 110, and the heavily doped region on the body region serves as a source terminal 112.

[0044] In some embodiments, the remaining LDMOS device structure further includes a body lead-out region 111 located on the body region, and a shallow trench isolation is formed between the body lead-out region 111 and the source terminal 112 .

[0045] The present invention also provides a method for manufacturing the above-mentioned silicon-on-insulator LDMOS device, comprising:

[0046] Step 1: Please refer to Figure 4 , providing an SOI substrate, wherein the SOI substrate is composed of a substrate 101, a buried oxide layer 102 and a thin silicon layer 103 stacked in sequence from bottom to top;

[0047] Step 2: Please refer to Figure 5 , forming a mask layer 104 for ion implantation of a P-type buried layer 105 on the thin silicon layer 103, patterning the mask layer 104 to form a plurality of open areas, wherein the critical dimensions of the open areas gradually increase from one side to the other side;

[0048] In some embodiments, the mask layer 104 in step 2 is a photoresist layer.

[0049] Step 3: Using the patterned mask layer 104 as an ion implantation mask, a P-type buried layer 105 with a linear doping concentration is formed on the thin silicon layer 103 by ion implantation. Figure 6 The structure shown;

[0050] In some embodiments, in step three, the photoresist layer is opened by photolithography to form an open area.

[0051] In some embodiments, the open area in step three is a plurality of linear grooves.

[0052] Step 4: remove the mask layer 104 and form an epitaxial layer 106 on the thin silicon layer 103 to form a Figure 7 The structure shown in FIG. 1 is formed by ion implantation of a P-type body region and an N-type drift region 107 on the epitaxial layer 106, with a lateral spacing between the body region and the drift region 107, a P-type buried layer 105 with a linear doping concentration is located in the drift region 107 at a lower corner close to the body region, and the remaining LDMOS device structure is formed on the epitaxial layer 106, forming a structure as shown in FIG. Figure 8 The structure shown.

[0053] See also Fig. 9 The linear doping concentration of the P-type buried layer 105 can increase the electric field strength at the interface between the thin silicon layer 103 and the buried oxide layer 102. Linear doping can increase the withstand voltage at the interface, and further increase the electric field strength in the buried oxide layer 102, thereby increasing the overall longitudinal withstand voltage.

[0054] In some embodiments, in step four, the photoresist layer is removed by using an ashing process and a wet cleaning method.

[0055] In some embodiments, the remaining LDMOS device structure in step four includes: a gate dielectric layer 108 and a gate polysilicon layer 109 located on the gate dielectric layer 108, and a sidewall located on the gate dielectric layer 108 and the gate polysilicon layer 109, one end of the gate dielectric layer 108 and the gate polysilicon layer 109 extending to the body region, and the other end thereof extending to the adjacent drift region 107; a heavily doped region located on the body region and the drift region 107 formed by ion implantation; wherein the heavily doped region on the drift region 107 serves as a drain terminal 110, and the heavily doped region on the body region serves as a source terminal 112.

[0056] In some embodiments, the remaining LDMOS device structure in step 4 further includes a body lead-out region 111 located on the body region, and a shallow trench isolation is formed between the body lead-out region 111 and the source terminal 112 .

[0057] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0058] In summary, the linear doping concentration of the P-type buried layer of the present invention can increase the electric field strength at the junction of the thin silicon layer and the buried oxide layer. Linear doping can increase the withstand voltage at the junction, and then increase the electric field strength in the buried oxide layer, thereby increasing the overall longitudinal withstand voltage. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A silicon-on-insulator LDMOS device, characterized in that: include: An SOI substrate, wherein the SOI is composed of a substrate, a buried oxide layer and a thin silicon layer stacked in sequence from bottom to top; forming a P-type buried layer having a linear doping concentration on the thin silicon layer; An epitaxial layer formed on the thin silicon layer, a P-type body region and an N-type drift region located on the epitaxial layer, a lateral spacing between the body region and the drift region, and a P-type buried layer with a linear doping concentration located in a lower corner of the drift region close to the body region; The remaining LDMOS device structure is formed on the epitaxial layer.

2. The silicon-on-insulator LDMOS device according to claim 1, characterized in that: The remaining LDMOS device structure includes: a gate dielectric layer and a gate polysilicon layer located on the gate dielectric layer, and a sidewall located on the gate dielectric layer and the gate polysilicon layer, wherein one end of the gate dielectric layer and the gate polysilicon layer extends to the body region, and the other end thereof extends to the adjacent drift region; a heavily doped region located on the body region and the drift region formed by ion implantation; wherein the heavily doped region on the drift region serves as a drain terminal, and the heavily doped region on the body region serves as a source terminal.

3. The silicon-on-insulator LDMOS device according to claim 2, characterized in that: The remaining LDMOS device structure further includes a body region lead-out region located on the body region, and a shallow trench isolation is formed between the body region lead-out region and the source terminal.

4. The method for manufacturing a silicon-on-insulator LDMOS device according to any one of claims 1 to 3, characterized in that: At least: Step 1, providing an SOI substrate, wherein the SOI substrate is composed of a substrate, a buried oxide layer and a thin silicon layer stacked in sequence from bottom to top; Step 2: forming a mask layer for P-type buried layer ion implantation on the thin silicon layer, and patterning the mask layer to form a plurality of open areas, wherein the critical dimensions of the open areas gradually increase from one side to the other side; Step 3: using the patterned mask layer as an ion implantation mask, and forming a P-type buried layer with a linear doping concentration on the thin silicon layer by ion implantation; Step 4: remove the mask layer, form an epitaxial layer on the thin silicon layer, and use ion implantation to form a P-type body region and an N-type drift region on the epitaxial layer, with a lateral spacing between the body region and the drift region. The P-type buried layer with a linear doping concentration is located in the drift region at a lower corner close to the body region, and the remaining LDMOS device structure is formed on the epitaxial layer.

5. The method for manufacturing a silicon-on-insulator LDMOS device according to claim 4, characterized in that: The mask layer in step 2 is a photoresist layer.

6. The method for manufacturing a silicon-on-insulator LDMOS device according to claim 5, characterized in that: In step three, the photoresist layer is opened by photolithography to form the open area.

7. The method for manufacturing a silicon-on-insulator LDMOS device according to claim 4, characterized in that: The open area in step three is a plurality of linear grooves.

8. The method for manufacturing a silicon-on-insulator LDMOS device according to claim 6, characterized in that: In step 4, the photoresist layer is removed by using an ashing process and a wet cleaning method.

9. The method for manufacturing a silicon-on-insulator LDMOS device according to claim 4, characterized in that: The remaining LDMOS device structure in step 4 includes: a gate dielectric layer and a gate polysilicon layer located on the gate dielectric layer, and a side wall located on the gate dielectric layer and the gate polysilicon layer, wherein one end of the gate dielectric layer and the gate polysilicon layer extends to the body region, and the other end thereof extends to the adjacent drift region; a heavily doped region located on the body region and the drift region formed by ion implantation; wherein the heavily doped region on the drift region serves as a drain terminal, and the heavily doped region on the body region serves as a source terminal.

10. The method for manufacturing a silicon-on-insulator LDMOS device according to claim 9, characterized in that: The remaining LDMOS device structure in step 4 further includes a body region lead-out region located on the body region, and a shallow trench isolation is formed between the body region lead-out region and the source terminal.

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