Non-polar plane micro-led with independent mesa structure and preparation method thereof

Abstract

The application discloses an independent mesa structure non-polar surface micro light emitting diode (Micro-LED) and a preparation method thereof, and full relaxation of an epitaxial structure is realized based on selective epitaxy and lateral epitaxy, so that generation of defects in an epitaxial layer can be effectively inhibited. Meanwhile, independent quantum wells and other Micro-LED functional layers are grown on independent mesas, Micro-LEDs can be prepared without quantum well etching damage, quantum well etching damage and non-radiative recombination caused additionally caused by reduction of LED size through a process etching in a traditional scheme are eliminated, and the efficiency of the Micro-LEDs is effectively improved. The application provides a new structure and method for preparing Micro-LEDs, and is favorable for promoting commercial application of the Micro-LEDs.

Description

TECHNICAL FIELD

[0001] The present application relates to a kind of independent mesa structure non-polar face Micro-LED and its preparation method, belong to semiconductor epitaxial growth, Micro-LED etc. BACKGROUND

[0002] Micro-LED technology as a new display technology, with its high brightness, high contrast, wide color gamut and low power consumption and other significant advantages, is receiving more and more attention. However, to successfully commercialize Micro-LED technology, it is necessary to solve the problems of defects in epitaxial layer, quantum well etching damage and non-radiative recombination caused thereby.

[0003] On the one hand, the core structure of Micro-LED is formed by semiconductor materials of epitaxial layer. Epitaxial layer is usually grown on a substrate by metal organic chemical vapor deposition (MOCVD) technology, which is often accompanied by the generation of various defects. Defects in epitaxial layer include lattice dislocation, vacancy and dislocation, etc. These defects can have a negative impact on the performance of Micro-LED. For example, defects can cause reduced light-emitting efficiency, uneven brightness and shortened lifetime. These problems are particularly serious in mass production, because defects not only affect the performance of individual Micro-LED, but also can affect the quality of the entire display panel. On the other hand, quantum well is a key structure for semiconductor light emission, with decisive light-emitting properties. However, during the etching process, etching damage can be introduced, which can affect the optoelectronic properties of quantum well. Etching damage can not only cause reduced light-emitting efficiency of quantum well, but also can induce non-radiative recombination process, further affecting the photoelectric conversion efficiency. This non-radiative recombination refers to the recombination of electrons and holes without light emission, which is converted into heat instead of photons, significantly reducing the brightness and power efficiency of Micro-LED. SUMMARY

[0004] The present application discloses a kind of independent mesa structure non-polar face Micro-LED and its preparation method, based on selected area epitaxy and lateral epitaxy realizes the full relaxation of epitaxial structure, can effectively inhibit the generation of defects in epitaxial layer. At the same time, grow independent quantum well and other Micro-LED functional layers on independent mesa, can prepare Micro-LED without quantum well etching damage, eliminate quantum well etching damage and additional non-radiative recombination caused by reducing LED size through etching in traditional scheme, effectively improve the efficiency of Micro-LED. In addition, the present application sets strain control layer, by adjusting mole fraction to make Al x1 Ga 1-x1 N and In x Ga 1-xThe lattice mismatch value of N in the c-direction is comparable to that of GaN, thus better releasing stress to obtain high-quality quantum wells and improving the overall luminous efficacy of Micro-LEDs. By setting up an electron blocking layer with a wider bandgap or a highly p-doped hole injection layer, carriers in the active region (multiple quantum wells) are confined, increasing the overlap of hole and electron wave functions and achieving higher radiative recombination efficiency. This further addresses the problem of decreased internal quantum efficiency with increasing injection current density. This invention provides a new structure and method for fabricating Micro-LEDs, which is beneficial for promoting the commercial application of Micro-LEDs.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] On one hand, the present invention provides a non-polar surface Micro-LED with an independent mesa structure, characterized in that it includes, from bottom to top, an N-type GaN layer 101 with a non-polar upward crystal plane, a mask layer 102 containing a micropore array, and an N-type In with an In composition x of 0 ≤ x ≤ 0.35 connected to the N-type GaN layer 101 through the micropores of the mask layer 102. x Ga 1-x N-type mesa structure 103, on which a strain control layer 104, a quantum well layer 105, a carrier control layer 106, and a P-type In with an In composition y of 0 ≤ y ≤ 0.15 are sequentially grown. y Ga 1-y N layers 107, covering N-type In x Ga 1-x N-mesa structure 103, strain modulation layer 104, quantum well layer 105, carrier modulation layer 106, and P-type In y Ga 1-y The N-layer 107 consists of five parts: a mesa with inclined surfaces and side surfaces, a passivation layer 108 (partially part of the mask layer 102), an N-electrode 109 that passes through the mask layer 102 and the passivation layer 108 and has good ohmic contact with the N-type GaN layer 101, an isolation layer 110 that fills the outside of the passivation layer 108 and the N-electrode 109, and a layer covering the P-type In... y Ga 1-y N-layer 107 is the P-electrode 111 above the isolation layer 110; wherein, strain control layer 104, quantum well layer 105, carrier control layer 106, and P-type In y Ga 1-y The surface of layer N-107 is all coated with N-type In. x Ga 1-x The N-platform structure 103 has parallel surfaces, and the strain control layer 104 and the carrier control layer 106 can be selectively set or not set.

[0007] Preferably, the mask layer 102 containing the micropore array is formed by etching a 5-50 nm thick dielectric film of SiO2, SiN, or hBN onto a non-polar N-type GaN layer 101 using a process technique, resulting in a micropore array etched from top to bottom, exposing the underlying non-polar N-type GaN layer 101 in the micropores. The micropore array is arranged in a close-packed form with the micropore centers densely packed, and the center distance between any micropore and its six adjacent micropores is equal and adjustable according to actual needs.

[0008] Preferably, the non-polar N-type GaN layer 101 and the N-type In layer... x Ga 1-x The top surface of the N-type mesa structure 103 is simultaneously a (11-20) face. In this case, the mesa structure 103 is a triangular mesa structure. Besides the top surface, it also includes two beveled faces that are both {1-101} crystal planes, and a side face with a (000-1) crystal plane perpendicular to the top surface; N-type In is set. x Ga 1-x When the top surface of the N-mesa structure 103 is the (11-20) plane, the {1-101} crystal plane family has a lower potential energy, which can form regular triangular islands, and the layer structure on top can grow regularly and controllably. At this time, the diameter of the micropores in the mask layer 102 is between 0.2 and 2 μm. When the diameter of the micropores in the mask layer 102 is no greater than 1.5 μm, the diameter of the circumscribed circle of the mesa structure 103 in the plane is between 5 and 20 μm, which can be adjusted as needed. This is because when the micropores are small, it is easy to form regular islands, and the size of the islands can be controlled as needed. When the diameter of the micropores in the mask layer 102 is greater than 1.5 μm, the diameter of the circumscribed circle of the mesa structure 103 in the plane is 3 to 4 times the diameter of the micropores, but not exceeding 15 μm. This is because when the micropores are large, the islands are prone to irregularity, thus limiting the size of the islands.

[0009] Preferably, the non-polar N-type GaN layer 101 and the N-type In layer... x Ga 1-x The top surface of the N-type mesa structure 103 can also be a (1-100) plane. In this case, the mesa structure 103 is a trapezoidal mesa structure. In addition to the top surface, it also includes two left and right inclined surfaces that are both {11-20} crystal planes, and two front and rear side surfaces that are perpendicular to the top surface and have crystal planes of (0001) and (000-1) respectively. An N-type In... x Ga 1-xWhen the top surface of the N mesa structure 103 is a (1-100) surface, the {11-20} crystal surface family is a lower potential surface, regular and flat crystal surfaces can be formed, and the layer structure above can be regularly and controllably grown. At this time, the size of the micropores of the mask layer 102 in the left-right direction is between 0.3-0.6 times the size of the mesa structure 103 in the left-right direction and at most 5 μm, the size in the up-down direction is the same as the size of the mesa structure 103 in the up-down direction, and is adjusted according to the size of the device. By setting the mesa structure, the damage of etching to the multi-quantum well is fundamentally avoided, the radiation recombination efficiency of the Micro-LED is improved, and the mesa structure is beneficial to releasing the stress of the bottom layer, improving the crystal quality of the prepared LED full structure, and then weakening the influence of defects and polarization on carriers, and improving the light-emitting efficiency of the LED.

[0010] Preferably, the N-type In x Ga 1-x N mesa structure 103 has a mole component x≤0.05, the strain regulation layer 104 is 1-3 periods of GaN / Al x1 Ga 1-x1 N / GaN composite layer, wherein Al x1 Ga 1-x1 N has a thickness of less than 3 nm, and x1<0.15. By setting a smaller x, the stress of In x Ga 1-x N is smaller, and only a lower component of AlGaN needs to be introduced to compensate for a certain in-plane stress in the c direction; the N-type In x Ga 1-x N mesa structure 103 has a mole component of 0.05<x<0.15, the strain regulation layer 104 is 1-3 periods of GaN / Al x1 Ga 1-x1 N / GaN / In x Ga 1-x N composite layer, wherein In x Ga 1-x N has a mole component x, which is the mole component of the N-type In x Ga 1-x N mesa structure 103, Al x1 Ga 1-x1 N has a thickness of less than 2 nm; wherein In x Ga 1-x N and GaN have a lattice mismatch value in the c direction of Δ1=0.09797×x, and GaN and Al x1 Ga 1-x1 N have a lattice mismatch value in the c direction of Δ2=-0.03915×x1; by adjusting the mole components x and x1, Al x1 Ga 1-x1 N and In x Ga1-x N has a lattice mismatch value in the c direction equivalent to that of GaN (i.e. satisfies Δ1 = - Δ2), i.e. satisfies x1 = 2.5 x x1 ± 0.05, to achieve stress compensation between layers and to obtain high-quality quantum wells and improve the overall Micro-LED light efficiency.

[0011] Preferably, when the light-emitting wavelengths of the quantum well layer 105 are red, green and blue light respectively, the number of pairs of quantum wells is not more than 2 pairs, 4 pairs and 5 pairs respectively; the layer structure of the quantum well is In x2 Ga 1-x2 N / GaN / Al x3 Ga 1-x3 N / GaN, wherein In x2 Ga 1-x2 N has a lattice mismatch value in the c direction equivalent to that of GaN (i.e. satisfies Δ1 = - Δ2), i.e. satisfies x1 = 2.5 x x1 ± 0.05, to achieve stress compensation between layers and to obtain high-quality quantum wells and improve the overall Micro-LED light efficiency. x3 Ga 1-x3 N has a lattice mismatch value in the c direction equivalent to that of GaN (i.e. satisfies Δ1 = - Δ2), i.e. satisfies x1 = 2.5 x x1 ± 0.05, to achieve stress compensation between layers and to obtain high-quality quantum wells and improve the overall Micro-LED light efficiency. x2 Ga 1-x2 N and Al x3 Ga 1-x3 N has a lattice mismatch value in the c direction equivalent to that of GaN (i.e. satisfies Δ1 = - Δ2), i.e. satisfies x3 = 2.5 x x2 ± 0.05, while controlling the thickness of In x2 Ga 1-x2 N to be 2-4 nm, and the total thickness of the two layers of GaN and Al x3 Ga 1-x3 N to be not more than 6 nm, to better release stress, improve the radiation recombination efficiency of the quantum well, and improve the light efficiency.

[0012] Preferably, the carrier regulation layer 106 is one of an electron blocking layer or a hole injection layer; the electron blocking layer is an Al y1 Ga (1-y1) N / GaN superlattice, wherein the molar component y1 is negatively correlated with the thickness of Al y1 Ga (1-y1) N; the hole injection layer is a P-doped Al y2 Ga (1-y2) N / In y3 Ga (1-y3) N / GaN superlattice, y2 = 0.5 x y3, and the Mg element doping concentration is 5 x 10 17 cm -3 ~ 1 x 10 19 cm -3The hole concentration is not higher than 1×10 18 cm -3 By setting the electron blocking layer with wider band gap or the high P-doped hole injection layer, the carrier in the active region, i.e., the multi-quantum well, is limited, and the overlap of the hole and electron wave functions in the multi-quantum well is increased, so that the radiation recombination efficiency is higher.

[0013] Preferably, the P-type In y Ga 1-y N layer 107 has a thickness of 50-200 nm, a molar component y of 0-0.15, and a Mg element doping concentration of 2×10 19 cm -3 -5×10 19 cm -3 , and a hole concentration of not less than 1×10 18 cm -3 ; wherein the P-type In y Ga 1-y N layer 107 has a Mg element doping concentration of not less than 1×10 20 cm -3 in a 5-30 nm thick region on the upper surface, and a hole concentration of not less than 5×10 18 cm -3 .

[0014] In another aspect, the application provides a preparation method of a non-polar face Micro-LED with an independent mesa structure, wherein the structure features of the Micro-LED are as follows from bottom to top: a non-polar face N-type GaN layer 101, a mask layer 102 containing a micro-pore array, an N-type In x Ga 1-x N mesa structure 103 with an In component x of 0≤x≤0.35, a strain regulation layer 104, a quantum well layer 105, a carrier regulation layer 106, and a P-type In y Ga 1-y N layer 107 with an In component y of 0≤y≤0.15, which are sequentially grown on the mesa structure 103. x Ga 1-x N mesa structure 103, the strain regulation layer 104, the quantum well layer 105, the carrier regulation layer 106, and the P-type In y Ga 1-yThe N-type InGaN layer 107 is composed of five parts of the mesa body inclined surface, the side surface, the passivation layer 108 of the part of the mask layer 102, the N electrode 109 passing through the mask layer 102 and the passivation layer 108 and having a good ohmic contact with the N-type GaN layer 101, the isolation layer 110 filled outside the passivation layer 108 and the N electrode 109, the P electrode 111 covering the isolation layer 110, and the P-type InGaN layer 107. y Ga 1-y N layer 107 is the P electrode 111 above the isolation layer 110; wherein the strain regulating layer 104, the quantum well layer 105, the carrier regulating layer 106 and the P-type In y Ga 1-y N layer 107 are all parallel to the surface of the N-type In x Ga 1-x N mesa structure 103, and the strain regulating layer 104 and the carrier regulating layer 106 can be selectively set or not set. When the top surface of the non-polar N-type GaN layer 101 is the (11-20) surface, the mesa structure 103 is a triangular mesa structure, and the diameter of the micropore of the mask layer 102 is between 0.2-2 μm. The preparation method of the Micro-LED comprises the following steps:

[0015] a) preparing a non-polar (11-20) N-type GaN template as the non-polar N-type GaN layer 101, preparing a layer of dielectric film (material is silicon oxide, silicon nitride or boron nitride) thereon, and then using micro-processing technology to process micropores (exposing the underlying N-type GaN layer 101) on the dielectric layer, i.e. the mask layer 102;

[0016] b) using a MOCVD (metal organic chemical vapor deposition) system, using the micropores of the mask layer 102 to perform selective epitaxial growth of the N-type In x Ga 1-x N triangular island, and the growth conditions are as follows: the growth temperature is 1080-1100℃, the V / III ratio (molar flow ratio of N source to Ga source) is 1800-2500, the growth pressure is 40-120 Torr, and the total flow rate v (in sccm) of the carrier gas flowing into the reaction chamber satisfies 100PA < 760v < 300PA (v act = v std

[0017] × P std / P act , wherein v act = gas flow rate × A, v std is the total flow rate v of the carrier gas flowing into the reaction chamber, P std is the standard pressure, usually 760 Torr, P act is the growth pressure P), wherein P is the growth pressure (in Torr), A is

[0018] The area of the graphite disk in the reaction chamber of the MOCVD system (in square centimeter). Lower flow rate and lower growth pressure are required to effectively transport the source into the micropores of the mask layer 102 to complete the selective epitaxy, and higher growth temperature and higher V / III ratio are beneficial to the three-dimensional growth, so that the triangular island of N-type In

[0019] c) Growth of N-type In x Ga 1-x N triangular island, the supply of Group III (Ga and In) source is turned off, the total flow rate of carrier gas into the reaction chamber is increased to more than twice that of the previous step, and other conditions remain unchanged, in-situ annealing is performed on the N-type In x Ga 1-x N triangular island to promote the thermal decomposition of the N-type In x Ga 1-x N triangular island from the top to form an N-type In x Ga 1-x N mesa structure 103; then, the growth conditions of the MOCVD system are controlled as follows: the growth temperature is 1050±20°C, the V / III ratio is 1000±

[0020] 200, the growth pressure is 40-200 Torr, and the total flow rate v of carrier gas into the reaction chamber satisfies 150 PA < 760 v < 250 PA, and a layer of 5-20 nm thick N-type In x Ga 1-x N with the same parameters is grown on the N-type In x Ga 1-x N mesa structure 103, and the damage repair of the mesa thermal annealing is completed;

[0021] d) The growth conditions of the MOCVD system are maintained as follows: the V / III ratio is 1000±200, the growth pressure is 40-200 Torr, and the total flow rate v of carrier gas into the reaction chamber satisfies 150 PA < 760 v < 250 PA, and the strain control layer 104, the quantum well layer 105, the carrier control layer 106, and the P-type In y Ga 1-y N layer 107 are sequentially epitaxially grown to complete the growth of the epitaxial layer structure;

[0022] e) A thin film of silicon oxide, silicon nitride, or boron nitride is deposited or sputtered on the surface of the epitaxial wafer as a passivation layer 108, and a standard microfabrication process is used to etch from top to bottom at the location where the N electrode is to be prepared, exposing the N-type GaN layer 101, and then the N electrode 109 is prepared;

[0023] f) A layer of polymer, such as SOG (spin on glass), is spin-coated to fill the space outside the passivation layer 108 and the N electrode 109, and its height is higher than that of the P-type In yGa 1-y N layer 107;

[0024] g) again using standard micro-processing technology, etching from top to bottom at the position where P electrode is needed, exposing P-type In y Ga 1-y N layer 107, and then preparing P electrode 111; the preparation of the Micro-LED main body structure is completed.

[0025] The application also provides a preparation method of a non-polar face Micro-LED with an independent mesa structure, wherein the structure features of the Micro-LED are sequentially arranged from bottom to top as follows: a non-polar face N-type GaN layer 101, a mask layer 102 containing a micro-pore array, an N-type In x Ga 1-x N mesa structure 103, a strain regulation layer 104, a quantum well layer 105, a carrier regulation layer 106 and a P-type In y Ga 1-y N layer 107, covering the N-type In x Ga 1-x N mesa structure 103, the strain regulation layer 104, the quantum well layer 105, the carrier regulation layer 106 and the P-type In y Ga 1-y N layer 107, a passivation layer 108 of part of the mask layer 102, an N electrode 109 passing through the mask layer 102 and the passivation layer 108 and having a good ohmic contact with the N-type GaN layer 101, an isolation layer 110 filled outside the passivation layer 108 and the N electrode 109, a P electrode 111 covering the P-type In y Ga 1-y N layer 107 on the isolation layer 110; wherein the strain regulation layer 104, the quantum well layer 105, the carrier regulation layer 106 and the P-type In y Ga 1-y N layer 107 are all in contact with the N-type In x Ga 1-xThe N-surface structure 103 is parallel, and the strain regulation layer 104 and the carrier regulation layer 106 can be selectively arranged or not arranged. When the top surface of the non-polar N-type GaN layer 101 is a (1-100) surface, the mesa structure 103 is a trapezoidal mesa structure, at this time, the size of the micro-hole of the mask layer 102 in the left-right direction is between 0.3-0.6 times of the size of the mesa structure 103 in the left-right direction and is at most 5 μm, the size in the up-down direction is the same as the size of the mesa structure 103 in the up-down direction, and is adjusted according to the size of the device. The preparation method of the Micro-LED comprises the following steps:

[0026] a) A non-polar (1-100) surface N-type GaN template is prepared as the non-polar N-type GaN layer 101, a layer of dielectric film (the material is silicon oxide, silicon nitride or boron nitride) is prepared thereon, and then a micro-hole (exposing the underlying N-type GaN layer 101) is processed on the dielectric layer by using a micro-processing technology, that is, the mask layer 102;

[0027] b) An N-type In x Ga 1-x N mesa structure 103 is grown by using a MOCVD (metal organic chemical vapor deposition) system and using the micro-hole of the mask layer 102 for selective epitaxial growth, and the growth conditions are as follows: the growth temperature is 1080-1100 ℃,

[0028] the V / III ratio (the molar flow ratio of the N source to the Ga source) is 1800-2500, the growth pressure is 40-120 Torr, and the total flow rate v (in sccm) of the carrier gas flowing into the reaction chamber satisfies 100PA < 760v < 300PA, wherein P is the growth pressure (in Torr), and A is the area (in square centimeters) of the graphite disc in the reaction chamber of the MOCVD system. Lower flow rate and lower growth pressure can effectively transport the source into the micro-hole of the mask layer 102 to complete the selective epitaxy, and higher growth temperature and higher V / III ratio are beneficial to three-dimensional growth, so that the mesa structure can be obtained by selective epitaxy.

[0029] c) The growth conditions of the MOCVD system are set as follows: the V / III ratio is 1000±200, the growth pressure is 40-200 Torr, and the total flow rate v of the carrier gas flowing into the reaction chamber satisfies 150PA < 760v < 250PA, and the strain regulation layer 104, the quantum well layer 105, the carrier regulation layer 106 and the P-type In y Ga 1-y N layer 107 are sequentially epitaxially grown to complete the growth of the epitaxial layer structure;

[0030] d) depositing or sputtering a silicon oxide, silicon nitride or boron nitride film as a passivation layer 108 on the surface of the epitaxial wafer, and etching from top to bottom at the position where the N electrode is to be prepared using a standard microfabrication process, exposing the N-type GaN layer 101,

[0031] Subsequently, the N electrode 109 is prepared;

[0032] e) spin-coating a layer of polymer, such as SOG, outside the passivation layer 108 and the N electrode 109, which is higher than the P-type

[0033] In y Ga 1-y N layer 107;

[0034] f) again etching from top to bottom at the position where the P electrode is to be prepared using a standard microfabrication process, exposing the P-type In y Ga 1-y N layer 107, and subsequently preparing the P electrode 111; the preparation of the Micro-LED main structure is completed.

[0035] Advantages:

[0036] The present application realizes full relaxation of the epitaxial structure based on selective epitaxy and lateral epitaxy, and can effectively inhibit the generation of defects in the epitaxial layer. At the same time, the independent quantum well functional layer of the Micro-LED is grown on the independent mesa, which can prepare the Micro-LED without quantum well etching damage, eliminate the quantum well etching damage and additional non-radiative recombination caused by reducing the size of the LED through the process etching in the traditional scheme, and effectively improve the efficiency of the Micro-LED. The mesa structure is set, which fundamentally avoids the damage of etching to the multi-quantum well, and improves the radiative recombination efficiency of the Micro-LED.

[0037] At the same time, the present application sets the non-polar N-type GaN layer 101 and the N-type In x Ga 1-x N mesa structure 103 upward top surface is also (11-20) surface, and the mesa structure 103 is a triangular mesa structure. Because the {1-101} crystal plane family is a lower potential surface, a regular triangular island can be formed, and the upper layer structure can be regularly and controllably grown. At this time, when the micro-hole diameter of the mask layer 102 is not greater than 1.5 μm, the circumscribed circle diameter of the mesa structure 103 in the plane is between 5-20 μm according to the need, because when the micro-hole is small, a regular island is easy to form, and the size of the island can be controlled according to the need at this time; when the micro-hole diameter of the mask layer 102 is greater than 1.5 μm, the circumscribed circle diameter of the mesa structure 103 in the plane is 3-4 times the micro-hole diameter, but the maximum does not exceed 15 μm, because when the micro-hole is large, the island is easy to be irregular, and therefore the size of the island is limited. The non-polar N-type GaN layer 101 and the N-type Inx Ga 1-x The top surface of the N mesa structure 103 is a (1-100) surface, and when the mesa structure 103 is a trapezoidal mesa structure, a regular and flat crystal surface can be formed because the {11-20} crystal surface family is a lower potential surface, and the layer structure above can be regularly and controllably grown. At this time, the size of the micropores of the mask layer 102 in the left-right direction is between 0.3-0.6 times the size of the mesa structure 103 in the left-right direction and is at most 5 μm, and the size in the up-down direction is the same as the size of the mesa structure 103 in the up-down direction and is adjusted according to the size of the device. Moreover, the mesa structure is beneficial to releasing the stress of the bottom layer, improving the crystal quality of the prepared LED full structure, and then weakening the influence of defects and polarization on the carriers, and improving the light-emitting efficiency of the LED.

[0038] In addition, in order to alleviate the adverse effects (such as defects caused by stress release) of the In x Ga 1-x N quantum well due to the large lattice mismatch with GaN, the present application sets a strain regulation layer and a specially designed quantum well structure before growing the quantum well, and introduces an AlGaN layer with a specific mole component to produce a strain opposite to that of InGaN, so as to offset the strain of InGaN. The principle is as follows: first, according to the formula

[0039]

[0040] The lattice mismatch value is calculated, where Δ is the lattice mismatch value, c GaN is the c-axis lattice constant of GaN, which is 5.185 angstroms, c n represents the c-axis lattice constant of Al x1 Ga 1-x1 N and In x Ga 1-x N. Wherein c n The calculation formula is:

[0041] c n = b x c AlN或InN + (1-b) c GaN

[0042] Where b is x, x1, x2 or x3, c AlN或InN is the c-axis lattice constant of AlN or InN, which is 4.982 angstroms and 5.693 angstroms respectively. By substituting the corresponding values, the lattice mismatch value of In x Ga 1-x N and GaN in the c direction is Δ1 = 0.09797 x x, and the lattice mismatch value of Al x1 Ga 1-x1 N and GaN in the c direction is Δ2 = -0.03915 x x1; and the lattice mismatch value of In x2 Ga 1-x2The lattice mismatch between N and GaN in the c-direction is Δ3 = 0.09797 × x²; Al x3 Ga 1-x3 The lattice mismatch between N and GaN in the c-direction is Δ4 = -0.03915 × x3. By adjusting the molar composition x, x1, x2, and x3, Al... x1 Ga 1-x1 N and In x Ga 1-x N has a lattice mismatch value comparable to that of GaN in the c-direction; In x2 Ga 1-x2 N and Al x3 Ga 1-x3 The lattice mismatch value of N in the c direction is equivalent to that of GaN (i.e., satisfying Δ1=-Δ2, Δ3=-Δ4), that is, satisfying x1=2.5×x±0.05, x3=2.5×x2±0.05. At this time, AlGaN will produce strain in the opposite direction and with a similar value to InGaN to counteract the strain of InGaN, suppress the defects generated by InGaN due to excessive strain, and thus obtain a high-quality quantum well and improve the overall luminous efficiency of Micro-LED.

[0043] By constructing an electron blocking layer with a wider bandgap or a highly p-doped hole injection layer, carriers in the active region (multiple quantum wells) are confined, increasing the overlap of hole and electron wave functions and achieving higher radiative recombination efficiency. This further addresses the issue of decreased internal quantum efficiency with increasing injection current density. Lower flow rates and lower growth pressures are necessary to effectively transport the source to the micropores of the mask layer 102 for selected-area epitaxy. Higher growth temperatures and higher V / III ratios are beneficial for three-dimensional growth, enabling the formation of triangular islands in selected-area epitaxy. This invention provides a new structure and method for fabricating Micro-LEDs, facilitating their commercial application. Attached Figure Description

[0044] Figure 1 This is a cross-sectional schematic diagram of a non-polar surface Micro-LED that includes a triangular platform structure and a trapezoidal platform structure, provided by the present invention.

[0045] Figure 2 This is a top view schematic diagram of a non-polar surface Micro-LED with a triangular mesa structure provided by the present invention. To illustrate the positional relationship of the different structures, the passivation layer 108, the isolation layer 110 filling the outer side of the passivation layer 108 and the N-electrode 109, and the layer covering the P-type In are not shown in the figure. y Ga 1-y N layer 107 is the P electrode 111 on the isolation layer 110, which makes it easier to show the overall structure.

[0046] Figure 3 A top view schematic diagram of a non-polar plane Micro-LED with a trapezoidal mesa structure provided by the present application. In order to reflect the positional relationship of different structures, the passivation layer 108, the isolation layer 110 filled outside the passivation layer 108 and the N electrode 109, and the P-type In y Ga 1-y N layer 107 are not shown in the figure. The P electrode 111 above the isolation layer 110 is convenient to reflect the overall structure.

[0047] Wherein, 101 is a non-polar plane N-type GaN layer; 102 is a mask layer containing a micropore array; 103 is an N-type In x Ga 1-x N mesa structure; 104 is a strain regulation layer; 105 is a quantum well layer; 106 is a carrier regulation layer; 107 is a P-type In y Ga 1-y N layer 107; 108 is a passivation layer; 109 is an N electrode; 110 is an isolation layer; and 111 is a P electrode. DETAILED DESCRIPTION

[0048] The present application will be further described below in conjunction with the accompanying drawings. The following examples are only used to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the protection scope of the present application.

[0049] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0050] Example 1

[0051] A cross-sectional view schematic diagram of a non-polar plane Micro-LED with a triangular mesa structure provided by the present application is shown in Figure 1 , and a top view schematic diagram is shown in Figure 2 The structural features of this Micro-LED are arranged in order from bottom to top as follows: the (11-20) plane N-type GaN layer 101, the mask layer 102 containing a micropore array, the N-type In x Ga 1-x GaN mesa structure 103, strain regulation layer 104, quantum well layer 105, carrier regulation layer 106 and P-type In y Ga 1-y N layer 107, covering the N-type In x Ga 1-x N mesa structure 103, strain regulation layer 104, quantum well layer 105, carrier regulation layer 106 and P-type In y Ga 1-y N layer 107 are composed of five parts of mesa body inclined surface and side surface, and part of passivation layer 108 of mask layer 102, N electrode 109 passing through mask layer 102 and passivation layer 108 and having good ohmic contact with N-type GaN layer 101, isolation layer 110 filled outside passivation layer 108 and N electrode 109, P electrode 111 covering N-type In y Ga 1-y N layer 107 is isolation layer 110; wherein, strain regulation layer 104, quantum well layer 105, carrier regulation layer 106 and P-type In y Ga 1-y N layer 107 surface are parallel to N-type In x Ga 1-x N mesa structure 103 surface is parallel, and strain regulation layer 104 and carrier regulation layer 106 can be selectively set or not set.

[0052] Non-polar N-type GaN layer 101 and N-type In x Ga 1-x N mesa structure 103 upward top surface is (11-20) surface at the same time, at this time, mesa structure 103 is a triangular mesa structure, in addition to the upward top surface, it also contains left and right two inclined surfaces which are {1-101} crystal surface family at the same time and side surface which is (000-1) and perpendicular to the top surface, and the inscribed circle diameter of mesa structure 103 in the surface is 10 μm.

[0053] 30 nm thick SiO2 dielectric film is plated on non-polar (11-20) N-type GaN layer 101 as mask layer 102, and micro-hole array is etched from top to bottom by process technology, the lower layer GaN layer 101 is exposed in the micro-hole, and the diameter of the micro-hole of mask layer 102 is 1 μm.

[0054] N-type In x Ga 1-x Mole component x of N mesa structure 103 is 0.1, strain regulation layer 104 is 3 periods of GaN / Al x1 Ga 1-x1 N / GaN / In x Ga 1-xN composite layer, wherein In x Ga 1-x N has a molar composition x = 0.1, Al x1 Ga 1-x1 N has a thickness of 1 nm, and a molar composition x1 = 0.25 ± 0.05.

[0055] The layer structure of the quantum well layer 105 is In x2 Ga 1-x2 N / GaN / Al x3 Ga 1-x3 N / GaN, wherein the molar composition x2 = 0.2, x3 = 0.5, and In x2 Ga 1-x2 N has a thickness of 3 nm, and two layers of GaN and Al x3 Ga 1-x3 N have a total thickness of 4 nm. When the light-emitting wavelengths of the quantum well layer 105 are red, green, and blue respectively, the number of quantum well pairs thereof are 1 pair, 2 pairs, and 3 pairs respectively.

[0056] The carrier modulation layer 106 is an electron blocking layer, wherein the electron blocking layer is a 4-period Al y1 Ga (1-y1) N / GaN superlattice, wherein the molar composition y1 = 0.2.

[0057] The P-type In y Ga 1-y N layer 107 has a thickness of 100 nm, a molar composition y = 0.1, and a Mg element doping concentration of 4 × 10 19 cm -3 , and a hole concentration of 2 × 10 18 cm -3 ; wherein the P-type In y Ga 1-y N layer 107 has a hole concentration of 6 × 10 20 cm -3 , and a hole concentration of 2 × 10 18 cm -3 .

[0058] The preparation method of the non-polar surface Micro-LED with a triangular mesa structure provided by the embodiment 1 of the present application comprises the following steps:

[0059] a) preparing a non-polar (11-20) surface N-type GaN template as a non-polar surface N-type GaN layer 101, preparing a layer of silicon oxide dielectric film thereon, and then using micro-processing technology to process micro-holes (exposing the underlying N-type

[0060] GaN layer 101, which is the mask layer 102;

[0061] b) Selective epitaxial growth of N-type In using an MOCVD system and the micropores of mask layer 102. x Ga 1-x The N-triangular island growth conditions are as follows: growth temperature 1100℃, V / III ratio (molar flow ratio of N to Ga source) 2000, growth pressure 100 Torr, and the total carrier gas flow rate v (in sccm) entering the reaction chamber satisfies 760v = 2 × 10⁻⁶. 4 A, where A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters) and the carrier gas flow rate is 200 cm / min.

[0062] c) Growth to obtain N-type In x Ga 1-x After the N-diameter island, shut off the supply of group III (Ga and In) sources, increase the total flow rate of carrier gas into the reaction chamber to 2.5 times that of the previous step, keeping other conditions unchanged, for N-type In x Ga 1-x In-situ annealing of the N-type delta island promotes the N-type In x Ga 1-x The N-triangular islands thermally decompose from the top, forming N-type In. x Ga 1-x N-mesa structure 103; subsequently, the growth conditions of the MOCVD system were controlled as follows: growth temperature 1050±20℃, V / III ratio 1000±

[0063] 200, growth pressure 100 Torr, and the total flow rate v of the carrier gas entering the reaction chamber simultaneously satisfies 760v = 2 × 10 4 A, where A is

[0064] The MOCVD system uses a graphite disk with an area (in square centimeters) in the reaction chamber and a carrier gas flow rate of 200 cm / min. In N-type In... x Ga 1-x A 10 nm thick layer of N-type In with the same parameters is grown on the N-mesa structure 103. x Ga 1-x N, complete the repair of the damage caused by the hot annealing of the countertop;

[0065] d) Maintain the following growth conditions for the MOCVD system: V / III ratio of 1000±200, growth pressure of 100 Torr, and the total flow rate v of the carrier gas entering the reaction chamber must satisfy 760v=2×10 4A, where A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters), and the carrier gas flow rate is 200 cm / min. A strain-controlled layer 104, a quantum well layer 105, a carrier-controlled layer 106, and a p-type In layer are epitaxially grown sequentially. y Ga 1-y N layers 107, completing the growth of the epitaxial layer structure;

[0066] e) A silicon oxide thin film is deposited on the surface of the epitaxial wafer as a passivation layer 108. Using standard microfabrication technology, the N electrode is etched from top to bottom at the location where the N electrode needs to be fabricated to expose the N-type GaN layer 101. Then the N electrode 109 is fabricated.

[0067] f) A layer of polymer SOG (spin on glass) is spin-coated to fill the outside of the passivation layer 108 and the N electrode 109, with a height higher than that of the P-type In. y Ga 1-y Nth floor 107;

[0068] g) Using standard micromachining techniques again, etch from top to bottom at the location where the P electrode needs to be fabricated, exposing the P electrode.

[0069] Type In y Ga 1-y N layer 107, followed by P electrode 111; thus completing the fabrication of this Micro-LED main structure.

[0070] Example 2:

[0071] A cross-sectional view of a non-polar surface Micro-LED with a trapezoidal mesa structure provided in Embodiment 2 of the present invention is shown below. Figure 1 As shown in the top view diagram Figure 3 As shown, the structural features of this Micro-LED, arranged from bottom to top, are: an N-type GaN layer 101 with an upward crystal plane of (1-100), a mask layer 102 containing a micropore array, and an N-type In with an In composition x = 0.1 connected to the N-type GaN layer 101 through the micropores of the mask layer 102. x Ga 1-x N-type mesa structure 103, on which a strain control layer 104, a quantum well layer 105, a carrier control layer 106, and a p-type In with an In composition y = 0.1 are sequentially grown. y Ga 1-y N layers 107, covering N-type In x Ga 1-x N-mesa structure 103, strain modulation layer 104, quantum well layer 105, carrier modulation layer 106, and P-type In y Ga 1-yThe N-type In y Ga 1-y N layer 107 is the P-electrode 111 above the isolation layer 110; wherein the strain regulation layer 104, the quantum well layer 105, the carrier regulation layer 106 and the P-type In y Ga 1-y N layer 107 are all parallel to the N-type In x Ga 1-x N mesa structure 103 surface, and the strain regulation layer 104 and the carrier regulation layer 106 can be selectively set or not set.

[0072] The non-polar N-type GaN layer 101 and the N-type In x Ga 1-x N mesa structure 103 upward top surface is (1-100) surface at the same time, at this time the mesa structure 103 is trapezoidal mesa structure, in addition to the upward top surface, it also contains left and right two inclined surfaces which are {11-20} surface family at the same time and front and back two vertical side surfaces which are (0001) and (000-1) surface respectively.

[0073] A 30nm thick SiO2 dielectric film is plated on the non-polar N-type GaN layer 101 as a mask layer 102, and a micro-hole array is etched from top to bottom by process technology, the lower layer GaN layer 101 is exposed in the micro-hole, the size of the micro-hole of the mask layer 102 in the left and right directions is 0.5 times of the size of the mesa structure 103 in the left and right directions, and the size in the up and down directions is the same as the size of the mesa structure 103 in the up and down directions.

[0074] The N-type In x Ga 1-x N mesa structure 103 has a mole component x=0.1, the strain regulation layer 104 is a 3-period self-down GaN / Al x1 Ga 1-x1 N / GaN / In x Ga 1-x N composite layer, wherein In x Ga 1-x N has a mole component x=0.1, Al x1 Ga 1-x1 N has a thickness of 1nm and a mole component x1=0.25±0.05.

[0075] The layer structure of the quantum well layer 105 is In x2 Ga 1-x2 N / GaN / Alx3 Ga 1-x3 N / GaN, where the molar composition x2 = 0.1, x3 = 0.25, and In x2 Ga 1-x2 The thickness of N is 3nm, consisting of two layers of GaN and Al. x3 Ga 1-x3 The total thickness of N is 4 nm. When the emission wavelengths of the quantum well layer 105 are red, green, and blue light, respectively, the number of quantum well pairs is 1, 2, and 3, respectively.

[0076] Carrier modulation layer 106 is an electron blocking layer, wherein the electron blocking layer is a 4-period Al with a single period thickness of 6 nm. y1 Ga (1-y1) N / GaN superlattice, wherein the molar composition y1 = 0.2.

[0077] P-type In y Ga 1-y The thickness of the N-layer 107 is 100 nm, the molar composition y = 0.1, and the Mg element doping concentration is 4 × 10⁻⁶. 19 cm -3 Its hole concentration is 2×10 18 cm -3 ; among which P-type In y Ga 1-y Within a 30nm thick region on the upper surface of the N-layer 107, the Mg doping concentration is 2×10⁻⁶. 20 cm -3 Its hole concentration is 6×10 18 cm -3 .

[0078] The method for fabricating a non-polar surface Micro-LED with a trapezoidal mesa structure provided in Embodiment 2 of the present invention includes the following steps:

[0079] a) Prepare a nonpolar (1-100) plane N-type GaN template as a nonpolar plane N-type GaN layer 101, and fabricate a silicon oxide dielectric film on it. Then, use microfabrication technology to fabricate micropores on the dielectric layer (exposing the underlying N-type GaN).

[0080] GaN layer 101, which is the mask layer 102;

[0081] b) Selective epitaxial growth of N-type In using an MOCVD system and the micropores of mask layer 102. x Ga 1-x The N-mesa structure 103 was grown under the following conditions: growth temperature of 1100℃ and V / III ratio (the molar flow ratio of N originating from the Ga source).

[0082] The growth pressure is 100 Torr, and the total flow rate v (in sccm) of the carrier gas entering the reaction chamber satisfies 760v = 2 × 10 4 A, where A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters) and the carrier gas flow rate is 200 cm / min.

[0083] c) Set the MOCVD system growth conditions as follows: V / III ratio of 1000±200, growth pressure of 100 Torr, and the total flow rate v of the carrier gas entering the reaction chamber satisfies 760v=2×10 4 A, where A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters), and the carrier gas flow rate is 200 cm / min. A strain-controlled layer 104, a quantum well layer 105, a carrier-controlled layer 106, and a p-type In layer are epitaxially grown sequentially. y Ga 1-y N layers 107, completing the growth of the epitaxial layer structure;

[0084] d) A silicon oxide thin film is deposited on the surface of the epitaxial wafer as a passivation layer 108. Using standard microfabrication technology, the N electrode is etched from top to bottom at the location where the N electrode needs to be fabricated to expose the N-type GaN layer 101. Then the N electrode 109 is fabricated.

[0085] e) A layer of polymer SOG (spin on glass) is spin-coated to fill the outer side of the passivation layer 108 and the N electrode 109, with a height higher than that of the P-type In. y Ga 1-y Nth floor 107;

[0086] f) Using standard micromachining techniques again, etch from top to bottom at the location where the P electrode needs to be fabricated, exposing the P-type In electrode. y Ga 1-y N layer 107, followed by P electrode 111; thus completing the fabrication of this Micro-LED main structure.

Claims

1. A non-polar face Micro-LED of a free-standing mesa structure, characterized in that: The mesa body is composed of five parts: a non-polar N-type GaN layer (101) with upward crystal faces, a mask layer (102) containing a micro-pore array, an N-type In x Ga 1-x N mesa structure (103), a strain regulation layer (104), a quantum well layer (105), a carrier regulation layer (106) and a P-type In y Ga 1-y N layer (107) grown successively on the N-type In x Ga 1-x N mesa structure (103), the strain regulation layer (104), the quantum well layer (105), the carrier regulation layer (106) and the P-type In y Ga 1-y N layer (107), a passivation layer (108) on part of the mask layer (102), an N electrode (109) passing through the mask layer (102) and the passivation layer (108) and having a good ohmic contact with the N-type GaN layer (101), an isolation layer (110) filled outside the passivation layer (108) and the N electrode (109), and a P electrode (111) on the isolation layer (110) covering the P-type In y Ga 1-y N layer (107); wherein the non-polar N-type GaN layer (101) and the N-type In x Ga 1-x N mesa structure (103) has a top surface upward, which is a (11-20) face, and the mesa structure (103) is a triangular mesa structure, which contains two inclined faces on the left and right sides, both of which are {1-101} crystal face families, and a side face which is a (000-1) face and is perpendicular to the top surface; or the non-polar N-type GaN layer (101) and the N-type In x Ga 1-x N mesa structure (103) has a top surface upward, which is a (1-100) face, and the mesa structure (103) is a trapezoidal mesa structure, which contains two inclined faces on the left and right sides, both of which are {11-20} crystal face families, and two side faces in front and back, both of which are (0001) and (000-1) faces and are perpendicular to the top surface; the strain regulation layer (104), the quantum well layer (105), the carrier regulation layer (106) and the P-type In y Ga 1-y N layer (107) are all perpendicular to the N-type In x Ga 1-x The N mesa structure (103) is parallel to the surface, and the strain regulation layer (104) and the carrier regulation layer (106) can be selectively arranged or not arranged.

2. The non-polar face Micro-LED of the free-standing mesa structure of claim 1, wherein: The mask layer (102) containing the micropore array is etched from the top down by a process after a 5-50 nm thick dielectric film of SiO2, SiN or hBN is plated on the non-polar N-type GaN layer (101). The micropores expose the underlying non-polar N-type GaN layer (101). The micropore array is arranged in a close-packed form with the centers of the micropores, and the distance between any micropore and the six adjacent micropores is equal. The distance can be adjusted according to actual needs. 3.The non-polar plane Micro-LED of the free-standing mesa structure according to claim 1, wherein: non-polar N-type GaN layer (101) and N-type In x Ga 1-x N mesa structure (103) upward top surface is (1-100) surface, at this time, mesa structure (103) is trapezoidal mesa structure, in addition to the upward top surface, it also contains left and right two inclined surfaces which are {11-20} surface family and front and back two side surfaces which are (0001) and (000-1) surface and are perpendicular to the top surface; at this time, the micro-hole diameter of the mask layer (102) is between 0.2-2 μm, when the micro-hole diameter of the mask layer (102) is not more than 1.5 μm, the circumscribed circle diameter of the mesa structure (103) in the plane is between 5-20 μm according to the need; when the micro-hole diameter of the mask layer (102) is greater than 1.5 μm, the circumscribed circle diameter of the mesa structure (103) in the plane is 3-4 times of the micro-hole diameter, but the maximum is not more than 15 μm; or, non-polar N-type GaN layer (101) and N-type In x Ga 1-x N mesa structure (103) upward top surface is (1-100) surface, at this time, mesa structure (103) is trapezoidal mesa structure, in addition to the upward top surface, it also contains left and right two inclined surfaces which are {11-20} surface family and front and back two side surfaces which are (0001) and (000-1) surface and are perpendicular to the top surface; at this time, the micro-hole diameter of the mask layer (102) is between 0.2-2 μm, when the micro-hole diameter of the mask layer (102) is not more than 1.5 μm, the circumscribed circle diameter of the mesa structure (103) in the plane is between 5-20 μm according to the need; when the micro-hole diameter of the mask layer (102) is greater than 1.5 μm, the circumscribed circle diameter of the mesa structure (103) in the plane is 3-4 times of the micro-hole diameter, but the maximum is not more than 15 μm; or, non-polar N-type GaN layer (101) and N-type In 4.The non-polar plane Micro-LED of the free-standing mesa structure of claim 1, wherein: N-type In x Ga 1-x When the molar fraction x of the N-type In x Ga 1-x N mesa structure (103) is ≤ 0.05, the strain control layer (104) is a 1-3 cycle GaN / Al x1 Ga 1-x1 N / GaN composite layer, where the thickness of Al x1 Ga 1-x1 N is less than 3 nm and x1 < 0.15; if the molar fraction 0.05 < x < 0.15, the strain control layer (104) is a 1-3 cycle bottom-up GaN / Al x1 Ga 1-x1 N / GaN / In x Ga 1-x N composite layer, where the molar fraction x of In x Ga 1-x N is the molar fraction of the N-type In x Ga 1-x N mesa structure (103), the thickness of Al x1 Ga 1-x1 N is less than 2 nm, and x1 = 2.5×x ± 0.05.​​​​​​​​​​​​​​​​​​​​​​​​​​​​ 5. The nonpolar face Micro-LED of the free-standing mesa structure of claim 1, wherein: When the light-emitting wavelength of the quantum well layer (105) is red, green and blue light respectively, the number of quantum well pairs is not more than 2 pairs, 4 pairs and 5 pairs respectively; the layer structure of the quantum well is In x2 Ga 1-x2 N / GaN / Al x3 Ga 1-x3 N / GaN, wherein x3=2.5x2±0.05, and In x2 Ga 1-x2 N, the thickness of the two layers of GaN and Al x3 Ga 1-x3 N is not more than 6 nm.

6. The nonpolar face Micro-LED of an isolated mesa structure of claim 1, wherein: The carrier modulation layer (106) is one of an electron blocking layer or a hole injection layer; wherein the electron blocking layer is an Al y1 Ga (1-y1) N / GaN superlattice with a molar composition y1 between 0.1 and 0.6 in negative correlation with the thickness of Al y1 Ga (1-y1) N; and the hole injection layer is a P-doped Al y2 Ga (1-y2) N / In y3 Ga (1-y3) N / GaN superlattice with y2 = 0.5 x y3 and a Mg element doping concentration of 5 x 10 17 cm -3 ~ 1 x 10 19 cm -3 , and a hole concentration not higher than 1 x 10 18 cm -3 .

7. The nonpolar face Micro-LED of the free-standing mesa structure of claim 1, wherein: P-type In y Ga 1-y N layer (107) has a thickness of 50-200 nm, a molar composition y of 0-0.15, and when y=0, it is GaN; the Mg element doping concentration is 2x10 19 cm -3 -5x10 19 cm -3 , and the hole concentration is not less than 1x10 18 cm -3 ; wherein the P-type In y Ga 1-y N layer (107) has a thickness of 5-30 nm on the upper surface, the Mg element doping concentration is not less than 1x10 20 cm -3 , and the hole concentration is not less than 5x10 18 cm -3 .

8. A preparation method of a non-polar face Micro-LED with a free-standing mesa structure, wherein the structure of the Micro-LED is characterized by a non-polar face N-type GaN layer (101) at the bottom, a mask layer (102) containing a micro-hole array, an N-type In x Ga 1-x N mesa structure (103) with 0≤x≤0.35, a strain regulation layer (104) grown on the mesa structure (103), a quantum well layer (105), a carrier regulation layer (106), and a P-type In y Ga 1-y N layer (107) grown on the N-type In x Ga 1-x N mesa structure (103), the strain regulation layer (104), the quantum well layer (105), the carrier regulation layer (106), and the P-type In y Ga 1-y N layer (107), a bevel and a side surface of the mesa body composed of the five parts, a passivation layer (108) on part of the mask layer (102), an N electrode (109) passing through the mask layer (102) and the passivation layer (108) and having a good ohmic contact with the N-type GaN layer (101), an isolation layer (110) filled outside the passivation layer (108) and the N electrode (109), and a P electrode (111) on the isolation layer (110) covering the P-type In y Ga 1-y N layer (107). The strain regulation layer (104), the quantum well layer (105), the carrier regulation layer (106) and the P-type In y Ga 1-y N layer (107) are all parallel to the N-type In x Ga 1-x N mesa structure (103), and the strain regulation layer (104) and the carrier regulation layer (106) can be selectively arranged or not arranged; the top surface of the non-polar N-type GaN layer (101) is a (11-20) surface, the mesa structure (103) is a triangular mesa structure, at this time, the diameter of the micropore of the mask layer (102) is between 0.2-2 μm, and the preparation method of the Micro-LED comprises the following steps: a) A non-polar (11-20) N-type GaN template is prepared as the non-polar N-type GaN layer (101), and a dielectric film of SiO2, SiN or hBN is prepared on the template. Then, a micropore is processed on the dielectric layer by a microfabrication technique to expose the underlying N-type GaN layer (101), which is the mask layer (102); b) using a MOCVD (Metal Organic Chemical Vapor Deposition) system, growing N-type In x Ga 1-x N triangular islands, the growth conditions are as follows: the growth temperature is 1080-1100 °C, the V / III ratio is 1800-2500, the growth pressure is 40-120 Torr, and the total flow rate v of the carrier gas flowing into the reaction chamber satisfies 100 PA < 760 v < 300 PA, wherein P is the growth pressure, A is the area of the graphite disc in the reaction chamber of the MOCVD system, v is in units of sccm, P is in units of Torr, and A is in units of square centimeters. c) Growth of N-type In x Ga 1-x N triangular island, shut off the supply of Group III source, increase the total flow of carrier gas into the reaction chamber to 2 times of the previous step, keep other conditions unchanged, in-situ anneal the N-type In x Ga 1-x N triangular island, promote the N-type In x Ga 1-x N triangular island to decompose from the top, forming N-type In x Ga 1-x N mesa structure (103); then, control the growth conditions of the MOCVD system: growth temperature is 1050±20℃, V / III ratio is 1000±200, growth pressure is 40-200 Torr, and the total flow of carrier gas into the reaction chamber v satisfies 150 PA < 760 v < 250 PA, on the N-type In x Ga 1-x N mesa structure (103) to grow a layer of 5-20 nm thick N-type In x Ga 1-x N of the same parameters, completing the repair of the mesa thermal annealing damage; d) maintaining the growth conditions of the MOCVD system: V / III ratio is 1000±200, growth pressure is 40-200 Torr, and the total flow rate of the carrier gas into the reaction chamber v satisfies 150 PA < 760 v < 250 PA, and sequentially epitaxially growing the strain regulation layer (104), the quantum well layer (105), the carrier regulation layer (106) and the P-type In y Ga 1-y N layer (107), completing the growth of the epitaxial layer structure; e) A dielectric film of SiO2, SiN or hBN is deposited or sputtered on the surface of the epitaxial wafer as a passivation layer (108). A standard microfabrication process is used to etch from the top down at the position where the N electrode is to be prepared to expose the N-type GaN layer (101), and then the N electrode (109) is prepared; f) spin-on a layer of polymer SOG outside the passivation layer (108) and the N electrode (109), with a height higher than the P-type In y Ga 1-y N layer (107); g) using standard microfabrication processes, etching down from the top at the locations where P electrodes are required, leaving P-type In y Ga 1-y N layer (107), followed by the fabrication of P electrodes (111); the fabrication of this Micro-LED host structure is complete.

9. A preparation method of a non-polar face Micro-LED with a free-standing mesa structure, wherein the structure of the Micro-LED is characterized by a non-polar face N-type GaN layer (101) at the bottom, a mask layer (102) containing a micro-hole array, an N-type In x Ga 1-x N mesa structure (103) with 0≤x≤0.35, a strain regulation layer (104), a quantum well layer (105), a carrier regulation layer (106), and a P-type In y Ga 1-y N layer (107) grown successively on the mesa structure (103), wherein the inclined surface and the side surface of the mesa body composed of the five parts of the N-type In x Ga 1-x N mesa structure (103), the strain regulation layer (104), the quantum well layer (105), the carrier regulation layer (106), and the P-type In y Ga 1-y N layer (107), a passivation layer (108) on part of the mask layer (102), an N electrode (109) passing through the mask layer (102) and the passivation layer (108) and having a good ohmic contact with the N-type GaN layer (101), an isolation layer (110) filled outside the passivation layer (108) and the N electrode (109), and a P electrode (111) covering the P-type In y Ga 1-y N layer (107) above the isolation layer (110); wherein, The strain regulation layer (104), the quantum well layer (105), the carrier regulation layer (106) and the P-type In y Ga 1-y N layer (107) are all parallel to the N-type In x Ga 1-x N mesa structure (103), and the strain regulation layer (104) and the carrier regulation layer (106) can be selectively arranged or not arranged; the top surface of the non-polar N-type GaN layer (101) is a (1-100) surface, the mesa structure (103) is a ladder mesa structure, at this time, the size of the micro-hole of the mask layer (102) in the left-right direction is between 0.3-0.6 times of the size of the mesa structure (103) in the left-right direction and is at most 5μm, the size in the up-down direction is the same as the size of the mesa structure (103) in the up-down direction, and the preparation method of the Micro-LED is adjusted according to the size of the device, which comprises the following steps: a) A non-polar (1-100) N-type GaN template is prepared as the non-polar N-type GaN layer (101), and a dielectric film of SiO2, SiN or hBN is prepared on the template. Then, a micropore is processed on the dielectric layer by a microfabrication technique to expose the underlying N-type GaN layer (101), which is the mask layer (102); b) using a MOCVD system, growing N-type InGaN on the micro-holes of the mask layer (102) by selective epitaxy x Ga 1-x N mesa structure (103), the growth conditions are as follows: the growth temperature is 1080-1100℃, the V / III ratio is 1800-2500, the growth pressure is 40-120 Torr, and the total flow rate v of the carrier gas flowing into the reaction chamber satisfies 100 PA < 760 v < 300 PA, wherein P is the growth pressure, A is the area of the graphite disc in the reaction chamber of the MOCVD system, v is in units of sccm, P is in units of Torr, and A is in units of square centimeter. c) setting the MOCVD system growth conditions as follows: V / III ratio of 1000±200, growth pressure of 40-200 Torr, total flow rate of carrier gas v into the reaction chamber satisfying 150 PA < 760 v < 250 PA, and sequentially epitaxially growing a strain regulation layer (104), a quantum well layer (105), a carrier regulation layer (106) and a P-type In y Ga 1-y N layer (107), to complete the growth of the epitaxial layer structure; d) A dielectric film of SiO2, SiN or hBN is deposited or sputtered on the surface of the epitaxial wafer as a passivation layer (108). A standard microfabrication process is used to etch from the top down at the position where the N electrode is to be prepared to expose the N-type GaN layer (101), and then the N electrode (109) is prepared; e) spin-on a layer of polymer SOG outside the passivation layer (108) and the N electrode (109) on the side of the P-type In y Ga 1-y N layer (107); f) using standard microfabrication processes, etching down from the top at the locations where P electrodes are needed, leaving P-type In y Ga 1-y N layer (107), followed by fabrication of P electrodes (111); fabrication of this Micro-LED body structure is complete.

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