A method for manufacturing a light-isolated full-color display array structure

Abstract

The application relates to the technical field of photoelectric devices, and discloses a preparation method of a full-color display array structure with light isolation. The method comprises the following steps: firstly, setting an LED material structure on a silicon-based gallium nitride epitaxial wafer, forming an LED mesa by adopting an ICP etching process, and establishing an array structure. Then, the isolation of sub-pixels is realized by further etching, and the accurate distribution of blue, red and green light-emitting areas is ensured. On this basis, a transparent electrode and an ohmic contact layer are set, a row control line electrode is formed, and the conductivity is improved and the contact resistance is reduced by optimizing the ohmic contact. Then, light isolation columns are formed by using organic insulating materials and inorganic optical films to prevent light cross talk between pixels and improve display quality. Finally, the preparation of the full-color display array is completed by depositing N-face electrodes, spraying fluorescent powder and integrating a driving circuit. The preparation method improves the light efficiency and color performance of the display array, and is suitable for high-resolution and high-brightness photoelectric display applications.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of photoelectric devices, and discloses a preparation method of a full-color display array structure with light isolation. BACKGROUND

[0002] At present, full-color display technology is widely used in various photoelectric display devices, and display arrays based on LEDs are widely used due to their high brightness, long service life and low power consumption. In the preparation process of such display arrays, silicon-based gallium nitride (GaN-on-Si) material has become a popular substrate material due to its compatibility with silicon-based integrated circuit technology and its superior heat dissipation performance. At the same time, ICP etching technology can be used to form a fine LED mesa array on the substrate, and then by setting row and column electrodes, independent control of RGB sub-pixels can be achieved to achieve full-color display effect. However, the existing full-color LED display array technology still faces some problems and challenges in practical application, which seriously affects the performance and user experience of the display.

[0003] Firstly, the light crosstalk phenomenon still exists in the prior art, although the light isolation column structure is adopted in the prior art to reduce the light interference between adjacent pixels, due to the limitations of materials and structure design, the light isolation column cannot completely eliminate the light reflection between pixels, which still leads to a certain degree of color distortion and light emitting efficiency reduction, which puts higher requirements on high resolution and high quality display effect. Secondly, the problem of high electrode contact resistance has not been completely solved in the prior art, although the existing P-face electrode and N-face electrode adopt transparent electrode materials and ohmic contact layers to improve the conductivity, under high current conditions, the contact resistance will still limit the conductivity efficiency of the electrode, thereby affecting the overall stability and power consumption performance of the display array. In addition, the material selection and compatibility problem also limits the long-term performance of the display array, and the silicon-based gallium nitride (GaN-on-Si) material is often used in the prior art to improve the heat dissipation performance, but due to the lattice mismatch between GaN and silicon, material defects are easily generated, which reduces the light emitting efficiency and affects the service life of the display.

[0004] In view of the above problems, the application provides a preparation method of a full-color display array structure with light isolation, which solves the problems of light crosstalk, high electrode contact resistance and poor material compatibility, and has significant technical advantages. SUMMARY

[0005] The application relates to a preparation method of a full-color display array structure with light isolation, and aims to solve the problems of display performance decline caused by lattice mismatch, thermal expansion coefficient mismatch and light crosstalk in the prior art.

[0006] To solve the above technical problems, the application provides the following technical scheme.

[0007] The application provides a preparation method of a full-color display array structure with light isolation, which comprises the following steps:

[0008] S1: preparing an array structure, arranging an LED material structure on a substrate to form an LED epitaxial wafer; removing part of the epitaxial layer by adopting an ICP etching process to form an LED mesa, and forming an array structure by the LED mesa;

[0009] S2: isolating a sub-pixel, arranging a blue pixel unit on the array structure, and continuing to etch the pedestal by adopting an ICP etching process to separate the blue pixel unit into a blue light-emitting area, a red light-emitting area and a green light-emitting area;

[0010] S3: preparing a row control line electrode, arranging a transparent electrode and an ohmic contact layer on the LED mesa to form a P-face electrode, and connecting the P-face electrodes of each sub-pixel to form a row control line electrode;

[0011] S4: preparing a light isolation column, forming a first part by coating and photolithography method by using an organic insulating column; forming a second part by thin film deposition and etching method by using an inorganic optical film; sleeving the second part on the first part; and arranging the light isolation column between the gaps of the pixel units;

[0012] S5: preparing a column control line electrode, preparing an N-face electrode in the gap of the pixel unit, and connecting the N-face electrodes of each sub-pixel to form a column control line electrode;

[0013] S6: spraying a sub-pixel, thinning and polishing the back surface of the substrate, aligning each column of sub-pixels by adopting a spraying process, aligning each column of red light-emitting areas and green light-emitting areas by adopting a spraying process, and coating red phosphor and green phosphor in sequence;

[0014] S7: increasing a driving circuit, increasing a driving circuit for the P-face electrode and the N-face electrode led out from the front surface of the substrate, and completing the preparation of the wafer-level display array.

[0015] Compared with the prior art, the application has the following beneficial effects:

[0016] 1. The application discloses a preparation method of a full-color display array structure with light isolation, which selects a silicon-based gallium nitride (GaN-on-Si) epitaxial wafer as a substrate material, significantly improves the heat conduction performance and stability of the material, calculates the lattice mismatch degree and the thermal expansion coefficient mismatch, reduces the defect generation of the GaN material on the silicon substrate, thereby improving the light emitting efficiency and material stability, and optimizes the array structure of the LED mesa, thereby effectively improving the light emitting efficiency of each pixel unit, avoiding the problem that the traditional GaN material is prone to defects on the silicon substrate, and significantly prolonging the service life of the display array and improving the overall performance.

[0017] 2. The application introduces a combination of organic insulating columns and inorganic optical films on the light isolation structure, accurately controls the thickness and light reflection performance of the isolation columns, and further reduces the light crosstalk phenomenon between adjacent pixels; this design effectively improves the color purity and display quality of the pixels, especially in small-pitch and high-resolution applications; in addition, by controlling the transmittance of the light isolation column to a specific wavelength, the display effect is further improved, so that the display device can still maintain excellent picture quality performance in complex light environments.

[0018] 3. In the design of the electrode, a transparent conductive oxide material (such as ITO, AZO, FTO) is selected as the P-face electrode material, the contact resistance of the electrode is significantly reduced by combining the optimized deposition process, and the conductivity of the electrode is improved; compared with the prior art, the application can maintain the stability and efficiency of the display array under high current, and further reduce the power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments, and understand that the following drawings only show some embodiments of the application, and should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0020] Fig. 1 is a method flowchart of the application;

[0021] Fig. 2 is a sub-pixel spraying schematic diagram of the application; DETAILED DESCRIPTION

[0022] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only for selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0023] Please refer to Figs. 1-2 It is a preparation method flow chart of a full-color display array structure with optical isolation provided by the embodiments of the present application.

[0024] The present application provides a preparation method of a full-color display array structure with optical isolation, S1: preparing an array structure, setting an LED material structure on a substrate to form an LED epitaxial wafer; removing part of the epitaxial layer by ICP etching process to form an LED mesa, and the LED mesa forms an array structure;

[0025] S101: selecting a substrate material, using a silicon-based gallium nitride (GaN-on-Si) epitaxial wafer as a substrate material; this material has excellent thermal conductivity and stability, and is compatible with silicon-based integrated process, and can be calculated by lattice mismatch and thermal expansion coefficient mismatch, specifically as formula (1)-formula (2);

[0026]

[0027] Δα=α GaN -α Si Formula (2)

[0028] Wherein, ∈ is the lattice mismatch, a GaN and a Si respectively represent the lattice constants of GaN and Si; Δα is the thermal expansion coefficient mismatch, α GaN and α SiGaN and Si thermal expansion coefficient mismatch; this formula is used to calculate the lattice mismatch and thermal expansion coefficient difference between gallium nitride (GaN) and silicon-based materials (Si). Lattice mismatch can cause stress and defects in the material during epitaxial growth, which can reduce light-emitting efficiency and affect the stability of the display. Through this formula, the degree of mismatch between GaN and Si can be evaluated, and the material performance can be optimized by adjusting process parameters such as deposition temperature and growth rate to reduce defects and improve light-emitting efficiency. Based on the calculation results of lattice mismatch, fine epitaxial growth control technology can be further developed to optimize deposition temperature, deposition rate and stress management to ensure material stability and efficient light emission.

[0029] S102: LED material structure setting, depositing multiple LED material layers including n-GaN layer, active region layer and p-GaN layer on silicon-based gallium nitride epitaxial wafer through epitaxial growth, finally forming LED epitaxial wafer, epitaxial growth model is specifically as formula (3);

[0030]

[0031] where R is the material deposition rate, D s is the surface diffusion coefficient, D b is the bulk diffusion coefficient; this formula is used to calculate the relationship between the surface diffusion coefficient D s and the bulk diffusion coefficient D b during material deposition to control the material deposition rate. Through this formula, the conditions of epitaxial growth can be optimized to ensure uniform deposition of LED material structure. This is crucial for improving the light-emitting efficiency and display effect of each pixel in LED display. Based on this formula, the epitaxial growth process of the material can be further optimized by adjusting the surface diffusion and bulk diffusion rates to control the uniformity and quality of the material.

[0032] S103: Forming LED mesa array structure, etching part of the epitaxial layer using ICP (plasma dry etching) process to form LED mesa, the LED mesa forms an array structure, each mesa as a pixel unit, ICP etching model and array arrangement are specifically as formula (4)-formula (5);

[0033]

[0034] where E is the electric field intensity, V biasis the bias voltage, d is the thickness of the etching gap; D is the array pitch, N is the number of pixels per unit area. Formula (4) is used to calculate the electric field strength during etching. By adjusting the electric field strength, the etching rate and precision can be controlled to ensure consistent etching depth for each sub-pixel, thereby improving the resolution and pixel uniformity of the display array. Based on this formula, more accurate etching process control techniques can be developed to achieve high-precision patterning control by adjusting the electric field strength, which is particularly suitable for the manufacture of high-resolution displays. Formula (5) uses standard rectangular or honeycomb arrangements to calculate the pitch of each pixel unit. ICP etching technology provides precise pattern control capabilities to ensure consistency and high-resolution display effects for each pixel unit.

[0035] S2: Isolate sub-pixels, the array structure is provided with blue pixel units respectively, and the ICP etching process is used to continue etching the base to separate the blue pixel units into blue, red and green light-emitting regions;

[0036] S201: Further etching the base, further using the ICP etching process to further segment the base on each LED mesa to form red, green and blue light-emitting regions, as formula (6) shows;

[0037]

[0038] wherein E is the etching rate, Ah is the etching depth, and At is the time; this formula is used to calculate the etching rate during etching. Through this formula, the etching process can be accurately controlled to ensure that the shape and size of each sub-pixel are consistent. This is very important for the high-resolution requirements of display arrays, and can effectively reduce optical crosstalk and color distortion caused by uneven etching. The technology derived from this formula is to dynamically adjust etching parameters such as plasma power and gas pressure to monitor and adjust the etching rate in real time, ensuring high-precision array structures, improving production efficiency and display quality, and particularly excellent in the production of small-pitch LED displays.

[0039] S202: Photolithography mask control area, using photolithography mask technology to accurately control the area of each sub-pixel to ensure uniform distribution of RGB three colors in the array, as formula (7) shows;

[0040] E exposure = I x t formula (7)

[0041] wherein E exposure is the exposure energy, I is the light intensity, and t is the exposure time; the area of the sub-pixel is defined by the photolithography process. Using photolithography mask technology to accurately control the sub-pixel area can avoid optical crosstalk and color distortion. By optimizing the exposure energy and light intensity, the precise positioning of each sub-pixel area can be ensured, thereby improving the overall picture quality of the display.

[0042] S203: Processing stress and lattice mismatch, for the lattice mismatch problem of gallium nitride material and silicon-based material, optimization of etching process and annealing treatment are adopted to reduce defect density and improve the light emitting efficiency of each sub-pixel, specifically as formula (8) - formula (9);

[0043]

[0044] Wherein, σ is stress, E is elastic modulus, ΔT is temperature change, v is Poisson's ratio; ∈ is lattice mismatch rate, a substrate is the lattice constant of the substrate material, a film is the lattice constant of the epitaxial layer material. Formula (9) is used to calculate the lattice mismatch rate between different materials, so as to optimize the etching process and stress management.

[0045] S3: Preparing row control line electrode, setting transparent electrode and ohmic contact layer on the LED mesa to form P surface electrode, connecting the P surface electrode of each sub-pixel to form row control line electrode;

[0046] S301: P surface electrode setting, on the top of each LED mesa (i.e. on the p-GaN layer), P surface electrode is formed by depositing transparent electrode and ohmic contact layer, and all sub-pixel P surface electrodes are connected together by lithography and etching process to form row control line electrode, and the light transmittance of transparent electrode and the contact resistance of ohmic contact layer are calculated and optimized for ohmic contact, specifically as formula (10) - formula (12);

[0047]

[0048]

[0049] Wherein, T is transmittance, I transmitted is the transmitted light intensity, I incident is the incident light intensity; R c is the ohmic contact resistance, p is the contact resistivity, A is the contact area; I is the current through the electrode, V is the voltage, and R is the total resistance of the electrode; Formula (11) is used to calculate the ohmic contact resistance, and through this formula, the selection of transparent conductive material and the design of contact area can be optimized to reduce the contact resistance of the electrode and improve the conductivity of the electrode. Based on this formula, appropriate transparent conductive materials (such as ITO, AZO, etc.) can be selected, and by optimizing the deposition process, the contact resistance can be reduced and the efficiency of the display array can be improved. This technical means can effectively reduce power consumption and improve the stability and brightness of the display. Formula (12) is used to calculate the current distribution of the row control line electrode to ensure uniform distribution of current.

[0050] S302: Ohmic contact optimization, to improve the electrical conductivity of the electrode and reduce the contact resistance, select the appropriate transparent conductive oxide material and optimize the deposition conditions. The material selection is ITO, which is a common choice for transparent conductive materials, with low resistivity and high light transmittance. AZO and FTO are also alternative materials with good conductivity and transparency, suitable for different application requirements. Deposition condition optimization is to adjust the working pressure, sputtering power, substrate temperature and post-processing conditions, so as to optimize the electrical and optical properties of TCO thin film, so as to realize low contact resistance and high conductivity.

[0051] S4: Preparation of light isolation column, forming the first part of the organic insulating column by coating and photolithography method; the second part of the inorganic optical film is formed by thin film deposition and etching method; the second part is set on the first part; the light isolation column is set between the pixel unit gap;

[0052] S401: Formation of organic insulating column, forming the first part of the organic insulating column between the sub-pixels by coating and photolithography method; the insulating column material is polyimide, which has good insulation and thermal stability, and the coating thickness of the organic insulating material is calculated as formula (13);

[0053]

[0054] Wherein, d is the coating thickness, V is the volume of the coating material, and A is the area of the coating area;

[0055] S402: Formation of inorganic optical film, using thin film deposition and etching method to form the second part of inorganic optical film on the outer surface of the organic insulating column, such as silicon nitride or silicon oxide film, which can provide excellent light isolation effect.

[0056] S403: Light isolation column setting, setting the light isolation column between each pixel unit to avoid light crosstalk between adjacent pixels, so as to improve the display quality, and controlling the thin film thickness by thin film deposition rate formula as formula (14)-(15);

[0057]

[0058] Wherein, T(λ) is the transmittance of the light isolation column to a specific wavelength, λ is the wavelength of light, n is the refractive index of the optical film, d is the thickness of the light isolation column, and θ is the incident angle; R dep is the deposition rate, d film is the film thickness, t depis the deposition time. Equation (14) is used to calculate the transmittance of the light isolation column for different wavelengths of light. Through this formula, a light isolation structure can be designed for different wavelengths to reduce light crosstalk and improve display effects. Based on this formula, optical optimization techniques can be developed to design the best light isolation column structure for different display environments (such as outdoor or high brightness scenes) to ensure color reproduction and brightness consistency. This technical means can significantly improve the performance of the display, especially in complex lighting conditions. Equation (15) is used to calculate the deposition rate of the thin film on the light isolation column. By controlling the deposition rate, the thickness of the light isolation column can be ensured to be uniform, thereby optimizing the optical performance of the display array and reducing light crosstalk. Based on this formula, precise thin film deposition techniques can be derived by adjusting the deposition rate to optimize the thickness and reflective performance of the light isolation column. This technology can further improve the color purity and luminous efficiency of the display array.

[0059] S5: Preparation of column control line electrode, N-face electrode is prepared in the gap between pixel units, and the N-face electrodes of each sub-pixel are connected to form a column control line electrode;

[0060] S501: N-face electrode setting, in the gap between each sub-pixel, N-face electrode material is deposited by sputtering or evaporation technology, and then the electrodes are connected by using photolithography and etching technology to form a column control line electrode, specifically as formula (15) - formula (16);

[0061]

[0062] wherein J is the current density, I is the current through the N-face electrode, A is the cross-sectional area of the N-face electrode, η is the injection efficiency, and V is the voltage; formula (15) is used to optimize the size and material of the column control line electrode to ensure sufficient current density. Formula (16) calculates the injection efficiency based on the current density calculated by formula (15).

[0063] S502: Electrode interface optimization, optimize the contact interface between the N-face electrode material and the gallium nitride layer to reduce the contact resistance and improve the current injection efficiency, and minimize the resistance of the column control line electrode, specifically as formula (17);

[0064]

[0065] wherein R is the resistance, ρ is the resistivity, L is the length of the electrode, and A is the cross-sectional area of the electrode. The optimized connection of the column control line electrode improves the control accuracy, reduces the complexity of the driving circuit, and enhances the response speed and stability of the display.

[0066] S6: Spraying sub-pixels, thinning and polishing the back of the substrate, aligning each column of sub-pixels using the spraying process, aligning each column of red and green light emitting regions using the spraying process, and sequentially coating red and green phosphor powders;

[0067] S601: Backside thinning and polishing, thinning and polishing the backside of the substrate to improve light transmittance and reduce the overall thickness of the device, and calculating the backside thinning as formula (18);

[0068]

[0069] Wherein, R is the thinning rate, H is the thickness after thinning, t is the thinning time; formula (18) is used to control the thickness and speed of substrate thinning, to ensure the light transmittance of the device.

[0070] S602: Fluorescent powder spraying, using a precision spraying device to align each sub-pixel area, respectively spraying red and green fluorescent powder, and the red and green fluorescent powder emits light under the excitation of blue LED light, thereby realizing full-color display, and the spraying density is controlled by spraying control and the coverage and thickness of the sprayed fluorescent powder are calculated for feedback, as formula (19) - formula (20);

[0071]

[0072] Wherein, D is the coverage density of spraying, v is the spraying speed, t is the spraying time, d is the distance between the nozzle and the substrate; A covered is the area covered by the fluorescent powder, A total is the total area. Formula (19) is used to control the spraying density of red and green fluorescent powder, to ensure uniform light emission of each sub-pixel.

[0073] S7: Increase the driving circuit, increase the driving circuit of the P-face electrode and the N-face electrode led out on the front side of the substrate, complete the preparation of the wafer-level display array.

[0074] S701: Design of driving circuit, connect the P-face electrode and N-face electrode led out on the front side of the substrate, increase the driving circuit including row driver, column driver and pixel driving circuit, complete the overall structure design of wafer-level display array, through the design of voltage distribution and output control in driving circuit and total power consumption of circuit, as formula (21) - formula (22);

[0075] P = V x I formula (21)

[0076]

[0077] Wherein, P is the power consumption, V is the voltage, I is the current; V out is the output voltage of the driving circuit, V inis the input voltage, R1 and R2 are voltage dividing resistors; formula (21) is used to calculate the power consumption of the driving circuit, through which the design of the driving circuit can be optimized to ensure that the display works efficiently while reducing power consumption and prolonging the service life of the display array. Based on this formula, the circuit design can be optimized to develop low-power display driving technology, which is particularly suitable for display devices used for a long time, can significantly reduce energy consumption and prolong the service life of the device.

[0078] S702: Circuit integration optimization, electromagnetic compatibility, power management, heat dissipation design and other aspects need to be considered in integrated circuit design, the electromagnetic compatibility and the output current of the driving circuit are calculated to ensure the stable operation of the display array, specifically as formula (23)-formula (24);

[0079]

[0080] Wherein, I out is the output current of the driving circuit, V out is the output voltage of the driving circuit, R load is the load resistance; EMI is electromagnetic interference, V noise is the noise voltage, and f is the frequency.

[0081] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application has various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for fabricating a full-color display array structure with optical isolation, comprising: The preparation method comprises the following steps: ​ S1: preparing an array structure, disposing an LED material structure on a substrate to form an LED epitaxial wafer; removing part of the epitaxial layer by using an ICP etching process to form an LED mesa, and the LED mesa forms an array structure; S1 comprises S101: selection of a substrate material, S102: structure setting of an LED material, and S103: LED mesa array structure; In S101: selection of a substrate material, a silicon-based gallium nitride epitaxial wafer is used as the substrate material, and the lattice mismatch degree and the thermal expansion coefficient mismatch are calculated, specifically as formula (1) to formula (2); Formula (1); Formula (2); wherein, is the lattice mismatch degree, and represent the lattice constants of GaN and Si, respectively; is the thermal expansion coefficient mismatch degree, represent the thermal expansion coefficient mismatch of GaN and Si, respectively; formula (1) and formula (2) are used to calculate the lattice mismatch degree and the thermal expansion coefficient difference between gallium nitride and silicon-based materials, and then the material performance is optimized by adjusting the process parameters; S2: isolating sub-pixels, the array structure is respectively provided with a blue pixel unit, and the base is further etched by using an ICP etching process to separate the blue pixel unit into a blue light-emitting area, a red light-emitting area and a green light-emitting area; S2 comprises S201: further etching of the base, S202: light etching mask control area, and S203: stress and lattice mismatch treatment; In S203: stress and lattice mismatch treatment, the lattice mismatch problem between the silicon-based gallium nitride epitaxial wafer and the gallium nitride material layer in the LED epitaxial wafer is solved by using an optimized etching process and annealing treatment, specifically as formula (8) to formula (9); Formula (8); Equation (9); wherein, is the stress, is the elastic modulus, is the temperature change is the Poisson's ratio; is the lattice mismatch rate, is the lattice constant of the silicon-based gallium nitride epitaxial wafer, is the lattice constant of the layer of gallium nitride material deposited in the LED epitaxial wafer; S3: preparing a row control line electrode, a transparent electrode and an ohmic contact layer are disposed on the LED mesa to form a P surface electrode, and the P surface electrodes of each sub-pixel are connected to form a row control line electrode; S4: preparing a light isolation column, an organic insulating column is formed into a first part by coating and photolithography, an inorganic optical film is formed into a second part by thin film deposition and etching, the second part is sleeved on the first part, and the light isolation column is arranged between the gaps of the pixel units; S5: preparing a column control line electrode, an N surface electrode is prepared in the gap of the pixel unit, and the N surface electrodes of each sub-pixel are connected to form a column control line electrode; S6: spraying sub-pixels, the back of the substrate is thinned and polished, each column of sub-pixels is aligned by using a spraying process, each column of red light-emitting areas and green light-emitting areas is aligned by using a spraying process, and red phosphor and green phosphor are coated in sequence; S7: adding a driving circuit, a driving circuit is added to the P surface electrode and the N surface electrode led out of the front of the substrate, and the preparation of the wafer-level display array is completed.

2. The preparation method of the full-color display array structure with light isolation according to claim 1, wherein S102: LED material structure setting, a plurality of LED material layers are deposited on the silicon-based gallium nitride epitaxial wafer by epitaxial growth, including an n-GaN layer, an active region layer and a p-GaN layer, to finally form an LED epitaxial wafer, and the epitaxial growth model is specifically as formula (3); S103: forming an LED mesa array structure, part of the epitaxial layer is etched away by using an ICP process to form an LED mesa, and the LED mesa forms an array structure, each mesa serves as a pixel unit, and the ICP etching model and the array arrangement are specifically as formula (4) to formula (5); Formula (3); wherein, is the material deposition rate, is the surface diffusion coefficient, is the bulk diffusion coefficient; equation (3) is used to calculate the relationship between the surface diffusion coefficient and the bulk diffusion coefficient to optimize the conditions for epitaxial growth; 3. The preparation method of the full-color display array structure with light isolation according to claim 1, wherein Equation (4); Equation (5); wherein, is the electric field intensity, is the bias voltage, is the thickness of the etching gap; is the array pitch, is the number of pixels per unit area; formula (4) is used to calculate the electric field intensity in the etching process, and the etching rate and precision are controlled by adjusting the electric field intensity to ensure that the etching depth of each sub-pixel is consistent. ​ S201: The base is further etched, and the ICP etching process is used to further divide the base on each LED mesa to form red, green, and blue light-emitting regions, as shown in formula (6); Equation (6); wherein is the etch depth, is time; equation (6) is used to calculate the rate during etching; S202: Photolithography mask control region, using photolithography mask technology to accurately control the area of each sub-pixel, to ensure that RGB three colors are uniformly distributed in the array, as shown in formula (7); Equation (7); wherein is the exposure energy, is the light intensity, is the exposure time.

4. The method of claim 1, wherein the method further comprises: In step S3, the setting of the P-face electrode, the ohmic contact optimization is performed according to the following steps: ​ S301: P-face electrode setting, on the top of each LED mesa, a P-face electrode is formed by depositing a transparent electrode and an ohmic contact layer, and all the P-face electrodes of the sub-pixels are connected together to form a row control line electrode, and the ohmic contact optimization is performed by calculating the light transmittance of the transparent electrode and the contact resistance of the ohmic contact layer, as shown in formulas (10)-(12); Equation (10); Equation (11); Equation (12); wherein, is the transmittance, is the transmitted light intensity, is the incident light intensity; is the ohmic contact resistance, is the contact resistivity, is the contact area; is the current through the electrode, is the voltage, is the total resistance of the electrode; equation (11) is used to calculate the ohmic contact resistance, optimizing the selection of the transparent conductive material and the contact area design; S302: Ohmic contact optimization, the material is selected as ITO, AZO or FTO, and the deposition conditions are optimized by adjusting the working pressure, sputtering power, substrate temperature and post-processing conditions.

5. The method of claim 1, wherein the method further comprises: In step S4, the formation of organic insulating pillars, the formation of inorganic optical films, and the setting of light isolation pillars are performed according to the following steps: ​ S401: Formation of organic insulating pillars, a first part of the organic insulating pillars is formed between the sub-pixels by coating and photolithography, and the insulating pillar material is polyimide, and the coating thickness of the organic insulating material is calculated as shown in formula (13); Equation (13); wherein is the volume of the coating material, is the area of the coating region; S402: Formation of inorganic optical film, a second part of the inorganic optical film is formed on the outer surface of the organic insulating pillar using thin film deposition and etching method, and the material of the inorganic optical film is silicon nitride or silicon oxide film; S403: Light isolation pillar setting, light isolation pillars are set between each pixel unit to avoid light crosstalk between adjacent pixels, and the thin film thickness is controlled by the thin film deposition rate formula, as shown in formulas (14)-(15); Equation (14); Equation (15); wherein, is the transmittance of the light isolation post for a specific wavelength, is the wavelength of the light, is the refractive index of the optical film, is the thickness of the light isolation post is the incident angle; is the film thickness, is the deposition time; equation (14) is used to calculate the transmittance of the light isolation post for different wavelengths of light, and equation (15) is used to calculate the rate of film deposition on the light isolation post.

6. The method of claim 1, wherein the method further comprises: In step S5, the setting of the N-face electrode, and the optimization of the electrode interface are performed according to the following steps: ​ S501: N-face electrode setting, in the gap between each sub-pixel, the N-face electrode material is deposited by sputtering or evaporation technology, and then the electrodes are connected using photolithography and etching technology to form a column control line electrode, as shown in formulas (16)-(17); Equation (16); Equation (17); wherein, is the current through the N-face electrode, is the cross-sectional area of the N-face electrode, is the injection efficiency, is the voltage; S502: Electrode interface optimization, the contact interface between the N-face electrode material and the gallium nitride layer is optimized, and the resistance of the column control line electrode is minimized, as shown in formula (18); Equation (18); wherein is the resistance, is the resistivity, is the length of the electrode, is the cross-sectional area of the electrode.

7. The method of claim 1, wherein the method further comprises: In step S6, the substrate back thinning and polishing, and the phosphor spraying are performed according to the following steps: ​ S601: Substrate back thinning and polishing, the substrate back is thinned and polished, and the back thinning is calculated, as shown in formula (19); Equation (19); wherein, is the thinning rate, is the thickness after thinning, is the thinning time; S602: Phosphor spraying, a precise spraying device is used to align the sub-pixel regions, and red and green phosphors are sprayed respectively, the red and green phosphors emit light under the excitation of blue LED light, and the spraying control is performed by controlling the spraying density, and the coverage and thickness of the spraying are calculated for feedback, as shown in formulas (20)-(21); Equation (20); Formula (21); wherein, is the coverage density of the spray, is the spray speed, is the spray time, is the distance between the nozzle and the substrate; is the coverage, is the area covered by the phosphor, is the total area.

8. The method of claim 1, wherein the method further comprises: In step S7, the design of the driving circuit, and the optimization of the circuit integration are performed according to the following steps: ​ S701: Design of the driving circuit, connect the P-face electrode and N-face electrode on the front surface of the substrate, increase the driving circuit including row driver, column driver and pixel driving circuit, complete the overall structure design of wafer-level display array, through the design of voltage distribution and output control in the driving circuit and the total power consumption of the circuit, specifically as formula (22) - formula (23); Equation (22); Equation (23); wherein, P is the power consumption, V is the voltage, I is the current; Vout is the output voltage of the driving circuit, Vin is the input voltage, and R is the voltage dividing resistor; equation (22) is used to calculate the power consumption of the driving circuit, to optimize the design of the driving circuit; S702: Circuit integration optimization, electromagnetic compatibility, power management and heat dissipation design need to be considered in integrated circuit design, through the calculation of electromagnetic compatibility and the output current of the driving circuit to ensure the stable operation of the display array, specifically as formula (24) - formula (25); Equation (24); Equation (25); wherein, is the output current of the driving circuit, is the output voltage of the driving circuit, is the load resistance; is the electromagnetic interference, is the noise voltage, is the frequency.

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