Light-emitting display device

Abstract

According to an example embodiment, a light emitting display device includes a transistor, a driving voltage line, a driving voltage connection electrode, an initialization control line, an output current passing region, and a shielding layer, in a plan view of the output current passing region, the initialization control line is disposed on a side of a channel of the transistor and overlaps the shielding layer, and in a plan view of the output current passing region, the initialization control line is disposed on a side of the channel of the transistor. And the shielding layer is connected to the driving voltage line through the driving voltage connection electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0089091 filed in the Korean Intellectual Property Office on July 10, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a light-emitting display device. Background Art

[0004] The display device is a device that displays an image, and includes a liquid crystal display (LCD) or an organic light emitting diode (OLED), etc.

[0005] Such display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, electronic books, portable game machines, and various terminals.

[0006] A display device such as an organic light emitting display device may have a bendable or foldable structure by using a flexible substrate.

[0007] In addition, in small electronic devices such as mobile phones, optical elements such as cameras and optical sensors are formed in a frame area located around a display area, but as the size of the display screen increases, the size of the frame area located around the display area is gradually reduced. A technology that can provide an optical sensor on the back of the display area is being developed. Summary of the invention

[0008] Embodiments are directed to providing a light emitting display device in which display quality is not deteriorated due to signal interference.

[0009] According to the embodiment, the light-emitting display device includes: a first semiconductor layer, which is arranged on a substrate and includes a channel of a driving transistor, a channel of a sixth transistor, and an output current passing region arranged on one side of the channel of the sixth transistor; a first gate conductive layer, which is arranged on the first semiconductor layer and includes a gate electrode of the driving transistor overlapping with the channel of the driving transistor in a plan view and a light-emitting control line overlapping with the channel of the sixth transistor in a plan view; a second gate conductive layer, which is arranged on the first gate conductive layer and includes a first storage electrode overlapping with the gate electrode of the driving transistor in a plan view and a shielding layer overlapping with the output current passing region in a plan view; a second semiconductor layer, which is arranged on the second gate conductive layer and includes a channel of a fourth transistor; a third gate conductive layer, which is arranged on the second semiconductor layer and includes a gate electrode overlapping with the gate electrode of the driving transistor in a plan view; an initialization control line overlapping the channels of the four transistors; a first data conductive layer, arranged on the third gate conductive layer, and including a driving voltage connection electrode and a first anode connection electrode electrically connected to the output current passing area arranged on the one side of the channel of the sixth transistor; a first organic layer, covering the first data conductive layer; a second data conductive layer, arranged on the first organic layer, and including a second anode connection electrode electrically connected to the first anode connection electrode, and a driving voltage line; a second organic layer, arranged on the second data conductive layer; and an anode, arranged on the second organic layer and electrically connected to the second anode connection electrode, wherein, in a plan view, the initialization control line overlaps with the output current passing area and the shielding layer arranged on the one side of the channel of the sixth transistor, and the shielding layer is connected to the driving voltage line through the driving voltage connection electrode.

[0010] The second gate conductive layer also includes a lower shielding layer of the fourth transistor, and the lower shielding layer of the fourth transistor is electrically connected to the initialization control line and may overlap with the channel of the fourth transistor in a plan view.

[0011] The second gate conductive layer also includes a lower second scan line, the second semiconductor layer also includes a channel of a third transistor, and the third gate conductive layer also includes an upper second scan line, in a plan view, the channel of the third transistor can overlap with the lower second scan line and the upper second scan line, and the same signal can be applied to the lower second scan line and the upper second scan line.

[0012] The first semiconductor layer further includes a channel of a seventh transistor having one end connected to a second initialization voltage line, and the output current passing region may be located between the channel of the seventh transistor and the channel of the sixth transistor.

[0013] The first semiconductor layer further includes a channel of a fifth transistor having one end connected to the driving voltage line, and in a plan view, the channel of the sixth transistor and the channel of the fifth transistor may overlap the light emission control line.

[0014] The first semiconductor layer may further include a channel of a second transistor, and one end of the second transistor may be connected to a data line.

[0015] The light emitting display device further includes: a third data conductive layer located between the second organic layer and the anode and disposed above the second organic layer; and a third organic layer covering the third data conductive layer, wherein the anode may be located above the third organic layer.

[0016] The data line may be located in the third data conductive layer.

[0017] The third data conductive layer may further include a third anode connection electrode, and the third anode connection electrode may connect the second anode connection electrode and the anode.

[0018] The light-emitting display device also includes: a metal layer, which is arranged between the substrate and the first semiconductor layer and includes an extension portion; and a buffer layer, which is arranged between the metal layer and the first semiconductor layer, wherein in a plan view, the extension portion of the metal layer can overlap with the channel of the driving transistor.

[0019] The light-emitting display device according to the embodiment includes: a first semiconductor layer, which is located on a substrate and includes a channel of a driving transistor; a first gate conductive layer, which is located above the first semiconductor layer and includes a gate electrode of the driving transistor overlapping with the channel of the driving transistor in a plan view; a second gate conductive layer, which is provided on the first gate conductive layer and includes a first storage electrode overlapping with the gate electrode of the driving transistor in a plan view, and a lower shielding layer; a second semiconductor layer, which is located above the second gate conductive layer and includes a channel of a fourth transistor overlapping with the lower shielding layer in a plan view; a third gate conductive layer, which is located above the second semiconductor layer and includes a gate electrode overlapping with the channel of the fourth transistor in a plan view; an initialization control line overlapping the channel; a first data conductive layer, located above the third gate conductive layer, and including a first connection electrode and a first anode connection electrode connecting the gate electrode of the driving transistor and one side of the channel of the fourth transistor; a first organic layer, covering the first data conductive layer; a second data conductive layer, located above the first organic layer, and including a second anode connection electrode electrically connected to the first anode connection electrode, and a driving voltage line; a second organic layer, located above the second data conductive layer; and an anode, located above the second organic layer and electrically connected to the second anode connection electrode, wherein the lower shielding layer has an island structure, and the initialization control line is electrically connected to the lower shielding layer through an opening.

[0020] The second gate conductive layer also includes a lower second scan line, the second semiconductor layer also includes a channel of a third transistor, and the third gate conductive layer also includes an upper second scan line, in a plan view, the channel of the third transistor can overlap with the lower second scan line and the upper second scan line, and the same signal can be applied to the lower second scan line and the upper second scan line.

[0021] The first semiconductor layer also includes a channel of a sixth transistor and an output current passing region arranged on one side of the channel of the sixth transistor, and the second gate conductive layer also includes a shielding layer overlapping with the output current passing region in a plan view, in which the initialization control line overlaps with the output current passing region and the shielding layer arranged on one side of the channel of the sixth transistor, and the shielding layer can be connected to the driving voltage line.

[0022] The first semiconductor layer further includes a channel of a seventh transistor, and one end of the seventh transistor is connected to a second initialization voltage line, and the output current passing region is disposed between the channel of the seventh transistor and the channel of the sixth transistor.

[0023] The first semiconductor layer further includes a channel of a fifth transistor, one end of the fifth transistor is connected to the driving voltage line, and the channel of the sixth transistor and the channel of the fifth transistor overlap the light emission control line in a plan view.

[0024] The first semiconductor layer may further include a channel of a second transistor, and one end of the second transistor may be connected to a data line.

[0025] The light emitting display device further includes: a third data conductive layer disposed between the second organic layer and the anode and disposed on the second organic layer; a third organic layer covering the third data conductive layer, and the anode may be directly disposed on the third organic layer.

[0026] The data line may be located in the third data conductive layer.

[0027] The third data conductive layer may further include a third anode connection electrode, and the third anode connection electrode may connect the second anode connection electrode and the anode.

[0028] The light-emitting display device also includes: a metal layer, which is arranged between the substrate and the first semiconductor layer and includes an extension portion; and a buffer layer, which is arranged between the metal layer and the first semiconductor layer, wherein in a plan view, the extension portion of the metal layer can overlap with the channel of the driving transistor.

[0029] According to the embodiment, when the voltage level of the initialization control signal applied to the fourth transistor is changed, the amount of light emitting current delivered to the light emitting diode is maintained constant by the shielding layer to prevent degradation of display quality.

[0030] According to an embodiment, an initialization control line for transmitting an initialization control signal to the fourth transistor is formed as a single layer, an island-shaped lower shielding layer is formed under the semiconductor layer included in the fourth transistor, and transmits the initialization control signal, so that the fourth transistor is properly controlled and leakage current is not generated in the fourth transistor, so that the display quality is not deteriorated. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic perspective view showing a use state of the display device according to the embodiment.

[0032] Figure 2 is an exploded perspective view of a display device according to an embodiment.

[0033] Figure 3 is a block diagram of a display device according to an embodiment.

[0034] Figure 4is a perspective view schematically showing a light emitting display device according to another embodiment.

[0035] Figure 5 is a plan view showing an enlarged portion of a light emitting display device according to an embodiment.

[0036] Figure 6 is a circuit diagram of one pixel included in the light emitting display device according to the embodiment.

[0037] Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 is a diagram specifically illustrating a structure of each layer according to a manufacturing order of a lower panel layer in a light-emitting display device according to an embodiment.

[0038] Fig. 22 is a cross-sectional view of a light emitting display device according to an embodiment.

[0039] Fig.23 is a plan view showing the vicinity of an initialization control line in the light emitting display device according to the embodiment.

[0040] Fig.24 It is along Fig.23 A cross-sectional view taken along the section line XXIV-XXIV'.

[0041] Fig.25 is a plan view showing the vicinity of an initialization control line in a light-emitting display device according to a comparative example.

[0042] Fig.26 It is along Fig.25 A cross-sectional view taken along the section line XXVI-XXVI'.

[0043] Fig. 27 and Fig.28 It is a view to compare and explain the difference in characteristics based on the comparative example and the embodiment.

[0044] Fig.29 is a cross-sectional view of a light emitting display device according to another embodiment. DETAILED DESCRIPTION

[0045] Hereinafter, with reference to the accompanying drawings, various embodiments will be described in detail so that those skilled in the art can easily implement the inventive concept.

[0046] The inventive concept may be embodied in many different forms and is not limited to the embodiments set forth herein.

[0047] In order to clearly describe the present inventive concept, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

[0048] In addition, since the size and thickness of each component shown in the drawings are arbitrarily illustrated for convenience of explanation, the present inventive concept is not necessarily limited to the size and thickness of each component shown.

[0049] In the drawings, the thickness is exaggerated to clearly express each layer and region.

[0050] Also, in the drawings, the thicknesses of some layers and regions are exaggerated for convenience of explanation.

[0051] Furthermore, when a component such as a layer, film, region, panel, or assembly is referred to as being “on” or “over” another component, this means not only when the component is “directly on” the other component but also when there is another component between the component and the other component.

[0052] In contrast, when a component is referred to as being “directly on” another component, it means that there are no other components between the component and the other component.

[0053] In addition, “above” or “on” a reference component means being located above or below the reference component, and does not necessarily mean being located “above” or “on” the reference component in an opposite direction of gravity.

[0054] In addition, throughout the specification, when a certain component is referred to as “comprising”, unless otherwise specified, it means that the certain component may also include other components rather than excluding the other components.

[0055] In addition, throughout the specification, when “in a plan view” is mentioned, it means when the target component is viewed from above, and when “in a cross-sectional view” is mentioned, it means when a vertically cut cross section of the target component is viewed from the side.

[0056] In addition, throughout the specification, when "connected" is used, it not only means that two or more components are directly connected, but also means that when two or more components are indirectly connected through other components, the two or more components are physically connected. In addition to being connected or electrically connected, a plurality of components that are referred to by different names according to their positions or functions but are substantially integral may also be connected to each other.

[0057] In addition, throughout the specification, when a portion such as a wiring, layer, film, region, board, component, etc. "extends in a first direction or a second direction", the portion only means a straight line extending in the corresponding direction. On the contrary, the portion is a structure extending substantially along the first direction or the second direction, and includes a structure that is bent at one part, has a zigzag structure, or extends while including a curved structure.

[0058] In addition, electronic devices (e.g., mobile phones, televisions (TVs), monitors, and notebook computers) that include the display devices and display panels described in this specification or the display devices and display panels manufactured by the manufacturing methods described in this specification are not excluded from the scope of this specification.

[0059] In the following, we will Figures 1 to 3 A schematic structure of a display device is described.

[0060] Figure 1 is a schematic perspective view showing a use state of a display device according to an embodiment, Figure 2 is an exploded perspective view of a display device according to an embodiment, and Figure 3 is a block diagram of a display device according to an embodiment.

[0061] Reference Figure 1 The display device 1000 according to the embodiment is a device for displaying a moving image (or dynamic image) or a static image, and may be a smart phone, a tablet personal computer (PC), or a mobile phone. Not only portable electronic devices such as communication terminals, electronic notebooks, electronic books, portable multimedia players (PMP), navigation devices, and ultra mobile PCs (UMPCs), but also such as televisions, laptop computers, monitors, billboards, Internet of Things (IoT), etc., can be used as a display screen for various products.

[0062] In addition, the display device 1000 according to the embodiment may be used for wearable devices such as a smart watch, a watch phone, a glasses-type display, and a head-mounted display (HMD).

[0063] In addition, the display device 1000 according to the embodiment includes a central information display (CID) set on the instrument panel of the vehicle, the central instrument panel or dashboard of the vehicle, or an interior rearview mirror display (interior rearview mirror display) of the vehicle instead of a side mirror, an entertainment facility for the rear seats of the vehicle, and can be used as a display placed on the back of the front seats of the vehicle.

[0064] For ease of explanation, Figure 1 The display device 1000 is shown used as a smartphone.

[0065] The display device 1000 may display an image in the third direction DR3 on a display surface parallel to each of the first direction DR1 and the second direction DR2 .

[0066] The display surface on which the image is displayed may correspond to the front surface of the display device 1000 , and may correspond to the front surface of the cover window WU.

[0067] Images can include static images as well as dynamic images.

[0068] In the present embodiment, the front (or upper) surface and the rear (or lower) surface of each member are defined based on the direction in which an image is displayed.

[0069] The front surface and the rear surface face away from each other in the third direction DR3, and a normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3.

[0070] A separation distance between the front surface and the rear surface in the third direction DR3 may correspond to a thickness of the display panel in the third direction DR3.

[0071] The display device 1000 according to the embodiment may detect a user's input applied from the outside (refer to Figure 1 hand in the middle).

[0072] The user's input may include various types of external inputs, such as a part of the user's body, light, heat, or pressure.

[0073] In one embodiment, the user's input is shown as being applied with the user's hand in the foreground.

[0074] However, the inventive concept is not limited thereto.

[0075] The user's input may be provided in various forms, and the display apparatus 1000 may detect the user's input applied to a side surface or a rear surface of the display apparatus 1000 according to the structure of the display apparatus 1000 .

[0076] Reference Figure 1 and Figure 2 , the display device 1000 may include a cover window WU, a housing HM, a display panel DP, and an optical element ES.

[0077] In one embodiment, the cover window WU and the housing HM may be combined to form an appearance of the display device 1000 .

[0078] The cover window WU may include an insulating panel.

[0079] For example, the cover window WU may be made of glass, plastic, or a combination thereof.

[0080] The front surface of the cover window WU may define the front surface of the display device 1000 .

[0081] The transmission area TA may be an optically transparent area.

[0082] For example, the transmission area TA may have a visible light transmittance (light transmittance) of about 90% or more.

[0083] The blocking area BA may define the shape of the transmission area TA.

[0084] The blocking area BA may be disposed adjacent to the transmission area TA, and may surround the transmission area TA.

[0085] The blocking area BA may have relatively low light transmittance compared to the transmission area TA.

[0086] The blocking area BA may include an opaque material that blocks light.

[0087] The barrier area BA may have a predetermined color.

[0088] The blocking area BA may be defined by a bezel layer provided separately from the transparent substrate defining the transmission area TA, or may be defined by an ink layer inserted into or colored in the transparent substrate.

[0089] The display panel DP may include display pixels PX (pixels PX) displaying an image and a driving unit 50 , and the display pixels PX are located in the display area DA.

[0090] The display panel DP may include a front surface including a display area DA and a peripheral area PA.

[0091] The display area DA may be a region including display pixels PX in which the pixels PX operate according to electrical signals to emit light.

[0092] In an embodiment, the display area DA may be a region including pixels PX and displaying an image, and may also be a region in which the touch sensors TS (see FIG. Figure 3 ) is an area positioned above the pixel PX in the third direction DR3 to detect an external input.

[0093] The transmission area TA of the cover window WU may at least partially overlap the display area DA of the display panel DP.

[0094] For example, the transmission area TA may overlap the entire surface of the display area DA or may overlap at least a portion of the display area DA.

[0095] Therefore, the user may observe an image through the transmissive area TA or provide an external input based on the image.

[0096] However, the inventive concept is not limited thereto.

[0097] For example, within the display area DA, an area in which an image is displayed and an area in which an external input is sensed may be separated from each other.

[0098] The peripheral area PA of the display panel DP may at least partially overlap the blocking area BA of the cover window WU.

[0099] The peripheral area PA may be an area covered by the barrier area BA.

[0100] The peripheral area PA is disposed adjacent to the display area DA and may surround the display area DA.

[0101] An image is not displayed in the peripheral area PA, and a driving circuit or driving wiring for driving the display area DA may be provided in the peripheral area PA.

[0102] The peripheral area PA may include a first peripheral area PA1 located outside the display area DA and a second peripheral area PA2 including the driving unit 50, the connection wiring, and the bending area.

[0103] exist Figure 2 In the embodiment of the present invention, the first peripheral area PA1 is located on three sides of the display area DA, and the second peripheral area PA2 is located on the remaining sides of the display area DA.

[0104] In one embodiment, the display panel DP may be assembled in a flat state having the display area DA and the peripheral area PA facing the cover window WU.

[0105] However, the inventive concept is not limited thereto.

[0106] A portion of the peripheral area PA of the display panel DP may be bent.

[0107] In this case, a portion of the peripheral area PA faces the rear surface of the display device 1000, so that the blocking area BA visible on the front surface of the display device 1000 can be reduced, and Figure 2 In the embodiment, the second peripheral area PA2 may be bent and positioned on the rear surface of the display area DA, and then assembled.

[0108] In addition, the display area DA of the display panel DP may include an assembly area EA, and specifically, may include a first assembly area EA1 and a second assembly area EA2.

[0109] The first assembly area EA1 and the second assembly area EA2 may be at least partially surrounded by the display area DA.

[0110] The first assembly area EA1 and the second assembly area EA2 are shown to be spaced apart from each other, but the configuration of the first assembly area EA1 and the second assembly area EA2 is not limited thereto and may be at least partially connected.

[0111] The first component area EA1 and the second component area EA2 may be areas in which components using infrared light, visible light, or / and sound are disposed.

[0112] In the display area DA, a plurality of light emitting diodes and a plurality of pixel circuit units that generate and transfer light emitting current are formed as a plurality of pixels PX.

[0113] Here, one light emitting diode and one pixel circuit unit are referred to as one pixel PX.

[0114] In the display area DA, one pixel circuit unit and one light emitting diode are formed in a one-to-one arrangement.

[0115] The first assembly area EA1 may include a transmission (transmission) portion through which light or / and sound may penetrate and a display portion including a plurality of pixels PX.

[0116] The transmission (transmission) portion is positioned between adjacent pixels PX, and is composed of a layer through which light or / and sound can penetrate.

[0117] The display unit may be formed to have one unit structure by combining a plurality of pixels PX, and a transmission (transmission) unit may be positioned between adjacent unit structures.

[0118] According to an embodiment, a layer that does not transmit light, such as a light blocking layer, may overlap the first component area EA1.

[0119] The second component area EA2 includes an area composed of a transparent layer that allows light to penetrate, no conductive layer or semiconductor layer is positioned, and a pixel defining layer such as a light blocking layer (including a light blocking material) is provided in the second component area EA2, and by including an opening in a region corresponding to a position corresponding to the second component area EA2, it is possible to have a structure that does not block light.

[0120] A portion of the second component area EA2 may include a portion in which pixels PX including light emitting diodes are formed to block light.

[0121] Reference Figure 3 In addition to the display area DA including the display pixels PX, the display panel DP may further include a touch sensor TS.

[0122] The display panel DP including the pixels PX can be Figure 2 ) is visually recognized by a user from the outside, and the pixel PX is a component for generating an image.

[0123] In addition, the touch sensor TS may be positioned above the pixel PX and may detect an external input applied from the outside.

[0124] The touch sensor TS can detect the touch signal provided to the cover window WU (see Figure 2 ) external input.

[0125] Again, refer to Figure 2 , the second peripheral area PA2 may include a bent portion.

[0126] The display area DA and the first peripheral area PA1 may have a flat surface substantially parallel to a plane defined by the first direction DR1 and the second direction DR2, and the second peripheral area PA2 may be bent. One side of the second peripheral area PA2 may extend from the flat surface. The second peripheral area PA2 may have a flat surface, a bent surface, and a flat surface sequentially disposed along the second direction DR2.

[0127] As a result, at least a portion of the second peripheral area PA2 may be bent and assembled to be positioned at the rear side of the display area DA.

[0128] When assembled, at least a portion of the second peripheral area PA2 overlaps the display area DA in a plan view, and thus the blocking area BA of the display device 1000 may be reduced.

[0129] However, the inventive concept is not limited thereto.

[0130] For example, the second peripheral area PA2 may not be bent.

[0131] The driving unit 50 may be mounted on the second peripheral area PA2, and may be mounted on the bent surface or on one of both sides of the bent surface.

[0132] The driving unit 50 may be provided in the form of a chip.

[0133] The driving unit 50 may be electrically connected to the display area DA to transmit an electrical signal to the display area DA.

[0134] For example, the driving unit 50 may provide data signals to the pixels PX disposed in the display area DA.

[0135] Alternatively, the driving unit 50 may include a touch driving circuit and may be electrically connected to the touch sensor TS provided in the display area DA (see FIG. Figure 3 ).

[0136] Meanwhile, the driving unit 50 may include various circuits other than the above-mentioned circuits, or may be designed to provide various electrical signals to the display area DA.

[0137] Meanwhile, the display device 1000 may have a pad part at an end of the second peripheral area PA2 and may be electrically connected to a flexible printed circuit board (FPCB) including a driving chip through the pad part.

[0138] Here, the driving chip positioned on the flexible printed circuit board may include various driving circuits for driving the display device 1000 or a connector for supplying power.

[0139] According to an embodiment, a rigid printed circuit board (PCB) may be used instead of a flexible printed circuit board.

[0140] The optical element ES may be disposed under the display panel DP.

[0141] The optical element ES may include a first optical element ES1 overlapping the first component area EA1 and a second optical element ES2 overlapping the second component area EA2.

[0142] The first optical element ES1 may use infrared light. In this case, a layer through which light is not transmitted, such as a light blocking layer, may overlap the first component area EA1.

[0143] The first optical element ES1 may be an electronic element using light and / or sound.

[0144] For example, the first optical element ES1 can be a sensor that receives and uses light (such as an infrared sensor), a sensor that outputs and detects light or sound to measure distance or recognize fingerprints, or a small lamp that outputs light, and the first optical element ES1 can be a speaker that outputs sound, etc.

[0145] In the case of an electronic component using light, light of various wavelength bands such as visible light, infrared light, and ultraviolet light can be used.

[0146] The second optical element ES2 may include at least one of a camera, an infrared (IR) camera, a dot projector, an IR illuminator, and a time-of-flight sensor (ToF sensor).

[0147] Reference Figure 3 , the display device 1000 may include a display panel DP, a power module PM, a first electronic module EM1 and a second electronic module EM2.

[0148] The display panel DP, the power module PM, the first electronic module EM1 and the second electronic module EM2 may be electrically connected to each other.

[0149] Figure 3 The display pixels PX and the touch sensors TS positioned in the display area DA are shown among the multiple components of the display panel DP.

[0150] The power module PM may supply power required for overall operations of the display apparatus 1000 .

[0151] The power module PM may include a conventional battery module.

[0152] The first electronic module EM1 and the second electronic module EM2 may include various functional modules for operating the display device 1000 .

[0153] The first electronic module EM1 may be directly mounted on a motherboard electrically connected to the display panel DP, or may be mounted on a separate board and electrically connected to the motherboard through a connector (not shown).

[0154] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and / or an external interface IF.

[0155] Some modules may not be mounted on the main board, and may be electrically connected to the main board through a flexible printed circuit board connected thereto.

[0156] The control module CM may control the overall operation of the display apparatus 1000 .

[0157] The control module CM may be a microprocessor.

[0158] For example, the control module CM activates or deactivates the display panel DP.

[0159] The control module CM may control other modules such as the image input module IIM or the audio input module AIM based on the touch signal received from the display panel DP.

[0160] The wireless communication module TM may send / receive radio signals to / from other terminals using Bluetooth or Wi-Fi lines.

[0161] The wireless communication module TM may send / receive voice signals using a general communication line.

[0162] The wireless communication module TM includes a transmitter TM1 for modulating and transmitting a signal to be transmitted and a receiver TM2 for demodulating a received signal.

[0163] The image input module IIM may process the image signal and convert it into image data that may be displayed on the display panel DP.

[0164] The audio input module AIM may receive an external sound signal through a microphone in a recording mode or a voice recognition mode, etc. and convert it into electrical voice data.

[0165] The external interface IF may be used as an interface to connect to an external charger, a wired / wireless data port, and a card slot (eg, a memory card slot, a Subscriber Identity Module (SIM) / User Identity Module (UIM) card slot), and the like.

[0166] As in Figure 1 and Figure 2 In the embodiment, the second electronic module EM2 may include an audio output module AOM, a light emitting module LM, a light receiving module LRM and a camera module CMM, and at least some of these modules may be located on the back side of the display panel DP as an optical element ES.

[0167] The optical element ES may include a light emitting module LM, a light receiving module LRM, and a camera module CMM.

[0168] In addition, the second electronic module EM2 may be directly mounted on the main board, or mounted on a separate board and electrically connected to the display panel DP through a connector (not shown), or the second electronic module EM2 may be electrically connected to the first electronic module EM1.

[0169] The audio output module AOM may convert audio data received from the audio input module AIM or audio data stored in the memory MM and output the converted audio data to the outside.

[0170] The light emitting module LM may generate and output light.

[0171] The light emitting module LM can output infrared rays (infrared light).

[0172] For example, the light emitting module LM may include a light emitting diode element.

[0173] For example, the light receiving module LRM may detect infrared rays.

[0174] When infrared rays of a predetermined level or more are detected, the light receiving module LRM may be activated.

[0175] The light receiving module LRM may include a complementary metal oxide semiconductor (CMOS) sensor.

[0176] After the infrared light generated by the light emitting module LM is output, the infrared light is reflected by an external object (eg, a finger or face of a user), and the reflected infrared light may be incident to the light receiving module LRM.

[0177] The camera module CMM may capture external images.

[0178] In one embodiment, the optical element ES may additionally include a light detection sensor or a heat detection sensor.

[0179] The optical element ES may detect an external object received through the front surface or provide a sound signal such as voice to the outside through the front surface.

[0180] Furthermore, the optical element ES may include a plurality of elements and is not limited to one embodiment.

[0181] Again, refer to Figure 2 , the housing HM can be coupled to the cover window WU.

[0182] A cover window WU may be provided on the front surface of the housing HM.

[0183] The housing HM may be coupled to the cover window WU to provide a predetermined accommodation space.

[0184] The display panel DP and the optical element ES may be accommodated in a predetermined accommodation space provided between the housing HM and the cover window WU.

[0185] The housing HM may include a material having relatively high rigidity.

[0186] For example, the housing HM may include a plurality of frames and / or panels made of glass, plastic, metal, or a combination thereof.

[0187] The housing HM may stably protect components of the display device 1000 accommodated in the internal space from external impact.

[0188] In the following, reference will be made to Figure 4 A structure of a display device 1000 according to another embodiment is described.

[0189] Figure 4 is a perspective view schematically showing a light emitting display device according to another embodiment.

[0190] Description of the same configuration as the above-described components will be omitted.

[0191] Figure 4 A foldable display device having a structure in which a display device (light-emitting display device) 1000 is folded by a folding axis FAX is shown.

[0192] Reference Figure 4 In one embodiment, the display device 1000 may be a foldable display device.

[0193] The display device 1000 may be folded outward or inward with respect to the folding axis FAX.

[0194] When folded outwardly with respect to the folding axis FAX, the display surface of the display device 1000 is positioned on the outside in the third direction DR3 so that images can be displayed in two directions.

[0195] When folded inwardly with respect to the folding axis FAX, the display surface may not be visually recognized from the outside.

[0196] In one embodiment, the display device 1000 may include a display area DA, an assembly area EA, and a peripheral area PA.

[0197] The display area DA may be divided into a 1-1th display area DA1-1, a 1-2nd display area DA1-2, and a folding area FA.

[0198] The first display area DA1-1 and the second display area DA1-2 may be located on the left and the right, respectively, based on the folding axis FAX (or centered on the folding axis FAX). The folding area FA may be located between the first display area DA1-1 and the second display area DA1-2.

[0199] In this case, when folded outwardly with respect to the folding axis FAX, the 1-1th display area DA1-1 and the 1-2nd display area DA1-2 are located on both sides in the third direction DR3, and images can be displayed in both directions.

[0200] In addition, when folded inwardly with respect to the folding axis FAX, the 1-1th display area DA1-1 and the 1-2nd display area DA1-2 may not be visually recognized from the outside.

[0201] Figure 5 is a plan view showing an enlarged portion of a light emitting display device according to an embodiment.

[0202] Figure 5 A portion of a light emitting display panel DP of a light emitting display device according to an embodiment is shown and is illustrated using a display panel for a mobile phone.

[0203] The light emitting display panel (display panel) DP has a display area DA positioned at the front, and may include an assembly area EA at the front. Specifically, the light emitting display panel DP may include a first assembly area EA1 and a second assembly area EA2.

[0204] In addition, Figure 5 In the embodiment of the present invention, the first component area EA1 is positioned adjacent to the second component area EA2.

[0205] exist Figure 5 In the embodiment of the present invention, the first component area EA1 is positioned to the left of the second component area EA2.

[0206] The location and number of the first assembly areas EA1 may vary depending on the embodiment.

[0207] exist Figure 5In the embodiment, the second optical element ES2 (see Figure 2 ) may be a camera, and the first optical element ES1 (see Figure 2 ) can be an optical sensor.

[0208] In the display area DA, a plurality of light emitting diodes and a plurality of pixel circuit units that generate and transfer light emitting current are formed as a plurality of pixels PX.

[0209] Here, one light emitting diode and one pixel circuit unit are referred to as one pixel PX.

[0210] In the display area DA, one pixel circuit unit and one light emitting diode are formed in a one-to-one arrangement.

[0211] The display area DA is also referred to as a “normal display area”.

[0212] although Figure 5 The structure of the light-emitting display panel DP below the cutting line is not shown in FIG. 1 , but the display area DA may be located below the cutting line.

[0213] The first component area EA1 is composed of only a transparent layer through which light can pass, has no conductive layer or semiconductor layer, has a light-transmitting area in the lower panel layer, and has a pixel-defining layer in the upper panel layer (see FIG. Fig. 22 The pixel defining layer 380 in the first component area EA1 may be a light blocking layer (refer to Fig. 22 The light blocking layer 220 in Fig. 22 An opening (hereinafter referred to as an additional opening) is formed in the color filter 230 in the image processing apparatus so as not to block light.

[0214] Meanwhile, even if the light transmission area is located in the lower panel layer, if there is no corresponding opening in the upper panel layer, it may be the display area DA instead of the first assembly area EA1.

[0215] Meanwhile, when the first optical element ES1 corresponding to the first component area EA1 uses infrared rays instead of visible light, the first component area EA1 may overlap the light blocking layer 220 that blocks the visible light.

[0216] The light emitting display panel DP according to the embodiment may be mainly divided into a lower panel layer and an upper panel layer.

[0217] The lower panel layer is a portion where the light emitting diodes constituting the pixels and the pixel circuit units are located, and may even include an encapsulation layer covering the lower panel layer (see Fig. 22 The encapsulation layer 400 in FIG.

[0218] That is, the lower panel layer includes an anode, a pixel defining layer (see Fig. 22 The pixel defining layer 380 in the embodiment of the present invention), the light emitting layer (see Fig. 22 The light-emitting layer EML in the substrate (see Fig. 22 The spacer of the substrate 110) (see Fig. 22 The spacer 385 in the functional layer (see Fig. 22 Functional layer FL in the cathode (see Fig. 22 The cathode in the structure is a cathode layer, an insulating layer between the substrate and the anode, a semiconductor layer and a conductive layer.

[0219] On the other hand, the upper panel layer is a portion located on top of the lower panel layer, and the upper panel layer includes a sensing insulating layer (see Fig. 22 The sensing insulating layers 501, 510 and 511 in FIG. 5 and the plurality of sensing electrodes capable of detecting touch (refer to FIG. 5 ) Fig. 22 The sensing electrodes 540 and 541 in FIG. 5 ) may include a light blocking layer (see FIG. Fig. 22 The light blocking layer 220 in Fig. 22 The color filter layer 230 in Fig. 22 The planarization layer 550 in FIG.

[0220] At the same time, Figures 7 to 22 The structure of the lower panel layer of the display area DA is reviewed.

[0221] although Figure 5 Not shown in the figure, the peripheral area may also be positioned outside the display area DA.

[0222] In addition, although Figure 5 A display panel for a mobile phone is shown, but the present embodiment can be applied to any display panel in which an optical element can be positioned on the rear surface of the display panel, or a flexible display device.

[0223] In the case of a foldable display device among the flexible display devices, the positions of the second assembly area EA2 and the first assembly area EA1 may be formed at the same Figure 5 The location is different from the location.

[0224] In the following, reference will be made to Figure 6 A circuit structure (pixel structure) of a pixel positioned on a lower panel layer of the light-emitting display panel DP is described in detail.

[0225] The following pixel structure may be a pixel structure of the display area DA, the first component area EA1 and / or the second component area EA2.

[0226] Figure 6is a circuit diagram of one pixel included in the light emitting display device according to the embodiment.

[0227] One pixel PX according to the embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to various wirings 127, 128, 151, 152, 153, 155, 171, 172, and 741, a storage capacitor Cst, a boosting capacitor C boost and light emitting diodes LEDs.

[0228] Here, the transistor and the capacitor except the light emitting diode LED constitute a pixel circuit unit.

[0229] According to an embodiment, the boost capacitor C can be omitted boost .

[0230] A plurality of wirings 127 , 128 , 151 , 152 , 153 , 155 , 171 , 172 , and 741 are connected to one pixel PX.

[0231] The plurality of wirings 127 , 128 , 151 , 152 , 153 , 155 , 171 , 172 and 741 include a first initialization voltage line 127 , a second initialization voltage line 128 , a first scan line 151 , a second scan line 152 , an initialization control line 153 , a light emission control line 155 , a data line 171 , a driving voltage line 172 and a common voltage line 741 .

[0232] The first scan line 151 is connected to a scan driving unit (not shown) to transmit a first scan signal GW to the second transistor T2 and the seventh transistor T7.

[0233] A voltage having a polarity opposite to that of the voltage applied to the first scan line 151 may be applied to the second scan line 152 simultaneously with the signal of the first scan line 151 .

[0234] For example, when a voltage of a negative polarity is applied to the first scan line 151 , a voltage of a positive polarity may be applied to the second scan line 152 .

[0235] The second scan line 152 transmits the second scan signal GC to the third transistor T3.

[0236] The initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4.

[0237] The light emitting control line 155 transmits the emission control signal EM to the fifth transistor T5 and the sixth transistor T6 .

[0238] The data line 171 is a wiring that transmits a data voltage DATA generated by a data driving unit (not shown), and thus, a size of a light emitting current transmitted to the light emitting diode LED is changed so that the light emitting diode LED emits light according to the light emitting current.

[0239] The driving voltage line 172 applies a driving voltage ELVDD.

[0240] The first initialization voltage line 127 transmits a first initialization voltage Vinit, and the second initialization voltage line 128 transmits a second initialization voltage Avinit.

[0241] The common voltage line 741 applies the common voltage ELVSS to the cathode of the light emitting diode LED.

[0242] In the present embodiment, the voltage applied to the driving voltage line 172 , the first and second initialization voltage lines 127 and 128 , and the common voltage line 741 may be a constant voltage.

[0243] The driving transistor T1 (also referred to as a first transistor) is a p-type transistor, and has a silicon semiconductor as a semiconductor layer.

[0244] The transistor adjusts the amount of light emitting current output to the anode of the light emitting diode LED according to the level of the voltage of the gate electrode of the driving transistor T1 (ie, the voltage stored in the storage capacitor Cst).

[0245] Since the brightness of the light emitting diode LED is adjusted according to the magnitude of the light emitting current output to the anode of the light emitting diode LED, the light emitting brightness of the light emitting diode LED can be adjusted according to the data voltage DATA applied to the pixel PX.

[0246] To this end, the first electrode of the driving transistor T1 receives the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5 .

[0247] The first electrode of the driving transistor T1 is also connected to the second electrode of the second transistor T2 to receive the data voltage DATA.

[0248] Meanwhile, the second electrode of the driving transistor T1 outputs a light emitting current to the light emitting diode LED, and is connected to the anode of the light emitting diode LED via the sixth transistor T6 (also referred to as an output control transistor).

[0249] The second electrode of the driving transistor T1 is also connected to the third transistor T3 to transfer the data voltage DATA applied to the first electrode to the third transistor T3.

[0250] Meanwhile, the gate electrode of the driving transistor T1 is connected to one electrode (hereinafter referred to as a 'second storage electrode') of the storage capacitor Cst.

[0251] Therefore, according to the voltage stored in the storage capacitor Cst, the voltage of the gate electrode of the driving transistor T1 changes, and the emission current output from the driving transistor T1 changes accordingly.

[0252] The storage capacitor Cst serves to keep the voltage of the gate electrode of the driving transistor T1 constant for one frame.

[0253] Meanwhile, the gate electrode of the driving transistor T1 may be connected to the third transistor T3 so that the data voltage DATA applied to the first electrode of the driving transistor T1 is transmitted to the gate electrode of the driving transistor T1 through the third transistor T3 .

[0254] Meanwhile, the gate electrode of the driving transistor T1 may also be connected to the fourth transistor T4 to be initialized by receiving the first initialization voltage Vinit.

[0255] The second transistor T2 is a p-type transistor, and has a silicon semiconductor as a semiconductor layer.

[0256] The second transistor T2 is a transistor that transmits the data voltage DATA to the first electrode of the driving transistor T1.

[0257] The gate electrode of the second transistor T2 is connected to the first scan line 151 and the boosting capacitor C boost An electrode (hereinafter referred to as the "lower boosting electrode").

[0258] A first electrode of the second transistor T2 is connected to the data line 171 .

[0259] The second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1.

[0260] When the second transistor T2 is turned on in response to the negative voltage (voltage of negative polarity) of the first scan signal GW transmitted through the first scan line 151, the data voltage DATA transmitted through the data line 171 is transmitted to the first electrode of the driving transistor T1, and the data voltage DATA is finally transmitted to the gate electrode of the driving transistor T1 and stored in the storage capacitor Cst.

[0261] The transistor T3 is an n-type transistor, and has an oxide semiconductor as a semiconductor layer.

[0262] The third transistor T3 is electrically connected to the second electrode of the driving transistor T1 and the gate electrode of the driving transistor T1 .

[0263] As a result, the data voltage DATA is compensated by the threshold voltage of the driving transistor T1 and is then stored in the second storage electrode of the storage capacitor Cst.

[0264] A gate electrode of the third transistor T3 is connected to the second scan line 152 , and a first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1 .

[0265] The second electrode of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the boosting capacitor Cst. boost another electrode (hereinafter referred to as the "upper boosting electrode").

[0266] The third transistor T3 is turned on in response to a voltage of positive polarity among the plurality of second scanning signals GC transmitted through the second scanning line 152, and the gate electrode of the driving transistor T1 and the second electrode of the driving transistor T1 are electrically connected (the driving transistor T1 is connected in a diode manner), and the voltage applied to the gate electrode of the driving transistor T1 is transmitted to the second storage electrode of the storage capacitor Cst and stored in the storage capacitor Cst.

[0267] The voltage stored in the storage capacitor Cst is the voltage of the gate electrode of the driving transistor T1 when the driving transistor T1 is turned off, so that the threshold voltage (Vth) of the driving transistor T1 is stored in a compensated state.

[0268] The transistor T4 is an n-type transistor, and has an oxide semiconductor as a semiconductor layer.

[0269] The fourth transistor T4 is used to initialize the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst.

[0270] A gate electrode of the fourth transistor T4 is connected to the initialization control line 153 , and a first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127 .

[0271] The second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the boosting capacitor Cst. boost The upper boost electrode.

[0272] The fourth transistor T4 is turned on in response to a voltage of a positive polarity among a plurality of initialization control signals GI transmitted through the initialization control line 153. The first initialization voltage Vinit is applied to the gate electrode of the driving transistor T1, the second storage electrode of the storage capacitor Cst, and the boosting capacitor C boostThe upper boosting electrode of the driving transistor T1 is initialized to initialize the gate electrode of the driving transistor T1, the second storage electrode of the storage capacitor Cst and the boosting capacitor C boost The upper boost electrode.

[0273] The fifth transistor T5 and the sixth transistor T6 are p-type transistors and have a silicon semiconductor as a semiconductor layer.

[0274] The fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1 .

[0275] A gate electrode of the fifth transistor T5 is connected to the light emission control line 155 , a first electrode of the fifth transistor T5 is connected to the driving voltage line 172 , and a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T1 .

[0276] The sixth transistor T6 is used to transmit the light emitting current output from the driving transistor T1 to the light emitting diode LED.

[0277] A gate electrode of the sixth transistor T6 is connected to the light emitting control line 155 , a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1 , and a second electrode of the sixth transistor T6 is connected to the anode of the light emitting diode LED.

[0278] The seventh transistor T7 is a p-type transistor or an n-type transistor and may have a silicon semiconductor or an oxide semiconductor as a semiconductor layer. Figure 6 In the embodiment of FIG. 5 , the seventh transistor T7 is a p-type transistor and includes a silicon semiconductor.

[0279] The seventh transistor T7 is used to initialize the anode of the light emitting diode LED.

[0280] A gate electrode of the seventh transistor T7 is connected to the first scan line 151 , a first electrode of the seventh transistor T7 is connected to the anode of the light emitting diode LED, and a second electrode of the seventh transistor T7 is connected to the second initialization voltage line 128 .

[0281] Here, the gate electrode of the seventh transistor T7 is connected to the first scan line 151 of the previous pixel PX and the same first scan line 151 as the gate electrode of the second transistor T2 belonging to the same pixel PX, but can be connected to the same first scan line 151 as the gate electrode of the second transistor T2 of the previous pixel PX.

[0282] When the seventh transistor T7 is turned on by the negative voltage of the first scan line 151, the second initialization voltage AVinit is applied to the anode of the light emitting diode LED to initialize it.

[0283] Meanwhile, the gate electrode of the seventh transistor T7 may be connected to a separate bypass control line through which the bypass signal GB is transmitted, and may be controlled by a wiring separate from the first scan line 151 .

[0284] In addition, according to an embodiment, the second initialization voltage line 128 to which the second initialization voltage Avinit is applied may be the same as the first initialization voltage line 127 to which the first initialization voltage Vinit is applied.

[0285] It has been described that one pixel PX includes seven transistors T1 to T7 and two capacitors (storage capacitor Cst and boost capacitor Cst). boost ), but the present invention is not limited thereto. The boost capacitor C may be omitted. boost .

[0286] Furthermore, although the third and fourth transistors are formed of n-type transistors, only one of the third and fourth transistors may be formed of an n-type transistor, or the other transistor (eg, the seventh transistor) may be formed of an n-type transistor.

[0287] In the above, it has been Figure 6 It is recalled that the display area DA (see Figure 5 ) is a circuit structure of a pixel PX.

[0288] In the following, we will Figures 7 to 22 Description is formed in Figure 5 Detailed planar structure and layered structure of a pixel PX in at least one location in the display area DA, the first component area EA1, and the second component area EA2.

[0289] First, in Figures 7 to 21 In this paper, we will mainly study planar structures.

[0290] Figures 7 to 21 is a diagram specifically illustrating a structure of each layer according to a manufacturing order of a lower panel layer in a light-emitting display device according to an embodiment.

[0291] Reference Figure 7 , the metal layer BML is positioned on the substrate (see Fig. 22 On the substrate 110).

[0292] The substrate 110 may include a rigid material such as glass that does not bend, or may include a flexible material such as plastic or polyimide that can bend.

[0293] In the case of flexible substrates, such as Fig. 22 As shown in , a double-layer structure of a polyimide layer and a barrier layer formed of an inorganic insulating material thereon can be formed.

[0294] The metal layer BML includes a plurality of expansions (extended portions) BML1 and a connection portion BML2 connecting the plurality of expansions BML1 to one another.

[0295] In a plan view, the expansion portion BML1 of the metal layer BML may be formed at a position adjacent to the driving transistor T1 (see FIG. Figure 6 ) channel (refer to Figure 8 At the position where the channel 1132) overlaps.

[0296] The metal layer BML is also referred to as a lower shielding layer, and may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), and titanium (Ti), and may additionally include amorphous silicon, and may be composed of a single layer or a multilayer.

[0297] Reference Fig. 22 , a buffer layer 111 covering the substrate 110 and the metal layer BML is positioned on the substrate 110 .

[0298] The buffer layer 111 is used to prevent impurity elements from penetrating into the first semiconductor layer 130 (see Figure 8 ) and may include silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0299] On the buffer layer 111, as Figure 8 As shown in FIG. 1 , a first semiconductor layer 130 formed of a silicon semiconductor (eg, a polycrystalline semiconductor) is located.

[0300] The first semiconductor layer 130 includes a driving transistor T1 (see Figure 6 )'s channel 1132, the first region 1131 and the second region 1133.

[0301] The first semiconductor layer 130 can not only form the channel 1132 of the driving transistor T1, but also form the second transistor T2 (see Figure 6 ) of the channel 1134, the fifth transistor T5 (see Figure 6 ) of the channel 1135 and the sixth transistor T6 (see Figure 6 ) of the channel 1136 and the seventh transistor T7 (see Figure 6 ) channel 1137, and each channel has a first region and a second region having conductive properties by plasma treatment or doping on both sides of the channel of each transistor, and the first region and the second region are used as a first electrode and a second electrode.

[0302] The channel 1132 of the driving transistor T1 may be bent to have a U-shape in a plan view.

[0303] However, the shape of the channel 1132 of the driving transistor T1 is not limited thereto and may be variously changed.

[0304] For example, the channel 1132 of the driving transistor T1 may be bent in various other shapes such as an S-shape or may be formed in a rod shape.

[0305] The first region 1131 and the second region 1133 of the driving transistor T1 may be positioned at both sides of the channel 1132 of the driving transistor T1 .

[0306] The first region 1131 and the second region 1133 located in the first semiconductor layer have conductive characteristics through plasma treatment or doping, and function as first and second electrodes of the driving transistor T1 .

[0307] In a portion of the first semiconductor layer 130 extending downward from the first region 1131 of the driving transistor T1 , a channel 1134 of the second transistor T2 and first and second regions of the second transistor T2 disposed on both sides of the channel 1134 are located.

[0308] The channel 1135 of the fifth transistor T5 and the first and second regions positioned at both sides of the channel 1135 are located in a portion extending upward from the first region 1131 of the driving transistor T1 .

[0309] The channel 1136 of the sixth transistor T6 and the first and second regions positioned at both sides of the channel 1136 are located in a portion extending upward from the second region 1133 of the driving transistor T1 .

[0310] The first and second regions located at both sides of the channel 1137 of the seventh transistor T7 and the channel 1137 of the seventh transistor T7 bend through the channel 1136 of the sixth transistor T6 and further extend upward.

[0311] Further references Fig. 22 , a first gate insulating layer 141 is formed on the first semiconductor layer 130 including the channel 1132 of the driving transistor T1 , the first region 1131 , and the second region 1133 .

[0312] The first gate insulating layer 141 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0313] Reference Fig. 9 , including the driving transistor T1 (see Figure 6 ) of the first gate conductive layer GAT1 of the gate electrode 1151 (see Fig. 22) can be positioned on the first gate insulating layer 141 (see Fig. 22 )superior.

[0314] The first gate conductive layer GAT1 may include not only the gate electrode 1151 of the driving transistor T1, but also the gate electrode 1152 of the second transistor T2 (see FIG. Figure 6 ) of the gate electrode, the fifth transistor T5 (see Figure 6 ) of the gate electrode, the sixth transistor T6 (see Figure 6 ) and the gate electrode of the seventh transistor T7 (see Figure 6 ) of the gate electrode.

[0315] The gate electrode 1151 of the driving transistor T1 may overlap the channel 1132 of the driving transistor T1 .

[0316] The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1 .

[0317] The first gate conductive layer GAT1 may further include a first scan line 151 and a light emitting control line 155 .

[0318] The first scan line 151 and the light emitting control line 155 may extend substantially in a horizontal direction (hereinafter, also referred to as a first direction DR1 ).

[0319] The first scan line 151 may be connected to the gate electrode of the second transistor T2 , and the first scan line 151 may be integrally formed with the gate electrode of the second transistor T2 .

[0320] The first scan line 151 may be connected to a gate electrode of a seventh transistor T7 of a next pixel or may be integrally formed with the gate electrode of the seventh transistor T7 of the next pixel.

[0321] The first scan line 151 may include a lower boosting electrode 151a having an extended width and connected to an upper boosting electrode 3138t (see FIG. 1 ) to be described later. Fig.11 ) overlap to form a boost capacitor C boost (See Figure 6 ).

[0322] Meanwhile, the light emission control line 155 may be connected to the gate electrodes of the fifth and sixth transistors T5 and T6 , and the light emission control line 155 , the fifth and sixth transistors T5 and T6 , and the gate electrode of the sixth transistor T6 may be integrally formed.

[0323] The first gate conductive layer GAT1 may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a multi-layer.

[0324] After forming the first gate conductive layer GAT1 including the gate electrode 1151 of the driving transistor T1 , plasma treatment or a doping process is performed so that the first semiconductor layer 130 exposed by and not covered by the first gate conductive layer GAT1 may become conductive.

[0325] In other words, the first semiconductor layer 130 covered by the first gate conductive layer GAT1 may form a channel without being conductive, and a portion of the first semiconductor layer 130 not covered by the first gate conductive layer GAT1 may have the same characteristics as a conductive layer.

[0326] The transistor including the doping portion may have p-type transistor characteristics, and the driving transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be p-type transistors.

[0327] Further references Fig. 22 , the second gate insulating layer 142 may be positioned on the first gate conductive layer GAT1 including the gate electrode 1151 of the driving transistor T1 and the first gate insulating layer 141 .

[0328] The second gate insulating layer 142 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0329] Reference Fig.10 , including the storage capacitor Cst (see Figure 6 ) of the second gate conductive layer GAT2 (see Fig. 22 ), including a third transistor T3 (see Figure 6 ) of the lower shielding layer 3155 of the lower second scanning line 152a, the fourth transistor T4 (see Figure 6 ) and the shielding layer SHL may be located at the second gate insulating layer 142 (see Fig. 22 )superior.

[0330] Here, the lower shielding layers 3155 and 4155 may be respectively located under the channel of the third transistor T3 and the channel of the fourth transistor T4 and may shield light or electromagnetic interference provided to the channels from below.

[0331] In addition, the shielding layer SHL overlaps a portion of the first semiconductor layer 130 in a plan view.

[0332] Here, in a plan view, a portion of the first semiconductor layer 130 that overlaps with the shielding layer SHL may be located at a position where the sixth transistor T6 (see FIG. Figure 6 ) of the channel 1136 and the seventh transistor T7 (see Figure 6 ) between channels 1137.

[0333] Therefore, the portion of the first semiconductor layer 130 overlapping with the shielding layer SHL in a plan view corresponds to the second region (or second electrode) of the sixth transistor T6 or the first region (or first electrode) of the seventh transistor T7, or is located between the second region (or second electrode) of the sixth transistor T6 and the first region (or first electrode) of the seventh transistor T7.

[0334] Since the portion of the first semiconductor layer 130 overlapping the shielding layer SHL in a plan view is located on a path where the output current output from the driving transistor T1 is transmitted to the anode of the light emitting diode LED, it is also referred to as an output current passing region of the first semiconductor layer 130 .

[0335] The first storage electrode 1153 overlaps the gate electrode 1151 of the driving transistor T1 to form a storage capacitor Cst.

[0336] An opening 1152 is formed in the first storage electrode 1153 of the storage capacitor Cst.

[0337] The opening 1152 of the first storage electrode 1153 of the storage capacitor Cst may overlap the gate electrode 1151 of the driving transistor T1 .

[0338] The plurality of first storage electrodes 1153 may be connected to adjacent first storage electrodes 1153 in a horizontal direction (first direction DR1 ).

[0339] According to an embodiment, all of the plurality of first storage electrodes 1153 adjacent to each other in the horizontal direction (first direction DR1) may be connected, but in Fig.10 In the embodiment of FIG. 1 , only two adjacent first storage electrodes 1153 are shown as a structure connected to each other.

[0340] The lower second scan line 152a extends substantially in the horizontal direction (first direction DR1), and may include a lower shielding layer 3155 of the third transistor T3 as an extension portion of the lower second scan line 152a.

[0341] Here, the lower shielding layer 3155 of the third transistor T3 may be connected to the channel of the third transistor T3 (see Fig.11 channel 3137) and the gate electrode (see Fig.12 Overlapping the gate electrode 3151).

[0342] Meanwhile, the lower shielding layer 4155 of the fourth transistor T4 is formed into an island structure, and the lower shielding layer 4155 of the fourth transistor T4 may be aligned with the channel of the fourth transistor T4 (see Fig.11 channel 4137) and the gate electrode (see Fig.12 The gate electrode 4151) overlaps.

[0343] The shielding layer SHL is disposed at both sides of the lower shielding layer 4155 of the fourth transistor T4 in the first direction DR1 , and shields both sides of the lower shielding layer 4155 in the first direction DR1 .

[0344] The second gate conductive layer GAT2 may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a multilayer.

[0345] Further references Fig. 22 , the first interlayer insulating layer 161 may be positioned on the second gate conductive layer GAT2 including the first storage electrode 1153 of the storage capacitor Cst, the lower shielding layer 3155 of the third transistor T3, and the lower shielding layer 4155 of the fourth transistor T4.

[0346] The first interlayer insulating layer 161 may include an inorganic insulating layer including silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) etc., and according to an embodiment, the inorganic insulating layer can be formed to have a considerable thickness.

[0347] Reference Fig.11 , an oxide semiconductor layer (which includes a third transistor T3 (see Figure 6 ) of the channel 3137, the first region 3136 and the second region 3138, and the fourth transistor T4 (see Figure 6 ) of the channel 4137, the first region 4136 and the second region 4138) may be located in the first interlayer insulating layer 161 (see Fig. 22 ) above.

[0348] In addition, the oxide semiconductor layer may include a boost capacitor C boost The upper boost electrode 3138t.

[0349] The channel 3137 , the first region 3136 , and the second region 3138 of the third transistor T3 and the channel 4137 , the first region 4136 , and the second region 4138 of the fourth transistor T4 may be connected to each other to form a whole.

[0350] The first region 3136 and the second region 3138 of the third transistor T3 are positioned at both sides of the channel 3137 of the third transistor T3 , and the first region 4136 and the second region 4138 of the fourth transistor T4 are positioned at both sides of the channel 4137 of the fourth transistor T4 .

[0351] The second region 3138 of the third transistor T3 is connected to the second region 4138 of the fourth transistor T4.

[0352] The channel 3137 of the third transistor T3 overlaps the lower shield layer 3155 , and the channel 4137 of the fourth transistor T4 overlaps the lower shield layer 4155 .

[0353] Boost capacitor C boost The upper boosting electrode 3138t has an expansion portion positioned between the second region 3138 of the third transistor T3 and the second region 4138 of the fourth transistor T4.

[0354] Boost capacitor C boost The upper boost electrode 3138t and the boost capacitor C boost The lower boosting electrode 151a positioned on the first gate conductive layer GAT1 overlaps to form a boosting capacitor C boost .

[0355] Further references Fig. 22 The third gate insulating layer 143 may be positioned at a portion including the channel 3137 of the third transistor T3, the first region 3136 and the second region 3138, the channel 4137 of the fourth transistor T4, the first region 4136 and the second region 4138, and the boost capacitor C boost On the oxide semiconductor layer of the upper boosting electrode 3138t.

[0356] The third gate insulating layer 143 may be positioned on the entire surfaces of the oxide semiconductor layer and the first interlayer insulating layer 161 .

[0357] Therefore, the third gate insulating layer 143 is formed on the channel 3137, the first region 3136 and the second region 3138 of the third transistor T3, the channel 4137, the first region 4136 and the second region 4138 of the fourth transistor T4, and may cover the boosting capacitor C boost The top surface and side surfaces of the upper boosting electrode 3138t.

[0358] However, the present embodiment is not limited thereto, and the third gate insulating layer 143 may not be located on the entire surfaces of the oxide semiconductor layer and the first interlayer insulating layer 161 .

[0359] For example, the third gate insulating layer 143 may overlap with the channel 3137 and may not overlap with the first region 3136 and the second region 3138 of the third transistor T3 .

[0360] In addition, the third gate insulating layer 143 may overlap with the channel 4137 and may not overlap with the first region 4136 and the second region 4138 of the fourth transistor T4.

[0361] The third gate insulating layer 143 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0362] Reference Fig.12 , including a third transistor T3 (see Figure 6 ) of the gate electrode 3151 and the fourth transistor T4 (see Figure 6 ) of the gate electrode 4151 of the third gate conductive layer GAT3 (see Fig. 22 ) can be positioned on the third gate insulating layer 143 (see Fig. 22 )superior.

[0363] The gate electrode 3151 of the third transistor T3 may overlap with the channel 3137 of the third transistor T3 .

[0364] The gate electrode 3151 of the third transistor T3 may overlap with the lower shielding layer 3155 of the third transistor T3 .

[0365] The gate electrode 4151 of the fourth transistor T4 may overlap with the channel 4137 of the fourth transistor T4.

[0366] The gate electrode 4151 of the fourth transistor T4 may overlap with the lower shielding layer 4155 of the fourth transistor T4.

[0367] The third gate conductive layer GAT3 may further include an upper second scan line 152 b and an initialization control line 153 .

[0368] The upper second scan line 152 b and the initialization control line 153 may extend substantially in the horizontal direction (the first direction DR1 ).

[0369] The upper second scan line 152b includes a gate electrode 3151 of the third transistor T3 and forms the second scan line 152 together with the lower second scan line 152a (see Figure 6 ).

[0370] The initialization control line 153 includes a gate electrode 4151 of the fourth transistor T4 and is electrically connected to the second gate conductive layer GAT2 through the opening OP1 (see FIG. 1 ). Fig. 22 )'s lower shielding layer 4155.

[0371] Here, the opening OP1 is formed in the third gate insulating layer 143 (see Fig. 22 ) and the first interlayer insulating layer 161 (see Fig. 22 ) to expose a portion of the lower shielding layer 4155 of the second gate conductive layer GAT2, and the portion of the lower shielding layer 4155 is electrically connected to the initialization control line 153 located thereover.

[0372] In addition, the third gate conductive layer GAT3 may further include a first initialization voltage line 127 .

[0373] The first initialization voltage line 127 may extend substantially in a horizontal direction (first direction DR1) and apply a first initialization voltage Vinit (see FIG. Figure 6 ).

[0374] The initialization control line 153 may overlap the shielding layer SHL and the lower shielding layer 4155 positioned in the second gate conductive layer GAT2 .

[0375] First, the role of the shield layer SHL overlapping the initialization control line 153 will be described below.

[0376] Even if the initialization control signal GI (see Figure 6 ) changes, the fluctuation of the initialization control signal GI does not affect the output current passing area overlapping with the initialization control line 153 and the shielding layer SHL in the plan view.

[0377] As a result, the output current delivered to the light emitting diode LED has no influence on the change of the initialization control signal GI, and the display quality can be improved.

[0378] Meanwhile, the lower shield layer 4155 overlapping the initialization control line 153 functions as follows.

[0379] Reference Fig.10 and Fig.12 , the second scan line 152 (see Figure 6 ) has a double-layer structure including a lower second scan line 152a and an upper second scan line 152b, but the initialization control line 153 only includes Fig.12 The initialization control line 153 in the embodiment has a single-layer structure.

[0380] As a result, due to the third transistor T3 (see Figure 6) is vertically applied in the cross-sectional view by the second scanning signal GC (see Figure 6 ) control, so the third transistor T3 can be more strongly controlled and properly operated, and leakage current can be avoided.

[0381] On the contrary, since the initialization control line 153 has a single-layer structure, the fourth transistor T4 (see FIG. 14 ) connected to the initialization control line 153 is larger than the third transistor T3. Figure 6 ) may be weakly controlled, which may cause leakage current.

[0382] However, in the present inventive concept, although the initialization control line 153 has a single-layer structure, the lower shielding layer 4155 is positioned below the channel 4137 of the fourth transistor T4, and the lower shielding layer 4155 is connected to the initialization control line 153 through the opening OP1, and the channel 4137 of the fourth transistor T4 can be subjected to the initialization control signal GI (see FIG. Figure 6 ) influence, the fourth transistor T4 is also more strongly controlled so that the fourth transistor T4 operates properly and leakage current can be avoided.

[0383] As a result, each pixel can be appropriately controlled to provide improved display quality.

[0384] The third gate conductive layer GAT3 may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a multilayer.

[0385] In forming the third gate conductive layer GAT3 including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4 (see Fig. 22 ), the portion of the oxide semiconductor layer not covered by the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4 may have enhanced conductivity through a plasma treatment or a doping process. The oxide semiconductor layer covered by the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4 may not have enhanced conductivity and may form a channel of the third transistor T3 and a channel of the fourth transistor T4.

[0386] The channel 3137 of the third transistor T3 may be positioned below the gate electrode 3151 to overlap with the gate electrode 3151 .

[0387] The first region 3136 and the second region 3138 of the third transistor T3 may not overlap with the gate electrode 3151 .

[0388] The channel 4137 of the fourth transistor T4 may be positioned under the gate electrode 4151 to overlap with the gate electrode 4151 .

[0389] The first region 4136 and the second region 4138 of the fourth transistor T4 may not overlap with the gate electrode 4151 .

[0390] The upper boosting electrode 3138t may not overlap with the third gate conductive layer GAT3.

[0391] A transistor including an oxide semiconductor layer can have characteristics of an n-type transistor.

[0392] Further references Fig. 22 , the second interlayer insulating layer 162 may be positioned on the third gate conductive layer GAT3 including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4.

[0393] The second interlayer insulating layer 162 may have a single-layer or multi-layer structure.

[0394] The second interlayer insulating layer 162 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) of an inorganic insulating material, and according to an embodiment, may include an organic material.

[0395] Reference Fig.13 and Fig. 22 , the opening OP2 is formed in the second interlayer insulating layer 162 (see Fig. 22 ) and / or positioned in an insulating layer therebelow to expose a conductive layer or a semiconductor layer therebelow.

[0396] At least some of the multiple openings OP2 can be formed in at least one of the second interlayer insulating layer 162, the third gate insulating layer 143, the first interlayer insulating layer 161, the second gate insulating layer 142 and the first gate insulating layer 141, the opening OP2 can expose the first semiconductor layer 130, the first gate conductive layer GAT1 or the second gate conductive layer GAT2, and another opening OP2 can be formed in the second interlayer insulating layer 162 to expose the third gate conductive layer GAT3, and yet another opening OP2 can be formed in the insulating layer 143 to expose the oxide semiconductor layer or the third gate conductive layer GAT3.

[0397] According to an embodiment, the entire opening OP2 may be formed through at least two processes using at least two masks.

[0398] Some detailed structures of the openings OP2 are as follows.

[0399] One of the plurality of openings OP2 may be connected to the driving transistor T1 (see Figure 6 ) overlaps at least a portion of the gate electrode 1151 and may also be formed in the third gate insulating layer 143, the first interlayer insulating layer 161 and the second gate insulating layer 142.

[0400] In this case, one of the plurality of openings OP2 may overlap with the opening 1152 of the first storage electrode 1153 and may be positioned inside the opening 1152 of the first storage electrode 1153 .

[0401] One of the plurality of openings OP2 may be at least partially connected to the boost capacitor C boost (See Figure 6 ) overlaps and may also be formed in the third gate insulating layer 143.

[0402] Another one of the plurality of openings OP2 overlaps with at least a portion of the second region 1133 of the driving transistor T1 , and the third gate insulating layer 143 , the first interlayer insulating layer 161 , the second gate insulating layer 142 , and the first gate insulating layer 141 .

[0403] Another one of the plurality of openings OP2 overlaps with at least a portion of the first region 3136 of the third transistor T3 and may be formed in the third gate insulating layer 143 .

[0404] Reference Fig.14 and Fig.15 The first data conductive layer including the first connection electrode 1175 and the second connection electrode 3175 may be positioned on the second interlayer insulating layer 162 (see Fig. 22 )superior.

[0405] Fig.14 is a plan view showing only the first data conductive layer and the opening OP2. Fig.15 is a plan view showing all layers disposed below the first data conductive layer.

[0406] The first connection electrode 1175 can be connected to the driving transistor T1 (see Figure 6 ) overlaps with the gate electrode 1151.

[0407] The first connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the opening OP2 and the opening 1152 of the first storage electrode 1153 .

[0408] The first connection electrode 1175 can be connected to the boost capacitor C boost (See Figure 6 )overlapping.

[0409] The first connection electrode 1175 may be connected to the boosting capacitor C through the opening OP2. boostThe upper boost electrode 3138t.

[0410] Therefore, the gate electrode 1151 of the driving transistor T1 and the boost capacitor C boost The upper boosting electrode 3138t may be connected via the first connection electrode 1175 .

[0411] The gate electrode 1151 of the driving transistor T1 is connected to the third transistor T3 through the first connecting electrode 1175 (see Figure 6 ) of the second region 3138 and the fourth transistor T4 (see Figure 6 )’s second zone 4138.

[0412] The second connection electrode 3175 may overlap the second region 1133 of the driving transistor T1 .

[0413] The second connection electrode 3175 may be connected to the second region 1133 of the driving transistor T1 through the opening OP2 .

[0414] The second connection electrode 3175 may overlap the first region 3136 of the third transistor T3 .

[0415] The second connection electrode 3175 may be connected to the first region 3136 of the third transistor T3 through the opening OP2 .

[0416] Therefore, the second region 1133 of the driving transistor T1 and the first region 3136 of the third transistor T3 may be connected through the second connection electrode 3175 .

[0417] The first data conductive layer may further include a second initialization voltage line 128 .

[0418] The second initialization voltage line 128 extends substantially in the horizontal direction (first direction DR1 ), and may have a portion bent in the vertical direction (second direction DR2 ).

[0419] The second initialization voltage line 128 is electrically connected to the seventh transistor T7 (see FIG. Figure 6 ) of the first semiconductor layer 130 adjacent to the channel 1137, and the second initialization voltage AVinit (see Figure 6 ) is transmitted to the seventh transistor T7.

[0420] The first data conductive layer may further include connection parts 127CM and 171CM, a first anode connection electrode ACM1, and a driving voltage connection electrode FL-SD1.

[0421] The connecting portion 127CM is connected to the first initialization voltage line 127 of the second gate conductive layer GAT2 through the opening OP2, and is connected to the first region 4136 of the oxide semiconductor layer through the opening OP2, so that the first initialization voltage Vinit (see FIG. 1 ) flowing through the first initialization voltage line 127 is Figure 6 ) is transmitted to the fourth transistor T4 of the oxide semiconductor layer.

[0422] The connection portion 171CM is electrically connected to a portion of the first semiconductor layer 130 disposed adjacent to the channel 1134 of the second transistor T2 through the opening OP2 , and is electrically connected to the second transistor T2 .

[0423] The first anode connection electrode ACM1 is electrically connected to the sixth transistor T6 (see FIG. 1 ) in the first semiconductor layer 130 through the opening OP2. Figure 6 )'s channel 1136 is adjacently disposed with respect to an output current passing region so as to be electrically connected to the sixth transistor T6.

[0424] The driving voltage connection electrode FL-SD1 is electrically connected to the fifth transistor T5 (see FIG. 1 ) in the first semiconductor layer 130 through the opening OP2. Figure 6 )'s channel 1135 and the first storage electrode 1153, and is electrically connected to the fifth transistor T5.

[0425] The driving voltage connection electrode FL-SD1 is also connected to the shielding layer SHL through the opening OP2.

[0426] The first data conductive layer may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may be composed of a single layer or a multi-layer.

[0427] Further references Fig. 22 , the first organic layer 181 may be positioned on the first data conductive layer including the first connection electrode 1175 and the second connection electrode 3175 .

[0428] The first organic layer 181 may be an organic insulating layer including an organic material, and the organic material includes at least one material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0429] Reference Fig.16 , Fig.17 and Fig. 22 , a lower organic layer opening OP3 (opening OP3 ) is positioned in the first organic layer 181 .

[0430] The second data conductive layer including the connection part 171CM2 , the driving voltage line 172 , and the second anode connection electrode ACM2 may be positioned on the first organic layer 181 .

[0431] The second organic layer 182 is positioned on the second data conductive layer, and an opening OP4 is formed in the second organic layer 182 .

[0432] Fig.16 is a plan view showing only the second data conductive layer and the openings OP3 and OP4. Fig.17 is a plan view showing all elements disposed below the second data conductive layer.

[0433] exist Fig.16 and Fig.17 The opening OP3 is arranged at Fig.14 The connection portion 171CM, the first anode connection electrode ACM1, and the driving voltage connection electrode FL-SD1 in the first data conductive layer in the embodiment of the present invention are formed to expose them.

[0434] The second data conductive layer may include a connection part 171CM2 , a driving voltage line 172 , and a second anode connection electrode ACM2 .

[0435] The driving voltage line 172 extends substantially in a vertical direction (second direction DR2 ), and may include a plurality of opening regions.

[0436] The connection portion 171CM2 and the second anode connection electrode ACM2 may be positioned within a plurality of opening regions of the driving voltage line 172 .

[0437] The driving voltage line 172 is electrically connected to the fifth transistor T5 through the driving voltage connection electrode FL-SD1 of the first data conductive layer through the opening OP3 (see FIG. Figure 6 ), the first storage electrode 1153 and the shielding layer SHL.

[0438] As a result, the driving voltage ELVDD (see Figure 6 ) is applied to one electrode of the fifth transistor T5, the first storage electrode 1153, and the shielding layer SHL.

[0439] The connection portion 171CM2 is connected to the first data conductive layer and the second transistor T2 through the opening OP3 (see FIG. Figure 6 ) connection part 171CM.

[0440] In addition, the second anode connection electrode ACM2 is electrically connected to the first anode connection electrode ACM1 of the first data conductive layer through the opening OP3, and is electrically connected to the sixth transistor T6 (see FIG. 2 ). Figure 6 ).

[0441] Reference Fig.16 , the driving voltage line 172 may further include an opening portion FL-SD2 disposed in a region corresponding to a portion in which the second anode connection electrode ACM2 and the connection portion 171CM2 are formed.

[0442] The opening portion FL-SD2 is formed wide enough to flatten the anode electrode located at the upper portion.

[0443] In a plan view, the opening portion FL-SD2 positioned on the second data conductive layer may be aligned with the anode electrode of the light emitting diode (refer to Fig. 20 The anode Anode) overlaps.

[0444] The structure of the lower portion of the anode including the opening portion FL-SD2 as described above and the organic layers 181, 182 and 183 has a flattening characteristic so that the light reflected from the anode does not propagate asymmetrically, and as a result, the display quality can be improved by reducing the reflective color band caused by the color diffusion (color separation) phenomenon caused by the reflected light.

[0445] The second data conductive layer may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may be composed of a single layer or a multi-layer.

[0446] Reference Fig. 22 , the second organic layer 182 is positioned on the second data conductive layer.

[0447] The second organic layer 182 may be an organic insulating layer, and may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0448] According to an embodiment, the third organic layer 183 may be omitted.

[0449] Reference Fig.16 , Fig.17 and Fig. 22 , an opening OP4 is formed in the second organic layer 182 .

[0450] exist Fig.18 , Fig.19 and Fig. 22 In the embodiment, a third data conductive layer including the data lines 171 and 171 - 1 and the third anode connection electrode ACM3 may be positioned on the second organic layer 182 .

[0451] The third organic layer 183 is positioned on the third data conductive layer, and an opening OP5 for connecting an anode (anode connection opening OP5 ) is formed in the third organic layer 183 .

[0452] The third anode connection electrode ACM3 is electrically connected to the anode through the anode connection opening OP5.

[0453] Fig.18 2 is a plan view showing only the third data conductive layer and the anode connection opening OP5 . Fig.19is a plan view showing all elements disposed under the third data conductive layer.

[0454] Reference Fig.18 and Fig.19 The opening OP4 overlaps with the connection portion 171CM2 and the second anode connection electrode ACM2 in the second data conductive layer and exposes the connection portion 171CM2 and the second anode connection electrode ACM2 in the second data conductive layer.

[0455] The third data conductive layer may include data lines 171 and 171 - 1 and a third anode connection electrode ACM3 .

[0456] The data lines 171 and 171 - 1 may extend substantially in a vertical direction (second direction DR2 ).

[0457] The data lines 171 and 171-1 are connected to the connection portion 171CM2 of the second data conductive layer and the first data conductive layer and the second transistor T2 (see FIG. 1 ) through the opening OP4. Figure 6 ) connection part 171CM.

[0458] Here, the data lines 171 and 171 - 1 may each have a structure connected to the second transistors T2 included in two adjacent pixels in the second direction DR2 .

[0459] The third anode connection electrode ACM3 is electrically connected to the second anode connection electrode ACM2 of the second data conductive layer through the opening OP4, and is thus electrically connected to the sixth transistor T6 (see FIG. 2 ). Figure 6 ).

[0460] The third data conductive layer may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may be composed of a single layer or a multi-layer.

[0461] Reference Fig. 22 , the third organic layer 183 is positioned on the third data conductive layer.

[0462] The third organic layer 183 may be an organic insulating layer, and may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0463] The opening OP5 is formed in the third organic layer 183, and the anode and the third anode connection electrode ACM3 (see Fig.18 ) are electrically connected to each other through the opening OP5.

[0464] The first organic layer 181 , the second organic layer 182 , and the third organic layer 183 are formed by stacking organic layers and then planarizing the surface using a slit mask, so that the anode thereon can be more planarly formed.

[0465] A process using such a slit mask may be formed every time each organic layer is stacked, and some organic layers may not be subjected to a process of being exposed to light through a slit mark even after being stacked.

[0466] Furthermore, the slit marks used at this time have patterns parallel to the first direction DR1 (ie, horizontal direction), so they can more easily remove steps of the organic layer occurring due to vertical direction (second direction DR2) patterns formed on the first data conductive layer and / or the second data conductive layer.

[0467] Reference Fig. 20 and Fig.21 , an anode Anode is formed on the third organic layer 183 .

[0468] The anode Anode may further include an extension portion Anode-e to form a contact hole to receive current from the pixel circuit through the anode connection opening OP5.

[0469] exist Fig. 20 , Fig.21 and Fig. 22 In the embodiment, the pixel defining layer 380 is positioned on the anode Anode, and the openings OPr, OPg, and OPb of the pixel defining layer 380 are connected to the anode Anode.

[0470] The openings OPr, OPg, OPb formed by the pixel defining layer 380 may include a red opening OPr overlapping an anode of a red LED, a green opening OPg overlapping an anode of a green LED, and a blue opening OPb overlapping an anode of a blue LED.

[0471] The extension portion Anode-e of the anode Anode is not exposed through the openings OPr, OPg, and OPb of the pixel defining layer 380 , and has a structure overlapping the pixel defining layer 380 in a plan view.

[0472] As a result, the anode connection opening OP5 also has a structure overlapping the pixel defining layer 380 in a plan view.

[0473] According to an embodiment, the pixel defining layer 380 may have an opaque property, and in this case, may include a black pigment.

[0474] exist Fig.21 A planar structure in which the above structures are completely stacked is shown in FIG.

[0475] Further references Fig. 22Since the opening OP5 for connecting the anode does not overlap with the openings OPr, OPg, and OPb of the pixel defining layer 380 and the opening OPBM of the light blocking layer 220 in a plan view, the pixel defining layer 380 and the light blocking layer 220 overlap each other.

[0476] In addition, some of the openings OP3 located in the first organic layer 181 overlap with the openings OPBM of the light blocking layer 220 in a plan view, and the remaining openings OP3 overlap with the light blocking layer 220 in a plan view.

[0477] Meanwhile, in a plan view, all the openings OP3 may overlap the pixel defining layer 380 .

[0478] In addition, in the present embodiment, the openings OPr, OPg, OPb of the pixel defining layer 380 are formed in a region corresponding to the opening portion FL-SD2 of the second data conductive layer under the anode Anode, and thus the anode Anode may be formed to be flat.

[0479] As a result, external light is not reflected asymmetrically, so that the user cannot recognize the reflective color band.

[0480] As a result, degradation of display quality due to reflection of external light can be eliminated.

[0481] Based on the plane structure described above, Fig. 22 The overall cross-sectional structure of the light emitting display device is explained.

[0482] Fig. 22 is a cross-sectional view of a light emitting display device according to an embodiment.

[0483] Fig. 22 In addition to the stack structure of the display area DA, the stack structure of the first assembly area EA1 is also shown.

[0484] The light emitting display device may include a lower panel layer and an upper panel layer, and the lower panel layer is a portion where a light emitting diode constituting a pixel and a pixel circuit unit are located, and may even include an encapsulation layer 400 covering them.

[0485] Here, the pixel circuit unit includes a second organic layer 182 and a third organic layer 183. A light emitting diode is disposed above the third organic layer 183.

[0486] The structure positioned above the encapsulation layer 400 may correspond to an upper panel layer.

[0487] According to an embodiment, the third organic layer 183 may not be included.

[0488] Reference Fig. 22 , the metal layer BML is positioned on the substrate 110 .

[0489] The substrate 110 may include a rigid material such as glass that does not bend, or may include a flexible material such as plastic or polyimide that can bend.

[0490] In the case of flexible substrates, such as Fig. 22 As shown in , a double-layer structure of a polyimide layer and a barrier layer formed of an inorganic insulating material thereon can be formed.

[0491] In a plan view, the metal layer BML may be formed between the driving transistor T1 (see Figure 6 )'s channel overlaps, and is also referred to as the lower shield layer.

[0492] The metal layer BML may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti).

[0493] A buffer layer 111 covering the substrate 110 and the metal layer BML is positioned on the substrate 110 .

[0494] The buffer layer 111 may prevent impurity elements from penetrating into the first semiconductor layer ACT (P-Si), and may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and other inorganic insulating layers.

[0495] A first semiconductor layer ACT1 (P—Si) formed of a silicon semiconductor (eg, a polycrystalline semiconductor (P—Si)) is positioned on the buffer layer 111 .

[0496] The first semiconductor layer ACT1 (P-Si) includes a channel of the polycrystalline transistor LTPS TFT including the driving transistor T1 and first and second regions positioned at both sides of the channel.

[0497] Here, the polycrystalline transistor LTPS TFT may include not only the driving transistor T1 but also Figure 6 The second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7.

[0498] In addition, both sides of the channel of the first semiconductor layer ACT1 (P-Si) may have conductivity through plasma treatment or doping to serve as a first electrode and a second electrode of the polycrystalline transistor LTPS TFT.

[0499] The first gate insulating layer 141 may be positioned on the first semiconductor layer ACT1 (P—Si).

[0500] The first gate insulating layer 141 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0501] A first gate conductive layer GAT1 including a gate electrode of the polycrystalline transistor LTPS TFT may be positioned on the first gate insulating layer 141 .

[0502] A first scan line or a light emission control line may be formed in the first gate conductive layer GAT1 except for the gate electrode of the polycrystalline transistor LTPS TFT.

[0503] The first gate conductive layer GAT1 may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a multi-layer.

[0504] After forming the first gate conductive layer GAT1, plasma treatment or a doping process may be performed to give conductivity to the exposed region of the first semiconductor layer.

[0505] That is, the first semiconductor layer ACT1 (P—Si) covered by the first gate conductive layer GAT1 has no conductivity, and the first semiconductor layer ACT1 (P—Si) not covered by the first gate conductive layer GAT1 may have conductivity similar to that of a conductive material.

[0506] The second gate insulating layer 142 may be positioned on the first gate conductive layer GAT1 and the first gate insulating layer 141 .

[0507] The second gate insulating layer 142 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0508] The second gate conductive layer GAT2 (which includes the storage capacitor Cst (see Figure 6 ) and a lower shielding layer GAT2 (BML) of the oxide transistor Oxide TFT may be located over the second gate insulating layer 142 .

[0509] The lower shielding layer GAT2 (BML) of the oxide TFT is located under each channel of the oxide TFT, and it can play a role of shielding light or electromagnetic interference provided from the bottom to the channel.

[0510] Meanwhile, the first electrode GAT2 (Cst) of the storage capacitor Cst overlaps the first gate conductive layer GAT1 including the gate electrode of the driving transistor T1 to form the storage capacitor Cst.

[0511] According to an embodiment, the second gate conductive layer GAT2 may further include a scan line, a control line, or a voltage line.

[0512] The second gate conductive layer GAT2 may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a multilayer.

[0513] The first interlayer insulating layer 161 may be positioned on the second gate conductive layer GAT2 .

[0514] The first interlayer insulating layer 161 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) or the like, and depending on the embodiment, the inorganic insulating material can be formed thickly.

[0515] An oxide semiconductor layer ACT2 (IGZO) (also referred to as a second semiconductor layer) including a channel of an oxide transistor Oxide TFT, a first region, and a second region may be located on the first interlayer insulating layer 161 .

[0516] The third gate insulating layer 143 may be positioned on the oxide semiconductor layer ACT2 (IGZO).

[0517] The third gate insulating layer 143 may be positioned on the entire surfaces of the oxide semiconductor layer ACT2 (IGZO) and the first interlayer insulating layer 161 .

[0518] The third gate insulating layer 143 may include silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) of an inorganic insulating layer.

[0519] A third gate conductive layer GAT3 including a gate electrode of the oxide transistor Oxide TFT may be positioned on the third gate insulating layer 143 .

[0520] The third gate conductive layer GAT3 including the gate electrode of the oxide transistor Oxide TFT may overlap the channel.

[0521] The third gate conductive layer GAT3 may further include a scan line or a control line.

[0522] The third gate conductive layer GAT3 may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a multilayer.

[0523] The second interlayer insulating layer 162 may be positioned on the third gate conductive layer GAT3 .

[0524] The second interlayer insulating layer 162 may have a single-layer or multi-layer structure.

[0525] The second interlayer insulating layer 162 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) of an inorganic insulating material, and according to an embodiment, may include an organic material.

[0526] Over the second interlayer insulating layer 162 , there may be a first data conductive layer including a connection electrode capable of being connected to each of first and second regions of the polycrystalline transistor LTPS TFT and the oxide transistor Oxide TFT.

[0527] The first data conductive layer may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may be composed of a single layer or a multi-layer.

[0528] The first organic layer 181 may be positioned on the first data conductive layer.

[0529] The first organic layer 181 may be an organic insulating layer containing an organic material, and the organic material may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0530] The second data conductive layer including the second anode connection electrode ACM2 may be positioned on the first organic layer 181 .

[0531] The second data conductive layer may include a driving voltage line.

[0532] The second data conductive layer may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may be composed of a single layer or a multi-layer.

[0533] The second organic layer 182 is positioned on the second data conductive layer, and an opening OP4 is formed in the second organic layer 182 .

[0534] The second organic layer 182 may be an organic insulating layer, and may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0535] A third data conductive layer including a third anode connection electrode ACM3 may be positioned on the second organic layer 182 .

[0536] The third data conductive layer may include a data line.

[0537] The second data conductive layer may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may be composed of a single layer or a multi-layer.

[0538] The third organic layer 183 is positioned on the third data conductive layer, and an opening OP5 for connecting an anode is formed in the third organic layer 183 .

[0539] The third anode connection electrode ACM3 is electrically connected to the anode Anode through the anode connection opening OP5.

[0540] The third organic layer 183 may be an organic insulating layer, and may include one or more materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0541] A pixel defining layer 380 covering at least a portion of the anode electrode Anode while having an opening OP exposing the anode electrode Anode may be positioned on the anode electrode Anode.

[0542] According to an embodiment, the pixel defining layer 380 may be a black pixel defining layer formed of a black organic material to prevent externally applied light from being reflected back to the outside, or may be formed of a transparent organic material.

[0543] Therefore, according to an embodiment, the pixel defining layer 380 may include a negative type black organic material and may include a black pigment.

[0544] The spacer 385 is positioned on the pixel defining layer 380 .

[0545] The spacer 385 may include a first portion 385 - 1 having a high height and a second portion 385 - 2 having a low height.

[0546] Unlike the pixel defining layer 380 , the spacer 385 may be formed of a transparent organic insulating material.

[0547] According to an embodiment, the spacer 385 may be formed of a positive type transparent organic material.

[0548] The functional layer FL and the cathode Cathode are sequentially formed on the anode Anode, the spacer 385, and the pixel defining layer 380, and in the display area DA and the first assembly area EA1. The functional layer FL and the cathode Cathode may be located in the entire area.

[0549] The light emitting layer EML is positioned between the functional layers FL, and the light emitting layer EML may be positioned only within the opening OP of the pixel defining layer 380 .

[0550] Hereinafter, the functional layer FL and the light emitting layer EML may be collectively referred to as an intermediate layer.

[0551] The functional layer FL may include at least one of an electron injection layer, an electron transport layer, a hole transport layer, and an auxiliary layer such as a hole injection layer, and the hole injection layer and the hole transport layer are disposed below the light emitting layer EML, and the electron transport layer and the electron injection layer may be located on the light emitting layer EML.

[0552] The encapsulation layer 400 is positioned on the cathode.

[0553] According to an embodiment, the encapsulation layer 400 includes at least one inorganic layer and at least one organic layer, and may have a triple-layer structure including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0554] The encapsulation layer 400 may serve to protect the light emitting layer EML from moisture or oxygen that may be introduced from the outside.

[0555] According to an embodiment, encapsulation layer 400 may include a structure in which an inorganic layer and an organic layer are sequentially stacked.

[0556] On the encapsulation layer 400 , sensing insulation layers 501 , 510 , and 511 and a plurality of sensing electrodes 540 and 541 for touch sensing are positioned.

[0557] exist Fig. 22 In the embodiment of FIG. 5 , two sensing electrodes 540 and 541 may be used to sense touch in a capacitive type.

[0558] Specifically, the first sensing insulating layer 501 is formed on the encapsulation layer 400 , and a plurality of sensing electrodes 540 and 541 are formed thereon.

[0559] The plurality of sensing electrodes 540 and 541 may be insulated with the second sensing insulating layer 510 interposed therebetween, and some of the sensing electrodes 540 and 541 may be electrically connected through openings located in the sensing insulating layer 510 .

[0560] Here, the sensing electrodes 540 and 541 include a metal or a metal alloy such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and may be composed of a single layer or a multilayer.

[0561] The third sensing insulating layer 511 is formed on the sensing electrode 540 .

[0562] The light blocking layer 220 and the color filter 230 are positioned on the sensing electrode 540 and the third sensing insulating layer 511 .

[0563] The light blocking layer 220 may be positioned to overlap the sensing electrodes 540 and 541 in a plan view, and may be positioned not to overlap the anode Anode in a plan view.

[0564] This is to prevent the anode electrode Anode capable of transmitting an image from being covered by the light blocking layer 220 and the sensing electrodes 540 and 541 .

[0565] The color filter 230 may be positioned on the third sensing insulating layer 511 and the light blocking layer 220 .

[0566] The color filter 230 includes a red color filter that transmits red light, a green color filter that transmits green light, and a blue color filter that transmits blue light.

[0567] Each color filter 230 may be positioned to overlap an anode Anode of a light emitting diode in a plan view.

[0568] Light emitted from the light emitting layer EML may be emitted while passing through the color filter and changing into a corresponding color.

[0569] The light blocking layer 220 may be positioned between each color filter 230 .

[0570] According to an embodiment, the color filter 230 may be replaced with a color conversion layer or may further include a color conversion layer.

[0571] The color conversion layer may include quantum dots.

[0572] In addition, according to an embodiment, a reflection control layer filling the opening OPBM of the light blocking layer 220 may be positioned instead of the color filter 230 .

[0573] The reflection control layer 235 may have a structure covering the light blocking layer 220, which will Fig.29 review.

[0574] A planarization layer 550 covering the color filter 230 may be positioned on the color filter 230 .

[0575] In this embodiment, the polarizer may not be attached to the top of the planarization layer 550 .

[0576] That is, a polarizing plate (polarizer) is attached to prevent external light from being reflected. In the present embodiment, the opening OPBM of the light blocking layer 220 is formed into a specific structure to reduce the reflection color band problem in which external light is asymmetrically reflected, so there is no need to include a polarizer. However, a polarizing plate may be attached to the planarization layer 550 to further reduce the light reflectivity.

[0577] At the same time, Fig. 22 , the cross-sectional structure of the first component area EA1 is also shown.

[0578] The first assembly area EA1 may be an area in the lower panel layer where the photo sensor area OPS is located, and the first assembly area EA1 may be an area where the pixel defining layer 380 , the light blocking layer 220 , and the color filter 230 are not formed.

[0579] According to an embodiment, the second component area EA2 (see Figure 5 ) may have a light transmission area with Fig. 22 The cross-sectional structure of the first component area EA1 is the same as the cross-sectional structure.

[0580] The first component area EA1 is composed only of a transparent layer so that light can penetrate the first component area EA1, no conductive layer or semiconductor layer is positioned, and the pixel defining layer 380, the light blocking layer 220 and the color filter 230 are not included, and an opening (hereinafter referred to as an additional opening) can be formed at a position corresponding to the light sensor area OPS to have a structure that does not block light.

[0581] Specifically, based on Fig. 22 , the stacking structure of the first assembly area EA1 according to the embodiment is as follows.

[0582] A buffer layer 111 as an inorganic insulating layer is positioned on the substrate 110 , and a first gate insulating layer 141 and a second gate insulating layer 142 as inorganic insulating layers are sequentially positioned thereon.

[0583] In addition, a first interlayer insulating layer 161 , a third gate insulating layer 143 , and a second interlayer insulating layer 162 , which are inorganic insulating layers, are sequentially stacked on the second gate insulating layer 142 .

[0584] Only the first organic layer 181 among the plurality of organic insulating layers is stacked on the second interlayer insulating layer 162 .

[0585] However, according to embodiments, the second organic layer 182 and the third organic layer 183 may be stacked on the first organic layer 181 .

[0586] The functional layer FL may be positioned on the third organic layer 183 , and the cathode Cathode may be positioned thereon.

[0587] The stack structure from the substrate 110 up to the cathode Cathode may correspond to the photo sensor region OPS.

[0588] The encapsulation layer 400 is positioned on the cathode, and the sensing insulating layers 501 , 510 , and 511 are sequentially positioned on the encapsulation layer 400 .

[0589] The encapsulation layer 400 may have a three-layer structure including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0590] In addition, all of the sensing insulating layers 501 , 510 , and 511 may be inorganic insulating layers.

[0591] Over the third sensing insulating layer 511 , additional openings of the light blocking layer 220 and the color filter 230 are positioned, and in the first assembly area EA1 , the light blocking layer 220 and the color filter 230 are not formed.

[0592] An additional opening is also located in the pixel defining layer 380 so that the pixel defining layer 380 is not formed in the first assembly area EA1.

[0593] The planarization layer 550 may be positioned on the third sensing insulation layer 511 in the first assembly area EA1 .

[0594] The first component area EA1 and the optical sensor area OPS do not include the metal layer BML, the first semiconductor layer ACT1 (P-Si), the first gate conductive layer GAT1, the second gate conductive layer GAT2, the oxide semiconductor layer ACT2 (IGZO), the third gate conductive layer GAT3, the first data conductive layer, the second data conductive layer, the third data conductive layer and the anode.

[0595] In addition, the light emitting layer EML and the sensing electrodes 540 and 541 are not formed.

[0596] In the first component area EA1 and the light sensor area OPS, additional openings are formed in the pixel defining layer 380, the light blocking layer 220, and the color filter 230 so that the pixel defining layer 380, the light blocking layer 220, and the color filter 230 may not be formed in the first component area EA1 and the light sensor area.

[0597] However, when the optical sensor uses a wavelength other than visible light (eg, a wavelength of infrared light), the light blocking layer 220 may be located in a region corresponding to the first component area EA1 and the optical sensor area OPS and located on the front side.

[0598] In the above, the overall structure of the light emitting display device and the pixel of the light emitting display device has been described in detail.

[0599] In the following, we will Fig.23 and Fig.24 The detailed study is located in the second gate conductive layer GAT2 (see Fig. 22 )The structure around the shielding layer SHL on and the function of the shielding layer SHL.

[0600] Fig.23 is a plan view showing the vicinity of an initialization control line in a light emitting display device according to an embodiment, and Fig.24 It is along Fig.23 A cross-sectional view taken along section line XXIV-XXIV'.

[0601] Fig.23 It is a reference Figures 7 to 21 The shielding layer SHL and an enlarged view of the surrounding structure of the shielding layer SHL among the multiple pixels described in detail include a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, an oxide semiconductor layer, a third gate conductive layer and a first data conductive layer.

[0602] Fig.24 is a cross-sectional view showing the overall stacked structure positioned above and below the shielding layer SHL.

[0603] The shielding layer SHL positioned on the second gate insulating layer is connected to the driving voltage connection electrode FL-SD1 positioned on the first data conductive layer through the opening OP2.

[0604] As reference Fig.16 and Fig.17 As shown in FIG. , the driving voltage is connected to the electrode FL-SD1 (see Fig.23 ) is connected to the driving voltage line 172 located in the second data conductive layer through the opening OP3, thereby transmitting the driving voltage ELVDD (see Figure 6 ).

[0605] Therefore, the driving voltage ELVDD is also transmitted to the shielding layer SHL.

[0606] The shielding layer SHL does not overlap with the first gate conductive layer in a plan view, and overlaps with the first semiconductor layer 130 (see FIG. Fig.15 )'s output current passes through the region and overlaps with the initialization control line 153 of the third gate conductive layer.

[0607] Here, the output current passing region of the first semiconductor layer 130 overlapping with the shielding layer SHL in a plan view is a portion of the first semiconductor layer 130, and refers to Fig.11 and Figure 6The output current passing region of the first semiconductor layer 130 may be a portion located between the channel 1136 of the sixth transistor T6 and the channel 1137 of the seventh transistor T7, and the output current passing region of the first semiconductor layer 130 may be a portion located between the second region (or second electrode) of the sixth transistor T6 and the first region (or first electrode) of the seventh transistor T7.

[0608] Reference Fig.24 In the cross-sectional view, the shielding layer SHL is positioned on the first semiconductor layer 130 (see Fig.15 ) output current passes through the initialization control line 153 between the region and the third gate conductive layer, and the driving voltage ELVDD (see Figure 6 ) is constantly applied to the shielding layer SHL, and the shielding layer SHL can play a shielding role so that the voltage change on one side is not transmitted to the other side.

[0609] Specifically, even if the initialization control signal GI applied to the initialization control line 153 changes, the output current passing region of the first semiconductor layer 130 located below the shielding layer SHL may not be affected by the initialization control signal GI (see FIG. Figure 6 )’s fluctuations.

[0610] The result is transmitted to the light emitting diode LED (see Figure 6 ) has no effect on the change of the initialization control signal GI, and can improve the display quality.

[0611] Reference Fig.23 Since the shielding layer SHL is formed on the second gate conductive layer in the present embodiment, the initialization control line 153 may not have a double-layer structure including the second gate conductive layer and the third gate conductive layer, but may have a single-layer structure including only the third gate conductive layer. Therefore, the fourth transistor T4 connected to the initialization control line 153 is relatively weakly controlled, and thus current leakage may occur.

[0612] However, in this embodiment, the lower shielding layer 4155 is formed as a fourth transistor T4 (see Figure 6 ) is formed in the second gate conductive layer below the channel 4137 and is connected to the initialization control line 153 through the opening OP1. The fourth transistor T4 is also strongly controlled so as to operate correctly and no current leakage occurs.

[0613] That is, since the lower shielding layer 4155 is also connected to the initialization control line 153 through the opening OP1 and receives the initialization control signal GI, the channel 4137 of the fourth transistor T4 is disposed between the lower shielding layer 4155 and the initialization control line 153 in the cross-sectional view. The initialization control signal GI is applied from the positioned initialization control line 153 and the lower shielding layer 4155, so that the fourth transistor T4 is more strongly controlled, so that the fourth transistor T4 operates correctly and current leakage may not occur.

[0614] As a result, each pixel can be appropriately controlled to provide improved display quality.

[0615] At the same time, in the following, reference will be made to Fig.25 and Fig.26 The structures of comparative examples are compared.

[0616] Fig.25 is a top view showing the vicinity of an initialization control line in a light-emitting display device according to a comparative example, and Fig.26 It is along Fig.25 A cross-sectional view taken along the section line XXVI-XXVI'.

[0617] Fig.25 is corresponding to Fig.23 A plan view of a comparative example, and Fig.26 It is along Fig.25 A cross-sectional view taken along the section line XXVI-XXVI'.

[0618] Reference Fig.25 In the comparative example, the initialization control line 153 has a double-layer structure with a gate insulating layer 142 positioned in the second gate insulating layer 142 (see Fig. 22 ) and the lower initialization control line 153a located on the third gate insulating layer 143 (see Fig. 22 ) on the upper initialization control line 153b.

[0619] Since the lower initialization control line 153a is formed on the second gate insulating layer 142, a separate shielding layer SHL is not formed (see Fig.24 ). A portion of the lower initialization control line 153a may be used as a lower shielding layer.

[0620] The biggest difference between the present embodiment and the comparative example is whether the shielding layer SHL is located between the output current passing region of the first semiconductor layer and the initialization control line.

[0621] Reference Fig.26 In the comparative example, due to the initialization control signal GI (see Figure 6) is applied to the lower initialization control line 153a, so when the initialization control signal GI changes, the first semiconductor layer 130 (see Fig.15 ) output current passes through the area not through the shield layer SHL (see Fig.24 ) shielding, and as a result, may be transmitted to the light emitting diode LED (see Figure 6 )’s output current quantity changes.

[0622] As a result, the brightness emitted by the light emitting diode LED may vary, resulting in degradation of display quality.

[0623] In contrast, in this embodiment, the shielding layer SHL is disposed on the initialization control line 153 (see Fig.25 ) and the output current passes between the regions.

[0624] Therefore, since the layer to which the initialization control signal GI is applied is located farther from the output current passing region of the first semiconductor layer 130 than in the comparative example, signal interference may be relatively small.

[0625] In addition, in this embodiment, the driving voltage ELVDD (see Figure 6 ) is located between the initialization control line 153 and the output current passing region of the first semiconductor layer 130, and the fluctuation of the initialization control signal GI does not affect the output current.

[0626] As a result, since the output current delivered to the light emitting diode LED is not affected by the fluctuation of the initialization control signal GI, the display quality can be improved.

[0627] In the following, we will Fig. 27 and Fig.28 The simulation results of the change of the output current according to the change of the initialization control signal GI are reviewed.

[0628] Fig. 27 and Fig.28 It is a view to compare and explain the difference in characteristics based on the comparative example and the embodiment.

[0629] first, Fig. 27 Shown in Fig.23 and Fig.24 Embodiments and Fig.25 and Fig.26 In the comparative example, when the initialization control signal GI (see Figure 6 ) when the voltage in the pixel increases. The peak values ​​of the output current I_Peak_R, I_Peak_G, and I_Peak_B are simulated in pixels displaying red (R), green (G), and blue (B).

[0630] exist Fig. 27 , ①③⑤ represent comparative examples, and ②④⑥ represent embodiments.

[0631] Reference Fig. 27 It can be seen that the fluctuation range of the peak value I_Peak_B of the output current of the blue pixel is not high overall, but in the comparative example, the peak value I_Peak_R of the output current of the red pixel and the peak value I_Peak_G of the output current of the green pixel can be confirmed to have a relatively large fluctuation range.

[0632] A light emitting diode receiving such an output current may gradually change to a normal brightness after emitting strong light, which deteriorates display quality.

[0633] In contrast, in the present embodiment, it can be confirmed that the fluctuation range of the peak values ​​I_Peak_R, I_Peak_G and I_Peak_B of the output current in all colors is not large, and it can also be confirmed that the fluctuation range of the peak value I_Peak_B of the output current of the blue pixel, the fluctuation range of the peak value I_Peak_R of the output current of the red pixel and the fluctuation range of the peak value I_Peak_G of the output current of the green pixel are almost the same.

[0634] In addition, since the range of changes is not large, it is difficult for users to recognize and detect it.

[0635] Therefore, in the present embodiment, it can be confirmed that the display quality is not deteriorated due to the fluctuation of the output current.

[0636] Fig.28 The above differences are shown in the table.

[0637] Fig.28 Comparative Example 1 and Comparative Example 2 are distinguished, wherein Comparative Example 1 corresponds to Fig.25 and Fig.26 , and Comparative Example 2 is a case where the shielding layer SHL is not formed in the present embodiment. Fig.23 and Fig.24 Examples in .

[0638] Reference Fig.28 , describes a parasitic capacitance between an output current of the first semiconductor layer 130 and an initialization control line 153 to which an initialization control signal GI is applied.

[0639] Comparing Comparative Examples 1 and 2, it can be seen that the parasitic capacitance of Comparative Example 2 is only about 44% and is reduced by about 56%.

[0640] However, it can be seen that the parasitic capacitance in the present embodiment is only about 21% of the parasitic capacitance of Comparative Example 1, which is reduced by about 79%.

[0641] Due to the difference in parasitic capacitance, the maximum variation values ​​of the peak values ​​I_Peak_R of the output current of the red pixel, the maximum variation values ​​of the peak values ​​I_Peak_G of the output current of the green pixel, and the maximum variation values ​​of the peak values ​​I_Peak_B of the output current of the blue pixel show that the variation values ​​are very small in this embodiment.

[0642] As a result, a change in the brightness of the light emitting diode that may occur in the comparative example does not occur in this example, and the display quality can be improved.

[0643] In the above, Fig. 22 As shown in FIG. 1 , an embodiment in which the color filter layer 230 is formed in the opening OPBM of the light blocking layer 220 is mainly reviewed.

[0644] More specifically, a red color filter, a blue color filter, and a green color filter may be formed in the openings OPBM corresponding to red, the openings OPBM corresponding to blue, and the openings OPBM corresponding to green of the light blocking layer 220, respectively.

[0645] However, a reflection control layer may be used instead of the color filter layer 230, and reference will be made to Fig.29 A stacked structure of an embodiment in which a reflection control layer 235 is applied instead of the color filter layer 230 is described.

[0646] Fig.29 is a cross-sectional view of a light emitting display device according to another embodiment.

[0647] Fig.29 is with Fig. 22 The corresponding cross-sectional view, and in the following, will focus on Fig. 22 The different parts are described.

[0648] The reflection control layer 235 may be disposed on the light blocking layer 220 .

[0649] The reflection control layer 235 may selectively absorb light having a partial band of wavelengths among light reflected inside the display device or light incident from outside the display device.

[0650] The reflection control layer 235 may fill the opening OPBM of the light blocking layer 220 .

[0651] For example, the reflection control layer 235 absorbs light having a first wavelength range of 490 nm to 505 nm and a second wavelength range of 585 nm to 600 nm, so that light transmittance in the first wavelength range and the second wavelength range of 40% or less may be provided.

[0652] The reflection control layer 235 can absorb the light from the light emitting diode LED (see Figure 6) emits light of wavelengths outside the red, green or blue emission wavelength range.

[0653] In this way, the reflection control layer 235 absorbs light of wavelengths that do not belong to the red, green or blue wavelength range emitted from the light emitting diode LED, thereby preventing or minimizing a reduction in the brightness of the display device and displaying an image at the same time, thereby preventing or minimizing a reduction in the luminous efficiency of the display device and improving visibility.

[0654] In one embodiment, the reflection control layer 235 may include an organic material layer including a dye, a pigment, or a combination thereof.

[0655] The reflection control layer 235 includes tetraazaporphyrin (TAP)-based compounds, porphyrin-based compounds, metal porphyrin-based compounds, oxazine-based compounds, as well as squarylium-based compounds, triarylmethane-based compounds, polymethine compounds, anthraquinone-based compounds, phthalocyanine-based compounds, azo-based compounds, perylene-based compounds, xanthene-based compounds, diimmonium-based compounds, dipyrromethene-based compounds, cyanine-based compounds and combinations thereof.

[0656] In one embodiment, the reflectivity measured in a specular component included (SCI) mode on the surface of the reflection control layer 235 may be 10% or less.

[0657] That is, the reflection control layer 235 may improve visibility by absorbing external light reflection of the display device.

[0658] In one embodiment, the reflection control layer 235 may have a transmittance of about 64% to about 72%.

[0659] The transmittance of the reflection control layer 235 may be adjusted according to the amount of the pigment and / or dye included in the reflection control layer 235 .

[0660] According to an embodiment, the reflection control layer 235 may not be located in the first element area EA1.

[0661] Furthermore, in the embodiment including the reflection control layer 235 , a cladding layer AL1 and a low reflection layer AL2 may be additionally formed between the cathode and the encapsulation layer 400 .

[0662] The cladding layer AL1 can be used to improve the luminous efficiency of the light emitting diode LED through the principle of constructive interference.

[0663] The cladding layer AL1 may include, for example, a material having a refractive index of 1.6 or higher with respect to light having a wavelength of 589 nm.

[0664] The coating layer AL1 may be an organic coating layer including an organic material, an inorganic coating layer including an inorganic material, or a composite coating layer including an organic material and an inorganic material.

[0665] For example, the coating layer AL1 may include a carbocyclic compound, a heterocyclic compound, an amine group-containing compound, a porphyrin derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or any combination thereof.

[0666] The carbocyclic compounds, heterocyclic compounds and amine group-containing compounds may be optionally substituted with substituents including O, N, S, Se, Si, F, Cl, Br, I or any combination thereof.

[0667] The low reflection layer AL2 may be disposed on the cladding layer AL1.

[0668] The low reflection layer AL2 may overlap the front surface of the substrate SUB.

[0669] The low reflection layer AL2 may include an inorganic material having low reflectivity, and in one embodiment may include a metal or a metal oxide.

[0670] When the low-reflection layer AL2 includes a metal such as ytterbium (Yb), bismuth (Bi), cobalt (Co), molybdenum (Mo), titanium (Ti), zirconium (Zr), aluminum (Al), chromium (Cr), niobium (Nb), platinum (Pt), tungsten (W), indium (In), tin (Sn), iron (Fe), nickel (Ni), tantalum (Ta), or manganese (Mn), the low-reflection layer AL2 may include zinc (Zn), germanium (Ge), silver (Ag), magnesium (Mg), gold (Au), copper (Cu), calcium (Ca), or a combination thereof.

[0671] In addition, when the low reflection layer AL2 includes a metal oxide, for example, SiO 2 、TiO 2 、ZrO 2 、 2 O 5 , HfO 2 、Al 2 O 3 , ZnO, Y 2 O 3 , BeO, MgO, PbO 2 , WO 3 、SiN x 、LiF、CaF 2 MgF 2 , CdS or a combination thereof may be included as a constituent compound.

[0672] In one embodiment, an absorption coefficient (k) of the inorganic material included in the low reflection layer AL2 may be 4.0 or less and 0.5 or more (0.5≤k≤4.0).

[0673] In addition, the inorganic material included in the low reflection layer AL2 may have a refractive index n of 1 or more (n≥1.0).

[0674] The low reflection layer AL2 causes destructive interference between light incident to the inside of the display device and light reflected from metal disposed under the low reflection layer AL2, thereby reducing external light reflectivity.

[0675] Therefore, the external light reflectivity of the display device is reduced by the low-reflection layer AL2, so that the display quality and visibility of the display device can be improved.

[0676] According to an embodiment, the cladding layer AL1 may be omitted so that the low reflection layer AL2 may be in contact with the cathode.

[0677] The encapsulation layer 400 is positioned on the low reflection layer AL2, and the other structures are the same as Fig. 22 The structures are the same, so the description is omitted.

[0678] Meanwhile, the cathode Cathode formed in the display area may not be formed in the first assembly area EA1, and Fig.29 In an embodiment, a low adhesion layer WAL may be positioned.

[0679] The low adhesion layer WAL may be positioned on the functional layer FL in the first component area EA1 .

[0680] The low adhesion layer WAL is a material having weak adhesion, and according to an embodiment, an upper surface of the low adhesion layer WAL may not have a cathode disposed thereon, or the low adhesion layer WAL may include a material having a property of being a very thin film on the cathode.

[0681] For example, the low adhesion layer WAL is 8-hydroxyquinolate lithium (Liq; [8-hydroxyquinolate lithium]), N,N-diphenyl-N,N-bis(9-phenyl-9H-carbazole-3-yl)biphenyl-4,4′-diamine (N,N-diphenyl-N,N-bis(9-phenyl-9H-carbazole-3-yl)biphenyl-4,4′-diamine; HT01), N(diphenyl-4-yl)9,9-dimethyl-N-(4(9-phenyl-9H-carbazole-3-yl)phenyl)-9H -fluoren-2-amine (N(diphenyl-4-yl)9,9-dimethyl-N-(4(9-phenyl-9H-carbazol-3-yl)phenyl)-9H-fluoren-2-amine; HT211), 2-(4-(9,10-di(naphthalene-2-yl)anthracen-2-yl)phenyl)-1-phenyl-1H-benzo-[D]imidazole (2-(4-(9,10-di(naphthalene-2-yl)anthracen-2-yl)phenyl)-1-phenyl-1H-benzo-[D]imidazole; LG201).

[0682] Although this specification has shown and described an embodiment in which the low adhesion layer WAL is located in the first assembly area EA1, in other embodiments the low adhesion layer WAL may be removed by a laser process or the like.

[0683] In this case, the laser process may be a laser process performed on a cathode.

[0684] In the first assembly area EA1 , the cover layer AL1 , the low reflection layer AL2 , and the encapsulation layer 400 may be disposed on the low adhesion layer WAL.

[0685] Although the embodiments have been described in detail above, the scope of the inventive concept is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the inventive concept defined in the appended claims are also included in the scope of the inventive concept.

Claims

1. A light-emitting display device, wherein: The light emitting display device comprises: A first semiconductor layer is disposed on the substrate and includes a channel of the driving transistor, a channel of the sixth transistor, and an output current passing region disposed on one side of the channel of the sixth transistor; a first gate conductive layer disposed on the first semiconductor layer and comprising a gate electrode of the driving transistor overlapping with the channel of the driving transistor in a plan view and a light emitting control line overlapping with the channel of the sixth transistor in a plan view; a second gate conductive layer disposed on the first gate conductive layer and including a first storage electrode overlapping the gate electrode of the driving transistor in a plan view and a shielding layer overlapping the output current passing region in a plan view; a second semiconductor layer, disposed on the second gate conductive layer and comprising a channel of a fourth transistor; a third gate conductive layer disposed on the second semiconductor layer and including an initialization control line overlapping the channel of the fourth transistor in a plan view; a first data conductive layer disposed on the third gate conductive layer and including a driving voltage connection electrode and a first anode connection electrode electrically connected to the output current passing region disposed on the one side of the channel of the sixth transistor; a first organic layer, covering the first data conductive layer; a second data conductive layer disposed on the first organic layer and comprising a second anode connection electrode electrically connected to the first anode connection electrode, and a driving voltage line; a second organic layer, disposed on the second data conductive layer; and an anode disposed on the second organic layer and electrically connected to the second anode connection electrode, wherein, in a plan view, the initialization control line overlaps with the output current passing region and the shielding layer provided on the one side of the channel of the sixth transistor, and Wherein, the shielding layer is connected to the driving voltage line through the driving voltage connection electrode.

2. The light emitting display device according to claim 1, wherein: The second gate conductive layer also includes a lower shielding layer of the fourth transistor, and The lower shield layer of the fourth transistor is electrically connected to the initialization control line and overlaps the channel of the fourth transistor in a plan view.

3. The light-emitting display device according to claim 2, wherein: The light-emitting display device further comprises: a metal layer disposed between the substrate and the first semiconductor layer and including an extension portion; and a buffer layer, disposed between the metal layer and the first semiconductor layer, in: The second gate conductive layer also includes a lower second scanning line, The second semiconductor layer also includes a channel of a third transistor, The third gate conductive layer also includes an upper second scanning line, In a plan view, the channel of the third transistor overlaps the lower second scan line and the upper second scan line, The same signal is applied to the lower second scan line and the upper second scan line, The first semiconductor layer also includes a channel of a fifth transistor, One end of the fifth transistor is connected to the driving voltage line, In a plan view, the channel of the sixth transistor and the channel of the fifth transistor overlap the light emission control line, and In a plan view, the extending portion of the metal layer overlaps the channel of the driving transistor.

4. The light emitting display device according to claim 2, wherein: The first semiconductor layer also includes a channel of a seventh transistor, One end of the seventh transistor is connected to a second initialization voltage line, and The output current passing region is provided between the channel of the seventh transistor and the channel of the sixth transistor.

5. The light-emitting display device according to claim 4, wherein: The light-emitting display device further comprises: a third data conductive layer disposed between the second organic layer and the anode and disposed on the second organic layer; and a third organic layer, covering the third data conductive layer, in: The first semiconductor layer also includes a channel of a second transistor, One end of the second transistor is connected to the data line, The anode is directly disposed on the third organic layer, The third data conductive layer further includes a third anode connection electrode, and The third anode connection electrode connects the second anode connection electrode and the anode.

6. A light-emitting display device, wherein: The light emitting display device comprises: A first semiconductor layer, disposed on the substrate and including a channel of the driving transistor; a first gate conductive layer disposed on the first semiconductor layer and including a gate electrode of the driving transistor overlapping the channel of the driving transistor in a plan view; a second gate conductive layer disposed on the first gate conductive layer and including a first storage electrode overlapping the gate electrode of the driving transistor in a plan view, and a lower shielding layer; a second semiconductor layer disposed on the second gate conductive layer and including a channel of a fourth transistor overlapping the lower shielding layer in a plan view; a third gate conductive layer disposed on the second semiconductor layer and including an initialization control line overlapping the channel of the fourth transistor in a plan view; a first data conductive layer disposed on the third gate conductive layer and comprising a first connection electrode and a first anode connection electrode connecting the gate electrode of the driving transistor and one side of the channel of the fourth transistor; a first organic layer, covering the first data conductive layer; a second data conductive layer disposed on the first organic layer and comprising a second anode connection electrode electrically connected to the first anode connection electrode, and a driving voltage line; a second organic layer, disposed on the second data conductive layer; and an anode disposed on the second organic layer and electrically connected to the second anode connection electrode, Wherein, the lower shielding layer has an island structure, and Wherein, the initialization control line is electrically connected to the lower shielding layer through the opening.

7. The light-emitting display device according to claim 6, wherein: The second gate conductive layer also includes a lower second scanning line, The second semiconductor layer also includes a channel of a third transistor, The third gate conductive layer also includes an upper second scanning line, In a plan view, the channel of the third transistor overlaps the lower second scan line and the upper second scan line, and The same signal is applied to the lower second scan line and the upper second scan line.

8. The light emitting display device according to claim 7, wherein: The first semiconductor layer further includes a channel of a sixth transistor and an output current passing region disposed on one side of the channel of the sixth transistor. The second gate conductive layer further includes a shielding layer overlapping the output current passing region in a plan view, In a plan view, the initialization control line overlaps the output current passing region and the shielding layer provided on the one side of the channel of the sixth transistor, The shielding layer is connected to the driving voltage line, The first semiconductor layer also includes a channel of a seventh transistor, One end of the seventh transistor is connected to a second initialization voltage line, The output current passing region is provided between the channel of the seventh transistor and the channel of the sixth transistor, The first semiconductor layer also includes a channel of a fifth transistor, One end of the fifth transistor is connected to the driving voltage line, and The channel of the sixth transistor and the channel of the fifth transistor overlap the light emission control line in a plan view.

9. The light-emitting display device according to claim 7, wherein: The light-emitting display device further comprises: a third data conductive layer disposed between the second organic layer and the anode and on the second organic layer; and a third organic layer, covering the third data conductive layer, in: The first semiconductor layer also includes a channel of a second transistor, One end of the second transistor is connected to the data line, The anode is directly disposed on the third organic layer, The data line is arranged in the third data conductive layer, The third data conductive layer further includes a third anode connection electrode, and The third anode connection electrode connects the second anode connection electrode and the anode.

10. The light emitting display device according to claim 7, wherein: The light-emitting display device further comprises: a metal layer disposed between the substrate and the first semiconductor layer and including an extension portion; and a buffer layer disposed between the metal layer and the first semiconductor layer, and Wherein, in a plan view, the extending portion of the metal layer overlaps with the channel of the driving transistor.

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