Electronic circuit and inspection method thereof

Abstract

Provided is an electronic circuit having a functional circuit capable of preventing an operation of erroneously entering a test mode when used on the market. This electronic circuit is provided with a functional circuit having a predetermined function, and an inspection circuit that performs inspection for debugging the functional circuit. The electronic circuit is provided with: an input circuit that decodes a start-up signal for operating the electronic circuit and outputs the decoded start-up signal to the functional circuit; the test signal generator is used for generating a trigger signal for a test signal based on the signal change contained in the starting signal; and an arithmetic element that performs a NOR operation of the decoding start signal and the trigger signal, and outputs a signal of the operation result to the inspection circuit as a test signal for instructing execution of the inspection.

Description

Technical Field

[0001] The present invention relates to an electronic circuit having a functional circuit having a predetermined function and a method for inspecting the same. Background Art

[0002] It is known that a test mode operation is provided for the purpose of factory testing or debugging which is not used by users in the market.

[0003] For example, Patent Document 1 provides an integrated circuit, an electronic circuit board, a DC-DC converter, and a method for inspecting these circuits that can be miniaturized. In the integrated circuit of this prior art example, when a specific inspection signal is input to a functional circuit FC, an output terminal SW,E (V OUT ) outputs a monitoring signal corresponding to the inspection signal. If the functional circuit is normal, the value of the monitoring signal input to the determiner becomes the expected signal when the functional circuit is normal, and if it is abnormal, it becomes different from the signal in the normal state. Therefore, by inputting the inspection signal from the test circuit to the functional circuit, the functional circuit can be inspected. The inspection signal is input to the test circuit via the power supply terminal Vcc of the functional circuit, so there is no need for an additional terminal for inspection, which can make the device miniaturized.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2008-224247 Summary of the invention

[0007] Problems to be solved by the invention

[0008] However, conventional circuits for inputting test signals have problems such that the circuit is invalidated after inspection and cannot be tested again, or the circuit is not invalidated and the circuit mistakenly enters the test mode, resulting in unexpected operation.

[0009] An object of the present invention is to solve the above-mentioned problems and to provide an electronic circuit having a functional circuit and a method for inspecting the electronic circuit and the like, which can prevent the electronic circuit from mistakenly entering a test mode when used in the market.

[0010] Means for solving problems

[0011] An electronic circuit according to a first aspect of the present invention is an electronic circuit including a functional circuit having a predetermined function and a test circuit for performing a test for debugging the functional circuit, and includes:

[0012] an input circuit that decodes an activation signal for causing the electronic circuit to be in an operating state and outputs the decoded activation signal to the functional circuit;

[0013] a test signal generator, which generates a trigger signal for a test signal based on a signal change included in the start signal; and

[0014] The operation element performs a "NOR" operation on the decoding start signal and the trigger signal, and outputs a signal of the operation result to the inspection circuit as a test signal instructing execution of the inspection.

[0015] An electronic circuit according to a second aspect of the present invention is an electronic circuit including a functional circuit having a predetermined function and a test circuit for performing a test for debugging the functional circuit, and includes:

[0016] a first input circuit that decodes an activation signal for causing the electronic circuit to be in an operating state and outputs the decoded activation signal to the functional circuit;

[0017] a second input circuit that decodes the specified command signal and outputs the decoded command signal to the functional circuit;

[0018] a test signal generator, which generates a trigger signal for a test signal based on a signal change included in the command signal; and

[0019] The operation element performs a "NOR" operation on the decoding start signal and the trigger signal, and outputs a signal of the operation result to the inspection circuit as a test signal instructing execution of the inspection.

[0020] An electronic circuit according to a third aspect of the present invention is an electronic circuit including a functional circuit having a predetermined function and a test circuit for performing a test for debugging the functional circuit, and includes:

[0021] a first input circuit that decodes an activation signal for causing the electronic circuit to be in an operating state and outputs the decoded activation signal to the functional circuit;

[0022] a second input circuit that decodes the specified first command signal and outputs the first decoded command signal to the functional circuit;

[0023] a first test signal generator, which generates a first trigger signal for a test signal based on a signal change included in the first command signal;

[0024] a third input circuit that decodes the specified second command signal and outputs the second decoded command signal to the functional circuit;

[0025] a second test signal generator for generating a second trigger signal for a test signal based on a signal change included in the second command signal; and

[0026] The operation element performs a "NOR" operation on the decoding enable signal, the first trigger signal and the second trigger signal, and outputs a signal of the operation result to the inspection circuit as a test signal instructing execution of the inspection.

[0027] Effects of the Invention

[0028] Therefore, the electronic circuit involved in the present invention is equipped with an operation element that performs an "OR" operation on the decoding start signal or the encoding instruction signal and the trigger signal, and outputs the signal of the operation result to the inspection circuit as a test signal instructing the execution of the inspection. Therefore, in the electronic circuit having the functional circuit, it is possible to prevent the action of erroneously entering the test mode when used in the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a block diagram showing a configuration example of the electronic circuit 1 according to the first embodiment.

[0030] Figure 2 Yes means Figure 1 A timing diagram of each voltage of the operation of the electronic circuit 1.

[0031] Figure 3 : is a circuit diagram showing a configuration example of a test signal generator 13A according to Modification 1.

[0032] Figure 4 Yes means Figure 3 A timing diagram of each voltage of the operation of the test signal generator 13A.

[0033] Figure 5 : is a circuit diagram showing a configuration example of a test signal generator 13B according to Modification 2.

[0034] Figure 6 Yes means Figure 5 A timing diagram of each voltage of the operation of the test signal generator 13B.

[0035] Figure 7 : is a circuit diagram showing a configuration example of a test signal generator 13C according to Modification 3.

[0036] Figure 8 : is a circuit diagram showing a configuration example of a test signal generator 13D according to Modification 4.

[0037] Fig. 9 This is a block diagram showing a configuration example of an electronic circuit 1A according to the second embodiment.

[0038] Fig.10 Yes means Fig. 9 A timing diagram of each voltage of the operation of the electronic circuit 1A.

[0039] Fig.11 This is a block diagram showing a configuration example of an electronic circuit 1B according to the third embodiment.

[0040] Fig.12 This is a block diagram showing a configuration example of an electronic circuit 1C according to the fourth embodiment.

[0041] Fig.13 : is a block diagram showing the structure of an electronic circuit 101 according to a comparative example.

[0042] Fig.14 Yes means Fig.13 A circuit diagram of the structure of the test signal generator 13.

[0043] Fig.15 Yes means Fig.14 A timing diagram of each voltage of the operation of the test signal generator 13.

[0044] Fig.16 is Fig.14 1 is a timing diagram of each voltage when noise is superimposed on the ground line in the test signal generator 13.

[0045] Fig.17 is Fig.14 1 is a timing diagram of each voltage when noise is superimposed on the connection line of the terminal T2 in the test signal generator 13. DETAILED DESCRIPTION

[0046] Hereinafter, embodiments and modifications of the present invention will be described with reference to the accompanying drawings. In addition, the same or similar components are denoted by the same reference numerals.

[0047] (Opinion of the inventor)

[0048] Patent document 1 discloses a structure that enables inspection without adding a dedicated terminal for inspection for the purpose of inspection, but it cannot solve the problem that the device cannot be tested again because it is set to invalid after inspection. That is, in the state of "chip enable signal EN = H level" where the functional circuit is operating, the state transition is not performed even if the entry condition of the test mode is met, so the inspection function is not invalidated after inspection and malfunction in actual use can be avoided.

[0049] Fig.13 : is a block diagram showing the structure of an electronic circuit 101 according to a comparative example.

[0050] exist Fig.13 In [the circuit], the electronic circuit 101 includes terminals T1 and T2, input interfaces 11 and 12, a test signal generator 13, and a functional circuit 10 that performs a prescribed function and incorporates an inspection circuit 20. The input interface 11 decodes the chip start signal EN input to the terminal T1 into a chip start signal ENa that is a prescribed rising edge signal (Japanese original: “立ち上りエッジ信号”), and then outputs it to the functional circuit 10. In addition, the input interface 12 decodes the command signal XXX input to the terminal T2 into a command signal XXXa that is a prescribed rising edge signal, and then outputs it to the functional circuit 10. Furthermore, when the command signal XXX input to the terminal T2 satisfies the signal condition of a prescribed test mode, the test signal generator 13 outputs a test signal TEST of H level to the functional circuit 10. Moreover, in response to the test signal TEST of H level, the inspection circuit 20 incorporated in the functional circuit 10 performs a prescribed inspection for debugging purposes on the functional circuit 10.

[0051] Fig.14 represents Fig.13 the circuit diagram of the structure of the test signal generator 13. In addition, Fig.15 represents Fig.14 the timing diagram of each voltage of the operation of the test signal generator 13. In Fig.15 and other drawings, Vxxx represents the voltage of the command signal XXX.

[0052] In Fig.14 [the circuit], the test signal generator 13 includes an N-channel MOS transistor Mtest, a resistor R11, and an inverter INV1. Here, the power supply voltage Vdd is connected to the terminal T2 via the resistor R11, the drain and source of the MOS transistor Mtest. The gate of the MOS transistor Mtest is grounded, and the MOS transistor Mtest is in the cut-off state. The signal from the drain of the MOS transistor Mtest is inverted by the inverter INV1 and then output as the test signal TEST.

[0053] As Fig.15 shown, in the test signal generator 13 configured as described above, when the voltage at the terminal T2 becomes equal to or lower than the voltage Vgstest that is the threshold voltage of the MOS transistor Mtest, the test signal TEST becomes H level.

[0054] That is, in Fig.13 and Fig.14 [the circuit], in order to put the functional circuit 10 into the test mode without adding a dedicated terminal, the operating recommended conditions of the terminal used in the control of the integrated circuit are set as the entry conditions, except for those.

[0055] However, when the electronic circuit 101 is used in a switching regulator, the output voltage, the power supply voltage and the ground voltage may change due to switching noise, etc., and the entry condition may be satisfied. In addition, the voltage of the command signal XXX at the terminal T2 as an external input may also contain noise.

[0056] Fig.16 is Fig.14 The timing diagram of each voltage when noise is superimposed on the ground line in the test signal generator 13 of FIG. Fig.16 In other figures, Vgnd represents the ground voltage. Fig.16 It can be seen that there is a case where the ground voltage changes and the test signal TEST erroneously becomes the H level.

[0057] Fig.17 is Fig.14 The timing diagram of each voltage when noise is superimposed on the connection line of the terminal T2 in the test signal generator 13. Fig.17 It can be seen that there is a case where the voltage of the command signal XXX changes and the test signal TEST becomes the H level.

[0058] In addition, the entry state of the test mode is usually latched, so there is the following problem, that is, Fig.16 or Fig.17 In this way, if the test signal TEST becomes H level even once, the functional circuit 10 cannot be restored unless the electronic circuit 101 is restarted.

[0059] The inventors of the present invention have designed the following embodiments and variations to solve the above-mentioned problems. The embodiments of the present invention have the following characteristics when the test mode is used for factory testing or debugging. The characteristic is that "when the functional circuit 10 is in the state of "chip enable signal EN = H level", even if the entry condition of the test mode is met, the test signal TEST will not be transferred from the L level state to the H level."

[0060] (Implementation Method 1)

[0061] Figure 1 1 is a block diagram showing a configuration example of an electronic circuit 1 according to Embodiment 1. Figure 2 : is a timing diagram of each voltage showing the operation of the electronic circuit 1. Here, Figure 1 The test signal generator 13 has, for example, Fig.14 Circuit structure. Figure 1 In the electronic circuit 1, Fig.13 Compared with the electronic circuit 101, the following points are different.

[0062] (1) The test signal from the test signal generator 13 is set as the trigger signal TRG.

[0063] (2) A NOR gate 14 is further provided. The NOR gate 14 is a computing element that performs a NOR operation on the enable signal ENa and the trigger signal TRG and outputs the signal of the operation result as a test signal TEST to the functional circuit 10.

[0064] Other structures and Fig.13 The electronic circuit 101 is also as Fig.14 as well as Fig.15 As shown, when the voltage of the terminal T2 becomes lower than the voltage Vgstest which is the threshold voltage of the MOS transistor Mtest, the test signal generator 13 turns the test signal TEST to the H level. In response to the test signal TEST at the H level, the inspection circuit 20 built into the functional circuit 10 performs a predetermined inspection for the functional circuit 10 for debugging purposes.

[0065] Furthermore, the test mode is not disabled even after the factory inspection. The input interfaces 11 and 12 are examples of input circuits that decode input signals and output coded signals.

[0066] In the electronic circuit 1 constructed as described above, when the enable signal ENa is at the H level, even if the test signal generator 13 outputs the trigger signal TRG at the H level, the NOR gate 14 prevents the test signal TEST from being output at the H level. Figure 2 As shown, even if noise is superimposed on the ground voltage, even if the trigger signal TRG is output at an H level, if the enable signal ENa is at an H level, the test signal TEST is not output at an H level.

[0067] As described above, according to the first embodiment, in the state of "chip enable signal EN = H level" when the functional circuit 10 is operating, even if the condition for entering the test mode is satisfied, the test signal TEST does not change from the L level state to the H level, that is, the generation of the H level test signal TEST can be prevented. Therefore, in the electronic circuit 1 having the functional circuit, the operation of mistakenly entering the test mode when used in the market can be prevented.

[0068] in addition, Figure 1 as well as Figure 1 The functional circuit 10 in the following drawings is, for example, a linear regulator, a switching regulator, a reference voltage generating circuit, a protection circuit such as an electronic circuit, a storage circuit, a digital processing circuit, etc.

[0069] (Variant 1)

[0070] Figure 3 : is a circuit diagram showing a configuration example of a test signal generator 13A according to Modification 1. Figure 4 Yes means Figure 3 A timing diagram of each voltage of the operation of the test signal generator 13A.

[0071] exist Figure 3 In the embodiment, the test signal generator 13A is composed of an offset DC voltage source 15 for applying a predetermined offset voltage to the command signal and a comparator 16. The command signal XXX input to the terminal T2 is DC-offset to a positive voltage direction by the DC voltage source 15, and then input to the inverting input terminal of the comparator 16. The non-inverting input terminal of the comparator 16 is grounded. When the voltage of the inverting input terminal becomes lower than the voltage of the non-inverting input terminal (the signal included in the command signal XXX changes), the comparator 16 outputs the H-level test signal TEST. That is, as Figure 4 As shown, when the voltage Vxxx of the command signal XXX becomes equal to or lower than -Voffset, the test signal TEST of the H level is output.

[0072] According to the modification example 1 configured as above, similarly to the embodiment 1, in the state of "chip enable signal EN = H level" when the functional circuit 10 is operating, even if the condition for entering the test mode is satisfied, the test signal TEST does not change from the L level state to the H level, that is, the generation of the H level test signal TEST can be prevented. Therefore, in the electronic circuit 1 having the functional circuit, the operation of mistakenly entering the test mode when used in the market can be prevented.

[0073] (Variant 2)

[0074] Figure 5 : is a circuit diagram showing a configuration example of a test signal generator 13B according to Modification Example 2. Figure 6 Yes means Figure 5 A timing diagram of each voltage of the operation of the test signal generator 13B.

[0075] exist Figure 5 In the embodiment, the test signal generator 13A is composed of an offset DC voltage source 15 for applying a predetermined offset voltage to the command signal and a comparator 16. The command signal XXX input to the terminal T2 is DC-offset to a negative voltage direction by the DC voltage source 15, and then input to the non-inverting input terminal of the comparator 16. The inverting input terminal of the comparator 16 is connected to the power supply voltage Vdd. When the voltage of the non-inverting input terminal (non-inverting input terminal) becomes higher than the voltage of the inverting input terminal, the comparator 16 outputs the H-level test signal TEST. That is, as Figure 6As shown, when the voltage Vxxx of the command signal XXX becomes equal to or higher than (Vdd+Voffset), the test signal TEST of the H level is output.

[0076] According to the modification example 2 configured as described above, similarly to the first embodiment and the modification example 1, in the state of "chip enable signal EN = H level" when the functional circuit 10 is operating, even if the condition for entering the test mode is satisfied, the test signal TEST does not change from the L level state to the H level, that is, the generation of the H level test signal TEST can be prevented. Therefore, in the electronic circuit 1 having the functional circuit, the operation of mistakenly entering the test mode when used in the market can be prevented.

[0077] (Variant 3)

[0078] Figure 7 FIG. 1 is a circuit diagram showing a configuration example of a test signal generator 13C according to Modification 3. Figure 7 In the test signal generator 13C, Figure 5 Compared with the test signal generator 13B, the following points are different.

[0079] (1) Instead of the offset DC voltage source 15, voltage dividing resistors R1 and R2 are provided which are connected in series with each other and inserted between the terminal T2 and the ground.

[0080] exist Figure 7 In the example, the voltage of the command signal XXX input to the terminal T2 is divided by the voltage-dividing resistors R1 and R2, and the divided voltage is input to the non-inverting input terminal of the comparator 16. Figure 5 The variant 2 operates in the same manner and has the same effect.

[0081] (Variant 4)

[0082] Figure 8 is a circuit diagram showing a configuration example of a test signal generator 13D according to Modification Example 4. Figure 8 In the test signal generator 13D, with Figure 7 Compared with the test signal generator 13C, the following points are different.

[0083] (1) At the inverting input terminal of the comparator 16 , the power supply voltage Vdd is divided by the voltage-dividing resistors R3 and R4 connected in series with each other, and the divided voltage is input to the inverting input terminal of the comparator 16 .

[0084] exist Figure 8 In the test signal generator 13D configured as above, except that the comparison reference voltage of the comparator 16 becomes a predetermined voltage lower than the power supply voltage Vdd, Figure 7 The variant 3 operates in the same manner and has the same effect.

[0085] (Implementation Method 2)

[0086] Fig. 9 This is a block diagram showing a configuration example of an electronic circuit 1A according to the second embodiment. Fig. 9 Electronic circuit 1A with Figure 1 Compared with the electronic circuit 1, the following points are different.

[0087] (1) A delay circuit 17 is inserted between the output terminal of the test signal generator 13 and the input terminal of the NOR gate 14 to delay the input signal by a predetermined delay time Td. Here, the delay time Td corresponds to the signal processing time of the input interface 11.

[0088] The differences are described below.

[0089] exist Fig. 9 In the delay circuit 17, after delaying the trigger signal TRG from the test signal generator 13 by a predetermined delay time Td, the delay signal TDLY is output to the NOR gate 14.

[0090] Fig.10 Yes means Fig. 9 The timing diagram of each voltage of the operation of the electronic circuit 1A. Fig.10 It can be seen that the circuit that fixes the test signal TEST to L level when the enable signal ENa is H level has a unique effect of being able to adjust the timing of the delay signal TDLY in consideration of the signal processing time of the input interface 11, etc. The other effects are the same as those of the first embodiment.

[0091] Furthermore, when the signal processing time of the input interface 11 is not considered, the delay circuit 17 may be deleted.

[0092] (Implementation 3)

[0093] Fig.11 This is a block diagram showing a configuration example of an electronic circuit 1B according to the third embodiment. Fig.11 The electronic circuit 1B, with Fig. 9 Compared with the electronic circuit 1A, the following points are different.

[0094] (1) It further includes a terminal T3 for receiving another command signal YYY.

[0095] (2) The device further includes an input interface 22 and a test signal generator 23 connected to the terminal T3.

[0096] (3) In place of the NOR gate 14, a NOR gate 14A having three input terminals is provided.

[0097] (4) A delay circuit 17A having the same structure as the delay circuit 17 is inserted between the test signal generator 23 and the NOR gate 14A.

[0098] The differences are described below.

[0099] exist Fig.11 In the example, the input interface 22 decodes the command signal YYY input to the terminal T3 into the command signal YYYa as a predetermined rising edge signal, and outputs the decoded command signal to the functional circuit 10. In addition, when the command signal YYY input to the terminal T3 meets the signal condition of the predetermined test mode, the test signal generator 23 outputs the trigger signal TRGA of the H level to the functional circuit 10 as the delay signal TDLYA via the delay circuit 17A.

[0100] According to the third embodiment configured as described above, the test signal TEST can be generated in response to the two command signals XXX and YYY, taking into account the signal processing time of the input interface 11. Other effects are the same as those of the second embodiment.

[0101] Furthermore, the delay circuits 17 and 17A may be deleted when the signal processing time of the input interface 11 is not considered. In the fourth embodiment, the test signal TEST is generated using two trigger signals TRG and TRGA, but the present invention is not limited thereto. For example, three or more trigger signals may be used to generate the test signal TEST.

[0102] (Implementation 4)

[0103] Fig.12 This is a block diagram showing a configuration example of an electronic circuit 1C according to the fourth embodiment. Fig.12 The electronic circuit 1C, with Figure 1 Compared with the electronic circuit 1, the following points are different.

[0104] (1) The terminal T2 and the input interface 12 are deleted.

[0105] (2) The test signal generator 13 generates a trigger signal TRG based on the start signal EN input to the terminal T1 under the prescribed signal conditions (implementation example 1, variation example 1, variation example 2, etc.) in the same manner as the command signal XXX, and outputs the trigger signal TRG as a delay signal TDLY to the NOR gate 14 via the delay circuit 17.

[0106] According to the fourth embodiment configured as above, based on the start signal EN, the trigger signal TRG is generated under the prescribed signal condition similarly to the command signal XXX, thereby, the command signal XXX and the terminal T2 can be omitted, and the start signal EN can be used as the entry condition of the command signal XXX to generate the trigger signal TRG and the test signal TEST. In addition, the fourth embodiment has the same effects as the first embodiment.

[0107] In addition, Fig.12 In the embodiment, when the signal processing time of the input interface 11 is not considered, the delay circuit 17 may not be provided. In addition, the test signal generators 13 and 23 may be constituted by the above-mentioned test signal generators 13A to 13D.

[0108] Possibility of industrial application

[0109] As described in detail above, according to the electronic circuit and the like according to the present invention, in an electronic circuit having a functional circuit, it is possible to prevent the electronic circuit from erroneously entering the test mode when used by a user in the market.

[0110] Explanation of symbols

[0111] 1, 1A~1C, 101 electronic circuit

[0112] 10 Functional Circuit

[0113] 11, 12, 22 input interfaces

[0114] 13, 13A~13D, 23 test signal generator

[0115] 14, 14A "NOR" gate

[0116] 15 DC voltage source

[0117] 16 Comparators

[0118] 17, 17A delay circuit

[0119] 20 Check the circuit

[0120] INV1 Inverter

[0121] Mtest MOS transistor

[0122] R1~R11 resistors

[0123] T1~T3 terminals.

Claims

1. An electronic circuit comprising a functional circuit having a predetermined function and a test circuit for performing a test for debugging the functional circuit, comprising: an input circuit that decodes an activation signal for causing the electronic circuit to be in an operating state and outputs the decoded activation signal to the functional circuit; a test signal generator, which generates a trigger signal for a test signal based on a signal change included in the start signal; and The operation element performs a "NOR" operation on the decoding start signal and the trigger signal, and outputs a signal of the operation result to the inspection circuit as a test signal instructing to execute the inspection.

2. The electronic circuit as claimed in claim 1, wherein: The electronic circuit further comprises: The delay circuit is inserted between the test signal generator and the operation element, delays the trigger signal by the processing time of the input circuit, and outputs the delayed trigger signal to the operation element.

3. An electronic circuit comprising a functional circuit having a predetermined function and a test circuit for performing a test for debugging the functional circuit, comprising: a first input circuit that decodes an activation signal for causing the electronic circuit to be in an operating state and outputs the decoded activation signal to the functional circuit; a second input circuit that decodes the specified command signal and outputs the decoded command signal to the functional circuit; a test signal generator, which generates a trigger signal for a test signal based on a signal change included in the command signal; as well as The operation element performs a "NOR" operation on the decoding start signal and the trigger signal, and outputs a signal of the operation result to the inspection circuit as a test signal instructing to execute the inspection.

4. The electronic circuit as claimed in claim 3, wherein: The electronic circuit further comprises: The delay circuit is inserted between the test signal generator and the operation element, delays the trigger signal by a processing time of the first input circuit, and outputs the delayed trigger signal to the operation element.

5. An electronic circuit comprising a functional circuit having a predetermined function and a test circuit for performing a test for debugging the functional circuit, comprising: a first input circuit that decodes an activation signal for causing the electronic circuit to be in an operating state and outputs the decoded activation signal to the functional circuit; a second input circuit that decodes the specified first command signal and outputs the first decoded command signal to the functional circuit; a first test signal generator, which generates a first trigger signal for a test signal based on a signal change included in the first command signal; a third input circuit that decodes the specified second command signal and outputs the second decoded command signal to the functional circuit; a second test signal generator for generating a second trigger signal for a test signal based on a signal change included in the second command signal; and The operation element performs a "NOR" operation on the decoding start signal, the first trigger signal and the second trigger signal, and outputs the signal of the operation result to the inspection circuit as a test signal instructing to execute the inspection.

6. The electronic circuit as claimed in claim 5, wherein: The electronic circuit further comprises: a first delay circuit, inserted between the first test signal generator and the operation element, delaying the first trigger signal by a processing time of the first input circuit and outputting the delayed first trigger signal to the operation element; as well as The second delay circuit is inserted between the second test signal generator and the operation element, delays the second trigger signal by the processing time of the first input circuit, and outputs the delayed second trigger signal to the operation element.

7. The electronic circuit according to any one of claims 3 to 6, wherein: The test signal generator has: a series circuit including a resistor and a MOS transistor with a grounded gate connected in series, connected between a predetermined power supply voltage and an input terminal of the command signal; as well as The inverter inverts the signal from the output terminal of the MOS transistor and outputs the inverted signal as the trigger signal.

8. The electronic circuit according to any one of claims 3 to 6, wherein: The test signal generator has: a direct current voltage source for applying a predetermined offset voltage to a signal input to an input terminal of the command signal; as well as The comparator compares the signal to which the offset voltage is applied with the power supply voltage or the ground voltage, and outputs a comparison result signal as the trigger signal.

9. The electronic circuit according to any one of claims 3 to 6, wherein: The test signal generator has: A voltage dividing resistor divides the signal input to the input terminal of the command signal and outputs a divided voltage; as well as The comparator compares the divided voltage with the power supply voltage and outputs a comparison result signal as the trigger signal.

10. The electronic circuit according to any one of claims 3 to 6, wherein: The test signal generator has: a first voltage-dividing resistor for dividing the power supply voltage to output a first divided voltage; a second voltage-dividing resistor for dividing a signal input to the input terminal of the command signal to output a second divided voltage; as well as The comparator compares the first divided voltage with the second divided voltage and outputs the trigger signal.

11. An inspection method for an electronic circuit, comprising: a functional circuit having a predetermined function and an inspection circuit for performing inspection for debugging the functional circuit, the method comprising: The step of an input circuit decoding an activation signal for causing the electronic circuit to enter an operating state, and outputting the decoded activation signal to the functional circuit; a step of generating, by a test signal generator, a trigger signal for a test signal based on a signal change included in the start signal; and The step of: an operation element performing a "NOR" operation on the decoding start signal and the trigger signal, and outputting a signal of the operation result to the inspection circuit as a test signal instructing execution of the inspection.

12. An inspection method for an electronic circuit, comprising: a functional circuit having a predetermined function and an inspection circuit for performing inspection for debugging the functional circuit, the method comprising: The first input circuit decodes the activation signal for causing the electronic circuit to be in an operating state, and outputs the decoded activation signal to the functional circuit; The second input circuit decodes the specified command signal and outputs the decoded command signal to the functional circuit; The test signal generator generates a trigger signal for a test signal based on a signal change included in the command signal; and The step of: an operation element performing a "NOR" operation on the decoding start signal and the trigger signal, and outputting a signal of the operation result to the inspection circuit as a test signal instructing execution of the inspection.

13. An inspection method for an electronic circuit, comprising: a functional circuit having a predetermined function and an inspection circuit for performing inspection for debugging the functional circuit, the inspection method comprising: The first input circuit decodes the activation signal for causing the electronic circuit to be in an operating state, and outputs the decoded activation signal to the functional circuit; The second input circuit decodes the specified first command signal and outputs the first decoded command signal to the functional circuit; The first test signal generator generates a first trigger signal for a test signal based on a signal change included in the first command signal; The step of decoding the specified second command signal by the third input circuit and outputting the second decoded command signal to the functional circuit; A step of generating a second trigger signal for a test signal by a second test signal generator based on a signal change included in the second command signal; and The step of: an operation element performing a "NOR" operation on the decoding start signal, the first trigger signal and the second trigger signal, and outputting a signal of the operation result to the inspection circuit as a test signal instructing execution of the inspection.

Images