Optical calculation device and optical calculation method

Abstract

The optical arithmetic device includes: an address conversion unit that converts a plurality of bit values into address values serving as input port numbers; and a port conversion unit including a scrambling circuit that outputs light input from an input port of the input port number from an output port of the output port number, the output port number corresponding to a result of the operation performed on the input port number.

Description

Technical Field

[0001] The present invention relates to a data operation method used in optical communication and optical computing infrastructure. Background Art

[0002] In conventional technology, a scheme of an optical operation circuit using an optical operation element has been proposed (e.g., Non-Patent Document 1). In conventional technology, an optical circuit is realized using a Ψ gate, a Y gate, and a Mach-Zehnder interferometer optical switch (MZI optical switch) as an optical operation element. In Non-Patent Document 1, a method of using an MZI optical switch in the nonlinear operation part of an encryption method and using a Y gate in the linear operation part is proposed.

[0003] In conventional calculation methods, the bit of an optical signal is represented as "0" or "1" based on the amplitude of the light (or the intensity of the light (the square of the amplitude of the light)) and the phase of the light. For example, if the phase difference between two optical signals is 0, it is represented as bit 0, and if the phase difference is π, it is represented as bit 1.

[0004] Non-patent document 1: "Cryptographic circuit technology composed of optical logic gates", Junko Takahashi, Hiroshi Chida, Kohiro Yamakoshi, Shota Kita, Akihiko Shinke, NTT Technology Journal 2021.11, pp. 59-63. Summary of the invention

[0005] <Problems to be Solved by the Invention>

[0006] In calculation methods based on traditional technology, especially when performing multi-bit calculations, the light loss is large due to the connection of multiple optical logic gates. In order to obtain correct calculation results, it is necessary to frequently convert the optical signal to the electrical signal (photoelectric conversion) in the middle of the calculation.

[0007] In addition, in the operation based on the Ψ gate and the Y gate (the optical gate excluding the bias light of the Ψ gate), in order to change the phase difference of the input optical signal according to the operation result when the operation result is used as the input of the next operation, it is necessary to frequently perform photoelectric conversion in the middle of the operation. Performing photoelectric conversion in the middle of the operation will cause operation delay and increase in power consumption.

[0008] In particular, it is difficult to use optical logic gates to perform multi-stage operations connected to nonlinear operations (such as exclusive OR (XOR)). In order to obtain correct operation results, threshold processing must be performed using circuits at the end of the operation (Non-Patent Document 1).

[0009] The present invention has been made in view of the above points, and an object of the present invention is to provide a technology for reducing photoelectric conversion processing in optical computing.

[0010] <Methods used to solve the problem>

[0011] According to the disclosed technology, an optical computing device is provided, comprising: an address conversion unit, which converts multiple bit values ​​into address values, wherein the address values ​​are used as input port numbers; and a port conversion unit, which comprises a scrambling circuit, wherein the scrambling circuit outputs light input from an input port of the input port number from an output port of an output port number, wherein the output port number is equivalent to a result of an operation performed on the input port number.

[0012] <Effects of the Invention>

[0013] According to the disclosed technology, photoelectric conversion processing can be reduced in optical computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 2 is a diagram showing a basic structure of the optical computing device 100 .

[0015] Figure 2 This is a diagram for explaining the code point calculation method.

[0016] Figure 3 This is a diagram showing a configuration example of the optical computing device 100 in Example 1-1-1.

[0017] Figure 4 It is a diagram showing a configuration example of an MZI optical switch.

[0018] Figure 5 It is a diagram for explaining the operation of the MZI optical switch.

[0019] Figure 6 This is a diagram showing a configuration example of the optical computing device 100 in Example 1-1-2.

[0020] Figure 7 This is a diagram showing a configuration example of the optical computing device 100 in Example 1-1-2.

[0021] Figure 8 This is a diagram showing a configuration example of the optical computing device 100 in Example 1-1-2.

[0022] Fig. 9 It is a diagram for explaining the error detection method.

[0023] Fig.10 1 is a diagram showing a configuration example of the optical computing device 100 in Embodiment 1-2.

[0024] Fig.11 This is a diagram showing a configuration example of the optical computing device 100 in Example 2-1-1.

[0025] Fig.12This is a diagram showing a configuration example of the optical computing device 100 in Example 2-1-2.

[0026] Fig.13 This is a diagram used to illustrate the operation of MixColumns.

[0027] Fig.14 This is a diagram showing a configuration example of an optical computing device 100 in Example 2-2.

[0028] Fig.15 1 is a diagram showing a configuration example of the doubling calculation circuit 123 (scrambling circuit 121 ).

[0029] Fig.16 : is a diagram showing a configuration example of the bit resolution circuit 122.

[0030] Fig.17 : is a diagram showing a configuration example of the multi-bit XOR operation circuit 130 .

[0031] Fig.18 : is a diagram showing a configuration example of the address conversion unit 110 . DETAILED DESCRIPTION

[0032] Hereinafter, an embodiment of the present invention (this embodiment) will be described with reference to the drawings. The embodiment described below is merely an example, and the embodiment to which the present invention is applied is not limited to the following embodiment.

[0033] (Basic structure of optical computing device)

[0034] In the technology of this embodiment, in the optical computing device 100, by representing multiple bits with optical port numbers and performing operations based on optical wiring, it is possible to construct any function or perform any operation. This can reduce the number of optical logic gates used in the operation and the number of photoelectric conversions.

[0035] Figure 1 The basic structure of the optical computing device 100 in this embodiment is shown. The optical computing device 100 takes the optical signal output from the optical output device 200 as input, performs optical computing, and outputs the optical signal to the optical detection device 300. Note that when the optical computing device 100 that performs path control by an electrical signal is used, an electrical signal output device 400 that outputs an electrical signal is also used.

[0036] like Figure 1 As shown, the optical computing device 100 includes an address converter 110 and a port converter 120. The address converter 110 converts a bit value (optical bit signal) represented by an optical signal (or electrical signal) into a corresponding address value. The port converter 120 performs computing as port conversion of an optical signal.

[0037] For example, the address conversion unit 110 converts the bit value (0, 1, 0) into an address value 010, and the optical signal is input to the position (port number) of the input port in the port conversion unit 120 corresponding to the address value.

[0038] The port conversion unit 120 has a scrambling circuit 121 and a bit decomposition circuit 122. The scrambling circuit 121 has a plurality of input ports for inputting optical signals and a plurality of output ports for outputting optical signals, and the input ports and the output ports are connected according to a predetermined rule. The connection method may be waveguide, optical fiber or other methods.

[0039] Port numbers are assigned to the input port and output port respectively. The optical signal input to the input port of a certain port number (set as port number A) is output from the output port of a certain port number (set as port number B), which means that a conversion (operation) is performed from port number A to port number B.

[0040] The input ports and output ports are wired according to predetermined rules so that the conversion of port numbers corresponds to the desired operation.

[0041] The bit decomposition circuit 122 performs processing for restoring the port number of the output port that outputted the optical signal in the shuffle circuit 121 to a bit value (decomposition into bits).

[0042] As described above, once the bit value represented by the optical signal is converted into an address value, the subsequent operation can be performed only through optical wiring. Using the technology of this embodiment, any operation with N-bit input and M-bit output can be performed based on optical wiring (N and M are arbitrary integers). In the following, a more specific structure and operation example of the optical computing device 100 are described in Examples 1 and 2.

[0043] (Example 1: Error Correction Calculation Method)

[0044] First, the first embodiment will be described. In the first embodiment, the optical computing device 100 performs computation for error correction processing.

[0045] In the error correction process, code bits are generally generated on the transmitting side of the information bits, the information bits and the code bits are sent, and the error correction process is performed on the receiving side using the received information bits and code bits.

[0046] Here, an example is described in which the information bit (the number of bits of information sent and received between the sender and the receiver) is 4 bits and the code bit for 1-bit error detection is 3 bits. However, this is only an example, and the same calculation method can be performed in the case of an arbitrary number of bits. Although a 1-bit operation error can be detected in the error correction processing described below, the application of the technology according to the present embodiment does not depend on the number of erroneous bits.

[0047] Hereinafter, the operation for generating code bits will be described as Embodiment 1-1, and the operation for error detection will be described as Embodiment 1-2.

[0048] (Example 1-1: Generation of code points)

[0049] When configuring the optical computing device 100 to generate code bits from information bits, the value of the code bit corresponding to the bit value of the information bit is calculated in advance. Here, the code bit (3 bits) of the Hamming code of the information bit (4 bits) is calculated in advance.

[0050] As a method for calculating code bits, for example, the method disclosed in Lecture 2 of the reference document "Basic Lecture on Error Detection and Correction of Large Frames of Hamming Codes" ("Basic Lecture on Error Detection and Correction with a General Framework of Hamming Codes", Embedded Technology Laboratory, published on September 23, 2020) can be used. Figure 2 An example of this method is shown in Figure 2 As shown, each of the information bits (4 bits) is represented by 3 bits corresponding to the position, and an exclusive OR (XOR) operation is performed between the 3 bits corresponding to 1 in the information bit, so that the code bit corresponding to the information bit can be obtained.

[0051] In the scrambling circuit 121, each value of the information bit is assigned to the port number of the input port, each value of the code bit is assigned to the port number of the output port, and the input port is connected to the output port to obtain the code bit corresponding to the information bit.

[0052] Hereinafter, a configuration example of the optical computing device 100 for generating a code bit corresponding to an arbitrary information bit will be described. Hereinafter, Embodiment 1-1-1 and Embodiment 1-1-2 will be described.

[0053] <Example 1-1-1: Example of using MZI optical switch for address conversion>

[0054] Figure 3 An example of the structure of the optical computing device 100 in Embodiment 1-1-1 is shown. Figure 3 As shown, the optical computing device 100 includes an address conversion unit 110 and a port conversion unit 120. The port conversion unit 120 includes a scrambling circuit 121 and a bit decomposition circuit 122.

[0055] The address conversion unit 110 has a structure in which a plurality of stages each including one or more MZI optical switches arranged in parallel are connected in series.

[0056] Figure 4 The following is an example of the structure of an MZI optical switch. An MZI optical switch is a type of optical logic gate, which consists of two optical couplers and an arm with a phase shifter embedded on one or both sides. Figure 4In the example shown in Figure 2, the phase shifter is embedded in the lower path.

[0057] The MZI optical switch functions as a switch that switches the optical path by changing the refractive index of the optical waveguide depending on whether a voltage is applied to the path in which the phase shifter is embedded, thereby changing the phase difference between the two paths.

[0058] For example, Figure 5 As shown in (b), when light is input to the upper path and a voltage is applied to the path in which the phase shifter is embedded (corresponding to the bit "1" of the electrical signal), an optical signal is output from the forward path (upper side). As shown in (a), when no voltage is applied (corresponding to the bit "0" of the electrical signal), an optical signal is output from the intersecting path (lower side). The same is true when light is input to the lower path, as shown in (c) and (d).

[0059] In this way, in the MZI optical switch, the path of the optical signal can be switched by turning the voltage on and off. Here, as an example, a case where the phase shifter is located on the lower side of the arm is considered.

[0060] exist Figure 3 In the address conversion unit 110 shown in FIG. 1 , among the information bits ((x3, x2, x1, x0): x0 is the least significant bit), x3 corresponds to class A, x2 corresponds to class B, x1 corresponds to class C, and x0 corresponds to class D. In class D, the number of paths (ports) that can output optical signals is 2. 4 indivual.

[0061] exist Figure 3 In the example shown, in each of the stages A to C, the arm (path) on the output side of each MZI optical switch is connected to the lower arm on the input side of the MZI optical switch of the next stage. However, this is only an example. The arm on the output side of the MZI optical switch may also be connected to the upper arm on the input side of the MZI optical switch of the next stage.

[0062] exist Figure 3 In the address conversion unit 110 , the path of light emitted from the light source (light output device 200 ) is switched depending on the information bit (4 bits), and the light reaches the input of the port conversion unit 120 .

[0063] For example, in Figure 3 In the example of , when the information bits are (0,0,0,0), the light passes through the arms of the uppermost MZI optical switches, and the light reaches the port numbered 0000 in the port conversion unit 120 (specifically, the scrambling circuit 121). In other words, the port number of the port to be reached when the information bits are (0,0,0,0) is set in advance to 0000. Alternatively, the connection of the address conversion unit 110 may be set in advance so that when the information bits are (0,0,0,0), the light reaches the input port numbered 0000.

[0064] Similarly, when the information bits are (0, 0, 0, 1), light is output from the second port from the top among the 16 output paths (output ports) in the D stage of the address conversion unit 110, and the light reaches the second input port from the top among the 16 input ports of the port conversion unit 121. The port number of this input port is set to 0001.

[0065] In the address conversion unit 110 , since the path of light is switched by inputting light into the MZI optical switch, the light passes through only one place in the address conversion unit 110 .

[0066] The method of mounting the MZI optical switch used in this embodiment is not limited to a specific method. For example, as the MZI optical switch, a switch that operates by utilizing a thermal effect, a switch that operates by injecting carriers, or switches other than these can be used.

[0067] Next, the port conversion unit 120 composed of the scrambling circuit 121 and the bit resolution circuit 122 will be described in detail.

[0068] In the scrambling circuit 121, the input port and the output port are connected in such a way that light is transmitted from the input port with the port number corresponding to the information bit (4 bits) to the output port with the port number corresponding to the code bit (3 bits). Transmission of light from the input port with the port number corresponding to the information bit (4 bits) to the output port with the port number corresponding to the code bit (3 bits) is equivalent to performing an operation of generating a code bit (3 bits) from the information bit (4 bits).

[0069] That is, if the 3-bit value representing the bit position of each bit of the information bit (4 bits) (refer to Figure 2 ) has been determined, the code bits corresponding to the information bits (4 bits) can be calculated. Therefore, by wiring between ports with corresponding port numbers, the code bits corresponding to the information bits can be calculated.

[0070] Generally, the value representing each bit position is often determined in a memory, so the code bit corresponding to the information bit can be calculated by connecting the input port and the output port in advance as in this embodiment.

[0071] For example, by pre-connecting the input port of the port number corresponding to the information bit (1001) and the output port of the port number corresponding to the code bit (100), light input from the input port corresponding to the information bit (1001) reaches the output port of the port number 100. Therefore, the port number corresponding to the code bit can be obtained.

[0072] The bit decomposition circuit 122 decomposes the output (port number) of the scrambling circuit 121 into bit values. Specifically, the bit decomposition circuit 122 transmits light to the output port corresponding to the value (0 or 1) of each bit of the output (3-bit port number) from the scrambling circuit 121. The bit decomposition circuit 122 can be implemented by a waveguide, an optical fiber, etc. to perform such light transmission.

[0073] For example, when the output of the scrambling circuit 121 is 000, that is, when light is output from the output port with the port number 000 in the scrambling circuit 121, light is input from the input port corresponding to the port number 000 in the bit decomposition circuit 122, and the light reaches the port position of (y2, y1, y0) = (0, 0, 0) (y0 is the least significant bit). Therefore, the output result is the bit value (0, 0, 0). The output result is converted into an optical signal, input into the optical transmission path, and sent to the receiver.

[0074] Similarly, when the output of the scrambling circuit 121 is 101, the light reaches (y2, y1, y0) = (1, 0, 1), so the result of receiving the light outputs the bit value (1, 0, 1). Here, the scrambling circuit 121 and the bit resolution circuit 122 may be combined and installed in one circuit.

[0075] As described above, by using the port conversion section 120, after temporarily converting the bit signal into an address, the code bit can be calculated without performing photoelectric conversion.

[0076] <Example 1-1-2: Example of using Ψ gate in address conversion>

[0077] Figure 6 A configuration example of the optical computing device 100 in Example 1-1-2 is shown. Figure 6 The address conversion unit 110 of the optical computing device 100 shown in the figure has a structure in which a plurality of Y branches and a plurality of Ψ gates are connected as shown in the figure. The port conversion unit 120 is the same as that described in the embodiment 1-1-1. Note that "branch" can also be referred to as "branch element".

[0078] The Y branch in the address conversion unit 110 splits the optical signal into two, and the Ψ gate receives the two input optical signals and the bias light (auxiliary light) as inputs, and functions as an AND gate for the two input optical signals.

[0079] The Ψ gate is a logic gate that utilizes the interference of light and introduces the concept of bias light to change the intensity (amplitude) and phase of the bias light, thereby being able to realize representative logic gate actions with a single gate (3 inputs, 1 output) (Reference: S. Kita, K. Nozaki, K. T anaka, A. Shinya and M. Notomi, "Ultrashort low-loss Ψgates for linear optical logic on Si photonics platform", Communications Physics, 3, Article No.: 33 (2020)).

[0080] In Example 1-1-2, the information bits (x3, x2, x1, x0) and their negation ( - x3, - x2, - x1, - x0) as an input to the address conversion unit 110 (x0 is the least significant bit). For example, assuming that x0=1 is a state in which light is emitted from the light source (light output device 200), and - x0=0 is a state where light is not emitted from the light source (a state where there is no light). Note that in the text of this specification, a symbol indicating the beginning of a character is marked at the upper left of the character. - x0" is an example.

[0081] like Figure 6 As shown in FIG. 1 , a string consisting of alternating bits and their negations is input. Figure 6 In the example of , the address conversion unit 110 includes 8 Y branches, 8 Ψ gates, 8 Y gates, 16 Y gates, and 16 Ψ gates from the input side, which are connected as shown in the figure (connected in a manner allowing light to pass therethrough).

[0082] exist Figure 6 In the example of FIG. 1 , if the information bit is (x3, x2, x1, x0) = (0, 0, 0, 0), the first Ψ gate from the top of the 16 Ψ gates of the last stage outputs light. Therefore, the first Ψ gate is connected to the 0th input port of the scrambling circuit 121.

[0083] In the case of information bit (x3, x2, x1, x0) = (0, 0, 0, 1), light is output from the fifth Ψ gate from the top of the 16 Ψ gates in the last stage. Therefore, the fifth Ψ gate is connected to the first input port of the scrambling circuit 121. The same is true for other information bits.

[0084] The operation in the port conversion unit 121 is as described above. In this embodiment, optical signals can be used as information bits to generate code bits without using electrical signals to input information bits.

[0085] Figure 7 is another structural example of the address conversion unit 110. Figure 7 In the example shown, a 4-branch optical gate is used. The 4-branch optical gate divides one light into 4 paths equally.

[0086] like Figure 7 As shown in FIG. 1 , the address conversion unit 110 includes 8 Y branches, 8 Ψ gates, 8 4 branches, and 16 Ψ gates from the input side, which are connected as shown in the figure. Figure 6 Compared with the structure, 16 branch gates can be cut.

[0087] also, Figure 8 FIG. 1 shows a configuration example of the address conversion unit 110 using an optical gate having 8 branches and an AND gate having 4 inputs. Figure 8 In the structure shown, a simple structure can be realized by using only one branch and one 4-input logic gate. A 4-input logic gate can be realized by connecting Ψ gates in two stages or by using one logic gate that expands the Ψ gate to 5 inputs (4 inputs and bias light).

[0088] (Example 1-2: Error Detection)

[0089] Next, as Example 1-2, the structure and operation of the optical computing device 100 that performs error detection based on the code bits generated according to the technique of Example 1-1 will be described.

[0090] Error detection can be performed by the method described in the second lecture of the reference document "Basic Lecture on Error Detection and Correction of Hamming Codes" ("Basic Lecture on Error Detection and Correction with a General Framework of Hamming Codes", Embedded Technology Laboratory, published on September 23, 2020)".

[0091] Fig. 9 An example of this method is shown. Fig. 9 As shown, similarly to the generation of code bits, each bit is represented by representing the value (3 bits) of each predetermined bit position, and an XOR operation is performed between the 3 bits at the position of "1" in the bit string (bitstring) composed of the information bit and the code bit. Here, in the case of an error, it is assumed that the position of the error is one position (any one of the 7 bits). If the result of the XOR is 000, it means that there is no error, and if it is a result other than 000, the position of the error is shown.

[0092] Fig.10FIG. 2 shows an example of a structure of an optical computing device 100 that performs error detection. Fig.10 As shown, the optical computing device 100 includes an address conversion unit 110 and a port conversion unit 120. The port conversion unit 120 includes a scrambling circuit 121 and a bit decomposition circuit 122.

[0093] The address conversion unit 110 has a structure in which a plurality of stages each including one or more MZI optical switches arranged in parallel are connected in series.

[0094] The address conversion unit 110 has stages corresponding to each of the seven bits ((x6, x5, x4, x3, x2, x1, x0): x0 is the least significant bit) of the information bit and the code bit, and in each stage, the arm (path) on the output side of each MZI optical switch is connected to the lower arm on the input side of the MZI optical switch of the next stage. However, this is only an example. The arm on the output side of the MZI optical switch may also be connected to the upper arm on the input side of the MZI optical switch of the next stage.

[0095] In the address converter 110 , similarly to the code bit generation, the path of light emitted from the light source (light output device 200 ) is switched depending on “information bit+code bit” (7 bits) given as an electrical signal, and the light reaches the input of the port converter 120 .

[0096] For example, in Fig.10 In the example of , when the information bit + code bit is (0,0,0,0,0,0,0), the light passes through the arms of the uppermost MZI optical switches, and the light reaches the port numbered 0000000 in the port conversion unit 120 (specifically, the scrambling circuit 121). In other words, the port number of the port that arrives when the information bit is (0,0,0,0,0,0,0) is set in advance to 0000000. The same applies to other port numbers.

[0097] As with the code bit generation, the output result of the address conversion unit 110 is used as the input to the scrambling circuit 121. At this time, assuming that only one bit is wrong, the output of the address conversion unit 110 becomes 2 7 (=2 4 ×2 3 ) {(Information bit pattern 2 4 )×(“no error + error” mode 2 3 indivual)}.

[0098] That is, since the "no error + error" pattern has 2 3 In order to make 2 7 "Information bit + code bit" corresponds to 2 3 The scrambling circuit 121 sets the input port to 2 7 and the output port is 2 3, through the scrambling circuit 121 from 2 7 To 2 3 The input port is assigned the value of "information bit + code bit" as the port number, and the output port is assigned 2 3 Each 3-bit value is used as the port number.

[0099] Because it indicates Fig. 9 The values ​​of each bit position of the scramble circuit 121 are fixed, so the value of the output of the scramble circuit 121 for the 7-bit value of "information bit + code bit" (value without error or error position) is uniquely determined. Therefore, the value of the output of the scramble circuit 121 for each of the 7-bit values ​​of "information bit + code bit" is calculated in advance, and the input port and output port corresponding to these values ​​(port numbers) are connected. As a result, the port number of the output port that outputs the light input to the input port becomes a 3-bit value without error or a value indicating an error position.

[0100] The structure and operation processing of the subsequent bit decomposition circuit 122 are the same as those of the case of generating code bits in Example 1-1-1. In this way, when error detection is performed based on information bits and code bits, photoelectric conversion is not required in the middle of the operation, and the operation can be performed in the port conversion unit 120 using only optical wiring.

[0101] (Example 2: Encryption calculation method)

[0102] Next, Example 2 is described. In Example 2, the optical computing device 100 performs operations in a public key encryption method. The encryption operation of the public key is mainly composed of nonlinear operations (S-box) and linear operations. In the following, the nonlinear operation is described as Example 2-1, and the linear operation is described as Example 2-2. Note that the nonlinear operation unit and the linear operation unit of the key scheduling unit can also perform calculations in the same method as the method described in Example 2.

[0103] (Example 2-1: Nonlinear calculation processing)

[0104] Here, as examples of nonlinear operation processing, the operation processing of the S-box of the Advanced Encryption Standard (AES) (Example 2-1-1) and the operation processing of the S-box of PRESENT (Example 2-1-2) are described.

[0105] <Example 2-1-1: AES S-box calculation processing>

[0106] Fig.11 The following is a structural example of the optical computing device 100 in Embodiment 2-1-1. Fig.11As shown, the optical computing device 100 includes an address conversion unit 110 and a port conversion unit 120. The port conversion unit 120 includes a scrambling circuit 121. The address conversion unit 110 has a structure in which a plurality of stages each of which is composed of one or more MZI optical switches arranged in parallel are connected in series.

[0107] The AES S-box is a table conversion that converts the input 8 bits into the output 8 bits in a one-to-one correspondence (reference: "Federal Information Processing Standards Publication 197, November 26, 2001Announcing the ADVANCED ENCRYPTION STANDARD (AES), https: / / nvlpubs.nist.gov / nistpubs / fips / nist.fips.197.pdf" Figure 7 ).

[0108] exist Fig.11 In the address conversion unit 110 shown in FIG. 1 , each of the input bits (x7, x6, x5, x4, x3, x2, x1, x0): x0 is the least significant bit) given as an electrical signal has a stage, and an electrical signal (ON / OFF) is given to each MZI optical switch of each stage. In the last stage, the number of paths (ports) that can output light is 2. 8 indivual.

[0109] exist Fig.11 In the example shown, the arm (path) on the output side of each MZI optical switch of each stage is connected to the lower arm on the input side of the MZI optical switch of the next stage. However, this is only an example. The arm on the output side of the MZI optical switch may also be connected to the upper arm on the input side of the MZI optical switch of the next stage.

[0110] exist Fig.11 In the address conversion unit 110, the path of the light emitted from the light source (light output device 200) is switched depending on the input bit (8 bits) of the S-box, and the light reaches one input of the port conversion unit 120. That is, the output of the address conversion unit 110 is determined as one path according to the value of the input 8 bits of the S-box.

[0111] For example, in Fig.11In the example of , when the input bit is (0,0,0,0,0,0,0,0), the light passes through the arms of the uppermost MZI optical switches, and the light reaches the port numbered 00000000 in the port conversion unit 120 (specifically, the scrambling circuit 121). In other words, the port number of the port reached when the input bit is (0,0,0,0,0,0,0,0) is set to 0000000. The same is true for other input bits.

[0112] The port conversion unit 120 is composed of a scrambling circuit 121, and uses the output light of the address conversion unit 110 as input light. In the scrambling circuit 121, the input port and the output port are connected, and the input port and the output port are connected in a way that light is transmitted from the input port with a port number corresponding to the input bit (8 bits) to the output port with a port number corresponding to the output bit (8 bits). Which input port is connected to which output port is determined by conversion based on the AES S-box table.

[0113] That is, in the scrambling circuit 121, optical wiring is performed in advance according to the AES S-box table conversion method, so the input light of the scrambling circuit 121 is converted into the output port of the corresponding S-box. For example, when the input of the scrambling circuit 121 is hexadecimal (00), since it is connected to the position of the output port (63), the light reaches the position of the port number (63), and the output value is (63).

[0114] As described above, 8-bit S-box operations can be performed. Therefore, for example, by repeating the above process 16 times in time series, using 16 optical computing devices 100, or using 16 wavelengths to perform operations by one optical computing device 100, 16-byte S-box operations can be achieved.

[0115] As described above, if address conversion is performed on input values, subsequent operations can be performed only through wiring.

[0116] <Example 2-1-2: Calculation Processing of S-box of PRESENT>

[0117] Fig.12 A configuration example of the optical computing device 100 in Example 2-1-2 is shown. Fig.12 The address conversion unit 110 of the optical computing device 100 shown in the figure has a structure in which a plurality of Y branches and a plurality of Ψ gates are connected as shown in the figure. The port conversion unit 120 is the same as that described in the embodiment 2-1-2 (the number of ports is different).

[0118] pass Fig.12The optical computing device 100 shown is used to calculate the S-box of the encryption method PRESENT (reference: A. Bogdanov, LR Knudsen, G. Leander, C. Paar, A. Poschman, MJB Robshaw, Y. Seurin, C. Vikkelsoe, PRESENT: An Ultra-Lightweight Block Cipher, CHES 2007: Cryptographic Hardware and Embedded Systems - CHES 2007 pp. 450-466).

[0119] The structure of the address conversion unit 110 and the connection structure for connecting to the scrambling circuit 121 are similar to Figure 6 The structure of the address conversion unit 110 and the connection structure for connecting to the scrambling circuit 121 of the embodiment 1-1-2 shown are the same.

[0120] In the present embodiment 2-1-2, whether to emit light from the light source is determined based on the input 4 bits of the S-box and its negated value. The light emitted from the light source is input to the scramble circuit 121 through the Y branch and the Ψ gate. Since the optical wiring is performed in advance in the scramble circuit 121 based on the S-box table conversion of the PRESENT, the input light of the scramble circuit 121 is converted to the output port of the corresponding S-box.

[0121] For example, when the input of the scrambling circuit is hexadecimal (0), since it is connected to the position of the output port (C), the light reaches the position of the port number (C) and the output value is (C).

[0122] Regarding the address conversion unit 110, similarly to the embodiment 1-1-2, Fig.12 The structure is replaced by using Figure 7 The 4-branch structure can also be replaced by using Figure 8 An 8-branch structure.

[0123] Similar to Example 2-1-1, 16-byte operations can be performed, for example, by repeating the above process 16 times in time series, using 16 optical computing devices 100, or using 16 wavelengths to perform operations by one optical computing device 100.

[0124] As described above, in this embodiment, once the input value is subjected to address conversion, subsequent operations can be performed only through wiring.

[0125] Note that in Embodiment 2-1 (Embodiment 2-1-1 and Embodiment 2-1-2), in the case of cryptographic operations, nonlinear operations or linear operations (e.g., ShiftRows in the case of AES) follow the S-box, and the subsequent operations can also be performed based on the port number, so the bit decomposition circuit 122 is omitted. However, the bit decomposition circuit 122 may be inserted. In addition, the technology of Embodiment 2-1 can also be applied to S-box operations (table permutation) of other cryptographic codes.

[0126] (Example 2-2: Linear operation processing)

[0127] Next, Example 2-2 will be described. In Example 2-2, the structure and operation of the optical computing device 100 that performs Mix Columns calculation which is a linear calculation of the encryption method AES will be described.

[0128] First, refer to Fig.13 Explain the operation of MixColumns. Fig.13 As shown, MixColumns operations include multiplication and XOR in 8-bit units, and the input / output is 32 bits. Note that Fig.13 The elements of the matrix shown are expressed in hexadecimal. In addition, for the convenience of description, in the text of the following specification, "XOR" is used as a symbol representing exclusive OR.

[0129] Here, for Fig.13 The following describes the optical computing device 100 that performs the 8-bit (y1) operation shown in (1). The same applies to the other 8-bit {y2, y3, y4}. Fig.13 The formula shown in (1) can be transformed as follows.

[0130] y1={02}·x1 XOR{02}·x2 XOR x2 XOR x3 XOR x4

[0131] Fig.14 FIG. 1 shows an example of the structure of the optical computing device 100 for calculating the deformed y1. Note that the optical computing device 100 includes an address conversion unit 110, a 2-times calculation circuit 123, a bit decomposition circuit 122, a multi-bit XOR operation circuit 130, and a photoelectric conversion unit 140. Note that the address conversion unit 110 has the same structure as the address conversion unit 110 described above, so Fig.14 In addition, the photoelectric conversion unit 140 may be a device other than the optical computing device 100. Here, when calculating y1, Fig.13 As shown in formula (1), it can be implemented using a 3x calculation circuit.

[0132] The 2x calculation circuit 123 is equivalent to the scrambling circuit 121. The 2x calculation circuit 123 and the bit decomposition circuit 122 may be collectively referred to as a port conversion unit 120. In addition, the optical computing device 100 may include all of the “address conversion unit 110, the 2x calculation circuit 123, the bit decomposition circuit 122, and the multi-bit XOR operation circuit 130”, or the “address conversion unit 110, the 2x calculation circuit 123, and the bit decomposition circuit 122” may be one optical computing device 100 and the “multi-bit XOR operation circuit 130” may be another optical computing device 100.

[0133] In addition, when a circuit that performs calculation using only an optical signal is used as the multi-bit XOR calculation circuit 130 , the photoelectric conversion unit 140 is not required.

[0134] exist Fig.14 In the structure shown, for the input value {x1, x2, x3, x4} after address conversion, {x1, x2} are respectively input to the 2-times calculation circuit 123 to obtain {z1, z2}. Then, {z1, z2, x2, x3, x4} are input to the bit decomposition circuit 122, and the obtained result is input to the multi-bit XOR operation circuit 130 via the photoelectric conversion unit 140.

[0135] Here, in a state where bit decomposition is completed with respect to {x3, x4}, it may be directly input to the bit decomposition circuit 122.

[0136] here, Fig.14 The 2x calculation circuits 123 may be respectively set for x1 and x2 (ie, using two 2x calculation circuits 123), or one 2x calculation circuit 123 may be used to simultaneously calculate {z1, z2} through wavelength division multiplexing.

[0137] In addition, circuits corresponding to the "bit decomposition circuit 122 and the multi-bit XOR operation circuit 130" can be arranged so that the operation processing of the "bit decomposition circuit 122 and the multi-bit XOR operation circuit 130" is performed jointly only by wiring. The following describes a configuration example of each circuit.

[0138] <Double calculation circuit 123>

[0139] Fig.15The structure of the 2x calculation circuit 123 (scrambling circuit 121) is shown. The 2x calculation is performed by left shifting, and the XOR sum of the irreducible polynomial (1b) is calculated when the most significant bit is "1" (reference: "Federal Information Processing Standards Publication 197, November 26, 2001 Announcing the ADVANCED ENCRYPTION STANDARD (AES), https: / / nvlpubs.nist.gov / nistpubs / fips / nist.fips.197.pdf").

[0140] By connecting the input with the output corresponding to the result of the 2x calculation, this can be achieved Fig.15 The 2x calculation circuit 123 (scrambling circuit 121) shown in FIG. 8 can calculate {z1, z2} by the 2x calculation circuit 123 (scrambling circuit 121) for the 8-bit value {x1, x2}.

[0141] <Bit resolution circuit 122>

[0142] Fig.16 FIG. 1 shows a configuration example of the bit decomposition circuit 122. In the bit decomposition circuit 122 for 8 bits, as shown in FIG. Fig.16 As shown, the values ​​of {z1, z2, x2, x3, x4} are converted from address values ​​to bits (x 7 ,x 6 ,x 5 ,x 4 ,x 3 ,x 2 ,x 1 ,x 0 )(x 0 is the least significant bit value). Fig.14 In the structure shown, the use of {z 1， z 2， x 2， x 3， x4} is a bit decomposition circuit 122 for each bit. However, wavelength multiplexing may be utilized to use one circuit.

[0143] <Multi-bit XOR operation circuit 130>

[0144] Fig.17 FIG. 2 shows a configuration example of a multi-bit XOR operation circuit 130. Fig.17 As shown, the multi-bit XOR operation circuit 130 includes an address conversion unit 110 and a scrambling circuit 121 .

[0145] The address conversion unit 110 performs 5-bit address conversion using the bit-decomposition value of the bit-decomposition circuit 122 as input. The scrambling circuit 121 performs wiring (connection between the input port and the output port) based on the 5-bit XOR calculation result and outputs the 5-bit XOR calculation result as input.

[0146] Fig.17 The least significant bit of each of {z1,z2,x2,x3,x4} (denoted as {z 0 1,z 0 2,x 0 2,x 0 3,x 0 4}) When performing XOR operation on 5 bits, operations on the other bits (2nd to 8th bits) can be performed using either one circuit or eight circuits by wavelength multiplexing.

[0147] Here, since a circuit using an MZI optical switch is used as the address conversion unit 110 ( Fig.18 ), so the input to the address conversion unit 110 is an electrical signal. Therefore, the photoelectric conversion unit 140 is required between the bit decomposition circuit 122 and the multi-bit XOR operation circuit 130. However, when the address conversion unit 110 adopts Fig.12 In the case of the structure using the Ψ gate shown, the photoelectric conversion unit 140 is not necessary.

[0148] exist Fig.17 In the embodiment, after address conversion, light is input to the scrambling circuit 121 for 5-bit XOR operation, and the light reaches the result of the XOR operation (z 0 1 XOR z 0 2 XOR x 0 2 XOR x 0 3 XOR x 0 4) A port representing "0" or "1" to obtain the result of the operation.

[0149] Note that an address conversion unit 110 that performs 5-bit address conversion and a scrambling circuit 121 for 5-bit XOR operations are shown here, but since the next operation of MixColumns is an XOR operation with a key, an address conversion unit 110 that performs 6-bit address conversion and a scrambling circuit 121 for 6-bit XOR operations can also be used.

[0150] In this way, a multi-bit XOR operation (non-linear operation) that is difficult to operate using optical logic gates alone can be performed only by address conversion and wiring, and there is no need to perform threshold processing using a circuit.

[0151] By using the technology of the second embodiment, the address conversion unit 110 and the port conversion unit 120 (the scrambling circuit 122, etc.) can be used to perform nonlinear operations and linear operations in cryptographic operations. In the case of AES, the operation of ShiftRows can also be performed by wiring processing, so the technology of the second embodiment can be used to perform the entire operation of one round of the cryptographic operation unit.

[0152] (Summary and Effects of Embodiments)

[0153] By using the above technology, by using optical port numbers to represent multiple bits of optical signals, various arbitrary operations can be performed using optical wiring. As a result, the number of optical logic gates used in the operation can be reduced, and the number of photoelectric conversions can be reduced. In addition, the operation when using the Ψ gate and MZI is basically an operation in units of 1 bit, but by using the technology described in this embodiment, as shown in the S-box operation of the password, it is possible to perform multiple-bit operations such as 8 bits at a time, which can reduce the number of operations.

[0154] That is, in the conventional technology, by using the Ψ gate and MZI in the calculation, the amplitude and phase are regarded as bits, and the calculation is performed for each bit. In addition, when the calculation such as the cryptographic calculation becomes complicated, multiple stages of calculation are required, and photoelectric conversion and phase conversion are required. In contrast, in the present technology, only the bit value needs to be converted into a port number, and arbitrary calculations can be performed only by wiring, which can reduce the number of photoelectric conversions and make installation easier.

[0155] (Note)

[0156] This specification discloses at least the following optical computing devices and optical computing methods.

[0157] (Note 1)

[0158] An optical computing device, comprising:

[0159] an address conversion section that converts a plurality of bit values ​​into an address value, the address value being used as an input port number; and

[0160] The port conversion unit includes a scrambling circuit configured to output light input from an input port having the input port number from an output port having an output port number corresponding to a result of a calculation performed on the input port number.

[0161] (Note 2)

[0162] The optical computing device according to note 1, wherein:

[0163] The address conversion section includes a plurality of Mach-Zehnder interference type optical switches to which the plurality of bit values ​​are input as electrical signals.

[0164] (Note 3)

[0165] The optical computing device according to note 1, wherein:

[0166] The address conversion section includes a plurality of branch elements and a plurality of optical logic gates, the plurality of branch elements being input with the plurality of bit values ​​as optical signals.

[0167] (Note 4)

[0168] An optical computing device according to any one of Notes 1 to 3, wherein:

[0169] The port conversion section includes a bit decomposition circuit that decomposes a bit value string corresponding to the output port number into individual bit values.

[0170] (Note 5)

[0171] An optical computing device according to any one of Notes 1 to 4, wherein:

[0172] The port conversion unit performs at least any one of an operation of generating code bits from information bits, an operation for detecting errors from information bits and code bits, a nonlinear operation in cryptographic processing, and a linear operation in cryptographic processing as the operation.

[0173] (Note 6)

[0174] An optical computing method, which is performed by an optical computing device, comprises:

[0175] An address conversion step of converting a plurality of bit values ​​into address values, the address values ​​being used as input port numbers; and

[0176] The port conversion step outputs light input from the input port having the input port number from the output port having the output port number, the output port number being equivalent to the result of the operation performed on the input port number.

[0177] As mentioned above, although this embodiment was described, this invention is not limited to such a specific embodiment, Various deformation|transformation and change are possible within the range of the summary of this invention described in a claim.

[0178] Description of Reference Numerals

[0179] 100 Optical computing device

[0180] 110 Address Conversion Unit

[0181] 120 Port conversion unit

[0182] 121 Scrambled Circuit

[0183] 122-bit decomposition circuit

[0184] 123 2 times calculation circuit

[0185] 130 Multi-bit XOR operation circuit

[0186] 140 Photoelectric conversion unit

[0187] 200 Light output device

[0188] 300 Light Detection Device

[0189] 400 Electrical signal output device.

Claims

1. An optical computing device, comprising: an address conversion section that converts a plurality of bit values ​​into an address value, the address value being used as an input port number; as well as The port conversion unit includes a scrambling circuit configured to output light input from an input port having the input port number from an output port having an output port number corresponding to a result of a calculation performed on the input port number.

2. The optical computing device according to claim 1, wherein: The address conversion section includes a plurality of Mach-Zehnder interference type optical switches to which the plurality of bit values ​​are input as electrical signals.

3. The optical computing device according to claim 1, wherein: The address conversion section includes a plurality of branch elements and a plurality of optical logic gates, the plurality of branch elements being input with the plurality of bit values ​​as optical signals.

4. The optical computing device according to any one of claims 1 to 3, wherein: The port conversion section includes a bit decomposition circuit that decomposes a bit value string corresponding to the output port number into individual bit values.

5. The optical computing device according to any one of claims 1 to 3, wherein: The port conversion unit performs at least any one of an operation of generating code bits from information bits, an operation for detecting errors from information bits and code bits, a nonlinear operation in cryptographic processing, and a linear operation in cryptographic processing as the operation.

6. An optical computing method, performed by an optical computing device, comprising: An address conversion step, converting a plurality of bit values ​​into address values, wherein the address values ​​are used as input port numbers; as well as The port conversion step outputs light input from the input port having the input port number from the output port having the output port number, the output port number being equivalent to the result of the operation performed on the input port number.

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