Ceramic circuit board and semiconductor device using same

Abstract

Provided is a ceramic circuit board having good adhesion to a molded resin. A ceramic circuit board according to an embodiment includes a ceramic substrate and a plurality of metal portions. The ceramic substrate has a first surface. The plurality of metal portions are respectively provided on the plurality of first regions of the first surface. The first surface has a second region located between adjacent first regions. The average length RSm of the roughness curve elements in the second region is 40 [mu] m or more. The average length RSm is preferably 100 [mu] m or less. The maximum peak height Rp of the roughness curve of the surface in the second region is preferably 1.0 [mu] m or more. The maximum valley depth Rv of the roughness curve of the surface in the second region is preferably 1.0 [mu] m or more.

Description

Technical Field

[0001] The embodiments described below generally relate to a ceramic circuit substrate and a semiconductor device using the same. Background Art

[0002] In recent years, along with the high performance of industrial equipment, the power modules installed therein have been promoted to be high-powered. Along with this, the power of semiconductor elements has been promoted to be high-powered. The guaranteed operating temperature of semiconductor elements is 125°C to 150°C, but it may rise to above 175°C in the future. As a circuit substrate for mounting semiconductor elements, a ceramic circuit substrate is used. The ceramic circuit substrate has a ceramic substrate and a metal plate bonded thereto. For example, in Japanese Patent Gazette No. 6789955 (Patent Document 1), there is an exposed portion where the bonding layer is exposed from the end of the metal plate. In Patent Document 1, the TCT characteristics (heat cycle resistance characteristics) are improved by controlling the hardness and size of the exposed portion of the bonding layer.

[0003] In addition, a resin mold is sometimes applied to protect semiconductor elements. The mold resin has the function of protecting semiconductor elements and wiring from external stress. The mold resin also has the function of protecting semiconductor elements from external gases such as moisture.

[0004] As the operating temperature of semiconductor elements rises, the adhesion between the ceramic circuit substrate and the molding resin becomes a problem. Due to the difference in thermal expansion coefficient between the ceramic circuit substrate and the molding resin, the molding resin may fall off from the ceramic circuit substrate. If the molding resin falls off, it may cause poor conduction of semiconductor elements, etc.

[0005] For example, in International Publication No. 2018 / 173921 (Patent Document 2), a recess is provided on a copper plate of a ceramic circuit substrate. In addition, in Japanese Patent Publication No. 2021-68850 (Patent Document 3), a recess is provided on a ceramic substrate.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent No. 6789955

[0009] Patent Document 2: International Publication No. 2018 / 173921

[0010] Patent Document 3: Japanese Patent Application Publication No. 2021-68850

[0011] Patent Document 4: International Publication No. 2019 / 054294 Summary of the invention

[0012] Problems to be solved by the invention

[0013] In the ceramic circuit substrates of Patent Documents 2 and 3, a recess is provided on a metal plate or a ceramic substrate, thereby improving the adhesion with the molding resin. On the other hand, the mounting density of semiconductor elements in ceramic circuit substrates has been improved in recent years. In order to improve the mounting density, a method of increasing the mounting area of ​​semiconductor elements on the surface of the metal plate can be cited. In order to increase the mounting area on the surface of the metal plate, a method of increasing the flat surface of the metal plate can be cited. There is also a method of increasing the mounting area of ​​the metal plate by narrowing the distance between the metal plates. In the method of providing a recess on the metal plate as in Patent Document 2, the mounting area cannot be increased. With respect to the previous ceramic circuit substrates, it cannot be said that both the ensuring of the mounting area and the adhesion of the molding resin are fully taken into account.

[0014] The embodiment is to cope with such a problem, and an object of the embodiment is to provide a ceramic circuit board that achieves both securing a mounting area and adhesion of a molding resin.

[0015] Means used to solve problems

[0016] The ceramic circuit substrate of the embodiment includes a ceramic substrate and a plurality of metal parts. The ceramic substrate has a first surface. The plurality of metal parts are respectively arranged in a plurality of first regions of the first surface. The first surface has a second region located between adjacent first regions. The average length RSm of the roughness curve element in the second region is greater than 40 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a plan view showing an example of the ceramic circuit board according to the embodiment.

[0018] Figure 2 It is a side view showing an example of the ceramic circuit board according to the embodiment.

[0019] Figure 3 It is a top view showing an example of a ceramic substrate.

[0020] Figure 4 It is a side view showing an example of a ceramic substrate.

[0021] Figure 5 It is a top view showing another example of the ceramic substrate.

[0022] Figure 6 It is a top view showing another example of the ceramic substrate.

[0023] Figure 7 It is a side view showing an example of a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0024] The ceramic circuit substrate of the embodiment includes a ceramic substrate and a plurality of metal parts. The ceramic substrate has a first surface. The plurality of metal parts are respectively arranged on a plurality of first regions of the first surface. The first surface has a second region located between adjacent first regions. The average length RSm of the roughness curve element in the second region is greater than 40 μm.

[0025] Figure 1 It is a plan view showing an example of the ceramic circuit board according to the embodiment. Figure 2 It is a side view showing an example of the ceramic circuit board according to the embodiment. Figure 1 and Figure 2 In the figure, reference numeral 1 denotes a ceramic circuit substrate, reference numeral 2 denotes a ceramic substrate, and reference numeral 3 denotes a metal portion. In the ceramic circuit substrate 1, a plurality of metal portions 3 are provided on at least one surface of a ceramic substrate 2 via a plurality of bonding layers 4, respectively.

[0026] Figure 3 It is a top view showing an example of a ceramic substrate. Figure 4 It is a side view showing an example of a ceramic substrate. Figure 3 and Figure 4 In the figure, reference numeral 2a indicates a first surface (front surface) of the ceramic substrate 2. Reference numeral 2b indicates a second surface (back surface) of the ceramic substrate 2. The second surface 2b is located on the opposite side to the first surface 2a.

[0027] like Figure 3 and Figure 4 As shown, the first surface 2a includes two or more first regions r1 and one or more second regions r2. Figure 3 In FIG. 1 , the first region r1 is indicated by a two-dot chain line. The second region r2 is indicated by an additional dot. Figure 3 In the figure, the metal part 3 bonded to the first surface 2a is indicated by a dotted line. The metal part 3 is bonded to the first region r1. The second region r2 is located between the first regions r1. The metal part 3 is not provided on the second region r2. The second region r2 is sometimes referred to as an inter-pattern region. In the example shown in the figure, three metal parts 3 are arranged on the ceramic substrate 2. In this case, the first surface 2a of the ceramic substrate 2 includes three first regions r1 and two second regions r2.

[0028] More specifically, the second region r2 is a region located between adjacent first regions r1 in the direction in which the distance between adjacent metal portions 3 is shortest. Here, the direction parallel to the thickness direction of the ceramic substrate 2 is referred to as the "Z direction". Two directions perpendicular to the Z direction and orthogonal to each other are referred to as the "X direction" and the "Y direction". For convenience, the X direction is referred to as the long side direction of the ceramic substrate 2, and the Y direction is referred to as the short side direction. Figure 3In the example shown, the plurality of metal parts 3 include a metal part 3a, a metal part 3b, and a metal part 3c. The distance d1 between the metal part 3a and the metal part 3b is the shortest in the X direction. Therefore, in the X direction, the region between the first region r1 to which the metal part 3a is bonded and the first region r1 to which the metal part 3b is bonded becomes the second region r2. Similarly, the distance d2 between the metal part 3b and the metal part 3c is the shortest in the X direction. In the X direction, the region between the first region r1 to which the metal part 3b is bonded and the first region r1 to which the metal part 3c is bonded becomes the second region r2.

[0029] Figure 5 and Figure 6 FIG. 1 is a top view showing another example of a ceramic substrate. Figure 5 and Figure 6 In the example shown, the size and position of the metal portion 3 bonded to the ceramic substrate 2 are similar to Figure 1 to Figure 4 The examples shown are different. Figure 1 to Figure 4 In the example shown, each metal portion 3 has a rectangular shape when viewed from the Z direction, and the longitudinal directions of each metal portion 3 are parallel to each other. Figure 5 In the example shown, a plurality of metal parts 3 are arranged in the X direction and the Y direction. Figure 6 In the illustrated example, the plurality of metal portions 3 are arranged such that the longitudinal directions of the metal portions 3 are inclined to each other.

[0030] about Figure 5 and Figure 6 The configuration shown can also be used with Figure 3 The second region r2 in the first surface 2a is identified by the same method as in the example shown. Specifically, Figure 5 In the example shown, metal parts 3a to 3d are provided. The distance d1 between the metal part 3a and the metal part 3b and the distance d2 between the metal part 3c and the metal part 3d are the shortest in the X direction. In the X direction, the area between the first area r1 bonded to the metal part 3a and the first area r1 bonded to the metal part 3b, and the area between the first area r1 bonded to the metal part 3c and the first area r1 bonded to the metal part 3d are respectively the second area r2. In addition, the distance d3 between the metal part 3a and the metal part 3c and the distance d4 between the metal part 3b and the metal part 3d are the shortest in the Y direction. In the Y direction, the area between the first area r1 bonded to the metal part 3a and the first area r1 bonded to the metal part 3c and the area between the first area r1 bonded to the metal part 3b and the first area r1 bonded to the metal part 3d are respectively the second area r2.

[0031] In addition, the distance d5 between the metal part 3a and the metal part 3d and the distance d6 between the metal part 3b and the metal part 3c are shortest in the direction inclined relative to the X direction and the Y direction. Therefore, in this inclined direction, the area between the first area r1 to which the metal part 3a is bonded and the first area r1 to which the metal part 3d is bonded and the area between the first area r1 to which the metal part 3b is bonded and the first area r1 to which the metal part 3c is bonded can also be respectively the second area r2. However, the area where the distance between the metal parts 3 exceeds 3mm is not treated as the second area r2. For example, even when the shortest distance between the metal parts 3 is less than 3mm, the area where the distance between the metal parts 3 exceeds 3mm is not included in the second area r2.

[0032] exist Figure 6 In the example shown, the distance d1 between the metal part 3a and the metal part 3b and the distance d2 between the metal part 3b and the metal part 3c are the shortest in the X direction. Therefore, in the X direction, the area between the first area r1 to which the metal part 3a is bonded and the first area r1 to which the metal part 3b is bonded becomes the second area r2. In the X direction, the area between the first area r1 to which the metal part 3b is bonded and the first area r1 to which the metal part 3c is bonded becomes the second area r2. However, the distance between a portion of the first area r1 to which the metal part 3a is bonded and a portion of the first area r1 to which the metal part 3b is bonded exceeds 3 mm. Therefore, the area between the portion of the first area r1 to which the metal part 3a is bonded and the portion of the first area r1 to which the metal part 3b is bonded is not included in the second area r2.

[0033] In addition, Figure 1 and Figure 2 In the figure, symbol 4 indicates a bonding layer provided on the first surface 2a. Symbol 5 indicates a metal portion. The metal portion 5 is also called a back metal portion. Symbol 6 indicates a bonding layer provided on the second surface 2b. The metal portion 3 may be directly bonded to the first surface 2a, or may be bonded to the second surface 2b. Figure 1 and Figure 2 As shown in FIG. 1 , the first surface 2a is bonded via the bonding layer 4. On the second surface 2b, the Figure 2 The metal part 5 may be directly bonded to the second surface 2b, or may be bonded to the second surface 2b as shown in FIG. Figure 2 As shown, the metal portion 5 is bonded to the second surface 2b via the bonding layer 6. The metal portion 5 can be used as a heat sink. The metal portion 5 is used to bond with a heat sink or a housing, etc., not shown. In the ceramic circuit substrate 1 according to the embodiment, the metal portion 5 can also be used as a circuit.

[0034] When the metal part 3 is bonded to the first surface 2a via the bonding layer 4, the bonding layer 4 preferably includes an exposed portion 4a. The exposed portion 4a is a portion of the bonding layer 4 that is exposed from the end of the metal part 3. When the bonding layer 4 includes the exposed portion 4a, the area of ​​the first surface 2a that is in contact with the exposed portion 4a is also included in the first region r1. The second region r2 is located between the first regions r1 that are in contact with the bonding layer 4 including the exposed portion 4a. In other words, the second region r2 is an area that does not overlap with any of the metal part 3 and the bonding layer 4 (including the exposed portion 4a) when viewed from the Z direction.

[0035] The ceramic circuit substrate 1 involved in the embodiment is characterized in that the average length RSm of the roughness curve element in the second region r2 of the first surface 2a is greater than 40μm. The so-called average length RSm of the roughness curve element is the average value of the length Xs of the profile curve element in the reference length. The average length RSm of the roughness curve element is specified in JIS-B-0601 (2013). As specified in JIS-B-0601 (2013), in the determination of the average length RSm of the roughness curve element, it is necessary to identify the minimum height and minimum length of the peak and valley. The standard value of the identifiable minimum height is set to 10% of the maximum height roughness Rz. The standard value of the identifiable minimum length is set to 1% of the reference length. After the peaks and valleys are determined in a manner that satisfies both of these two conditions, the average value of the length Xs of the profile curve element is obtained. Furthermore, JIS-B-0601 corresponds to ISO4287.

[0036] The average length RSm of the roughness curve element is greater than 40 μm, which means that one cycle of peaks and valleys is greater than 40 μm. The RSm in the second region r2 is greater than 40 μm, which means that one cycle of peaks and valleys is larger. As a result, when the ceramic circuit substrate 1 is molded with resin, the adhesion between the ceramic substrate 2 and the molding resin can be improved. In the previous ceramic substrate, RSm was as small as less than 40 μm. If the cycle of peaks and valleys is small, a microscopic gap is formed between the ceramic substrate 2 and the molding resin. Generally speaking, the thermal expansion coefficient of the molding resin is greater than the thermal expansion coefficient of the ceramic substrate 2. If the temperature of the ceramic substrate 2 and the molding resin changes due to the heat of the semiconductor element, stress is generated at the interface between the ceramic substrate 2 and the molding resin due to the difference in thermal conductivity. If there is a microscopic gap between the ceramic substrate 2 and the molding resin, the molding resin becomes easy to fall off from the ceramic substrate 2 due to the stress generated by the heat of the semiconductor element.

[0037] In addition, the molded resin near the second region r2 is easily affected by the heat of the semiconductor element mounted on the metal part. Generally speaking, the thermal conductivity of the metal part 3 is higher than the thermal conductivity of the ceramic substrate 2. The heat of the semiconductor element can be dissipated through the metal part 3. By providing the exposed portion 4a, the stress generated at the end of the metal part 3a is relieved. On the other hand, the heat transmitted to the metal part 3 is also transmitted to the second region r2 where the metal part 3 is not provided. Since the metal part 3 is not provided in the second region r2, the heat transmitted to the second region r2 is difficult to dissipate. Therefore, the temperature near the second region r2 is easy to rise. In addition, stress caused by the thermal expansion of the metal part 3 is also applied to the molded resin in contact with the second region r2. Therefore, between the second region r2 and the molded resin, the molded resin is more likely to fall off from the ceramic substrate 2 than in other parts.

[0038] According to the embodiment, by controlling RSm in the second region r2, the adhesion between the ceramic substrate 2 and the molding resin can be improved. If the adhesion between the ceramic substrate 2 and the molding resin is improved, when stress is applied to the molding resin in a direction parallel to the XY plane, the peaks and valleys on the surface of the second region r2 are hung on the molding resin. In other words, an anchoring effect is produced on the molding resin. As a result, the molding resin can be prevented from falling off the ceramic substrate 2. The embodiment is particularly effective for a ceramic circuit substrate where the interval between the metal parts 3 is less than 3 mm.

[0039] The upper limit of the average length RSm of the roughness curve element is not particularly limited, but is preferably 100 μm or less. If RSm is larger than 100 μm, it is possible that RSm control becomes difficult. Therefore, RSm in the second region r2 is preferably in the range of 40 μm or more and 100 μm or less, and more preferably in the range of 50 μm or more and 80 μm or less.

[0040] In addition, the maximum peak height Rp of the roughness curve in the second region r2 is preferably greater than 1.0 μm. The maximum valley depth Rv of the roughness curve in the second region r2 is preferably greater than 1.0 μm. The maximum peak height Rp of the roughness curve and the maximum valley depth Rv of the roughness curve are also specified in JIS-B-0601 (2013).

[0041] The maximum peak height Rp of the roughness curve is the height of the largest peak in the roughness curve. By setting Rp to be greater than 1.0 μm, the adhesion between the ceramic substrate 2 and the molding resin can be improved. If Rp is less than 1.0 μm, there is a possibility that the adhesion between the ceramic substrate 2 and the molding resin is reduced. There is no particular limit to the upper limit of Rp, but it is preferably less than 3.0 μm. If Rp is greater than 3.0 μm, there is a possibility that a place where the molding resin cannot enter is generated in the gap between the concave and convex surfaces in the second region r2. Therefore, Rp is preferably in the range of greater than 1.0 μm and less than 3.0 μm, and more preferably in the range of greater than 1.2 μm and less than 2.0 μm.

[0042] The maximum valley depth Rv of the roughness curve is the depth of the largest valley in the roughness curve. By setting Rv to be greater than 1.0 μm, the adhesion between the ceramic substrate 2 and the molding resin can be improved. If Rv is less than 1.0 μm, there is a possibility that the adhesion between the ceramic substrate 2 and the molding resin decreases. The upper limit of Rv is not particularly limited, but is preferably less than 3.0 μm. If Rv is greater than 3.0 μm, there is a possibility that a place where the molding resin cannot enter is generated in the gap between the concave and convex surfaces in the second region r2. Therefore, Rv is preferably in the range of greater than 1.0 μm and less than 3.0 μm, and more preferably in the range of greater than 1.2 μm and less than 2.0 μm. If the valley is deep, Rv becomes larger.

[0043] By controlling one or both of Rp and Rv in addition to controlling RSm, the adhesion between the ceramic substrate 2 and the molding resin can be further improved. The molding resin becomes more difficult to fall off from the ceramic substrate 2 .

[0044] RSm, Rp and Rv are measured by the method according to JIS-B-0601 (2013). The measurement conditions are set as measurement length: 4.0 mm, measurement speed: 0.6 mm / s, shape removal: least squares straight line, λs filter: yes, λs cutoff ratio: 300, cutoff category: Gaussian, cutoff wavelength (λc): 0.8 mm. When a measurement length of 4.0 mm cannot be ensured by one measurement, the measurement can also be performed in multiple times. In addition, the measurement direction of the average length RSm of the roughness curve element in the second region r2 is arbitrary. The 4.0 mm measurement length is the reference length.

[0045] In the ceramic circuit substrate 1 involved in the embodiment, the average length RSm of the roughness curve element in the second region r2 is controlled. For example, when the above-mentioned measurement conditions are followed, RSm is 40 μm or more regardless of which part of the second region r2 is measured. In addition, regardless of which part of the second region r2 is measured, Rp is preferably 1.0 μm or more. Regardless of which part of the second region r2 is measured, Rv is preferably 1.0 μm or more. Furthermore, in the first region r1 bonded to the metal portion 3, there may be a place where RSm is less than 40 μm.

[0046] In addition, the total area of ​​each second region r2 relative to the surface area of ​​the first surface 2a is preferably within a range of 5% or more and 50% or less. In other words, it is preferably 5(%) ≤ [total area of ​​the second region r2 / area of ​​the first surface 2a] × 100 ≤ 50(%). For example, in the case of a ceramic substrate with a 50 mm long side × 40 mm short side, the surface area of ​​the first surface 2a is 50 × 40 = 2000 mm. 2 When there is only one second region r2 in the first surface 2a, the area of ​​the second region r2 is equivalent to the above-mentioned "total area of ​​the second regions r2". When there are multiple second regions r2 in the first surface 2a, the total area of ​​each second region r2 is equivalent to the above-mentioned "total area of ​​the second regions r2". For example, Figure 1 to Figure 4 In the example shown, there are two second regions r2. The total area of ​​the two second regions r2 is the "total area of ​​the second regions r2".

[0047] By setting the total area of ​​the second region r2 within a range of 5% to 50% of the surface area of ​​the first surface 2a, it is possible to achieve both the adhesion of the molding resin and the securing of the mounting area of ​​the semiconductor element. If the total area of ​​the second region r2 is less than 5%, there is a possibility that the effect of improving the adhesion between the ceramic substrate 2 and the molding resin is insufficient. If the total area of ​​the second region r2 is larger than 50%, there is a possibility that the area for mounting semiconductor elements, etc. is insufficient. Therefore, the total area of ​​the second region r2 is preferably within a range of 5% to 50% of the surface area of ​​the first surface 2a, and more preferably within a range of 10% to 40%.

[0048] As the ceramic substrate 2, various substrates can be used. As the ceramic substrate, silicon nitride substrates, aluminum nitride substrates, aluminum oxide substrates, zirconium oxide substrates and alusil high silicon heat-resistant aluminum alloy substrates can be listed. The so-called alusil high silicon heat-resistant aluminum alloy substrate is a ceramic sintered body mixed with aluminum oxide and zirconium oxide. The thickness of the ceramic substrate is preferably 0.2 mm or more and 3 mm or less.

[0049] The three-point bending strength of the silicon nitride substrate is preferably 600 MPa or more. The thermal conductivity of the silicon nitride substrate is preferably 80 W / m·K or more. By increasing the strength of the silicon nitride substrate, the thickness of the substrate can be reduced. Therefore, the three-point bending strength of the silicon nitride substrate is preferably 600 MPa or more, more preferably 700 MPa or more. By using a silicon nitride substrate, the thickness of the substrate can be reduced to less than 2 mm, and further reduced to less than 0.40 mm.

[0050] The three-point bending strength of the aluminum nitride substrate is in the range of 300 to 450 MPa. On the other hand, the thermal conductivity of the aluminum nitride substrate is above 160 W / m·K. Since the strength of the aluminum nitride substrate is low, the preferred substrate thickness is 0.60 mm or more. The three-point bending strength of the alumina substrate is in the range of 300 to 450 MPa, but the alumina substrate is relatively cheap. The three-point bending strength of the Alusil high-silicon heat-resistant aluminum alloy substrate is as high as about 550 MPa, but the thermal conductivity is in the range of 30 to 50 W / m·K.

[0051] It is preferred to use a silicon nitride substrate as the ceramic substrate 2. Since the silicon nitride substrate has high strength, it can withstand the thermal shrinkage of the molding resin. In addition, by adopting a silicon nitride substrate with a thermal conductivity of 80 W / m·K or more, the heat dissipation can be improved. In addition, in the silicon nitride substrate, silicon nitride grains with an aspect ratio of 1.5 or more are the main body. By entanglement of slender silicon nitride grains, the strength of the ceramic substrate 2 can be improved. In addition, by irregularly orienting the slender silicon nitride grains, it becomes easy to control RSm.

[0052] Examples of the metal portion 3 include metal plates, thin films, and metallized films. A thin film refers to a conductive film formed by sputtering or plating, etc. A metallized film refers to a conductive film formed by applying a metal powder paste and firing it.

[0053] The metal part 3 is preferably a part processed from a metal plate. The thickness of the metal plate (metal part 3) is preferably 0.3 mm or more. Heat dissipation can be improved by thickening the metal plate. The current carrying capacity can also be improved. Therefore, the thickness of the metal plate is preferably 0.3 mm or more, and more preferably 0.6 mm or more. There is no particular upper limit to the thickness of the metal plate, but it is preferably 5 mm or less. If the thickness exceeds 5 mm, it is possible that the control of the inclined shape of the side of the metal part 3 becomes difficult. In addition, from the viewpoint of heat dissipation, a copper plate with a thickness of 0.3 mm or more is preferably used as the metal part 3. In addition, the thickness of the metal part 3 and the thickness of the metal part 5 are preferably 0.3 mm or more. By using a metal plate in the metal part 3, the current carrying capacity and heat dissipation of the metal part 3 can be improved on the basis of improving the adhesion between the metal part 3 and the molding resin.

[0054] As the metal plate, one or more selected from the group consisting of a copper plate, a copper alloy plate, an aluminum plate, and an aluminum alloy plate can be listed. A copper plate is preferably used as the metal plate. In addition, an oxygen-free copper plate is preferred. Oxygen-free copper has a copper purity of 99.96wt% or more as shown in JIS-H-3100. The thermal conductivity of copper is about 400W / m·K, and the thermal conductivity of aluminum is about 240W / m·K. Copper has a higher thermal conductivity than aluminum. By using a copper plate in the metal part 3, the heat dissipation of the metal part 3 is improved. In addition, the aluminum plate is preferably pure aluminum. Pure aluminum is shown in JIS-H-4000. Furthermore, JIS-H-4000 corresponds to ISO6361. JIS-H-3100 corresponds to ISO197, etc.

[0055] The ceramic substrate 2 and the metal part 3 are preferably joined together via a joining layer 4. The joining layer 4 is preferably a component formed by an active metal joining method. The so-called active metal joining method is a joining method using one or more active metals selected from Ti (titanium), Zr (zirconium), and Hf (hafnium). An active metal brazing material having copper (Cu) or silver (Ag) as the main component and containing an active metal can be used. The main component mentioned here is the component that is contained in the largest amount in the metal component of the brazing material.

[0056] The active metal brazing filler metal preferably contains Ag (silver) of more than 0 mass % and less than 60 mass %, Cu (copper) of more than 15 mass % and less than 70 mass %, Ti (titanium) or TiH2 (titanium hydride) of more than 1 mass % and less than 15 mass %. When both Ti and TiH2 are used, their total is set within the range of more than 1 mass % and less than 15 mass %. When both Ag and Cu are used, it is preferred that Ag is within the range of more than 20 mass % and less than 60 mass %, and Cu is within the range of more than 15 mass % and less than 40 mass %. As required, one or two of Sn (tin) or In (indium) may be contained in the active metal brazing filler metal in the range of more than 1 mass % and less than 50 mass %. In addition, as required, C (carbon) may be contained in the active metal brazing filler metal in the range of more than 0.1 mass % and less than 2 mass %.

[0057] The ratio of the active metal brazing filler metal composition is calculated based on the total of the mixed raw materials being 100 mass %. For example, when the active metal brazing filler metal is composed of three materials, Ag, Cu, and Ti, it is Ag+Cu+Ti=100 mass %. When the active metal brazing filler metal is composed of four materials, Ag, Cu, TiH2, and In, it is Ag+Cu+TiH2+In=100 mass %. When the active metal brazing filler metal is composed of five materials, Ag, Cu, Ti, Sn, and C, it is Ag+Cu+Ti+Sn+C=100 mass %.

[0058] Ag or Cu is a component that becomes the solder base material. Sn or In has the effect of lowering the melting point of the solder. C (carbon) has the effect of controlling the fluidity of the solder or controlling the structure of the bonding layer by reacting with other components. Therefore, as the components of the solder, Ag-Cu-Ti, Ag-Cu-Sn-Ti, Ag-Cu-Ti-C, Ag-Cu-Sn-Ti-C, Ag-Ti, Cu-Ti, Ag-Sn-Ti, Cu-Sn-Ti, Ag-Ti-C, Cu-Ti-C, Ag-Sn-Ti-C, Cu-Sn-Ti-C can be listed. In can also be used instead of Sn. Both Sn and In can also be used.

[0059] One or more selected from tungsten (W), molybdenum (Mo), and rhenium (Re) may be added to the active metal brazing filler metal in an amount of 0.1 mass % to 10 mass %. By adding tungsten, molybdenum, and rhenium, the fluidity of the active metal brazing filler metal can be controlled. Magnesium (Mg) may also be added to the active metal brazing filler metal.

[0060] The above-mentioned active metal brazing material is effective for joining copper plates. Preferably, the metal part 3 is a copper part, and preferably the ceramic substrate and the copper part are joined together via a bonding layer that does not contain Ag. The so-called bonding layer that does not contain Ag refers to a part formed by using an active metal brazing material to which Ag is not added. As an inevitable impurity, it may also contain Ag of less than 0.01 mass % (including zero as a detection limit). By adopting a bonding layer that does not contain Ag, the occurrence of Ag ion migration can be suppressed. The so-called Ag ion migration refers to the phenomenon that Ag in the bonding layer is ionized and moved when a voltage is applied in an environment with high humidity. If the Ag ions move, Ag is precipitated elsewhere. As a result, it becomes a cause of poor insulation. Among active metal brazing materials, Ag is most likely to undergo ion migration. By not using Ag in the bonding layer, Ag ion migration can be suppressed.

[0061] When the metal plate is an aluminum plate, an Al—Si or AlMg brazing filler metal is preferably used as the active metal brazing filler metal. The content of one or both of Si and Mg in the active metal brazing filler metal is preferably in the range of 0.1 mass % to 20 mass %.

[0062] The ceramic circuit board according to the embodiment can be used for a semiconductor device in which a semiconductor element is mounted on the metal portion 3. The ceramic circuit board preferably includes a molding resin.

[0063] Figure 7 It is a side view showing an example of a semiconductor device according to an embodiment. Figure 7 In the figure, reference numeral 1 denotes a ceramic circuit substrate, reference numeral 6 denotes a semiconductor element, reference numeral 7 denotes a molding resin, and reference numeral 10 denotes a semiconductor device. The semiconductor element 7 is mounted on the metal portion 3. Figure 7 2 shows an example of a semiconductor device 10 having two semiconductor elements 7 mounted thereon. The semiconductor device 10 according to the embodiment is not limited to this form. The number of semiconductor elements 7 is arbitrary. The semiconductor device 10 may also include bonding wires or lead frames, etc., which are not shown.

[0064] exist Figure 7 In the illustrated embodiment, the first surface 2a on which the semiconductor element 7 is mounted is covered with the mold resin 8. The mold resin 8 is not limited to this embodiment, and the metal portion 5 of the semiconductor device 10 may be covered with the mold resin 8.

[0065] The molding resin 8 has the function of protecting the semiconductor element 7 and wiring from external stress. In addition, the molding resin also has the function of protecting the semiconductor element 7 from external gases such as moisture. As the molding resin, a thermosetting resin is mainly used. As the thermosetting resin, epoxy resin, silicone resin, etc. can be listed.

[0066] As molding methods, transfer method, compression method and the like can be cited. The transfer method is a sealing method in which molten resin is injected into a mold and then solidified. A mold formed by the transfer method is called a transfer mold. The compression method is a sealing method in which resin is placed in the mold in advance, and then melted and solidified. A mold formed by the compression method is called a compression mold. Transfer molding is excellent in mass productivity because it is a method of injecting resin. Since transfer molding is accompanied by resin flow, there is a possibility of positional deviation of semiconductor elements and bonding leads. In the compression method, since the resin is injected into the mold in advance and melted, the influence on the positional deviation of semiconductor elements is small. On the other hand, the resin must be injected into the mold in advance. Therefore, the mass productivity using the compression method is lower than that of transfer molding.

[0067] In the ceramic circuit substrate involved in the embodiment, the average length RSm of the roughness curve element of the ceramic substrate surface in the gap between the metal parts is set to be greater than 40μm. Increase one cycle of peaks and valleys. Thus, the adhesion with the molding resin is improved. Regardless of which method is used, transfer molding or compression molding, the adhesion can be improved. For example, transfer molding is accompanied by resin flow. Even if the resin flows, by increasing one cycle of peaks and valleys in advance, the flowing resin gradually flows into the surface unevenness. Thus, the adhesion can be improved. In other words, it is suitable for a semiconductor device 10 having a molding resin 8.

[0068] In a semiconductor device having a molding resin, when measuring the average length RSm of the roughness curve element of the gap portion (metal portion inter-region), the average length RSm is measured after removing the molding resin. As a method of removing the molding resin, a chemical solution treatment that only dissolves the resin can be cited.

[0069] Next, a method for manufacturing the ceramic circuit board 1 according to the embodiment will be described. The method for manufacturing the ceramic circuit board 1 according to the embodiment is not limited as long as it has the above-mentioned configuration. Here, a method for manufacturing the ceramic circuit board 1 with a high yield will be described.

[0070] First, a joint body of a ceramic substrate 2 and a metal plate is prepared. The metal plate is disposed on one or both sides of the ceramic substrate 2. Preferably, the ceramic substrate 2 is one selected from a silicon nitride substrate, an aluminum nitride substrate, an aluminum oxide substrate, a zirconium oxide substrate, and an Alusil high silicon heat-resistant aluminum alloy substrate. Preferably, the metal plate is one or more selected from a copper plate, a copper alloy plate, an aluminum plate, and an aluminum alloy plate. In the joining of the ceramic substrate 2 and the metal plate, a method using an active metal joining method is preferred.

[0071] When the metal plate is a copper plate (including a copper alloy plate), the active metal brazing filler metal has Cu or Ag as the main component, and further contains one or more selected from Ti, Zr, and Hf. As required, one or more selected from Sn, In, or C (carbon) may also be added. When the metal plate is an aluminum plate, as the active metal brazing filler metal, Al-Si system and Al-Mg system brazing filler metals are preferably used. The preferred composition range of the active metal brazing filler metal is as described above.

[0072] The bonding step may include heating the laminate of the ceramic substrate and the metal plate at 600 to 980° C. in a vacuum or in an inert atmosphere. In the case of a vacuum, the pressure is preferably 10 -2 Pa or less. As an inactive atmosphere, a nitrogen atmosphere is preferred. In the bonding process in a vacuum, an intermittent furnace is preferably used. In the bonding process in an inactive atmosphere, a continuous furnace is preferably used. Through the bonding process, a bonded body in which the ceramic substrate 2 and the metal plate are bonded via the bonding layer 4 can be prepared.

[0073] Next, an etching process is performed. The etching process is performed to give the metal plate a circuit shape. By giving the metal plate a circuit shape, the above-mentioned metal portion 3 can be obtained. In addition, by giving the metal plate a circuit shape, a ceramic circuit substrate 1 can be manufactured. Furthermore, a metal plate pre-processed into a circuit shape can also be joined to the ceramic substrate 2. In this case, the etching process is not required, and the metal plate in the circuit shape is equivalent to the above-mentioned metal portion 3.

[0074] For the control of RSm, Rp, and Rv, it is effective to apply an etching process. In the bonding layer using an active metal brazing filler metal, a layer with Ag or Cu as the main component and a layer with an active metal as the main component can be formed. In the International Publication No. WO2019 / 054294 (Patent Document 4), as an etching process for a bonding layer using an active metal brazing filler metal, a method using a brazing filler metal etching process and a chemical polishing process is listed.

[0075] If a part of the copper plate is etched, a part of the bonding layer becomes exposed. In the solder etching process, the exposed part of the bonding layer is removed. In addition, when a part of the solder is exposed, there is a possibility that the surface of the exposed solder is oxidized. There is also a possibility that a reaction product is generated on the solder surface by the etching process of the copper plate. The chemical grinding process is performed to remove oxides or reaction products formed on the solder surface. By performing the chemical grinding process, the bonding layer can be efficiently removed in the solder etching process that is performed continuously.

[0076] For the control of RSm, increasing the etching amount of the solder etching solution is effective. As a method for increasing the etching amount of the solder etching solution, at least one method selected from increasing the etching rate of the solder etching solution, suppressing the decrease of the etching rate of the solder etching solution, and extending the etching time is effective.

[0077] As the solder etching solution, a solution with a pH of less than 6 containing hydrogen peroxide can be cited. In order to increase the etching rate of the solder etching solution, it is effective to increase the concentration of hydrogen peroxide water. The etching solution can also contain ammonium fluoride and a pH stabilizer in addition to hydrogen peroxide. As the pH stabilizer, one or more selected from HBF4, EDTA, NTA, CyDTA, DTPA, TTHA, GEDTA, tyrosine, dicarboxylic acids, tricarboxylic acids, hydroxy acids and their salts can be cited.

[0078] For suppressing the decrease in the etching rate of the solder etching solution, it is effective to add a new etching solution when the concentration of hydrogen peroxide solution changes by 5% by mass. Thus, the decrease in the etching rate of the solder etching solution can be suppressed. Prolonging the etching time of the solder etching is also effective for controlling RSm. As a goal, the time of one solder etching process is set to more than 15 minutes.

[0079] In addition, for the control of RSm, etc., it is effective to increase the removal amount of the bonding layer by a chemical polishing process. As a method for increasing the removal amount by a chemical polishing process, it is possible to cite increasing the concentration of hydrochloric acid or sulfuric acid and extending the time for the chemical polishing process. For example, when a combination of hydrogen peroxide and sulfuric acid is used in a solder etching solution, a method of setting the sulfuric acid to 5% by mass or more can be cited. When hydrochloric acid is used in a solder etching solution, a method of setting the hydrochloric acid to 7% by mass or more can be cited. It is also effective to set the time for the chemical polishing process to more than 5 minutes.

[0080] The above-mentioned solder etching process and chemical polishing process may also be performed in combination. That is, the above-mentioned method may be used in the chemical polishing process and the solder etching process respectively. In addition, the chemical polishing process and the solder etching process may also be performed alternately. In this case, it is effective to apply the above-mentioned method in the last chemical polishing process among a plurality of chemical polishing processes and to apply the above-mentioned method in the last solder etching process among a plurality of solder etching processes.

[0081] The final brazing material etching step becomes a step for completely removing the bonding layer. When the ceramic substrate 2 and the metal plate are bonded by the active metal bonding method, a layer composed mainly of active metal is formed. When Ti is used as the active metal and a silicon nitride substrate is used as the ceramic substrate, the layer composed mainly of active metal is a titanium nitride (TiN) layer. By forming a layer composed mainly of active metal in the bonding layer, the bonding strength is improved. On the other hand, since the layer composed mainly of active metal has conductivity, if it remains in the ceramic circuit substrate 1, it is possible to cause poor conduction between the metal parts 3. Therefore, it is necessary to remove the layer composed mainly of active metal. In the etching step or the chemical polishing step, by increasing the removal amount, the layer composed mainly of active metal and a portion of the surface of the ceramic substrate thereunder can be removed. Thus, RSm and the like can be controlled.

[0082] In the case where a metal plate having a circuit shape is bonded to the ceramic substrate 2 in advance without performing an etching process, it is effective to perform a chemical polishing process on the gap between the metal plates. In addition, it is also effective to perform a sandblasting and polishing process on the second region to control RSm, etc. as needed.

[0083] The ceramic circuit board 1 according to the embodiment can be manufactured through the above steps. The semiconductor device 10 can be manufactured by mounting the semiconductor element 7 and the like on the ceramic circuit board 1. The mold resin 8 is provided in the semiconductor device 10 as necessary.

[0084] (Examples 1 to 7, Comparative Examples 1 to 2)

[0085] A silicon nitride substrate was prepared as the ceramic substrate of Examples 1 to 6. The thermal conductivity of the silicon nitride substrate was 90 W / m·K and the three-point bending strength was 700 MPa. The vertical dimension of the silicon nitride substrate was 50 mm, the horizontal dimension was 40 mm, and the thickness was 0.32 mm. A copper plate with a thickness of 0.8 mm was prepared as the metal plate.

[0086] Next, an active metal bonding method was used to produce a bonded body of a silicon nitride substrate and a copper plate (silicon nitride circuit substrate). Copper plates with a thickness of 0.8 mm were bonded to both surfaces of the silicon nitride substrate. The composition of the active metal brazing material is shown in Table 1.

[0087] As the ceramic substrate of Example 7, an aluminum nitride substrate was prepared. The thermal conductivity of the aluminum nitride substrate was 170 W / m·K, and the three-point bending strength was 400 MPa. As the metal plate, a copper plate with a thickness of 0.4 mm was prepared. Using the active metal bonding method, copper plates with a thickness of 0.4 mm were bonded to both sides of the aluminum nitride substrate to manufacture a bonded body (aluminum nitride circuit substrate). In addition, as Comparative Example 1, a silicon nitride circuit substrate was manufactured. As Comparative Example 2, an aluminum nitride circuit substrate was manufactured.

[0088] Table 1

[0089] Active metal brazing filler metal (mass %) Example 1 <![CDATA[Ag(50)、Cu(35)、Sn(10)、TiH2(5)]]> Example 2 <![CDATA[Ag(43.9)、Cu(33)、Sn(15)、TiH2(8)、C(0.1)]]> Example 3 <![CDATA[Ag(60)、Cu(32)、Sn(5)、TiH2(3)]]> Example 4 <![CDATA[Cu(68)、Sn(20)、TiH2(12)]]> Example 5 <![CDATA[Cu(76.9)、Sn(15)、TiH2(8)、C(0.1)]]> Example 6 <![CDATA[Cu(70)、Sn(20)、TiH2(10)]]> Example 7 <![CDATA[Cu(74.8)、Sn(18)、TiH2(7)、C(0.2)]]> Comparative Example 1 <![CDATA[Ag(50)、Cu(35)、Sn(10)、TiH2(5)]]> Comparative Example 2 <![CDATA[Ag(59)、Cu(30)、Sn(8)、TiH2(3)]]>

[0090] Next, the copper plate is given a circuit shape by an etching process to form the metal portion 3. For the ceramic circuit board of the example, a method of increasing the etching amount of the brazing material etching solution or a method of increasing the removal amount by a chemical polishing process is adopted.

[0091] In the manufactured ceramic circuit board, the total area (%) of the second region r2 is shown in Table 2. The total area (%) of the second region r2 is calculated by (the total area of ​​each second region r2 / the surface area of ​​the first surface 2a) × 100 (%). The surface area of ​​the first surface 2a is 50 mm in length × 40 mm in width = 2000 mm 2 In addition, RSm, Rp, and Rv in the second region r2 were measured. The method for measuring RSm, Rp, and Rv is as described above.

[0092] Table 2

[0093]

[0094] In the ceramic circuit board of the example, RSm was set to 40 μm or more. In addition, Rp was set to 1.0 μm or more, and Rv was set to 1.0 μm or more. In Comparative Examples 1 and 2, RSm was set to less than 40 μm.

[0095] Next, semiconductor elements were mounted on the ceramic circuit boards of the examples and comparative examples to produce semiconductor devices. Molding resin was applied to the semiconductor devices. Ag migration characteristics and resin adhesion were measured for the semiconductor devices with the molding resin applied.

[0096] In the evaluation of Ag migration characteristics, a voltage was applied to the semiconductor device in a high temperature and high humidity atmosphere, and the occurrence rate of Ag migration traces was measured. As a measuring device, an electrochemical migration evaluation system manufactured by Espec was used. Under an environment of temperature 85°C and humidity 85%, an AC2000V applied voltage (peak voltage of 2820V) was applied to the semiconductor device for 40 consecutive hours. The presence or absence of Ag migration traces on the surface of the ceramic circuit substrate was investigated.

[0097] In each embodiment and each comparative example, 100 semiconductor devices were evaluated. In each example, the number of semiconductor devices with at least one Ag migration trace was counted. The example in which the counted number was 0 was regarded as "best". The example in which the counted number was 1 or more and 10 or less was regarded as "good". The example in which the counted number was 11 or more was regarded as "bad".

[0098] Regarding the resin adhesion, the presence of falling off of the molding resin after the TCT test (thermal cycle test) was measured. In the TCT test, -40℃×30 minutes→room temperature (25℃)×10 minutes→175℃×30 minutes→room temperature (25℃)×10 minutes was taken as one cycle, and the presence of falling off of the molding resin after 300 cycles was measured. The presence of resin falling off on the surface of the second region r2 was measured by ultrasonic flaw detection (SAT). The molding resin falling rate (%) was calculated by (total resin falling off in the second region r2 / total area of ​​the second region r2)×100. The results are shown in Table 3.

[0099] Table 3

[0100] Ag ion migration Molding resin shedding rate (%) Example 1 good 0 Example 2 good 0 Example 3 good 0 Example 4 optimal 0 Example 5 optimal 0 Example 6 optimal 2 Example 7 optimal 2 Comparative Example 1 bad 4 Comparative Example 2 bad 7

[0101] As can be seen from Table 3, in the semiconductor device of the embodiment, the adhesion between the ceramic substrate and the resin is good. Even if a recess is not provided in the copper plate as in Patent Document 2, the adhesion is improved. Therefore, according to the embodiment, it is possible to suppress the reduction in the area for mounting semiconductor elements.

[0102] As shown in Examples 6 and 7, if RSm deviates from the range of 40 μm or more and 100 μm or less, resin peeling occurs. Therefore, RSm is preferably within the range of 40 μm or more and 100 μm or less. In addition, in Examples 4 to 7 using low-Ag solder, Ag ion migration did not occur. Based on this point, it is preferred to use low-Ag solder. In other words, by using low-Ag solder, it is possible to take into account both suppressing Ag ion migration and improving the adhesion of the molding resin. In contrast, in Comparative Examples 1 and 2, the adhesion of the molding resin is reduced due to the small RSm.

[0103] The embodiments of the present invention may include the following configurations.

[0104] (Composition 1)

[0105] A ceramic circuit substrate, comprising:

[0106] a ceramic substrate having a first surface; and

[0107] a plurality of metal parts respectively provided in the plurality of first regions of the first surface,

[0108] The first surface has a second region located between adjacent first regions.

[0109] An average length RSm of the roughness curve elements in the second region is 40 μm or more.

[0110] (Composition 2)

[0111] The ceramic circuit board according to Configuration 1, wherein the average length RSm in the second region is 100 μm or less.

[0112] (Composition 3)

[0113] The ceramic circuit board according to any one of Configurations 1 to 2, wherein a maximum peak height Rp of a surface roughness curve in the second region is 1.0 μm or more.

[0114] (Composition 4)

[0115] The ceramic circuit board according to any one of Configurations 1 to 3, wherein a maximum valley depth Rv of a surface roughness curve in the second region is 1.0 μm or more.

[0116] (Composition 5)

[0117] The ceramic circuit board according to any one of Configurations 1 to 4, wherein the sum of the areas of the one or more second regions relative to the surface area of ​​the first surface is within a range of 5% to 50%.

[0118] (Composition 6)

[0119] The ceramic circuit substrate according to any one of Configurations 1 to 5, wherein the ceramic substrate is a silicon nitride substrate.

[0120] (Composition 7)

[0121] The ceramic circuit substrate according to any one of Configurations 1 to 6, wherein:

[0122] The plurality of metal parts are copper parts respectively,

[0123] The plurality of copper members are bonded to the plurality of first regions via a plurality of bonding layers not containing Ag, respectively.

[0124] (Composition 8)

[0125] The ceramic circuit board according to Configuration 7, wherein a maximum peak height Rp of a roughness curve in the second region is 1.0 μm or more, and a maximum valley depth Rv of the roughness curve is 1.0 μm or more.

[0126] (Composition 9)

[0127] The ceramic circuit board according to Configuration 8, wherein the sum of the areas of the one or more second regions relative to the surface area of ​​the first surface is within a range of 5% to 50%.

[0128] (Composition 10)

[0129] A semiconductor device comprising:

[0130] The ceramic circuit substrate according to any one of configurations 1 to 9; and

[0131] A semiconductor element is mounted on any one of the plurality of metal portions.

[0132] (Composition 11)

[0133] The semiconductor device according to Configuration 10 further comprises a molding resin covering the second region.

[0134] Several embodiments of the present invention are illustrated above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the scope of the main purpose of the invention. These embodiments and their modifications are included in the scope and main purpose of the invention, and are also included in the invention recorded in the claims and their equivalents. In addition, the above-mentioned embodiments can also be implemented by combining with each other.

[0135] Explanation of symbols

[0136] 1-Ceramic circuit substrate

[0137] 2-Ceramic substrate

[0138] 2a - Surface 1 (surface)

[0139] 2b - Side 2 (Back)

[0140] 3. 3a~3d - Metal part

[0141] 4 - Bonding layer

[0142] 5-Metal part (back metal part)

[0143] 6 - Bonding layer

[0144] 7-Semiconductor components

[0145] 8-Molding resin

[0146] 10-Semiconductor devices

[0147] r1 - Region 1

[0148] r2 - Area 2

Claims

1. A ceramic circuit substrate, comprising: a ceramic substrate having a first surface; and a plurality of metal parts respectively provided on the plurality of first regions of the first surface, The first surface has a second region located between adjacent first regions. An average length RSm of the roughness curve elements in the second region is 40 μm or more.

2. The ceramic circuit substrate according to claim 1, wherein: The average length RSm in the second region is 100 μm or less.

3. The ceramic circuit substrate according to claim 1 or 2, wherein: The maximum peak height Rp of the surface roughness curve in the second region is 1.0 μm or more.

4. The ceramic circuit substrate according to claim 1 or 2, wherein: The maximum valley depth Rv of the roughness curve of the surface in the second region is 1.0 μm or more.

5. The ceramic circuit substrate according to claim 1 or 2, wherein: The sum of the areas of the one or more second regions relative to the surface area of ​​the first surface is in a range of 5% to 50%.

6. The ceramic circuit substrate according to claim 1 or 2, wherein: The ceramic substrate is a silicon nitride substrate.

7. The ceramic circuit substrate according to claim 1 or 2, wherein: The plurality of metal parts are copper parts respectively, The plurality of copper members are bonded to the plurality of first regions via a plurality of bonding layers not containing Ag, respectively.

8. The ceramic circuit substrate according to claim 6, wherein: The maximum peak height Rp of the roughness curve in the second region is 1.0 μm or more, and the maximum valley depth Rv of the roughness curve is 1.0 μm or more.

9. The ceramic circuit substrate according to claim 6, wherein: The sum of the areas of the one or more second regions relative to the surface area of ​​the first surface is in a range of 5% to 50%.

10. A semiconductor device comprising: The ceramic circuit substrate according to claim 1 or 2; and A semiconductor element is mounted on any one of the plurality of metal portions.

11. The semiconductor device according to claim 10, wherein The invention further includes a molding resin covering the second region.

12. A semiconductor device comprising: The ceramic circuit substrate according to claim 9; and A semiconductor element is mounted on any one of the plurality of metal portions.

13. The semiconductor device according to claim 12, wherein: The invention further includes a molding resin covering the second region.

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