Circuit arrangement and method of operating circuit arrangement

Abstract

A circuit arrangement and a method of operating a circuit arrangement are disclosed wherein the circuit arrangement (900) comprises a first diode (110) and a semiconductor switching device (190) electrically connected in series between a first node (301) and a second node (302). A semiconductor switching device (190) controls a switching current including a forward current through the first diode and a load current. A second diode (210) and a calibration switching element (290) are electrically connected in series between the first node (301) and the second node (302). The voltage acquisition circuit (310) acquires a voltage difference between a first voltage between the first node (301) and the second node (302) when the semiconductor switching device (190) is turned on and the calibration switching element (290) is turned off and a second voltage between the first node (301) and the second node (302) when the calibration switching element (290) is turned on and the power semiconductor device (190) is turned off.

Description

Technical Field

[0001] The present disclosure relates to obtaining expected lifetime information about power semiconductor devices and includes circuit arrangements and methods of operating the circuit arrangements. Background Art

[0002] The electrical parameters of power semiconductor devices degrade over their lifetime due to continuous and changing temperature loads until the power semiconductor device fails. Preventive monitoring methods continuously determine the accumulated thermal load. Physical methods measure the temperature directly using thermal sensors thermally coupled to the power semiconductor device or through thermal imaging. Other methods monitor electrical parameters that are sensitive to temperature and infer information about the thermal load from the electrical parameters. Methods that monitor such temperature-sensitive electrical parameters (e.g., short-circuit saturation current or gate flatband voltage) usually require interrupting normal operation to apply monitoring control or are susceptible to noise.

[0003] There is a need to obtain information indicative of device degradation with high reliability and low circuit complexity. Summary of the invention

[0004] Embodiments of the present disclosure facilitate deriving information about expected lifetime based on measurements of voltage drop across power semiconductor switches, rather than estimating accumulated thermal load.

[0005] The circuit device according to the related disclosure includes a first diode and a semiconductor switch device which are electrically connected in series between a first node and a second node. The semiconductor switch device controls a switching current I SW , switching current I SW Including load current I L and a forward current I1 through the first diode. A second diode and a calibration switch element are electrically connected in series between the first node and the second node. The voltage acquisition circuit obtains a voltage difference ΔV between a first voltage V1 between the first node and the second node when the semiconductor switch device is turned on and the calibration switch element is turned off and a second voltage V2 between the first node and the second node when the calibration switch element is turned on and the power semiconductor device is turned off.

[0006] The voltage difference ΔV follows the on-resistance RDSOn of the semiconductor switching device, and the drift of the voltage difference ΔV accounts for the drift of the on-resistance RDSOn. The first diode decouples the voltage acquisition circuit from the high voltage in the load path of the semiconductor switching device. Measuring the second voltage through a compensation path with a second diode enables the adverse effect of the first diode on the measurement result to be minimized. The circuit arrangement can utilize resources that are already available for other purposes in a typical gate driver circuit and provide highly reliable life expectancy information with low circuit complexity.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are provided for further understanding of the embodiments and form an integral part of this specification. The accompanying drawings show embodiments of circuit arrangements and operating methods and together with the specification illustrate the principles of the embodiments. Additional embodiments are described in the following detailed description and in the claims. The features of the various embodiments may be combined with each other.

[0009] Figure 1 is a schematic circuit diagram of a circuit arrangement for obtaining expected lifetime information with strong thermal coupling between a first diode in a monitoring path and a second diode in a calibration path according to an embodiment.

[0010] Figure 2 is a schematic circuit diagram of a circuit arrangement having a desaturation control circuit for obtaining expected lifetime information according to an embodiment.

[0011] Figure 3 is a schematic circuit diagram of a circuit device having an acquisition control circuit for obtaining expected lifetime information according to an embodiment.

[0012] Figure 4 is a schematic circuit diagram of a circuit device for obtaining lifetime expectancy information having a gate driver stage and a junction voltage acquisition circuit according to an embodiment.

[0013] Figure 5 is a schematic circuit diagram of a circuit arrangement for obtaining expected lifetime information in which a monitoring path and a calibration path share a common current limiting resistor according to an embodiment.

[0014] Figure 6 is a schematic flow chart for illustrating a method for operating a circuit arrangement for obtaining life expectancy information according to another embodiment. DETAILED DESCRIPTION

[0015] In the following detailed description, reference is made to the accompanying drawings which form a part of this document and in which certain embodiments of semiconductor devices having active elements integrated in a high voltage terminal structure are shown as illustrations. Structural or logical changes may be made to the illustrated embodiments without departing from the scope of the present disclosure. For example, features shown or described for one embodiment may be used on other embodiments or used in combination with other embodiments to produce another embodiment. The present disclosure is intended to include such modifications and variations. The embodiments are described in a manner that should not be interpreted as limiting the scope of the appended claims. The drawings are not drawn to scale but are for illustration purposes only. Unless otherwise indicated, corresponding elements are represented by the same reference numerals in the various drawings.

[0016] The terms "having", "containing", "including", "comprising" and the like are open ended, and these terms indicate the presence of certain structures, elements or features, but do not preclude the presence of additional elements or features. The articles "a", "an" and "the" include both the plural and the singular unless the context clearly indicates otherwise.

[0017] The term "direct electrical connection" describes a permanent low resistance ohmic connection between electrically connected elements, such as a direct contact between the relevant elements, or a low resistance connection via metal and / or heavily doped semiconductor material.

[0018] The terms "signal connection" and "electrical coupling" include permanent low-resistance ohmic connections between electrically connected elements, such as direct contact between the relevant elements, or low-resistance connections via metal and / or heavily doped semiconductor materials, but do not exclude the presence of additional passive and / or active elements in the signal path between the "signal connected" elements or "electrically coupled" elements. For example, the additional elements may include resistors, resistive conductor lines, capacitors and / or inductors, transistors, semiconductor diodes, Schottky diodes, transformers, optocouplers, and other elements.

[0019] The term "power semiconductor device" refers to a semiconductor device having a high voltage blocking capability of at least 30 V (e.g., 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV, or higher) and having a nominal on-state current or forward current of at least 200 mA (e.g., 1 A, 10 A, or greater).

[0020] A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a voltage controlled device and includes all types of IGFETs (Insulated Gate Field Effect Transistors) having a gate electrode based on doped semiconductor material and / or metal and having a gate dielectric made of oxide and / or dielectric material other than oxide.

[0021] The safe operating area (SOA) is defined as the current conditions and voltage conditions under which a semiconductor device can be expected to operate without self-damage.

[0022] Ohmic contact refers to a non-rectifying electrical junction between two conductors, such as a semiconductor material and a metal. According to Ohm's law, an ohmic contact has a linear or nearly linear IV curve in the first and third quadrants of a current-voltage (IV) diagram.

[0023] Ranges given for physical dimensions include the boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value such as "at most" and "at least".

[0024] The term “on” should not be interpreted as meaning only “directly on.” Rather, if one element is “on” another element (e.g., a layer is “on” another layer or is “on” a substrate), additional components (e.g., additional layers) may be located between the two elements (e.g., if a layer is “on” a substrate, the additional layers may be located between the layer and the substrate).

[0025] Two adjacent doped regions in a semiconductor layer form a semiconductor junction. Two adjacent doped regions of the same conductivity type and having different dopant concentrations form a unipolar junction, such as an n / n+ or p / p+ junction along the boundary surface between the two doped regions. At the unipolar junction, the dopant concentration profile orthogonal to the unipolar junction may show a step or turning point where the dopant concentration profile changes from concave to convex, or vice versa. Two adjacent doped regions with complementary conductivity form a pn junction.

[0026] The accompanying drawings illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions can have the same or different absolute doping concentrations.

[0027] The present disclosure relates to a circuit arrangement including a first diode and a semiconductor switch device electrically connected in series between a first node and a second node, wherein the semiconductor switch device is configured to control a switching current I SW , switching current I SW Including load current I L and the forward current I1 through the first diode.

[0028] The first diode is connected between the first node and the switch node in a forward direction, wherein the anode of the first diode is oriented to the first node and the cathode is oriented to the switch node. One or more additional electrical components may be electrically connected in series with the first diode between the first node and the first diode. When current is drawn from the first node and absorbed at the second node, the drawn current flows through the first diode as a forward current I1.

[0029] The semiconductor switching device is connected between the switch node and the second node. One or more additional electrical components may be electrically connected in series with the first diode between the first node and the switch node.

[0030] The semiconductor switching device may be a single power semiconductor device. The power semiconductor device may be an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), an insulated gate field effect transistor (IGFET), such as a metal oxide semiconductor field effect transistor (MOSFET) or a silicon carbide MOSFET (SiC-MOSFET), or a high electron mobility transistor (HEMT), such as a gallium nitride hybrid drain embedded gate injection transistor (GaN-HDGIT).

[0031] The semiconductor switch device conducts and turns off the switching current I SW , switching current I SW Including the forward current I1 through the first diode and the load current I L . Load current I L Flows in the load circuit and is supplied to a switching node between the first diode and the semiconductor switching device.

[0032] The semiconductor switching device is part of a load circuit, which also includes a power supply and a load. The power supply may be capable of supplying a current of at least 100 mA at a voltage of at least 12 V. The load may include an inductive load, such as a transformer winding or a motor winding. When the semiconductor switching device is turned on, a forward current I1 flows through the first diode and the semiconductor switching device, and a load current flows through the load and the semiconductor switching device.

[0033] In a single switch configuration, the switch node may be directly connected to the positive power supply voltage. Alternatively, the semiconductor switch device may be a low-side switch, and the high-side switch may be electrically connected between the positive power supply voltage and the switch node. The negative power supply voltage and the second node may be directly electrically connected.

[0034] A second diode and a calibration switch element are electrically connected in series between the first node and the second node.

[0035] The second diode is connected between the first node and the calibration switch element in a forward direction, wherein the anode of the second diode is oriented to the first node and the cathode is oriented to the calibration switch element. When current is sourced from the first node and sunk at the second node, the sourced current flows through the second diode as a forward current I2.

[0036] The calibration switch element is connected between the second diode and the second node. One or more further electrical elements may be electrically connected in series with the second diode between the first node and the calibration switch element. One or more further electrical elements may be electrically connected between the calibration switch element and the second node.

[0037] When the calibration switch element is turned on, a forward current I2 flows through the calibration switch element via the second diode.

[0038] The calibration switch element may be a silicon IGFET.The calibration switch element may be a discrete device or part of an integrated gate driver circuit with a further integrated gate driver stage.

[0039] The circuit device also includes a voltage acquisition circuit configured to obtain a voltage difference ΔV between a first voltage V1 between the first node and the second node when the semiconductor switching device is turned on and the calibration switching element is turned off and a second voltage V2 between the first node and the second node when the calibration switching element is turned on and the power semiconductor device is turned off.

[0040] The voltage acquisition circuit or components of the voltage acquisition circuit may be integrated in an integrated circuit. For example, the voltage acquisition circuit may be integrated in a gate driver circuit.

[0041] The voltage acquisition circuit may include a constant current source that supplies a constant current to the first node. In a monitoring period, when the semiconductor switch device is turned on and not reverse biased, the constant current flows through a first path including a first diode and the semiconductor switch device. In a calibration period, when the calibration switch element is turned on and the semiconductor switch device is not reverse biased, the constant current flows through a second path including a second diode and the calibration switch element.

[0042] The first voltage V1 contains information about the voltage drop across the semiconductor switching device and the on-resistance RDSOn of the semiconductor switching device. The first diode decouples the voltage acquisition circuit from the load circuit controlled by the semiconductor switching device, but adds a temperature-dependent offset voltage to the voltage drop across the semiconductor switching device. Since it can be assumed that the second diode and the first diode are thermally coupled at least to a certain extent, and the thermal coefficients of both diodes are known, the second path with the second diode and the calibration switch element provides the possibility of compensating for the temperature-dependent offset voltage at least to a certain extent.

[0043] The drift in the compensation voltage reflects the drift of the voltage across the semiconductor switching device. By observing the trend of the compensation voltage over time for the same temperature and / or load current, a prediction of the expected remaining life can be made. For example, a rise in the average value of the compensation voltage by at least one characteristic amplitude within a predetermined period may indicate an impending failure. The characteristic amplitude and the predetermined period can be determined separately by comparative measurements for different types of semiconductor switching devices.

[0044] In some embodiments, the first diode and the second diode may be integrated into an integrated circuit together with other elements of the circuit device, such as integrated into an integrated circuit together with a voltage acquisition circuit and / or a calibration switch element. For example, the first diode and the second diode may be integrated into a gate driver circuit, which may further integrate a voltage acquisition circuit and / or a calibration switch element. In some examples, such an integrated circuit may be monolithically integrated on a single semiconductor substrate.

[0045] Depending on the embodiment, the first diode and the second diode are formed in the same semiconductor die, the first diode and the second diode are formed in different semiconductor dies integrated in the same package, or the first diode and the second diode are discrete devices comprising anode pins soldered to adjacent pads of the same circuit trace on a printed circuit board (PCB) or a direct bonded copper (DCB) substrate.

[0046] For example, the first diode and the second diode have cathode regions of the same size and the same doping formed in the same semiconductor die. In addition, the first diode and the second diode may have anode regions of the same size and the same doping formed in the same semiconductor die, or the cathode regions of the first diode and the second diode may extend as wells into a common anode region of uniform doping.

[0047] Alternatively, the first diode and the second diode are formed in different semiconductor dies that share common packaging elements (e.g., pins and / or mold packaging). Each semiconductor die includes an anode disk and a cathode disk, wherein the anode disks of the two semiconductor dies are soldered to the same anode pin, or wherein the anode disks are connected to the same anode pin by bonding wiring. Alternatively or additionally, the first diode and the second diode are embedded in the same package, for example sealed in the same mold.

[0048] Alternatively, the first diode and the second diode are separate discrete devices, each of which has at least one anode component pin and at least one cathode component pin. The component pins can be pin wiring for through-hole technology or terminal contacts for surface mounting technology (SMT). The anode component pin of the first diode is soldered to the first anode disk of the PCB or DBC substrate. The anode component pin of the second diode is soldered to the second anode disk of the PCB or DBC substrate. The first anode disk can be adjacent to the second anode disk, wherein there is no additional solder disk closer to the first anode disk than the second anode disk. The circuit trace between the first anode disk and the second anode disk does not show shrinkage and bending.

[0049] A strong thermal coupling is generated between the first diode and the second diode. The thermal coupling between the first diode and the second diode may be stronger than between the first diode and any other active element of the circuit arrangement.

[0050] According to an embodiment, the thermal coupling between the first diode and the second diode is configured to limit a difference between a first junction temperature of the first diode and a second junction temperature of the second diode to a value of maximum 20 degrees Celsius during operation of the circuit arrangement.

[0051] The first diode and the second diode are thermally coupled to each other sufficiently strongly that a difference between a first junction temperature of the first diode and a second junction temperature of the second diode during operation is no greater than 20 degrees Celsius.

[0052] For example, during operation under conditions within the safe operating region, the difference between the first junction temperature and the second junction temperature is no greater than 10 degrees Celsius or 5 degrees Celsius.

[0053] According to an embodiment, the first diode and the second diode have the same nominal device parameters.

[0054] The device parameters of the first diode and the device parameters of the second diode deviate from each other only due to process defects. The first diode and the second diode have the same or at least almost the same forward voltage characteristics and the same or almost the same thermal coefficient relative to the forward voltage.

[0055] The thermal coupling between the first diode and the second diode is strong enough and the thermal coefficient relative to the forward voltage is sufficiently identical so that for the same forward current, the voltage drop across the first diode and the voltage drop across the second diode are the same regardless of temperature. Subtracting the second voltage from the first voltage compensates for the temperature-related effect of the first diode on the measurement of the voltage drop across the semiconductor switching device. Information about the on-resistance RDSOn can be obtained without complex characterization or estimation of the voltage drop in the first path.

[0056] When the first diode and the second diode have approximately the same thermal coefficient for forward voltage, and when the pn junction of the first diode and the pn junction of the second diode are approximately the same, then the same diode current causes an equal amount of voltage drop across the first diode and the second diode.

[0057] According to an embodiment, the voltage acquisition circuit may be configured to obtain a voltage difference ΔV between the first voltage V1 and the second voltage V2 as the compensation voltage. The influence of the temperature of the first diode on the quality of the expected lifetime estimation may be significantly reduced.

[0058] According to an embodiment, the circuit arrangement may further include a desaturation control circuit configured to output a valid desaturation signal when the semiconductor switching device is turned on, the blanking time has elapsed, and the first voltage V1 exceeds a desaturation threshold voltage.

[0059] The desaturation control circuit monitors the voltage across the conducting semiconductor switching device, wherein an effective desaturation signal indicates that the load current through the semiconductor switching device is high enough to indicate an overcurrent condition of the semiconductor switching device. If the semiconductor switching device is an IGBT, the overcurrent condition indicates desaturation of the IGBT. If the semiconductor switching device is a MOSFET, the overcurrent condition indicates saturation of the MOSFET. The effective desaturation signal is typically used to turn off the semiconductor switching device before the semiconductor switching device is irreversibly damaged and / or to signal a fault to a higher level instance in the system.

[0060] The voltage detection input of the desaturation control circuit needs to be protected against high supply voltages in the load circuit of the semiconductor switching device. The first diode can be used for online monitoring of the voltage drop across the semiconductor switching element for both obtaining the expected lifetime information and for desaturation detection, making the circuit overhead for obtaining the expected lifetime information small.

[0061] The blanking time is chosen to be long enough to avoid erroneous desaturation detection close to the turn-on time of the semiconductor switching device.

[0062] The desaturation control circuit or elements of the desaturation control circuit may be integrated in an integrated circuit. For example, some of the elements of the desaturation control circuit may be integrated in a gate driver circuit.

[0063] According to an embodiment, the circuit arrangement may further include an acquisition control circuit configured to control the voltage acquisition circuit to acquire and / or process the compensation voltage when a predetermined condition is met.

[0064] The predetermined condition may be an active signal of a measurement start signal received from outside the circuit arrangement or generated within the circuit arrangement in response to a change in operating conditions or in response to a regular clock signal. The predetermined condition may be derived from information about the instantaneous temperature or load current.

[0065] In order to obtain the compensation voltage, a new measurement of at least the first voltage V1 is triggered. For the second voltage V2, a previously obtained value can be used. Alternatively, a new measurement of both the first voltage V1 and the second voltage V2 is triggered, wherein the measurement of the second voltage V2 can be before or after the measurement of the first voltage V1. The two measurements can be separated by one or more complete switching cycles.

[0066] According to an embodiment, for each complete measurement, in an off-state period directly preceding an on-state period in which the first voltage V1 is measured, the measurement of the second voltage V2 may precede the measurement of the first voltage V1. Alternatively, in an off-state period directly following an on-state period in which the first voltage V1 is measured, the measurement of the second voltage V2 may follow the measurement of the first voltage V1.

[0067] The acquisition control circuit or elements of the acquisition control circuit may be integrated in an integrated circuit. For example, some of the elements of the acquisition control circuit may be integrated in a gate driver circuit.

[0068] According to an embodiment, the circuit arrangement may further include a processing circuit configured to receive information about the compensation voltage, generate expected lifetime information based on the compensation voltage obtained at different time points, and output the expected lifetime information.

[0069] When the first diode and the second diode are of the same type and have inherently the same forward voltage thermal coefficient, the compensation voltage may be a voltage difference ΔV between the first voltage and the second voltage.

[0070] The processing circuit can also receive information about the instantaneous load current. The processing circuit can be L Results of multiple measurements of the voltage drop across the semiconductor switching device and the on-resistance RDSon performed under the present invention are compared with empirical data of long-term on-resistance gradients indicative of impending failure.

[0071] The processing circuit or elements of the processing circuit may be integrated in an integrated circuit. For example, the processing circuit or some of the elements of the processing circuit may be integrated in a gate driver circuit.

[0072] According to an embodiment, the circuit arrangement may further include a gate driver stage configured to output a gate signal to the semiconductor switching device, wherein the gate signal varies between an active voltage level turning on the semiconductor switching device and an inactive voltage level turning off the semiconductor switching device.

[0073] The gate driver stage is capable of charging and discharging the gate capacitance effective at the gate input of the semiconductor switching device fast enough to achieve a desired switching frequency in the load circuit.The gate driver stage or elements of the gate driver stage may be integrated in a gate driver circuit.

[0074] According to an embodiment, the circuit arrangement may include a gate voltage acquisition circuit configured to obtain and output gate voltage information about an instantaneous effective voltage level of a gate signal.

[0075] The on-resistance RDSon and the voltage drop across the conducting semiconductor switching device in the on state depend on the effective voltage level of the gate signal (effective signal level). Knowing the current effective signal level of the gate signal allows to improve the expected lifetime information. If the effective voltage level has not changed since the beginning of the operating lifetime, the expected lifetime information derived from the compensation voltage may potentially be marked as more reliable than otherwise.

[0076] The gate voltage acquisition circuit or elements of the gate voltage acquisition circuit can be integrated in the gate driver circuit. If the IGFET has a conversion function that gives the drain-source voltage VDS as a function of the gate-source voltage VGS, or the IGBT has a conversion function that gives the collector-emitter voltage VCE as a function related to the gate-emitter voltage VGE, the gate voltage information can be used to refine the expected lifetime information. By way of example, the conversion function can be stored locally in the gate voltage acquisition circuit, the voltage acquisition circuit or the processing circuit.

[0077] For example, the gate voltage acquisition circuit can obtain the gate voltage information based on the measurement of the gate voltage, the measurement of the voltage at the gate plate of the gate driver, the measurement of the voltage at the gate signal output terminal of the gate driver stage, the measurement of the voltage at the gate signal output terminal of the gate driver circuit, the voltage at the gate terminal of the semiconductor switching device and / or the measurement of the power supply voltage of the voltage source of the gate driver circuit.

[0078] According to an embodiment, the circuit arrangement may further include a junction voltage acquisition circuit configured to obtain a third voltage V3 between the first node and the second node when the calibration switching element is turned off and the semiconductor switching device is reverse biased and turned off.

[0079] When the load in the load circuit includes an inductor, the semiconductor switching device may be reverse biased. The inductor has a tendency to oppose changes in the load current flowing through the inductor. For example, when one of the switches is turned off in a full bridge or H-bridge having four switches and a freewheeling diode in parallel with each switch, the inductor may drive current through the freewheeling diode of one of the other turned-off switches to provide a path for current dissipation, thereby reverse biasing the corresponding switch.

[0080] If the semiconductor switching device comprises a body diode which is in forward conduction mode when the semiconductor switching device is reverse biased, for example if the semiconductor switching device is a reverse conducting IGBT (RC-IGBT) or an IGFET, such as a MOSFET, the third voltage V3 gives information about the forward voltage of the body diode of the semiconductor switching device. The forward voltage of the body diode can be monitored in situ during operation of the device.

[0081] Similar to the way in which the (first) compensation voltage is obtained based on the first voltage V1, the second compensation voltage can be obtained based on the third voltage V3. For example, in the case of two thermally strongly coupled diodes of the same type, the second compensation voltage is obtained by subtracting the second voltage V2 obtained from the second path during the calibration period from the third current V3.

[0082] The junction voltage acquisition circuit or elements of the junction voltage acquisition circuit may be integrated in the gate driver circuit. If the IGFET has a degradation function that gives the degradation as a function of the body diode forward voltage, the body diode forward voltage may be used to refine the expected lifetime information. By way of example, the degradation function may be stored locally in the junction voltage acquisition circuit, the voltage acquisition circuit or the processing circuit.

[0083] Alternatively or additionally, the body diode forward voltage can be used to obtain information about the instantaneous temperature in the IGFET and / or about the total thermal budget to which the semiconductor switching device has been subjected since the beginning of its operating lifetime.

[0084] According to an embodiment, the processing circuit may be further configured to receive information about the third voltage V3 and / or gate voltage information, generate expected lifetime information based on the voltage difference ΔV, the third voltage V3 and / or the gate voltage information, and output the expected lifetime information.

[0085] The same circuit elements provide information about the current, gate voltage, and body diode forward voltage of the on-resistance. In addition to sharing circuit resources, embodiments provide a large number of independent sources of information about the degradation state of the device. Embodiments can provide highly accurate lifetime predictions with low circuit complexity.

[0086] According to an embodiment, the voltage acquisition circuit may include a constant current source configured to supply a constant current at the first node.

[0087] The constant current source may include a resistive element having a first terminal connected to a positive low power supply voltage or a medium power supply voltage and a second terminal connected to a first node. Alternatively, the constant current source may include a FET having a controlled path electrically connected between the positive low power supply voltage or the medium power supply voltage and the first node.

[0088] The constant current source may be a discrete component, or may be integrated in an integrated circuit, for example in a gate driver circuit.

[0089] According to an embodiment, the circuit arrangement may include a current limiting resistor, wherein a first terminal of the current limiting resistor is electrically connected to the first node, and wherein a second terminal of the current limiting resistor is electrically connected to an anode of the first diode and an anode of the second diode.

[0090] In combination with the gate capacitance of the semiconductor switching device, the current limiting resistor defines the switching speed of the semiconductor switching device. The resistance value is selected according to the application requirements. By placing the current limiting resistor between the second node and the anodes of both the first diode and the second diode, the effect of the current limiting resistor on the measured voltage drop across the semiconductor switching device can be fully compensated by subtracting the second voltage V2 from the first voltage V1.

[0091] The present disclosure also relates to a method of operating a circuit device. The method includes supplying a constant current ISRC to a first path, the first path including a first diode and a semiconductor switch device electrically connected in series between a first node and a second node, wherein the semiconductor switch device controls the constant current ISRC and a load current I L The switching current I SW A first voltage V1 caused by a constant current between the first node and the second node is determined. The method also includes supplying a constant current ISRC to a second path including a second diode and a calibration switching element electrically connected in series between the first node and the second node. A second voltage V2 caused by a constant current between the first node and the second node is determined. The method also includes outputting information about a compensation voltage obtained based on the first voltage V1 and the second voltage V2.

[0092] The first voltage V1 includes information about the voltage drop across the semiconductor switching device in the on state and the forward voltage of the first diode, wherein the forward voltage of the first diode is a function of temperature. The compensation voltage is obtained by at least partially compensating the effect of the first diode on the measurement of the voltage drop across the semiconductor switching device using the second voltage V2, wherein the compensation uses information about the temperature dependency of the forward voltages in the first diode and the second diode and about a possible temperature difference between the first diode and the second diode.

[0093] According to an embodiment, a voltage difference ΔV between the first voltage V1 and the second voltage V2 is determined as a compensation voltage.

[0094] The stronger the thermal coupling between the first diode and the second diode, and the smaller the difference in forward voltage temperature coefficients of the first diode and the second diode for a given forward current, the better the effect of the second diode on the measurement of the voltage drop across the semiconductor switching device, which can be compensated by simply subtracting the second voltage from the first voltage.

[0095] According to an embodiment, the method may further include generating an effective desaturation signal when the semiconductor switching device is turned on, the blanking time elapses, and the first voltage V1 exceeds a desaturation threshold voltage. The method uses the first diode for both desaturation detection and life expectancy estimation.

[0096] According to an embodiment, the second voltage V2 may be obtained and / or processed when a predetermined condition is met. The predetermined condition may be derived from information about the instantaneous temperature, the instantaneous load current and / or a timer signal.

[0097] According to an embodiment, the method may further include generating and outputting expected lifetime information based on a compensation voltage, such as a voltage difference ΔV, if the thermal coupling between the first diode and the second diode is sufficiently strong.

[0098] According to an embodiment, the method may further include supplying a gate signal to the semiconductor switching device, wherein the gate signal varies between an active voltage level that turns on the semiconductor switching device and an inactive voltage level that turns off the semiconductor switching device.

[0099] According to an embodiment, the method may further include obtaining and outputting gate voltage information about an instantaneous effective voltage level of the gate signal.

[0100] According to an embodiment, the method may further include obtaining a third voltage V3 between the first node and the second node when the calibration switching element is turned off and the semiconductor switching device is reverse biased.

[0101] According to an embodiment, the method may further include generating expected lifetime information based on the compensation voltage, the third voltage V3 and / or the gate voltage information, and outputting the expected lifetime information.

[0102] Figure 1 A circuit arrangement 900 is shown having a semiconductor switching device 190. The semiconductor switching device 190 shown is a MOSFET. Alternatively, the semiconductor switching device 190 may be an IGBT, a HEMT or a GIT. The semiconductor switching device 190 is part of a load circuit which also includes a power voltage source and a low resistance load.

[0103] The power voltage source supplies a DC supply voltage of at least 12V, 30V, 60V, 100V at a load current of at least 100mA, 1A or 3A. The positive supply voltage is supplied through the first load terminal 191. Depending on the application, the positive supply voltage is supplied directly, supplied through another semiconductor switch or supplied through a low resistance load to the first load terminal 191. The negative supply voltage is supplied to the second load terminal 192.

[0104] The low resistance load may include an inductor, such as a motor winding or a transformer winding, and may be a single switch configuration or a multi-switch configuration. For example, the low resistance load may be a load having a current direction controlled by a switch in a full bridge or H-bridge configuration. A first terminal of the low resistance load is connected to a first load terminal 191. Depending on the switch configuration, a second terminal of the low resistance load may be connected to a positive supply voltage, to a second load terminal 192, or to a switch node of a second half bridge in the case where the semiconductor switching device 190 is a low-side switch in a first half bridge.

[0105] The first path (monitoring path) 100 between the first node 301 and the second node 302 includes a controlled load path of a first diode 110 and a semiconductor switching device 190 electrically connected in series. The anode of the first diode 110 is electrically connected to the first node 301. The cathode of the first diode 110 is electrically connected to the switch node 150. The switch node 150 is electrically connected to the drain or collector of the semiconductor switching device 190 and the first load electrode 191. The source or emitter of the semiconductor switching device 190 is connected to the second load electrode 192 and the second node 302. The gate of the semiconductor switching device 190 is connected to the gate terminal 193.

[0106] The semiconductor switch device 190 controls the switch current I SW , switching current I SW The forward current I1 passing through the first diode and the load current I flowing in the load circuit and supplied through the switch node 150 are included. L .

[0107] In response to the active gate signal received through the gate terminal 193, the semiconductor switch device 190 is turned on. When the semiconductor switch device 190 is turned on, the switching current I SW flows through the semiconductor switch device 190, wherein the switching current I SW The forward current I1 through the first diode 110 and the load current I L .

[0108] The second path 200 between the first node 301 and the second node 302 comprises a controlled load path of a second diode 210 and a calibration switching element 290 electrically connected in series. In the illustrated embodiment, the calibration switching element 290 is a MOSFET.

[0109] The anode of the second diode 210 is electrically connected to the first node 301. The cathode of the second diode 210 is electrically connected to the drain of the calibration switch element 290. The source of the calibration switch element 290 is connected to the second node 302. When the calibration switch element 290 is turned on, the forward current I2 through the second diode 210 flows through the calibration switch element 290.

[0110] The first diode 110 and the second diode 210 have the same device type, the same specifications, and are from the same batch or lot. The first diode 110 and the second diode 210 have the same forward voltage under the constant current ISRC supplied from the voltage acquisition circuit 310. The first diode 110 and the second diode 210 form a diode device 400, which provides a strong thermal coupling between the first diode 110 and the second diode 220. If the first diode 110 and the second diode 210 are discrete components, the anode leads of the first diode 110 and the second diode 210 are welded to contact pads arranged closely adjacent to each other, and are directly connected to each other through short-circuit traces.

[0111] The voltage acquisition circuit 310 is electrically connected to the first node 301, the second node 302 and the gate of the calibration switch element 290. The voltage acquisition circuit 310 supplies a constant current ISRC to the first node 301 and measures the voltage between the first node 301 and the second node 302 at least in the monitoring period and the calibration period.

[0112] In the monitoring period, the voltage acquisition circuit 310 and the semiconductor switch device 190 are turned on, and the calibration switch element is turned off. The voltage acquisition circuit 310 measures the first voltage V1 caused by the constant current ISRC flowing through the first path 100.

[0113] During the calibration period, the voltage acquisition circuit 310 generates a valid calibration signal. The calibration signal is valid only when the semiconductor switch device 190 is turned off and in a voltage blocking mode, where no freewheeling current flows through the parallel freewheeling diode and / or body diode of the semiconductor switch device 190. When the calibration switch element 290 receives a valid calibration signal, the calibration switch element 290 is turned on. Outside the calibration period, the calibration signal is non-valid and the calibration switch element 290 is turned off. During the calibration period, the voltage acquisition circuit 310 measures the second voltage V2 caused by the constant current ISRC flowing through the second path 200.

[0114] According to equation (1), the first voltage V1 is the temperature-dependent forward voltage VFV1 (T, ISRC) of the first diode 110 and the voltage drop VSWon (T, I SW ) and:

[0115] V1=VFV1(T,ISRC)+VSWon(T,I SW ) (1)

[0116] According to equation (2), the voltage V2 is the sum of the temperature-dependent forward voltage VFV2(T) of the second diode 210 and the voltage drop VCALon(T, ISRC) across the calibration switch element 290 in the on state:

[0117] V2=VFV2(T,ISRC)+VCALon(T,ISRC) (2)

[0118] If the first diode 110 and the second diode 210 are identical and have the same junction temperature, and if the same constant current ISRC is supplied to the first node 301 during the monitoring period and the calibration period, the voltage drops VFV1(T, ISRC) and VFV2(T, ISRC) are identical, and the effect of the first diode 110 on the measurement of the on-resistance RDSon can be fully compensated by subtracting the second voltage V2 from the first voltage V1 according to equations (3), (4) and (5):

[0119] ΔV=V1-V2 (3)

[0120] ΔV=VFV1(T,ISRC)+VSWon(T,I SW )-VFV2(T,ISRC)-VCALon

[0121] (T, ISRC)(4)

[0122] ΔV=VSWon(T,I SW )-VCALon(T,ISCR) (5)

[0123] The voltage drop VSWon(T, ISRC) across the semiconductor switch device 190 in the on state is determined by the constant current ISRC supplied by the voltage acquisition circuit 310, the load current I L , the on-resistance RDSon,Q1 of the semiconductor switch device and the on-impedance RDSon,Q2 of the calibration switch element 290 are given as shown in equation (6):

[0124] ΔV = RDSon,Q1 * (I L + ISRC) - RDSon,Q2 * ISRC (6)

[0125] The value of the constant current ISRC supplied by the voltage acquisition circuit 310 and the value of the on-resistance RDSon,Q2 of the calibration switching element 290 are inherently known and can be stored locally in the voltage acquisition circuit 310. L The constant current ISRC is exceeded by more than two orders of magnitude, and equation (5) can be approximated by equation (7):

[0126] ΔV = RDSon,Q1 * I L (7)

[0127] About the instantaneous load current I L The information is often useful and / or can be obtained from a current sensing element integrated in the semiconductor switching device 190 or otherwise in the load circuit.

[0128] Subtracting the second voltage V2 from the first voltage V1 compensates for the measurement of the voltage drop across the semiconductor switching device 190 by the first diode 110 and the temperature-related effects on the on-resistance R DSon,Q1 of the semiconductor switching device 190 without requiring complex characterization or estimation of the voltage drop in the first path 100 .

[0129] During normal operation, the compensation voltage is obtained on-site multiple times at regular intervals. The change of the compensation voltage over time is analyzed. The drift in the compensation voltage reflects the drift of the on-resistance RDSon,Q1 of the semiconductor switching device 190. Based on the characteristic drift of the on-resistance RDSon,Q1, a prediction about the expected remaining life can be made. For example, a sharp rise in the average value of the compensation voltage by at least a certain characteristic magnitude within a predetermined period may indicate an impending failure.

[0130] The characteristic magnitude and predetermined period may be predetermined by comparative measurements of different types of semiconductor switching devices, and may depend on the load current in the application and the typical junction temperature during operation.

[0131] The voltage acquisition circuit 310 and the calibration switch element 290 may be integrated in an integrated circuit. For example, the voltage acquisition circuit 310 and the calibration switch element 290 are integrated in a gate driver circuit 800 having a terminal 810 for accessing the first node 301 , the second node 302 and the drain of the calibration switch element 290 .

[0132] exist Figure 2 In the embodiment of the present invention, the circuit device 900 includes a desaturation control circuit 320. The desaturation control circuit 320 includes a comparison circuit 321 and a desaturation clamp switch 325.

[0133] When the semiconductor switching device 190 is turned off, the active clamp enable signal turns on the desaturation clamp switch 325. After the semiconductor switching device 190 is turned on, the clamp enable signal remains active until the blanking time elapses. The blanking time ensures that no accidental tripping occurs when the semiconductor switching device 190 is turned on. When the blanking time elapses, the clamp enable signal becomes inactive and the desaturation clamp switch 325 turns off, thereby releasing the clamp.

[0134] When the clamp is released, the voltage at the first node 301 follows the voltage at the switch node 150. The comparison circuit 321 compares the voltage at the first node 301 with a desaturation threshold voltage.

[0135] If the semiconductor switching device 190 is a bipolar semiconductor switching device, the semiconductor switching device 190 is generally saturated when the semiconductor switching device 190 is turned on. When the semiconductor switching device 190 exceeds the maximum rated current, the bipolar semiconductor switching device 190 is considered to be oversaturated. The voltage across the semiconductor switching device 190 increases, and the voltage at the first node 301 increases accordingly.

[0136] If the semiconductor switching device 190 is a unipolar device that conducts using only one type of charge carrier, such as a SiC-MOSFET, the semiconductor switching device 190 is not necessarily saturated when the semiconductor switching device 190 is turned on. However, when the semiconductor switching device 190 exceeds the maximum rated current, the unipolar semiconductor switching device 190 may be saturated. The voltage across the semiconductor switching device 190 increases, and the voltage at the first node 301 increases accordingly.

[0137] If the voltage at the first node 301 exceeds the desaturation threshold voltage during the on-state of the semiconductor switching device 190 , the comparison circuit 321 outputs an effective desaturation signal. In response to the effective desaturation signal, another logic circuit may initiate a safety shutdown procedure to protect the semiconductor switching device 190 .

[0138] The measurement of the first voltage V1 and the comparison with the desaturation threshold voltage may be performed simultaneously and may share some circuit elements other than the first diode 110, such as an analog-to-digital converter (ADC) that converts the voltage at the first node 301 to a digital value. For the measurement of the second voltage V2, the desaturation clamp is released and the desaturation clamp switch 325 is turned off. Alternatively, the second diode 210 and the calibration switch element 290 may be used as the desaturation clamp.

[0139] Figure 3 The circuit arrangement shown includes an acquisition control circuit 330 and a processing circuit 390 .

[0140] The acquisition control circuit 330 includes a timer 335, and the timer 335 controls the acquisition control circuit 330 to output a valid acquisition signal each time a timing condition is met. In response to the valid acquisition signal, the voltage acquisition circuit 310 triggers the measurement of the first voltage V1, and may also trigger the measurement of the second voltage V2, and obtains information about the voltage difference ΔV based on the newly obtained first voltage V1 and the last obtained second voltage V2.

[0141] The processing circuit 390 receives information about the voltage difference ΔV. The processing circuit 390 outputs information about the voltage difference ΔV and / or expected lifetime information obtained from the voltage difference ΔV through the data interface. The expected lifetime information may be based on additional information locally stored and accessible by the processing circuit 390 and / or information obtained from further measurements.

[0142] Figure 4 A circuit arrangement 900 including a gate driver stage 340 and a gate voltage acquisition circuit 350 is shown.

[0143] The gate driver stage 340 outputs a gate signal at a gate signal output terminal. The voltage level of the gate signal varies between an inactive low level for turning off the semiconductor switching device 190 and an active high level for turning on the semiconductor switching device 190. The gate resistor 341 is electrically connected between the gate signal output terminal of the gate driver stage 340 and the gate of the semiconductor switching device 190.

[0144] The gate voltage acquisition circuit 350 obtains gate voltage information about the instantaneous effective voltage level of the gate signal. For example, the gate voltage acquisition circuit 350 may include an ADC that converts the voltage of the effective gate signal at the gate signal output terminal of the gate driver stage 340 or at the gate of the semiconductor switching device 190 into a digital value.

[0145] The circuit arrangement 900 further includes a junction voltage acquisition circuit 360. The junction voltage acquisition circuit 360 obtains a third voltage V3 between the first node 301 and the second node 302 when the calibration switch element 290 is turned off and the semiconductor switch device 190 is reverse biased and turned off.

[0146] If with Figure 2 In conjunction with the desaturation control circuit 320 shown, the desaturation clamp is released and the desaturation clamp switch 325 is turned off in order to measure the third voltage V3.

[0147] If the semiconductor switching device 190 is a MOSFET, the third voltage V3 gives information about the forward voltage of the body diode of the semiconductor switching device 190. The forward voltage of the body diode can be monitored in situ during operation of the device and can be used to further refine the expected lifetime estimate.

[0148] exist Figure 5 , the circuit arrangement 900 includes a constant current source 315 electrically connected between the positive analog supply voltage VDDA and the first node 301. The constant current source 315 may be electrically connected to the first node 301 directly or through an intervening element such as a semiconductor switch. The constant current source 315 is part of the voltage acquisition circuit 310. The constant current source 315 supplies a constant current ISRC to the first node 301 for voltage measurement during the monitoring period and the calibration period, and, if applicable, for measurement of the third voltage V3 to obtain information about the forward voltage across the body diode. The constant current ISRC may be in the range from 100 μA to 10 mA, for example, from 500 μA to 2 mA.

[0149] A first terminal of the current limiting resistor 306 is electrically connected to the first node 301 , and a second terminal of the current limiting resistor 306 is electrically connected to an anode of the first diode 110 and an anode of the second diode 210 .

[0150] The voltage drop across the current limiting resistor 306 is the same when the first voltage V1 is measured and when the second voltage V2 is measured, and is fully compensated when the second voltage V2 is subtracted from the first voltage V1 .

[0151] The circuit arrangement 900 includes a gate driver stage 340 , a gate voltage acquisition circuit 350 , and a second gate resistor 342 electrically connected between a gate clamp output terminal of the gate driver stage 340 and a gate of the semiconductor switching device 190 .

[0152] The smoothing capacitor 820 is electrically connected between the positive analog supply voltage VDDA and the negative analog supply voltage VSSA. The negative analog supply voltage VSSA, the second node 302 and the second load terminal 192 are directly electrically connected to each other through a permanent low resistance wire.

[0153] The desaturation control circuit 320 includes an n-channel MOSFET as a desaturation clamp switch 325. The voltage acquisition circuit 310 and the desaturation circuit 320 share a common ADC 312 for converting the voltage at the first node 301 into a digital value.

[0154] The processing circuit 390 receives information about the voltage difference ΔV, a third voltage V3 including information about the forward voltage of the body diode and / or gate voltage information, generates expected lifetime information based on the voltage difference ΔV, the third voltage V3 and / or the gate voltage information, and outputs the expected lifetime information through a digital interface.

[0155] Figure 6 A method of operating a circuit device is shown. A constant current ISRC is supplied to a first path, the first path including a first diode and a semiconductor switch device (702) electrically connected in series between a first node and a second node, wherein the semiconductor switch device controls the constant current ISRC and a load current I L The switching current I SW A first voltage V1 between the first node and the second node is determined (704). A constant current ISRC is supplied to a second path including a second diode and a calibration switch element electrically connected in series between the first node and the second node (706). A second voltage V2 caused by the constant current between the first node and the second node is determined (708). The method further includes outputting information about a compensation voltage obtained based on the first voltage V1 and the second voltage V2 (710).

Claims

1. A circuit device (900), comprising: A first diode (110) and a semiconductor switch device (190) electrically connected in series between a first node (301) and a second node (302), wherein the semiconductor switch device (190) is configured to control a switching current, the switching current comprising a load current and a forward current passing through the first diode (110); A second diode (210) and a calibration switch element (290) electrically connected in series between the first node (301) and the second node (302); and A voltage acquisition circuit (310) is configured to obtain a compensation voltage based on a first voltage between the first node (301) and the second node (302) when the semiconductor switch device (190) is turned on and the calibration switch element (290) is turned off, and a second voltage between the first node (301) and the second node (302) when the calibration switch element (290) is turned on and the semiconductor switch device (190) is turned off.

2. The circuit arrangement according to claim 1, in, The first diode (110) and the second diode (210) are formed in the same semiconductor die, or the first diode (110) and the second diode (210) are formed in different semiconductor dies integrated in the same package, or the first diode (110) and the second diode (210) are discrete devices including anode pins of adjacent pads soldered to the same circuit trace on a printed circuit board or a directly bonded copper substrate.

3. The circuit arrangement according to claim 1 , in, The thermal coupling between the first diode and the second diode is configured to limit a difference between a first junction temperature of the first diode and a second junction temperature of the second diode to a value of maximum 20 degrees Celsius during operation of the circuit arrangement.

4. The circuit arrangement according to claim 1, in, The first diode (110) and the second diode (210) have the same nominal device parameters.

5. The circuit arrangement according to claim 1, in, The voltage acquisition circuit (310) is configured to obtain a voltage difference between the first voltage and the second voltage as the compensation voltage.

6. The circuit arrangement according to any one of the preceding claims, further comprising: A desaturation control circuit (320) is configured to output a valid desaturation signal when the semiconductor switch device (190) is turned on, a blanking time has elapsed, and the first voltage exceeds a desaturation threshold voltage.

7. The circuit arrangement according to any one of the preceding claims, further comprising: An acquisition control circuit (330) is configured to control the voltage acquisition circuit (310) to acquire and / or process the compensation voltage when a predetermined condition is met.

8. The circuit arrangement according to any one of the preceding claims, further comprising: A processing circuit (390) is configured to receive information about the compensation voltage, generate life expectancy information based on the compensation voltage obtained at different time points, and output the life expectancy information.

9. The circuit arrangement according to claim 8, further comprising: A gate driver stage (340) is configured to output a gate signal to the semiconductor switching device (190), wherein the gate signal varies between an effective voltage level for turning on the semiconductor switching device (190) and an ineffective voltage level for turning off the semiconductor switching device (190).

10. The circuit arrangement according to claim 9, further comprising: A gate voltage acquisition circuit (350) is configured to acquire and output gate voltage information about an instantaneous effective voltage level of the gate signal.

11. The circuit arrangement according to claim 10, further comprising: A junction voltage acquisition circuit (360) is configured to obtain a third voltage between the first node (301) and the second node (302) when the calibration switch element (290) is turned off and the semiconductor switch device (190) is reverse biased and turned off.

12. The circuit arrangement according to claim 11, in, The processing circuit (390) is also configured to receive information about the third voltage and / or the gate voltage information, generate the expected lifetime information based on the voltage difference, the third voltage and / or the gate voltage information, and output the expected lifetime information.

13. The circuit arrangement according to any one of the preceding claims, further comprising: A constant current source (315) is configured to supply a constant current at the first node (301).

14. The circuit arrangement according to any one of the preceding claims, further comprising: A current limiting resistor (306), wherein a first terminal of the current limiting resistor (306) is electrically connected to the first node (301), and wherein a second terminal of the current limiting resistor (306) is electrically connected to an anode of the first diode (110) and an anode of the second diode (210).

15. A method of operating a circuit device (900), the method comprising: supplying a constant current to a first path (100) and determining a first voltage between a first node (301) and a second node (302), wherein the first path (100) includes a first diode (110) and a semiconductor switch device (190) electrically connected in series between the first node (301) and the second node (302), wherein the semiconductor switch device (190) controls a switch current including the constant current and a load current; supplying the constant current to a second path (200) and determining a second voltage caused by the constant current between the first node (301) and the second node (302), the second path (200) comprising a second diode (210) and a calibration switching element (290) electrically connected in series between the first node (301) and the second node (302); and Information about a compensation voltage obtained according to the first voltage and the second voltage is output.

16. The method according to claim 15, in, A voltage difference between the first voltage and the second voltage is determined as the compensation voltage.

17. The method according to claim 16, further comprising: An active desaturation signal is generated when the semiconductor switching device (190) is turned on, a blanking time has elapsed, and the first voltage exceeds a desaturation threshold voltage.

18. The method according to claim 16 or 17, in, The second voltage is obtained and / or processed when a predetermined condition is met.

19. The method according to any one of claims 16 to 18, further comprising: Life expectancy information is generated and output based on the compensation voltage.

20. The method according to any one of claims 16 to 19, further comprising: A gate signal is supplied to the semiconductor switching device (190), wherein the gate signal varies between an active voltage level for turning on the semiconductor switching device (190) and an inactive voltage level for turning off the semiconductor switching device (190).

21. The method according to claim 20, further comprising: Gate voltage information about the instantaneous effective voltage level of the gate signal is obtained and output.

22. The method according to claim 21, further comprising: When the calibration switching element (290) is turned off, and the semiconductor switching device (190) is turned off and reverse biased, a third voltage between the first node (301) and the second node (302) is obtained.

23. The method according to claim 22, further comprising: Expected lifetime information is generated based on the compensation voltage, the third voltage and / or the gate voltage information and the expected lifetime information is output.

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