Temperature compensation circuit and electronic equipment

Abstract

The invention provides a temperature compensation circuit and electronic equipment, and the temperature compensation circuit comprises a first current module which is configured to output a first current signal, and the first current signal has a positive temperature coefficient characteristic; the second current module is configured to output a second current signal, and the second current signal has a negative temperature coefficient characteristic; the reference voltage module is configured to output a reference voltage signal; and the compensation module is connected with the first current module, the second current module and the reference voltage module, and the compensation module is configured to perform temperature detection, inject the first current signal into the reference voltage signal when the temperature is in a first temperature range, and inject the second current signal into the reference voltage signal when the temperature is in a second temperature range. According to the mode, segmented temperature compensation is carried out on the reference signal, so that the output of a clock with lower temperature drift can be realized, an output clock with higher precision is provided, and the requirement of a high-precision clock on an MCU (Microprogrammed Control Unit) chip is met.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits, and in particular to a temperature compensation circuit and an electronic device. Background Art

[0002] On-chip clock refers to the clock signal generated inside the integrated circuit chip. It is used to drive the operation and synchronization of various parts on the chip. The frequency and stability of the on-chip clock are crucial to the performance of the chip.

[0003] MCU (Microcontroller Unit) requires a stable on-chip clock signal to ensure the normal operation of internal digital circuits and other circuits. In some processing matters, high-precision on-chip clock support is required. For example, in motor control application scenarios, automotive MCUs require ADC (Analog-to-Digital Converter) modules for accurate sampling, which increases the requirements for ADC sampling clocks. For example, automotive MCUs also require high-precision on-chip clocks to support LIN communication under low-cost solutions. Existing on-chip high-precision RC clocks mostly use zero-drift capacitors and two resistors with different temperature characteristics (positive and negative drift) for temperature compensation. The accuracy of the on-chip clock signal is improved by reducing the temperature drift, but the existing temperature compensation method cannot meet the needs of high-precision clocks on MCU chips. Summary of the invention

[0004] To solve the above problems, the present application provides a temperature compensation circuit and an electronic device, which can achieve the output of a lower temperature drift clock, provide a higher precision output clock, and meet the demand for high-precision clock on the MCU chip.

[0005] A technical solution adopted in the present application is: to provide a temperature compensation circuit, which includes: a first current module, configured to output a first current signal, the first current signal has a positive temperature coefficient characteristic; a second current module, configured to output a second current signal, the second current signal has a negative temperature coefficient characteristic; a reference voltage module, configured to output a reference voltage signal; a compensation module, connecting the first current module, the second current module and the reference voltage module, the compensation module is configured to perform temperature detection, when the temperature is within the first temperature range, the first current signal is injected into the reference voltage signal, when the temperature is within the second temperature range, the second current signal is injected into the reference voltage signal.

[0006] In one embodiment, the compensation module includes: a first mirror module, connected to the first current module, the first mirror module is configured to output a third current signal mirrored with the first current signal; a first switch, the first end of the first switch is connected to the output end of the first mirror module, and the second end of the first switch is connected to the reference voltage module; a second mirror module, connected to the second current module, the second mirror module is configured to output a fourth current signal mirrored with the second current signal; a second switch, the first end of the second switch is connected to the output end of the second mirror module, and the second end of the second switch is connected to the reference voltage module; a first temperature detection module, connected to the control end of the first switch and the control end of the second switch, the first temperature detection module is configured to perform temperature detection, when the temperature is within the first temperature range, the first switch is controlled to be turned on and the second switch is controlled to be turned off, so as to inject the first current signal into the reference voltage signal, and when the temperature is within the second temperature range, the first switch is controlled to be turned off and the second switch is controlled to be turned on, so as to inject the second current signal into the reference voltage signal.

[0007] In one embodiment, the first temperature detection module includes: a third mirror module, connected to the first current module, the third mirror module is configured to output a fifth current signal mirrored with the first current signal; a first resistor, the first end of the first resistor is connected to the output end of the third mirror module, and the second end of the first resistor is grounded; a first operational amplifier, the first input end of the first operational amplifier is connected to the first end of the first resistor, the second input end of the first operational amplifier is configured to input a first reference voltage signal, and the output end of the first operational amplifier is connected to the control end of the first switch; an inverter, the input end of the inverter is connected to the output end of the first operational amplifier, and the output end of the inverter is connected to the control end of the second switch.

[0008] In one embodiment, the temperature compensation circuit also includes a third current module, which is configured to output a sixth current signal, and the sixth current signal has a zero temperature coefficient characteristic; wherein the compensation module is also configured to inject the second current signal into the reference voltage signal when the temperature is in the second temperature range, and inject the sixth current signal into the reference voltage signal when the temperature is in the third temperature range, and the third temperature range is between the first temperature range and the second temperature range.

[0009] In one embodiment, the compensation module includes: a first mirror module, connected to the first current module, the first mirror module is configured to output a third current signal mirrored with the first current signal; a first switch, the first end of the first switch is connected to the output end of the first mirror module, and the second end of the first switch is connected to the reference voltage module; a second mirror module, connected to the second current module, the second mirror module is configured to output a fourth current signal mirrored with the second current signal; a second switch, the first end of the second switch is connected to the output end of the second mirror module, and the second end of the second switch is connected to the reference voltage module; a fourth mirror module, connected to the third current module, the fourth mirror module is configured to output a seventh current signal mirrored with the sixth current signal; a third switch, the first end of the third switch is connected to the fourth mirror module an output end of the third switch, a second end of the third switch is connected to a reference voltage module; a second temperature detection module is connected to the control end of the first switch, the control end of the second switch and the control end of the third switch, the second temperature detection module is configured to perform temperature detection, when the temperature is within a first temperature range, control the first switch to be turned on, the second switch to be turned off, and the third switch to be turned off, so as to inject the first current signal into the reference voltage signal, when the temperature is within a second temperature range, control the first switch to be turned off, the second switch to be turned on, and the third switch to be turned off, so as to inject the second current signal into the reference voltage signal, when the temperature is within a third temperature range, control the first switch to be turned off, the second switch to be turned off, and the third switch to be turned on, so as to inject the seventh current signal into the reference voltage signal.

[0010] In one embodiment, the second temperature detection module includes: a third mirror module, connected to the first current module, the third mirror module is configured to output a fifth current signal equal to the first current signal; a first resistor, the first end of the first resistor is connected to the output end of the third mirror module, and the second end of the first resistor is grounded; a second operational amplifier, the first input end of the second operational amplifier is connected to the first end of the first resistor, and the second input end of the second operational amplifier is configured to input a first reference voltage signal; a third operational amplifier, the first input end of the third operational amplifier is connected to the first end of the first resistor, and the second input end of the third operational amplifier is configured to input a second reference voltage signal; wherein the voltage value of the second reference voltage signal is different from the voltage value of the first reference voltage signal; a logic processing module, the input end of the logic processing module is respectively connected to the output end of the second operational amplifier and the output end of the third operational amplifier, and the output end of the logic processing module is respectively connected to the control end of the first switch, the control end of the second switch, and the control end of the third switch.

[0011] In one embodiment, the logic processing module includes: an XENOR logic gate, wherein the first input end of the XENOR logic gate is connected to the output end of the second operational amplifier, the second input end of the XENOR logic gate is connected to the output end of the third operational amplifier, and the output end of the XENOR logic gate is connected to the control end of the third switch; an OR logic gate, wherein the first input end of the OR logic gate is connected to the output end of the second operational amplifier, the second input end of the OR logic gate is connected to the output end of the third operational amplifier, and the output end of the OR logic gate is connected to the control end of the first switch; and a NAND gate, wherein the first input end of the NAND gate is connected to the output end of the second operational amplifier, the second input end of the NAND gate is connected to the output end of the third operational amplifier, and the output end of the NAND gate is connected to the control end of the second switch.

[0012] In one embodiment, the first current module includes: a first MOS tube, a first end of the first MOS tube is configured to input a power supply voltage signal, and a control end of the first MOS tube is connected to a control end of the first mirror module and a control end of the third mirror module; a second resistor, a first end of the second resistor is connected to a second end of the first MOS tube; a third resistor, a first end of the third resistor is connected to a second end of the second resistor; a fourth resistor, a first end of the fourth resistor is connected to a second end of the second resistor; a fourth operational amplifier, a first input end of the fourth operational amplifier is connected to a second end of the fourth resistor, a second input end of the fourth operational amplifier is connected to a second end of the third resistor, and an output end of the fourth operational amplifier is connected to the control end of the first MOS tube; a fifth resistor, a first end of the fifth resistor is connected to a first input end of the fourth operational amplifier; a first triode, a first end of the first triode is connected to a second input end of the fourth operational amplifier, and a second end and a control end of the first triode are grounded; a second triode, a first end of the second triode is connected to a second end of the fifth resistor, and a second end and a control end of the second triode are grounded.

[0013] In one embodiment, the second current module includes: a second MOS tube, a first end of the second MOS tube is configured to input a power supply voltage signal, and a control end of the second MOS tube is connected to the control end of the second mirror module; a third MOS tube, a first end of the third MOS tube is connected to the second end of the second MOS tube; a sixth resistor, a first end of the sixth resistor is connected to the second end of the third MOS tube, and the second end of the sixth resistor is grounded; a current source, a first end of the current source is connected to the first end of the second MOS tube; a fifth operational amplifier, a first input end of the fifth operational amplifier is connected to the second end of the current source, a second input end of the fifth operational amplifier is connected to the first end of the sixth resistor, and an output end of the fifth operational amplifier is connected to the control end of the third MOS tube; a third triode, a first end of the third triode is connected to the first input end of the fifth operational amplifier, and a second end and a control end of the third triode are grounded.

[0014] In one embodiment, the reference voltage module includes: a seventh resistor, a first end of the seventh resistor is configured to input a power supply voltage signal; an eighth resistor, a first end of the eighth resistor is connected to a second end of the seventh resistor, and a second end of the eighth resistor is grounded; wherein a voltage dividing node between the seventh resistor and the eighth resistor is configured to output a reference voltage signal.

[0015] In one embodiment, the third current module includes: a fourth MOS tube, a first end of the fourth MOS tube is configured to input a power supply voltage signal, and a control end of the fourth MOS tube is connected to the control end of the fourth mirror module; a fifth MOS tube, a first end of the fifth MOS tube is connected to the second end of the fourth MOS tube; a ninth resistor, a first end of the ninth resistor is connected to the second end of the fifth MOS tube, and a second end of the ninth resistor is grounded; a sixth operational amplifier, a first input end of the sixth operational amplifier is grounded, a second input end of the sixth operational amplifier is connected to the first end of the ninth resistor, and an output end of the sixth operational amplifier is connected to the control end of the fifth MOS tube; a voltage source, a first end of the voltage source is connected to the first input end of the sixth operational amplifier, and a second end of the voltage source is grounded.

[0016] The present application also provides an electronic device, which includes the temperature compensation circuit as described above.

[0017] The present application provides a temperature compensation circuit, which includes: a first current module, configured to output a first current signal, the first current signal having a positive temperature coefficient characteristic; a second current module, configured to output a second current signal, the second current signal having a negative temperature coefficient characteristic; a reference voltage module, configured to output a reference voltage signal; a compensation module, connected to the first current module, the second current module and the reference voltage module, the compensation module is configured to perform temperature detection, when the temperature is in the first temperature range, the first current signal is injected into the reference voltage signal, when the temperature is in the second temperature range, the second current signal is injected into the reference voltage signal. In the above manner, by performing segmented temperature compensation on the reference signal, the output of a lower temperature drift clock can be achieved, a higher precision output clock is provided, and the requirements of a high-precision clock on the MCU chip are met. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] in:

[0020] Figure 1 is a structural schematic diagram of a first embodiment of a temperature compensation circuit provided by the present application;

[0021] Figure 2 is a structural schematic diagram of a second embodiment of a temperature compensation circuit provided by the present application;

[0022] Figure 3 is a structural schematic diagram of a third embodiment of a temperature compensation circuit provided by the present application;

[0023] Figure 4 is a structural schematic diagram of a fourth embodiment of a temperature compensation circuit provided by the present application;

[0024] Figure 5 is a schematic diagram of a fifth embodiment of a temperature compensation circuit provided by the present application;

[0025] Figure 6 It is a structural schematic diagram of an embodiment of an electronic device provided by the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0027] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0028] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0029] See also Figure 1 , Figure 11 is a schematic diagram of the structure of the first embodiment of the temperature compensation circuit provided in the present application. The temperature compensation circuit 100 includes: a first current module 10, a second current module 20, a reference voltage module 30 and a compensation module 40.

[0030] Among them, the first current module 10 is configured to output a first current signal S1, and the first current signal S1 has a positive temperature coefficient characteristic; the second current module 20 is configured to output a second current signal S2, and the second current signal S2 has a negative temperature coefficient characteristic; the reference voltage module 30 is configured to output a reference voltage signal VREF; the compensation module 40 is connected to the first current module 10, the second current module 20 and the reference voltage module 30, and the compensation module 40 is configured to perform temperature detection, when the temperature is in the first temperature range, the first current signal S1 is injected into the reference voltage signal VREF, and when the temperature is in the second temperature range, the second current signal S2 is injected into the reference voltage signal VREF.

[0031] Specifically, existing on-chip high-precision RC clocks mostly use zero-drift capacitors and two resistors with different temperature characteristics (positive and negative drift) for temperature compensation. Zero-drift capacitors refer to capacitors whose capacitance remains relatively stable when the temperature changes. Positive drift resistors are resistors whose resistance increases as the temperature rises, and negative drift resistors are resistors whose resistance decreases as the temperature rises. When the temperature rises, the resistance of the positive drift resistor increases, while the resistance of the negative drift resistor decreases. The changes in these two resistance values ​​can offset the performance changes caused by other components with the increase in temperature, so that the RC time constant remains consistent at different temperatures. This temperature compensation method can easily achieve an output clock with an accuracy of about 1%, but cannot meet the needs of higher-precision clock output.

[0032] In some complex clock circuits or occasions that require high-precision clocks, reference signals are usually required to calibrate or synchronize the clock signal. For example, for a high-precision on-chip RC clock with an FLL (Frequency Locked Loop) structure, the temperature drift of its output clock is determined by R, a combination of two resistors, and a capacitor C. The temperature drift of capacitor C can usually be ignored, and the output frequency can be approximately considered to be determined only by R. The clock output frequency fout can be expressed by the following formula:

[0033]

[0034] Among them, x is the fixed ratio obtained by dividing the resistor R, which can be understood as the ratio of the resistance values ​​of the two resistors. By using two resistors with different temperature drifts to form R, a certain temperature compensation can be performed. The voltage-dividing node of the two resistors outputs a reference signal, which is the key to ensuring the stable and accurate output of the clock signal. As a frequency reference, it synchronizes the frequency of the local oscillator with the reference signal or forms a certain frequency multiplication relationship through the adjustment mechanism of the FLL system. Therefore, the temperature drift of the reference signal will affect the temperature drift of the clock output frequency. By performing temperature compensation on the reference signal, the influence of temperature on the clock signal can be further reduced, and the accuracy of the output clock can be improved.

[0035] In an application scenario, if the resistor R has a negative temperature characteristic in the low temperature stage and a positive temperature characteristic in the high temperature stage, it can be seen from the above formula of the clock output frequency that if the temperature characteristic of x is not changed, the clock output frequency has a positive temperature characteristic in the low temperature stage and a negative temperature characteristic in the high temperature stage, that is, after the first-order RC compensation, the parabola of the clock frequency temperature characteristic opens downward. If R has a positive temperature characteristic, then 1 / RC has a negative temperature characteristic. At this time, it is necessary to set When the temperature is positive, that is, x is negative, it can offset the negative temperature characteristic of 1 / RC. It is only necessary to inject a compensation current with a negative temperature characteristic into the reference signal VREF. Similarly, if R is a negative temperature characteristic, it is necessary to inject a compensation current with a positive temperature characteristic into the reference signal VREF. The compensation module 40 performs temperature detection. When the temperature is in the first temperature range (corresponding to the low temperature stage), the first current signal S1 is injected into the reference voltage signal VREF. When the temperature is in the second temperature range (corresponding to the high temperature stage), the second current signal S2 is injected into the reference voltage signal VREF. The first temperature range is smaller than the second temperature range.

[0036] In another application scenario, if the resistor R has a positive temperature characteristic in the low temperature stage, and has a negative temperature characteristic in the high temperature stage, the clock frequency temperature characteristic parabola opens upward, that is, it is necessary to inject a compensation current with a positive temperature characteristic into the reference signal VREF in the low temperature stage, and it is necessary to inject a compensation current with a negative temperature characteristic into the reference signal VREF in the high temperature stage. The compensation module 40 performs temperature detection, and when the temperature is in the first temperature range (corresponding to the high temperature stage), the first current signal S1 is injected into the reference voltage signal VREF, and when the temperature is in the second temperature range (corresponding to the low temperature stage), the second current signal S2 is injected into the reference voltage signal VREF. Among them, the first temperature range is greater than the second temperature range.

[0037] The present application provides a temperature compensation circuit 100. The temperature compensation circuit 100 takes a compensation module 40 as the core. In different temperature ranges, the first current signal S1 with a positive temperature coefficient characteristic output by the first current module 10 and the second current signal S2 with a negative temperature coefficient characteristic output by the second current module 20 are respectively injected into a reference voltage signal VREF, thereby using two different temperature coefficient characteristics to offset each other, thereby performing segmented temperature compensation on the reference signal VREF, achieving the output of a lower temperature drift clock, providing a higher precision output clock, and meeting the requirements of a high-precision clock on an MCU chip.

[0038] See also Figure 2 , Figure 2 1 is a schematic diagram of the structure of the second embodiment of the temperature compensation circuit provided in the present application. The temperature compensation circuit 100 includes: a first current module 10, a second current module 20, a reference voltage module 30 and a compensation module 40.

[0039] Among them, the first current module 10 is configured to output a first current signal S1, and the first current signal S1 has a positive temperature coefficient characteristic; the second current module 20 is configured to output a second current signal S2, and the second current signal S2 has a negative temperature coefficient characteristic; the reference voltage module 30 is configured to output a reference voltage signal VREF; the compensation module 40 is connected to the first current module 10, the second current module 20 and the reference voltage module 30, and the compensation module 40 is configured to perform temperature detection, when the temperature is in the first temperature range, the first current signal S1 is injected into the reference voltage signal VREF, and when the temperature is in the second temperature range, the second current signal S2 is injected into the reference voltage signal VREF.

[0040] Optionally, the compensation module 40 includes a first mirror module 41 , a first switch SW1 , a second mirror module 42 , a second switch SW2 and a first temperature detection module 43 . The first mirror module 41 is connected to the first current module 10, and the first mirror module 41 is configured to output a third current signal S3 mirrored with the first current signal S1; the first end of the first switch SW1 is connected to the output end of the first mirror module 41, and the second end of the first switch SW1 is connected to the reference voltage module 30; the second mirror module 42 is connected to the second current module 20, and the second mirror module 42 is configured to output a fourth current signal S4 mirrored with the second current signal S2; the first end of the second switch SW2 is connected to the output end of the second mirror module 42, and the second end of the second switch SW2 is connected to the reference voltage module 30; the first temperature detection module 43 is connected to the control end of the first switch SW1 and the control end of the second switch SW2, and the first temperature detection module 43 is configured to perform temperature detection, when the temperature is within the first temperature range, the first switch SW1 is controlled to be turned on, and the second switch SW2 is controlled to be turned off, so as to inject the first current signal S1 into the reference voltage signal VREF, and when the temperature is within the second temperature range, the first switch SW1 is controlled to be turned off, and the second switch SW2 is controlled to be turned on, so as to inject the second current signal S2 into the reference voltage signal VREF.

[0041] Specifically, the first mirror module 41 can be a MOS transistor, specifically a PMOS transistor. The input end of the first mirror module 41 is connected to the output end of the first current module 10, and the first current signal S1 with a positive temperature coefficient characteristic output by the first current module 10 can be mirrored at a certain ratio to output a third current signal S3. The current value of the third current signal S3 can be proportional to the current value of the first current signal S1, and the third current signal S3 has the same temperature coefficient characteristic as the first current signal S1, that is, the third current signal S3 is also a current with a positive temperature coefficient characteristic. Similarly, the second mirror module 42 can also be a PMOS transistor, and the fourth current signal S4 with a negative temperature coefficient characteristic is obtained by mirroring the second current signal S2.

[0042] Specifically, the first switch SW1 and the second switch SW2 may also be PMOS transistors, and the control signal is a gate voltage signal of the PMOS transistor. When the control signal is at a high level, the PMOS transistor is in an off state, and when the control signal is at a low level, the PMOS transistor is in an on state. The first temperature detection module 43 is connected to the control end of the first switch SW1 and the control end of the second switch SW2 (i.e., the gate of the PMOS transistor), that is, the output signal of the first temperature detection module 43 is a control signal for controlling the first switch SW1 and the second switch SW2 to be turned on and off.

[0043] Next, when the first temperature detection module 43 detects that the temperature is within the first temperature range, the first temperature detection module 43 outputs a low level signal to the control end of the first switch SW1, and outputs a high level signal to the control end of the second switch SW2, controls the first switch SW1 to be turned on, and controls the second switch SW2 to be turned off. The first end of the first switch SW1 is connected to the output end of the first mirror module 41, so the first current signal S1 of the first switch SW1 in the on state is injected into the reference voltage signal VREF. When the temperature is detected to be within the second temperature range, the first temperature detection module 43 outputs a high level signal to the control end of the first switch SW1, and outputs a low level signal to the control end of the second switch SW2, controls the first switch SW1 to be turned off, and controls the second switch SW2 to be turned on, and the first end of the second switch SW2 is connected to the output end of the second mirror module 42, so the second switch SW2 in the on state injects the second current signal S2 into the reference voltage signal VREF.

[0044] Optionally, the first temperature detection module 43 includes a third mirror module 431, a first resistor R1, a first operational amplifier A1 and an inverter P. The third mirror module 431 is connected to the first current module 10, and the third mirror module 431 is configured to output a fifth current signal S5 mirrored with the first current signal S1; the first end of the first resistor R1 is connected to the output end of the third mirror module 431, and the second end of the first resistor R1 is grounded; the first input end of the first operational amplifier A1 is connected to the first end of the first resistor R1, the second input end of the first operational amplifier A1 is configured to input the first reference voltage signal V1, and the output end of the first operational amplifier A1 is connected to the control end of the first switch SW1; the input end of the inverter P is connected to the output end of the first operational amplifier A1, and the output end of the inverter P is connected to the control end of the second switch SW2.

[0045] Specifically, the third mirror module 431 can be a MOS transistor, specifically a PMOS transistor, and the fifth current signal S5 with a positive temperature coefficient characteristic is obtained by mirroring the first current signal S1. The output end of the first operational amplifier A1 is directly connected to the control end of the first switch SW1 and connected to the control end of the second switch SW2 through the inverter P. Therefore, the output signal of the first operational amplifier A1 is the control signal for controlling the first switch SW1 and the second switch SW2 to be turned on and off. The output signal of the first operational amplifier A1 is determined by the voltage of its positive input end (i.e., the first input end) and the voltage of the negative input end (i.e., the second input end). After the fifth current signal S5 flows through the first resistor R1, a voltage is formed at the first input end of the first operational amplifier A1. The first resistor R1 is set as a variable resistor, and the voltage of the first input end of the first operational amplifier A1 can be changed by changing the resistance value of the first resistor R1. Because the first reference voltage signal V1 input to the second input end of the first operational amplifier A1 remains unchanged, the output signal of the first operational amplifier A1 can be changed by changing the resistance value of the first resistor R1.

[0046] Next, when the temperature is within the first temperature range, the resistance value of the first resistor R1 is controlled to make the voltage value of the first input terminal of the first operational amplifier A1 less than the voltage value of the first reference voltage signal V1, and the first operational amplifier A1 outputs a low-level signal to control the first switch SW1 to be turned on. The low-level signal is inverted by the inverter P to become a high-level signal, and the second switch SW2 is controlled to be turned off to inject the first current signal S1 into the reference voltage signal VREF; when the temperature is within the second temperature range, the resistance value of the first resistor R1 is controlled to make the voltage value of the first input terminal of the first operational amplifier A1 greater than the voltage value of the first reference voltage signal V1, and the first operational amplifier A1 outputs a high-level signal to control the first switch SW1 to be turned off. The high-level signal is inverted by the inverter P to become a low-level signal, and the second switch SW2 is controlled to be turned on to inject the second current signal S2 into the reference voltage signal VREF.

[0047] It can be understood that the first resistor R1 can adjust the temperature point at which the first switch SW1 and the second switch SW2 are switched on, that is, adjust the temperature threshold. For example, the initial temperature point of the switching on is set to 50 degrees Celsius. When the temperature is less than 50 degrees Celsius, the first switch SW1 is turned on and the second switch SW2 is turned off. When the temperature is greater than 50 degrees Celsius, the first switch SW1 is turned off and the second switch SW2 is turned on. The resistance value of the first resistor R1 is increased so that the switching on temperature point is 40 degrees Celsius. When the temperature is less than 40 degrees Celsius, the first switch SW1 is turned on and the second switch SW2 is turned off. When the temperature is greater than 40 degrees Celsius, the first switch SW1 is turned off and the second switch SW2 is turned on. The resistance value of the first resistor R1 is reduced so that the switching on temperature point is 60 degrees Celsius. When the temperature is less than 60 degrees Celsius, the first switch SW1 is turned on and the second switch SW2 is turned off. When the temperature is greater than 60 degrees Celsius, the first switch SW1 is turned off and the second switch SW2 is turned on. Through the above methods, the robustness of the circuit can be improved, which plays an important role in enhancing the stability, reliability, anti-interference ability, adaptability of the circuit system and supporting the design and optimization of complex systems.

[0048] See also Figure 3 , Figure 3 1 is a schematic diagram of the structure of the third embodiment of the temperature compensation circuit provided in the present application. The temperature compensation circuit 100 includes: a first current module 10, a second current module 20, a reference voltage module 30 and a compensation module 40.

[0049] Among them, the first current module 10 is configured to output a first current signal S1, and the first current signal S1 has a positive temperature coefficient characteristic; the second current module 20 is configured to output a second current signal S2, and the second current signal S2 has a negative temperature coefficient characteristic; the reference voltage module 30 is configured to output a reference voltage signal VREF; the compensation module 40 is connected to the first current module 10, the second current module 20 and the reference voltage module 30, and the compensation module 40 is configured to perform temperature detection, when the temperature is in the first temperature range, the first current signal S1 is injected into the reference voltage signal VREF, and when the temperature is in the second temperature range, the second current signal S2 is injected into the reference voltage signal VREF.

[0050] Figure 3 The temperature compensation circuit 100 shown is Figure 2 The main difference of the temperature compensation circuit 100 shown in FIG. 1 is that the components added to the third current module 50 and the compensation module 40 are described. Therefore, the components added to the third current module 50 and the compensation module 40 are mainly described below. For other components in the temperature compensation circuit 100, please refer to FIG. Figure 2 The relevant description of the embodiment shown, for example Figure 3 The first mirror module 41 in Figure 2 The description of the first mirror module 41 in will not be repeated here.

[0051] Optionally, the temperature compensation circuit 100 also includes a third current module 50, which is configured to output a sixth current signal S6, and the sixth current signal S6 has a zero temperature coefficient characteristic; wherein the compensation module 40 is also configured to inject the second current signal S2 into the reference voltage signal VREF when the temperature is in the second temperature range, and inject the sixth current signal S6 into the reference voltage signal VREF when the temperature is in the third temperature range, and the third temperature range is between the first temperature range and the second temperature range.

[0052] Optionally, the compensation module 40 includes: a first mirror module 41, a first switch SW1, a second mirror module 42, a second switch SW2, a fourth mirror module 44, a third switch SW3, and a second temperature detection module 45. The first mirror module 41 is connected to the first current module 10, and the first mirror module 41 is configured to output a third current signal S3 mirrored with the first current signal S1; the first end of the first switch SW1 is connected to the output end of the first mirror module 41, and the second end of the first switch SW1 is connected to the reference voltage module 30; the second mirror module 42 is connected to the second current module 20, and the second mirror module 42 is configured to output a fourth current signal S4 mirrored with the second current signal S2; the first end of the second switch SW2 is connected to the output end of the second mirror module 42, and the second end of the second switch SW2 is connected to the reference voltage module 30; the fourth mirror module 44 is connected to the third current module 50, and the fourth mirror module 44 is configured to output a seventh current signal S7 mirrored with the sixth current signal S6; the first end of the third switch SW3 is connected to the output end of the fourth mirror module 44, and the second end of the third switch SW3 is connected to the reference voltage module 30; The reference voltage module 30; the second temperature detection module 45 is connected to the control end of the first switch SW1, the control end of the second switch SW2 and the control end of the third switch SW3. The second temperature detection module 45 is configured to perform temperature detection. When the temperature is within the first temperature range, the first switch SW1 is controlled to be turned on, the second switch SW2 is controlled to be turned off, and the third switch SW3 is controlled to be turned off, so as to inject the first current signal S1 into the reference voltage signal VREF. When the temperature is within the second temperature range, the first switch SW1 is controlled to be turned off, the second switch SW2 is controlled to be turned on, and the third switch SW3 is controlled to be turned off, so as to inject the second current signal S2 into the reference voltage signal VREF. When the temperature is within the third temperature range, the first switch SW1 is controlled to be turned off, the second switch SW2 is controlled to be turned off, and the third switch SW3 is controlled to be turned on, so as to inject the sixth current signal S6 into the reference voltage signal VREF.

[0053] Specifically, the first mirror module 41, the first switch SW1, the second mirror module 42, and the second switch SW2 can be referred to in Figure 2The description of the first mirror module 41, the first switch SW1, the second mirror module 42, and the second switch SW2 in the embodiment will not be repeated here. The fourth mirror module 44 can be a PMOS transistor, and obtains the seventh current signal S7 with a zero temperature coefficient characteristic by mirroring the sixth current signal S6. The third switch SW3 can also be a PMOS transistor, and the second temperature detection module 45 is connected to the control ends of the first switch SW1, the second switch SW2, and the third switch SW3, that is, the output signal of the second temperature detection module 45 is a control signal for controlling the first switch SW1, the second switch SW2, and the third switch SW3 to be turned on and off.

[0054] Next, when the second temperature detection module 45 detects that the temperature is within the first temperature range, it outputs a low-level signal to the control end of the first switch SW1, and outputs a high-level signal to the control ends of the second switch SW2 and the third switch SW3, controls the first switch SW1 to be turned on, controls the second switch SW2 to be turned off, and controls the third switch SW3 to be turned off, so as to inject the first current signal S1 into the reference voltage signal VREF; when it is detected that the temperature is within the second temperature range, the second temperature detection module 45 outputs a high-level signal to the control ends of the first switch SW1 and the third switch SW3, and outputs a low-level signal to the second switch SW1. The control end of switch SW2 controls the first switch SW1 to be turned off, the second switch SW2 to be turned on, and the third switch SW3 to be turned off, so as to inject the second current signal S2 into the reference voltage signal VREF; when it is detected that the temperature is within the third temperature range, the second temperature detection module 45 outputs a high level signal to the control ends of the first switch SW1 and the second switch SW2, and outputs a low level signal to the control end of the third switch SW3, controls the first switch SW1 to be turned off, the second switch SW2 to be turned off, and the third switch SW3 to be turned on, so as to inject the sixth current signal S6 into the reference voltage signal VREF.

[0055] Optionally, the second temperature detection module 45 includes: a third mirror module 431 , a first resistor R1 , a second operational amplifier A2 , a third operational amplifier A3 and a logic processing module 451 . The third mirror module 431 is connected to the first current module 10, and the third mirror module 431 is configured to output a fifth current signal S5 equal to the first current signal S1; the first end of the first resistor R1 is connected to the output end of the third mirror module 431, and the second end of the first resistor R1 is grounded; the first input end of the second operational amplifier A2 is connected to the first end of the first resistor R1, and the second input end of the second operational amplifier A2 is configured to input the first reference voltage signal V1; the first input end of the third operational amplifier A3 is connected to the first end of the first resistor R1, and the second input end of the third operational amplifier A3 is configured to input the second reference voltage signal V2; wherein the voltage value of the second reference voltage signal V2 is different from the voltage value of the first reference voltage signal V1; the input end of the logic processing module 451 is respectively connected to the output end of the second operational amplifier A2 and the output end of the third operational amplifier A3, and the output end of the logic processing module is respectively connected to the control end of the first switch SW1, the control end of the second switch SW2, and the control end of the third switch SW3.

[0056] Specifically, the third mirror module 431 and the first resistor R1 can be seen in Figure 2 The description of the third mirror module 431 and the first resistor R1 in the logic processing module 451 is not repeated here. The output ends of the second operational amplifier A2 and the third operational amplifier A3 are connected to the control ends of the first switch SW1, the second switch SW2 and the third switch SW3 through the logic processing module 451. Therefore, the output signals of the second operational amplifier A2 and the third operational amplifier A3 are control signals for controlling the first switch SW1, the second switch SW2 and the third switch SW3 to be turned on and off. The output signals of the second operational amplifier A2 and the third operational amplifier A3 are determined by the voltage of the positive input end (i.e., the first input end) and the voltage of the negative input end (i.e., the second input end) of each operational amplifier A2 and the third operational amplifier A3. After the fifth current signal S5 flows through the first resistor R1, a voltage is formed at the first input end of the second operational amplifier A2 and the third operational amplifier A3. The first resistor R1 is set as a variable resistor, and the voltage of the first input end of the second operational amplifier A2 and the third operational amplifier A3 can be changed by changing the resistance value of the first resistor R1, thereby changing the output signals of the second operational amplifier A2 and the third operational amplifier A3.

[0057] Specifically, for the first reference voltage signal V1 and the second reference voltage signal V2, it is only necessary to ensure that the sizes of the two are different, that is, the control signal for controlling the first switch SW1, the second switch SW2 and the third switch SW3 can be obtained by changing the resistance value of the first resistor R1. For example, when the first reference voltage signal V1 is greater than the second reference voltage signal V2, the resistance value of the first resistor R1 is changed so that the voltage at the first input terminal of the second operational amplifier A2 and the third operational amplifier A3 is less than the second reference voltage signal V2, and at this time, the second operational amplifier A2 and the third operational amplifier A3 both output low-level signals; when the voltage at the first input terminal of the second operational amplifier A2 and the third operational amplifier A3 is greater than the second reference voltage signal V2 and less than the first reference voltage signal V1, the second operational amplifier A2 outputs a low-level signal and the third operational amplifier A3 outputs a high-level signal; when the voltage at the first input terminal of the second operational amplifier A2 and the third operational amplifier A3 is greater than the first reference voltage signal V1, the second operational amplifier A2 and the third operational amplifier A3 both output high-level signals.

[0058] Optionally, the logic processing module 451 includes: an XENOR logic gate G1, an OR logic gate G2, and a NAND gate G3. The first input end of the XENOR logic gate G1 is connected to the output end of the second operational amplifier A2, the second input end of the XENOR logic gate G1 is connected to the output end of the third operational amplifier A3, and the output end of the XENOR logic gate G1 is connected to the control end of the third switch SW3; the first input end of the OR logic gate G2 is connected to the output end of the second operational amplifier A2, the second input end of the OR logic gate G2 is connected to the output end of the third operational amplifier A3, and the output end of the OR logic gate G2 is connected to the control end of the first switch SW1; the first input end of the NAND gate G3 is connected to the output end of the second operational amplifier A2, the second input end of the NAND gate G3 is connected to the output end of the third operational amplifier A3, and the output end of the NAND gate G3 is connected to the control end of the second switch SW2.

[0059] Specifically, the output of the XOR logic gate G1 depends on whether the input signals are the same. When the two input signals are the same (both high or low), the output is high; when the two input signals are different, the output is low. The output of the OR logic gate G2 depends on whether at least one of the input signals is high. When one or more input signals are high, the output is high; when all input signals are low, the output is low. The output of the NAND gate G3 depends on the logical relationship between the input terminals. When all inputs are high, the output is low; when at least one of the inputs is low, the output is high.

[0060] Next, when it is detected that the temperature is within the first temperature range, the resistance value of the first resistor R1 is changed so that the output signals of the second operational amplifier A2 and the third operational amplifier A3 are both low level, then the XNOR logic gate G1 and the NAND gate G3 output high level signals, the OR logic gate G2 outputs a low level signal, and the output end of the OR logic gate G2 is connected to the control end of the first switch SW1, so the first switch SW1 is turned on, the second switch SW2 and the third switch SW3 are turned off, and the first current signal S1 is injected into the reference voltage signal VREF; when it is detected that the temperature is within the second temperature range, the resistance value of the first resistor R1 is changed so that the output signals of the second operational amplifier A2 and the third operational amplifier A3 are both low level, then the XNOR logic gate G1 and the OR logic gate G2 output high level signals, The NAND gate G3 outputs a low level signal, and the output end of the NAND gate G3 is connected to the control end of the second switch SW2, so the second switch SW2 is turned on, the first switch SW1 and the third switch SW3 are turned off, and the second current signal S2 is injected into the reference voltage signal VREF; when it is detected that the temperature is in the third temperature range, the resistance value of the first resistor R1 is changed so that the output signal levels of the second operational amplifier A2 and the third operational amplifier A3 are different, then the OR logic gate G2 and the NAND gate G3 output high level signals, the NOR logic gate G1 outputs a low level, and the output end of the NOR logic gate G1 is connected to the control end of the third switch SW3, so the third switch SW3 is turned on, the first switch SW1 and the second switch SW2 are turned off, and the sixth current signal S6 is injected into the reference voltage signal VREF.

[0061] See also Figure 4 , Figure 4 1 is a schematic diagram of the structure of the fourth embodiment of the temperature compensation circuit provided in the present application. The temperature compensation circuit 100 includes: a first current module 10, a second current module 20, a reference voltage module 30 and a compensation module 40.

[0062] Among them, the first current module 10 is configured to output a first current signal S1, and the first current signal S1 has a positive temperature coefficient characteristic; the second current module 20 is configured to output a second current signal S2, and the second current signal S2 has a negative temperature coefficient characteristic; the reference voltage module 30 is configured to output a reference voltage signal VREF; the compensation module 40 is connected to the first current module 10, the second current module 20 and the reference voltage module 30, and the compensation module 40 is configured to perform temperature detection, when the temperature is in the first temperature range, the first current signal S1 is injected into the reference voltage signal VREF, and when the temperature is in the second temperature range, the second current signal S2 is injected into the reference voltage signal VREF.

[0063] Figure 4 The temperature compensation circuit 100 shown is Figure 3The main difference of the temperature compensation circuit 100 shown in FIG. 1 is that the first current module 10, the second current module 20, the third current module 50 and the reference voltage module 30 are added. Therefore, the following mainly describes the components added to the first current module 10, the second current module 20, the third current module 50 and the reference voltage module 30. For other components in the temperature compensation circuit 100, please refer to FIG. Figure 3 The relevant description of the embodiment shown, for example Figure 4 The logic processing module 451 in Figure 3 The description of the logic processing module 451 in will not be repeated here.

[0064] Optionally, the first current module 10 includes: a first MOS transistor M1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth operational amplifier A4, a fifth resistor R5, a first transistor Q1 and a second transistor Q2. The first end of the first MOS tube M1 is configured to input the power supply voltage signal VDD, and the control end of the first MOS tube M1 is connected to the control end of the first mirror module 41 and the control end of the third mirror module 431; the first end of the second resistor R2 is connected to the second end of the first MOS tube M1; the first end of the third resistor R3 is connected to the second end of the second resistor R2; the first end of the fourth resistor R4 is connected to the second end of the second resistor R2; the first input end of the fourth operational amplifier A4 is connected to the second end of the fourth resistor R4, the second input end of the fourth operational amplifier A4 is connected to the second end of the third resistor R3, and the output end of the fourth operational amplifier A4 is connected to the control end of the first MOS tube M1; the first end of the fifth resistor R5 is connected to the first input end of the fourth operational amplifier A4; the first end of the first triode Q1 is connected to the second input end of the fourth operational amplifier A4, and the second end and the control end of the first triode Q1 are grounded; the first end of the second triode Q2 is connected to the second end of the fifth resistor R5, and the second end and the control end of the second triode Q2 are grounded.

[0065] Specifically, the first MOS transistor M1 may be a PMOS transistor. In one embodiment, the number ratio of the first transistor Q1 to the second transistor Q2 may be 1:8. The base-emitter voltage of the first transistor Q1 is VBE1, and the base-emitter voltage of the second transistor Q2 is VBE2. The difference between VBE1 and VBE2 is proportional to the absolute temperature, that is, it has a positive temperature coefficient characteristic. Due to the virtual short principle of the fourth operational amplifier A4, the voltage values ​​of the first input terminal and the second input terminal of the fourth operational amplifier A4 are equal. Therefore, the current I1 flowing through the second transistor is:

[0066]

[0067] When the resistance values ​​of the third resistor R3 and the fourth resistor R4 are equal, the current values ​​flowing through the first transistor Q1 and the second transistor Q2 are also equal, that is, the current flowing through the first MOS transistor M1 is 2I, and the current is the first current signal S1 with a positive temperature coefficient characteristic. The fifth resistor R5 is set as a variable resistor, and the value of the first current signal S1 can be changed by changing the resistance value of the fifth resistor R5.

[0068] Optionally, the second current module 20 includes: a second MOS tube M2, a third MOS tube M3, a sixth resistor R6, a current source IS, a fifth operational amplifier A5 and a third triode Q3. The first end of the second MOS tube M2 is configured to input a power supply voltage signal VDD, and the control end of the second MOS tube M2 is connected to the control end of the second mirror module 42; the first end of the third MOS tube M3 is connected to the second end of the second MOS tube M2; the first end of the sixth resistor R6 is connected to the second end of the third MOS tube M3, and the second end of the sixth resistor R6 is grounded; the first end of the current source IS is connected to the first end of the second MOS tube M2; the first input end of the fifth operational amplifier A5 is connected to the second end of the current source IS, the second input end of the fifth operational amplifier A5 is connected to the first end of the sixth resistor R6, and the output end of the fifth operational amplifier A5 is connected to the control end of the third MOS tube M3; the first end of the third triode Q3 is connected to the first input end of the fifth operational amplifier A5, and the second end and the control end of the third triode Q3 are grounded.

[0069] Specifically, the second MOS transistor M2 may be a PMOS transistor, the third MOS transistor M3 may be an NMOS transistor, and the base-emitter voltage of the third transistor Q3 is inversely proportional to the absolute temperature, that is, it has a negative temperature coefficient characteristic. The current of the current source IS flows through the third transistor Q3, so that the third transistor Q3 generates a base-emitter voltage VBE3 with a negative temperature coefficient characteristic. Due to the virtual short principle of the fifth operational amplifier A5, it can be known that the potential of the second input terminal of the fifth operational amplifier A5 is equal to the first input terminal, that is, the current I2 flowing through the sixth resistor R6 can be expressed by the following formula:

[0070]

[0071] That is, the current flowing through the second MOS transistor M2 is I2, which is the second current signal S2 with a negative temperature coefficient characteristic. The sixth resistor R6 is set as a variable resistor, and the value of the second current signal S2 can be changed by changing the resistance of the sixth resistor R6.

[0072] Optionally, the reference voltage module 30 includes: a seventh resistor R7 and an eighth resistor R8, wherein the first end of the seventh resistor R7 is configured to input a power supply voltage signal VDD; the first end of the eighth resistor R8 is connected to the second end of the seventh resistor R7, and the second end of the eighth resistor R8 is grounded; wherein the voltage dividing node between the seventh resistor R7 and the eighth resistor R8 is configured to output a reference voltage signal VREF.

[0073] Specifically, the seventh resistor R7 and the eighth resistor R8 have a positive temperature coefficient characteristic and a negative temperature coefficient characteristic respectively, and the two positive and negative temperature characteristics cancel each other out, which is equivalent to performing a temperature compensation on the reference voltage signal VREF outputted by the two resistor voltage-dividing nodes.

[0074] Optionally, the third current module 50 includes: a fourth MOS tube M4, a fifth MOS tube M5, a ninth resistor R9, a sixth operational amplifier A6 and a voltage source VS. The first end of the fourth MOS tube M4 is configured to input a power supply voltage signal VDD, and the control end of the fourth MOS tube M4 is connected to the control end of the fourth mirror module 44; the first end of the fifth MOS tube M5 is connected to the second end of the fourth MOS tube M4; the first end of the ninth resistor R9 is connected to the second end of the fifth MOS tube M5, and the second end of the ninth resistor R9 is grounded; the first input end of the sixth operational amplifier A6 is grounded, the second input end of the sixth operational amplifier A6 is connected to the first end of the ninth resistor R9, and the output end of the sixth operational amplifier A6 is connected to the control end of the fifth MOS tube M5; the first end of the voltage source VS is connected to the first input end of the sixth operational amplifier A6, and the second end of the voltage source VS is grounded.

[0075] Specifically, the fourth MOS transistor M4 may be a PMOS transistor, the fifth MOS transistor M5 may be an NMOS transistor, the voltage of the voltage source VS is input to the first input terminal of the sixth operational amplifier A6, and the potential of the second input terminal of the sixth operational amplifier A6 is equal to the first input terminal, that is, the current I3 flowing through the ninth resistor R9 can be expressed by the following formula:

[0076]

[0077] That is, the current flowing through the fourth MOS tube M4 is I3, which is close to zero temperature coefficient, that is, the sixth current signal S6. The ninth resistor R9 is set as a variable resistor, and the value of the sixth current signal S6 can be changed by changing the resistance value of the ninth resistor R9.

[0078] It can be understood that the temperature compensation circuit 100 of the present application performs two-stage temperature compensation on the reference voltage signal VREF through the first current module 10, the second current module 20, the first mirror module 41, the first switch SW1, the second mirror module 42, the second switch SW2 and the first temperature detection module 43, and then performs three-stage temperature compensation on the reference voltage signal VREF through the first current module 10, the second current module 20, the third current module 50, the first mirror module 41, the first switch SW1, the second mirror module 42, the second switch SW2, the fourth mirror module 44, the third switch SW3 and the second temperature detection module 45. In the above manner, by performing segmented temperature compensation on the reference signal VREF, the output of a lower temperature drift clock can be achieved, and a higher precision output clock is provided to meet the requirements of a high-precision clock on the MCU chip.

[0079] In an application scenario, such as Figure 5 As shown, 20 temperature points are sampled in the temperature range of -40℃~150℃. Before adding the second-stage temperature compensation, the temperature drift of the output clock frequency is about 0.83%. After adding the second-stage temperature compensation, the temperature drift of the output clock frequency is reduced to 0.25%. After using the third-stage temperature compensation, the temperature drift of the output clock frequency is reduced to 0.09%.

[0080] See also Figure 6 , Figure 6 1 is a schematic diagram of the structure of an embodiment of an electronic device 1000 provided in the present application. The electronic device includes a temperature compensation circuit 100. The temperature compensation circuit is the temperature compensation circuit 100 described above and will not be described in detail here.

[0081] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only illustrative, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0082] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0083] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0084] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A temperature compensation circuit, characterized in that: The temperature compensation circuit comprises: A first current module is configured to output a first current signal, wherein the first current signal has a positive temperature coefficient characteristic; A second current module is configured to output a second current signal, wherein the second current signal has a negative temperature coefficient characteristic; A reference voltage module is configured to output a reference voltage signal; A compensation module is connected to the first current module, the second current module and the reference voltage module. The compensation module is configured to perform temperature detection. When the temperature is within a first temperature range, the first current signal is injected into the reference voltage signal. When the temperature is within a second temperature range, the second current signal is injected into the reference voltage signal.

2. The temperature compensation circuit according to claim 1, characterized in that: The compensation module comprises: A first mirror module, connected to the first current module, the first mirror module is configured to output a third current signal mirrored with the first current signal; A first switch, wherein a first end of the first switch is connected to an output end of the first mirror module, and a second end of the first switch is connected to the reference voltage module; A second mirror module, connected to the second current module, the second mirror module is configured to output a fourth current signal mirrored with the second current signal; a second switch, wherein a first end of the second switch is connected to an output end of the second mirror module, and a second end of the second switch is connected to the reference voltage module; A first temperature detection module is connected to a control end of the first switch and a control end of the second switch. The first temperature detection module is configured to perform temperature detection. When the temperature is within the first temperature range, the first switch is controlled to be turned on and the second switch is controlled to be turned off so as to inject the first current signal into the reference voltage signal. When the temperature is within the second temperature range, the first switch is controlled to be turned off and the second switch is controlled to be turned on so as to inject the second current signal into the reference voltage signal.

3. The temperature compensation circuit according to claim 2, characterized in that: The first temperature detection module comprises: A third mirror module, connected to the first current module, the third mirror module is configured to output a fifth current signal mirrored with the first current signal; A first resistor, wherein a first end of the first resistor is connected to an output end of the third mirror module, and a second end of the first resistor is grounded; a first operational amplifier, wherein a first input terminal of the first operational amplifier is connected to a first terminal of the first resistor, a second input terminal of the first operational amplifier is configured to input a first reference voltage signal, and an output terminal of the first operational amplifier is connected to a control terminal of the first switch; An inverter, wherein an input end of the inverter is connected to an output end of the first operational amplifier, and an output end of the inverter is connected to a control end of the second switch.

4. The temperature compensation circuit according to claim 1, characterized in that: The temperature compensation circuit further includes a third current module configured to output a sixth current signal, wherein the sixth current signal has a zero temperature coefficient characteristic; Wherein, the compensation module is also configured to inject the second current signal into the reference voltage signal when the temperature is in the second temperature range, and to inject the sixth current signal into the reference voltage signal when the temperature is in a third temperature range, and the third temperature range is between the first temperature range and the second temperature range.

5. The temperature compensation circuit according to claim 4, characterized in that: The compensation module comprises: A first mirror module, connected to the first current module, the first mirror module is configured to output a third current signal mirrored with the first current signal; A first switch, wherein a first end of the first switch is connected to an output end of the first mirror module, and a second end of the first switch is connected to the reference voltage module; A second mirror module, connected to the second current module, the second mirror module is configured to output a fourth current signal mirrored with the second current signal; a second switch, wherein a first end of the second switch is connected to an output end of the second mirror module, and a second end of the second switch is connected to the reference voltage module; a fourth mirror module, connected to the third current module, the fourth mirror module being configured to output a seventh current signal mirrored with the sixth current signal; A third switch, wherein a first end of the third switch is connected to the output end of the fourth mirror module, and a second end of the third switch is connected to the reference voltage module; A second temperature detection module is connected to the control end of the first switch, the control end of the second switch and the control end of the third switch. The second temperature detection module is configured to perform temperature detection. When the temperature is within the first temperature range, the first switch is controlled to be turned on, the second switch is controlled to be turned off, and the third switch is controlled to be turned off, so as to inject the first current signal into the reference voltage signal. When the temperature is within the second temperature range, the first switch is controlled to be turned off, the second switch is controlled to be turned on, and the third switch is controlled to be turned off, so as to inject the second current signal into the reference voltage signal. When the temperature is within the third temperature range, the first switch is controlled to be turned off, the second switch is controlled to be turned off, and the third switch is controlled to be turned on, so as to inject the sixth current signal into the reference voltage signal.

6. The temperature compensation circuit according to claim 5, characterized in that: The second temperature detection module includes: a third mirror module, connected to the first current module, the third mirror module being configured to output a fifth current signal equal to the first current signal; A first resistor, wherein a first end of the first resistor is connected to an output end of the third mirror module, and a second end of the first resistor is grounded; a second operational amplifier, wherein a first input terminal of the second operational amplifier is connected to a first end of the first resistor, and a second input terminal of the second operational amplifier is configured to input a first reference voltage signal; a third operational amplifier, wherein a first input terminal of the third operational amplifier is connected to the first end of the first resistor, and a second input terminal of the third operational amplifier is configured to input a second reference voltage signal; wherein a voltage value of the second reference voltage signal is different from a voltage value of the first reference voltage signal; A logic processing module, wherein the input end of the logic processing module is respectively connected to the output end of the second operational amplifier and the output end of the third operational amplifier, and the output end of the logic processing module is respectively connected to the control end of the first switch, the control end of the second switch, and the control end of the third switch.

7. The temperature compensation circuit according to claim 6, characterized in that: The logic processing module includes: an XNOR logic gate, wherein a first input terminal of the XNOR logic gate is connected to an output terminal of the second operational amplifier, a second input terminal of the XNOR logic gate is connected to an output terminal of the third operational amplifier, and an output terminal of the XNOR logic gate is connected to a control terminal of the third switch; an OR logic gate, wherein a first input terminal of the OR logic gate is connected to an output terminal of the second operational amplifier, a second input terminal of the OR logic gate is connected to an output terminal of the third operational amplifier, and an output terminal of the OR logic gate is connected to a control terminal of the first switch; A NAND gate, wherein a first input terminal of the NAND gate is connected to an output terminal of the second operational amplifier, a second input terminal of the NAND gate is connected to an output terminal of the third operational amplifier, and an output terminal of the NAND gate is connected to a control terminal of a second switch.

8. The temperature compensation circuit according to claim 1, characterized in that: The first current module comprises: A first MOS transistor, wherein a first end of the first MOS transistor is configured to input a power supply voltage signal, and a control end of the first MOS transistor is connected to a control end of the first mirror module and a control end of the third mirror module; A second resistor, a first end of the second resistor is connected to the second end of the first MOS tube; a third resistor, a first end of the third resistor being connected to a second end of the second resistor; a fourth resistor, a first end of the fourth resistor being connected to a second end of the second resistor; a fourth operational amplifier, wherein a first input end of the fourth operational amplifier is connected to the second end of the fourth resistor, a second input end of the fourth operational amplifier is connected to the second end of the third resistor, and an output end of the fourth operational amplifier is connected to the control end of the first MOS tube; a fifth resistor, a first end of the fifth resistor being connected to the first input end of the fourth operational amplifier; A first triode, wherein a first end of the first triode is connected to the second input end of the fourth operational amplifier, and a second end and a control end of the first triode are grounded; a second triode, wherein a first end of the second triode is connected to a second end of the fifth resistor, and a second end of the second triode and a control end are grounded; or The second current module comprises: A second MOS transistor, wherein a first end of the second MOS transistor is configured to input a power supply voltage signal, and a control end of the second MOS transistor is connected to a control end of a second mirror module; a third MOS tube, a first end of the third MOS tube being connected to a second end of the second MOS tube; a sixth resistor, wherein a first end of the sixth resistor is connected to the second end of the third MOS tube, and a second end of the sixth resistor is grounded; A current source, a first end of which is connected to a first end of the second MOS tube; a fifth operational amplifier, wherein a first input terminal of the fifth operational amplifier is connected to the second terminal of the current source, a second input terminal of the fifth operational amplifier is connected to the first terminal of the sixth resistor, and an output terminal of the fifth operational amplifier is connected to the control terminal of the third MOS tube; A third triode, wherein the first end of the third triode is connected to the first input end of the fifth operational amplifier, and the second end and the control end of the third triode are grounded; or The reference voltage module comprises: a seventh resistor, wherein a first end of the seventh resistor is configured to input a power supply voltage signal; an eighth resistor, a first end of the eighth resistor being connected to the second end of the seventh resistor, and a second end of the eighth resistor being grounded; Wherein, the voltage division node between the seventh resistor and the eighth resistor is configured to output the reference voltage signal.

9. The temperature compensation circuit according to claim 4, characterized in that: The third current module comprises: A fourth MOS tube, wherein a first end of the fourth MOS tube is configured to input a power supply voltage signal, and a control end of the fourth MOS tube is connected to a control end of a fourth mirror module; a fifth MOS tube, wherein a first end of the fifth MOS tube is connected to a second end of the fourth MOS tube; a ninth resistor, wherein a first end of the ninth resistor is connected to the second end of the fifth MOS tube, and a second end of the ninth resistor is grounded; a sixth operational amplifier, wherein a first input terminal of the sixth operational amplifier is grounded, a second input terminal of the sixth operational amplifier is connected to the first terminal of the ninth resistor, and an output terminal of the sixth operational amplifier is connected to the control terminal of the fifth MOS tube; A voltage source, a first end of the voltage source is connected to the first input end of the sixth operational amplifier, and a second end of the voltage source is grounded.

10. An electronic device, characterized in that: The electronic device comprises the temperature compensation circuit as claimed in any one of claims 1 to 9.

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