Voltage drop compensation method and related device

Abstract

The invention provides a voltage drop compensation method and a related device, and the method comprises the steps: receiving a feedback signal from a calculation chip, the feedback signal being used for representing that the calculation chip starts to execute a target calculation program; obtaining current output delay of the power management chip; obtaining a running state of the target calculation program; when the running state of the target calculation program is a target state, a current output signal is sent to a power management chip, and the target state is used for representing that the time interval between the current time point and the target time point is equal to the current output delay; the target time point refers to the time point when the calculation chip executes the high-power-consumption calculation task next time to generate the voltage drop. Therefore, when the calculation chip executes a high-power-consumption calculation task next time to generate the voltage drop, the generated large voltage drop can be compensated through the output peak current, and operation faults of the chip are avoided.

Description

Technical Field

[0001] The present application belongs to the technical field of electrical digital data processing, and specifically relates to a voltage drop compensation method and related devices. Background Art

[0002] Currently, when computing devices are running large computing programs, a large voltage drop will occur on their computing chips, and excessive voltage drop is likely to cause chip operation failures.

[0003] In order to avoid the above situation, the voltage drop of the chip needs to be compensated. The traditional method is to modify the circuit design and add capacitors to achieve this. However, this method involves the addition and modification of hardware, which takes up a large amount of PCB (Printed circuit board) area and increases the board manufacturing cost. Summary of the invention

[0004] The embodiments of the present application provide a voltage drop compensation method and related devices, in order to reduce the voltage drop through a software program and avoid operational failures of the chip.

[0005] In a first aspect, an embodiment of the present application provides a voltage drop compensation method, which is applied to a controller on a target board, wherein the target board is provided with the controller, a computing chip, and a power management chip, and the method comprises:

[0006] receiving a feedback signal from the computing chip, wherein the feedback signal is used to indicate that the computing chip starts to execute a target computing program, wherein the target computing program includes a plurality of computing tasks, wherein the plurality of computing tasks include at least one high-power computing task;

[0007] Obtaining a current output delay of the power management chip, where the current output delay refers to the time required for the power management chip to output a peak current from receiving a current output signal;

[0008] Obtaining the running status of the target computing program;

[0009] When the running state of the target computing program is the target state, the current output signal is sent to the power management chip. The target state is used to characterize that the time interval between the current time point and the target time point is equal to the current output delay. The target time point refers to the time point when the computing chip next executes a high-power computing task and generates a voltage drop.

[0010] In a second aspect, an embodiment of the present application provides a voltage drop compensation device, which is applied to a controller on a target board, and the target board is provided with the controller, a computing chip and a power management chip, and the device includes:

[0011] A receiving unit, configured to receive a feedback signal from the computing chip, wherein the feedback signal is used to indicate that the computing chip starts to execute a target computing program, wherein the target computing program includes a plurality of computing tasks, wherein the plurality of computing tasks include at least one high-power computing task;

[0012] A first acquisition unit, used to acquire the current output delay of the power management chip, where the current output delay refers to the time required for the power management chip to output the peak current from receiving the current output signal;

[0013] A second acquisition unit, used to acquire the running status of the target computing program;

[0014] A sending unit is used to send the current output signal to the power management chip when the running state of the target computing program is the target state, and the target state is used to characterize that the time interval between the current time point and the target time point is equal to the current output delay, and the target time point refers to the time point when the computing chip next executes a high-power computing task and generates a voltage drop.

[0015] In a third aspect, an embodiment of the present application provides a controller comprising a processor, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the program comprises instructions for executing the steps in the first aspect of the embodiment of the present application.

[0016] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program / instructions stored thereon, which, when executed by a processor, implement the steps in the first aspect of the embodiment of the present application.

[0017] It can be seen that in the embodiment of the present application, the controller can obtain the current output delay of the power management chip and the running state of the target computing program when determining that the computing chip starts to execute the target computing program, so that when the running state of the target computing program is the target state, the current output signal is sent to the power management chip, so that the power management chip can successfully output the peak current when the computing chip performs a high-power computing task next time and generates a voltage drop, and compensate for the large voltage drop generated by the peak current. In this way, the voltage drop caused by the computing chip performing a high-power computing task can be reduced without modifying the circuit design, avoiding operational failures of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a structural block diagram of a target board provided in an embodiment of the present application;

[0020] Figure 2 It is a flow chart of a voltage drop compensation method provided in an embodiment of the present application;

[0021] Figure 3 It is the oscilloscope waveform without voltage drop compensation;

[0022] Figure 4 This is the oscilloscope waveform when the monitoring path delay is not adjusted;

[0023] Figure 5 It is the oscilloscope waveform after adjusting the monitoring path delay;

[0024] Figure 6 It is a structural block diagram of a voltage drop compensation device provided in an embodiment of the present application;

[0025] Figure 7 is a structural block diagram of another voltage drop compensation device provided in an embodiment of the present application;

[0026] Figure 8 It is a structural block diagram of a controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0029] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0030] See also Figure 1 , Figure 1 : is a structural block diagram of a target board provided in an embodiment of the present application. Figure 1 As shown, the target board 10 is provided with a controller 11, a computing chip 12 and a power management chip 13. Among them, the computing chip 12 is used to run the computing program and execute each computing task in the computing program; the power management chip 13 is used to power the entire system, and can output the peak current after a certain delay when receiving the current output signal. Under normal circumstances, the computing chip 12 will generate voltage drops of different magnitudes when it starts to execute the computing task. The greater the power consumption required for the computing task to be executed, the higher the magnitude of the voltage drop generated by it is. When the voltage drop drops to a certain extent, it may cause the operation failure of the chip. Therefore, testers usually mark the computing tasks that generate large voltage drops as high-power computing tasks, and carry out targeted design to minimize the impact of the large voltage drops generated when executing such computing tasks on the chip. Specifically, the computing chip 12 can be an RPP (Reconfigurable Parallel Processing) chip.

[0031] A voltage drop compensation method provided in an embodiment of the present application is introduced below.

[0032] See also Figure 2 , Figure 2 is a flow chart of a voltage drop compensation method provided in an embodiment of the present application, which is applied to Figure 1 In the controller 11 shown, as Figure 2 As shown, the method includes:

[0033] S201, receiving a feedback signal from the computing chip.

[0034] Among them, the feedback signal is used to characterize that the computing chip starts to execute the target computing program, and the target computing program includes multiple computing tasks, and the multiple computing tasks include at least one high-power computing task. That is, when the computing chip starts to execute the target computing program including the high-power computing task, it sends a feedback signal to the controller, and the controller triggers the voltage drop compensation mechanism involved in the embodiment of the present application after receiving the feedback signal. Specifically, the high-power computing task can be a Kernel task.

[0035] S202, obtaining the current output delay of the power management chip.

[0036] The current output delay refers to the time required for the power management chip to output the peak current from receiving the current output signal, and the current output signal is specifically expressed as a pulse. Therefore, if the pulse is applied only when it is detected that the chip starts to execute a high-power computing task, due to the current output delay, the peak current cannot arrive at the start time of the execution of the high-power computing task, and when the subsequent peak current arrives, the charge stored in the capacitor itself can no longer support such a large current.

[0037] The current output delay can be data written manually after testing. Specifically, the tester uses an oscilloscope to manually give the PMIC (Power Management IC) a feedback signal, which is a pulse. The width of the pulse is continuously adjusted. At this time, the larger the width of the pulse, the higher the output current peak. The time interval between the time point of giving the pulse and the time point of the maximum current peak is the current output delay, and this data can be obtained from the oscilloscope.

[0038] S203, obtaining the running status of the target computing program.

[0039] S204, when the running state of the target computing program is the target state, sending the current output signal to the power management chip.

[0040] In the embodiment of the present application, the operation state of the target computing program may be acquired by the controller monitoring the operation state of the target computing program until the operation state of the target computing program is the target state. In other embodiments, the operation state of the target computing program may be acquired by the computing chip sending a signal to the controller to inform the controller that the operation state of the target computing program is the target state when the computing chip detects that the operation state of the target computing program is the target state, which is not limited here.

[0041] In the embodiment of the present application, the running state of the target computing program includes a target state and a non-target state. The target state is used to indicate that the time interval between the current time point and the target time point is equal to the current output delay, and the target time point refers to the time point when the computing chip next performs a high-power computing task and generates a voltage drop.

[0042] It can be seen that in the embodiment of the present application, the controller can obtain the current output delay of the power management chip and the running state of the target computing program when determining that the computing chip starts to execute the target computing program, so that when the running state of the target computing program is the target state, the current output signal is sent to the power management chip, so that the power management chip can successfully output the peak current when the computing chip performs a high-power computing task next time and generates a voltage drop, and compensate for the large voltage drop generated by the peak current. In this way, the voltage drop caused by the computing chip performing a high-power computing task can be reduced without modifying the circuit design, avoiding operational failures of the chip.

[0043] In one possible example, obtaining the running status of the target computing program includes: sending a status query instruction to the computing chip, the status query instruction is used to obtain the running time, preset execution information and actual execution information of the target computing program, the running time is used to indicate the current time point, the preset execution information includes the preset execution order, the preset execution start time point and the preset execution end time point of each computing task in the multiple computing tasks, and the actual execution information is used to characterize the execution progress of the target computing program at the current time point; determining the target computing task according to the actual execution information and the preset execution order of each computing task, The target computing task refers to the next high-power computing task to be executed by the computing chip; based on the preset execution order of each computing task and the target computing task, it is determined whether there is a reference computing task, and the reference computing task refers to a computing task whose preset execution order is one position before the preset execution order of the target computing task; if it exists, the running status of the target computing program is determined according to the actual execution information and the reference computing task; if it does not exist, the preset execution start time point of the target computing task is determined to be the target time point; and the running status of the target computing program is determined according to the current time point, the target time point and the current output delay.

[0044] Among them, in this example, the controller obtains the running status of the target computing program by monitoring. Specifically, monitoring the running status of the target computing program depends on the monitoring path delay, and the monitoring path delay refers to the time interval required for the controller to access the computing chip twice in a row. In each visit, the controller obtains the running time, preset execution information and actual execution information of the target computing program by sending a status query instruction to the computing chip, wherein the current time point is determined by the running time, that is, in the embodiment of the present application, the target computing program starts running as the reference origin, and the running state of the target computing program is characterized by the running time. For example, if the monitoring path delay is 1 microsecond, the controller can obtain the running state of the target computing program at 1 microsecond, 2 microseconds, 3 microseconds and other time points when the program is running; if the monitoring path delay is 0.5 microseconds, the controller can obtain the running state of the target computing program at 0.5 microseconds, 1 microsecond, 1.5 microseconds and other time points when the program is running.

[0045] Among them, the target computing program to be executed by the computing chip is known, that is, each computing task in the target computing program has corresponding preset execution information, that is, the preset execution order, the preset execution start time point and the preset execution end time point. This information is stored in the storage unit of the computing chip. After receiving the status query instruction of the controller, the computing chip will call out this data and send it to the controller.

[0046] Normally, if there is no problem in the program running process, each computing task will be executed according to the preset execution information. In this case, the time point when the high-power computing task starts to execute can be clearly determined, that is, the time point when a large voltage drop is generated can be determined, and then the running state of the target computing program can be clearly determined. In particular, if it is determined at the current time point that there is no reference computing task, it indicates that the target computing task is the first computing task of the target computing program. At this time, the default program operation is normal, and it is determined that the target computing task can start execution at its corresponding preset execution start time point, then the preset execution start time point of the target computing task is determined to be the target time point, and then according to the current time point, the target time point and the current output delay, it is determined whether the running state of the target computing program is the target state. For example, taking task B as the target computing task, assuming that task B is the first computing task of the target computing program, its corresponding preset execution start time point is 5 microseconds of the program running, and the current output delay is 3 microseconds. Then, 2 microseconds of the program running is the target state. At this time, sending a current output signal to the power management chip can make the peak current reach the computing chip just at 5 microseconds of the program running to compensate for the generated voltage drop.

[0047] However, during the actual operation of the program, there may be various problems that lead to early or delayed execution of computing tasks, and the time point at which the high-power computing task starts execution may also change, resulting in inconsistency with the preset execution start time point. At this time, the running state of the target computing program cannot be accurately determined based on the preset execution start time point of the target computing task. In response to this problem, the embodiment of the present application determines the running state of the target computing program based on the actual execution information of the target computing program and the reference computing task that precedes the target computing task in the preset execution order, comprehensively considers the actual running situation of the target computing program, and then determines the running state of the target computing program. Among them, the actual execution information is used to characterize the execution progress of the target computing program at the current time point, and may specifically include the execution information of the computing tasks that have been executed, such as the actual execution start time point, the actual execution end time point, the actual execution duration, etc.

[0048] It can be seen that in this example, the controller obtains the running time, preset execution information and actual execution information of the target computing program by sending a status query instruction to the computing chip, and then determines the target computing task that will produce a large voltage drop, and determines the running state of the target computing program according to the actual execution information and the reference computing task when there is a reference computing task, and directly determines the preset execution start time point of the target computing task as the target time point when there is no reference computing task, thereby determining the running state of the target computing program according to the current time point, the target time point and the current output delay. In this way, the controller can directly determine the target time point and then determine the running state of the target computing program when the first computing task of the target computing program is a high-power computing task, which simplifies the calculation process, reduces the amount of calculation of the system, improves the accuracy of the calculation results, and thus improves the compensation effect of the voltage drop.

[0049] In one possible example, determining the running status of the target computing program based on the actual execution information and the reference computing task includes: judging whether the reference computing task is a computing task that has been executed based on the actual execution information; if so, determining the running status of the target computing program based on the preset execution information and the actual execution information; if not, determining that the running status of the target computing program is not the target status.

[0050] For example, the scheme is described below by taking Task A as the reference computing task and Task B as the target computing task. Each computing task in the target computing program has a preset execution order, that is, each computing task is serial, and Task A is the previous task of Task B. At this time, the controller sends a status query instruction to the computing chip at the current time point, and uses whether Task A has been completed as the detection standard. The target computing program includes three situations: Task A has not started to execute, Task A is being executed, and Task A has been completed. Task A has not started to execute and Task A is being executed can be summarized as the situation where Task A has not been completed. In this case, since it is impossible to determine whether the execution process of Task A will be accelerated or delayed, that is, it is impossible to determine when Task A will be completed, it is impossible to determine the task start execution time point of Task B, that is, the target time point, and thus it is impossible to determine the running status of the target computing program. Based on the above situation, in this example, if task A is not completed, it is determined that the running state of the target computing program is not the target state. Only when task A is completed, the running state of the target computing program is further determined based on the preset execution information and the actual execution information, thereby avoiding the situation where the target time point cannot be accurately determined due to the delay or advance of the execution of other computing tasks, and thus the running state of the target computing program cannot be accurately determined.

[0051] It can be seen that in this example, when there is a reference computing task in the target computing program, the controller determines whether the reference computing task has been completed based on the actual execution information. If the reference computing task has not been completed at the current time point, it is directly determined that the running state of the target computing program is not the target state. If the reference computing task has been completed at the current time point, the running state of the target computing program is further determined based on the preset execution information and the actual execution information, thereby avoiding the situation where the running state of the target computing program cannot be accurately determined due to the delay or advance execution of other computing tasks, thereby improving the accuracy of the calculation results and thereby improving the compensation effect of the voltage drop.

[0052] In one possible example, the actual execution information includes the actual execution end time point of the reference computing task, and determining the running status of the target computing program based on the preset execution information and the actual execution information includes: determining the task execution time interval based on the preset execution end time point of the reference computing task and the preset execution start time point of the target computing task; determining the running status of the target computing program based on the actual execution end time point of the reference computing task, the task execution time interval and the current output delay.

[0053] Among them, when designing a computing program, a tester or designer may design a time interval between two consecutive computing tasks. This time interval is usually used to allow the previous computing task to completely write the calculation results into the memory, so as to avoid data inconsistency when the subsequent computing task needs to use the calculation results of the previous computing task as the basis for calculation. Among them, the task execution time interval can be calculated based on the preset execution end time point of the reference computing task and the preset execution start time point of the target computing task. Taking task A as the reference computing task and task B as the target computing task as an example, the preset execution end time point of task A is 50 microseconds of the program running, and the preset execution start time point of task B is 52 microseconds of the program running. Then the task execution time interval between task A and task B is 2 microseconds. Furthermore, if task A is delayed or advanced during the execution process, the actual execution end time point of task A will be inconsistent with its corresponding preset execution end time point. At this time, the target time point cannot be determined, and the running state of the target computing program cannot be determined. The task execution time interval can associate the execution start time point of task B with task A. Therefore, in this example, the running status of the target computing program can be further determined by the actual execution end time point of task A, the task execution time interval and the current output delay.

[0054] It can be seen that in this example, when the reference computing task is a computing task that has been completed, the controller determines the task execution time interval based on the preset execution end time point of the reference computing task and the preset execution start time point of the target computing task, and then determines the running state of the target computing program based on the actual execution end time point of the reference computing task, the task execution time interval and the current output delay. In this way, the target computing task is associated with the reference computing task through the task execution time interval. When the actual execution information of the reference computing task is known, the execution information of the target computing task, i.e., the high-power computing task, can be determined, thereby determining the running state of the target computing program, improving the accuracy of the calculation results, and further improving the compensation effect of the voltage drop.

[0055] In one possible example, determining the running state of the target computing program based on the actual execution end time point of the reference computing task, the task execution time interval and the current output delay includes: determining the task execution start time point of the target computing task based on the actual execution end time point of the reference computing task and the task execution time interval; if the task execution time interval is greater than or equal to the current output delay, determining the task execution start time point of the target computing task as the target time point; if the task execution time interval is less than the current output delay, determining the target time point based on the actual execution end time point of the reference computing task and the current output delay; determining the running state of the target computing program based on the current time point, the target time point and the current output delay.

[0056] Among them, taking task A as the reference computing task and task B as the target computing task as an example, assuming that the preset execution end time point of task A is 50 microseconds of the program running, and the preset execution start time point of task B is 52 microseconds of the program running, then the task execution time interval is 2 microseconds. The actual execution end time point of task A is 55 microseconds of the program running, then it can be calculated that the task execution start time point of task B is 57 microseconds of the program running.

[0057] It should be noted that, in this example, the running state of the target computing program can only be the target state after task A is executed, and the controller will send a current output signal to the PMIC, that is, the earliest time point when the controller sends a current output signal to the PMIC is the actual execution end time point of task A, such as 55 microseconds in the above example.

[0058] In this case, if the task execution time interval is greater than or equal to the current output delay, for example, the task execution time interval is 5 microseconds and the current output delay is 3 microseconds, then task B will start to execute at 60 microseconds, and the controller can detect that the running state of the target computing program is the target state at 57 microseconds and then send a current output signal to the PMIC, so that the peak current can be output at 60 microseconds to compensate for the voltage drop. In other words, when the task execution time interval is greater than or equal to the current output delay, the peak current can be output in time when task B starts to execute, and no adjustment is required at this time, and the task execution start time point of task B is determined to be the target time point.

[0059] However, if the task execution time interval is less than the current output delay, for example, the task execution time interval is 2 microseconds and the current output delay is 3 microseconds, then task B will start executing at 57 microseconds, and task A will be completed at 55 microseconds, that is, the earliest time point when the controller sends a current output signal to the PMIC is 55 microseconds, and the peak current will not be output until 58 microseconds at the earliest, and the voltage drop generated at 57 microseconds cannot be compensated. At this time, it is necessary to modify the target time point at which the computing chip will generate a large voltage drop when executing task B, so that the peak current output can compensate for the large voltage drop generated. In this example, after detecting that the task execution time interval is less than the current output delay, the controller re-determines the target time point based on the actual execution end time point of task A and the current output delay, and then determines the running status of the target computing program.

[0060] It can be seen that in this example, the controller first determines the task start execution time point of the target computing task, and then determines whether it is necessary to modify the target time point of the large voltage drop generated by the computing chip when executing the target computing task by comparing the size relationship between the task execution time interval and the current output delay. If the task execution time interval is greater than or equal to the current output delay, it is determined that the target time point does not need to be modified, and the task start execution time point of the target computing task is determined as the target time point. If the task execution time interval is less than the current output delay, it is determined that the target time point needs to be modified, and the target time point is determined according to the actual execution end time point of the reference computing task and the current output delay. Finally, the running state of the target computing program is determined according to the current time point, the target time point and the current output delay. In this way, the controller can determine the target time point according to the size relationship between the task execution time interval and the current output delay, thereby ensuring that the peak current can be output in time to compensate when a large voltage drop is generated, thereby improving the compensation effect of the voltage drop.

[0061] In one possible example, determining the target time point based on the actual execution end time point of the reference computing task and the current output delay includes: determining a time point that is after the actual execution end time point of the reference computing task and whose time interval with the actual execution end time point of the reference computing task is the current output delay as the target time point.

[0062] Among them, taking task A as the reference computing task, task B as the target computing task, the actual execution end time point of task A at 55 microseconds, the task execution start time point of task B at 57 microseconds, and the current output delay of 3 microseconds as an example, that is, the task execution time interval is 2 microseconds, and it is necessary to re-determine the target time point so that the peak current can be output in time at the target time point to compensate for the voltage drop. Among them, the target time point only needs to satisfy that the time interval between the actual execution end time point of task A is greater than or equal to the current output delay, that is, the target time point only needs to be at 58 microseconds and later, and the peak current can be output in time for compensation. In particular, in this example, the time point that is located after the actual execution end time point of the reference computing task and the time interval between the actual execution end time point of the reference computing task and the current output delay is determined as the target time point, that is, 58 microseconds is determined as the target time point when the computing chip generates a large voltage drop when executing task B.

[0063] It can be seen that in this example, when the task execution time interval is less than the current output delay, the controller determines the time point that is after the actual execution end time point of the reference calculation task and whose time interval with the actual execution end time point of the reference calculation task is the current output delay as the target time point, so that the peak current can be output in time to compensate for the voltage drop, thereby improving the compensation effect for the voltage drop.

[0064] In one possible example, the task execution time interval is less than the current output delay, and after sending the current output signal to the power management chip, the method further includes: sending a frequency reduction instruction to the computing chip, the frequency reduction instruction being used to instruct the computing chip to reduce the clock frequency at the task execution start time point of the target computing task, and to restore the clock frequency at the target time point.

[0065] Among them, the computing chip usually generates a large voltage drop when it starts to execute a high-power computing task. When the task execution time interval is less than the current output delay, it is necessary to modify the time point when the large voltage drop is generated. Specifically, there are multiple modification methods. In this example, after the controller determines that the running state of the target computing program is the target state and sends a current output signal to the PMIC, it sends a frequency reduction instruction to the computing chip, so that the computing chip reduces the clock frequency when it starts to execute the target computing task. Such a large voltage drop will not be generated in the low-frequency stage, and the clock frequency will be restored at the target time point. When the computing chip restores the clock frequency, a voltage drop will also occur, and at this time the peak current is just output for compensation.

[0066] For example, the current time point, i.e., the time point when the controller sends a current output signal to the PMIC, is 55 microseconds, the start time point of task execution of task B is 57 microseconds, and the target time point is 58 microseconds. The controller sends a frequency reduction instruction to the computing chip at 55 microseconds at the same time, so that the computing chip reduces its own clock frequency when it starts executing task B at 57 microseconds, and restores the clock frequency at 58 microseconds, so that a large voltage drop is generated at 58 microseconds, and the peak current is also output at 58 microseconds, thereby compensating for the large voltage drop.

[0067] It can be seen that in this example, after sending the current output signal to the power management chip, the controller sends a frequency reduction instruction to the computing chip, so that the computing chip reduces the clock frequency when it starts to execute the target computing task, and restores the clock frequency at the target time point, ensuring that the peak current can be output in time when a large voltage drop occurs, thereby improving the compensation effect for the voltage drop.

[0068] The scheme involved in the embodiments of the present application is explained below through specific examples.

[0069] Let's assume that the actual execution end time of task A is 60 microseconds and the current output delay is 3 microseconds. Then, the following situations can be classified according to the different time intervals of task execution:

[0070] (1) The task execution time interval is 2 microseconds, and task B starts to execute at 62 microseconds. In this case, the controller sends a current output signal to the PMIC at 60 microseconds and sends a frequency reduction instruction to the computing chip, causing the computing chip to reduce the frequency at 62 microseconds and restore the frequency at 63 microseconds. At this time, a large voltage drop and peak current are both generated at 63 microseconds to achieve compensation.

[0071] (2) The task execution time interval is 3 μs, and task B starts to execute at 63 μs. In this case, the controller sends a current output signal to the PMIC at 60 μs. At this time, a large voltage drop and a peak current are both generated at 63 μs to achieve compensation.

[0072] (3) The task execution time interval is 4 μs, and task B starts to execute at 64 μs. In this case, the controller sends a current output signal to the PMIC at 61 μs. At this time, a large voltage drop and a peak current are both generated at 64 μs to achieve compensation.

[0073] It should be noted that the controller monitors the running state of the target computing program depending on the monitoring path delay. The monitoring path delay refers to the time interval required for the controller to send status query instructions to the computing chip twice in a row. Due to the influence of the monitoring path delay, the controller may not be able to obtain the time point corresponding to the target state of the running state of the target computing program. For example, the target time point is recorded as 30.5 microseconds when the program is running, and the current output delay is 3 microseconds. In this scenario, the time point corresponding to the target state should be 27.5 microseconds when the program is running. If the monitoring path delay is 1 microsecond at this time, the controller can only obtain the time point corresponding to the target state at 27 microseconds and 28 microseconds when the program is running. Although the controller can send a current output signal to the power management chip at 27 microseconds and 28 microseconds when the program is running, so that the peak current arrives at the closest target time point, the compensation effect is not good and there is an error.

[0074] Based on this, after determining the target time point, the controller can further calculate the time point corresponding to the target state based on the target time point and the current output delay, and then adjust the monitoring path delay according to the time point, so that the controller can obtain the running status of the target computing program at the corresponding time point, and send a current output signal to the power management chip to achieve the effect of on-time compensation.

[0075] Specifically, the monitoring path delay can be shortened by increasing the clock frequency of the monitoring path; the monitoring path delay can also be shortened by adjusting the programmed monitoring loop algorithm. Taking the monitoring loop algorithm as a while(1) loop as an example, irrelevant programs can be deleted to achieve the effect of shortening the monitoring path delay.

[0076] See also Figure 3-Figure 5 , Figure 3 This is the oscilloscope waveform without voltage drop compensation. Figure 4 This is the oscilloscope waveform when the monitoring path delay is not adjusted. Figure 5 This is the oscilloscope waveform after adjusting the monitoring path delay. The horizontal axis in the figure is the time axis, and the vertical axis is the operating voltage of the parallel computing chip. The C3 baseline represents the voltage applied to the parallel computing chip, which is 810mV. Figure 3 It can be seen that under the input voltage of 810mV, the core operating voltage of the parallel computing chip is about 800mV. Among them, a large voltage drop occurs from 90us to 100us, and the lowest voltage drops to between 760mV and 770mV, about 763mV. Figure 4 In the example, the delay of the monitoring path was not adjusted, which resulted in a chaotic waveform after the pulse was applied, resulting in a large error. Figure 5 After the delay of the monitoring path is adjusted, the lowest working voltage is about 778mV, which is lower than Figure 3 The rise was about 15mV, which was in line with expectations.

[0077] It can be understood that the process of determining the running status of the target computing program in the above-mentioned embodiment can also be completed by the computing chip and synchronized to the controller when the running status of the target computing program is the target state, so that the controller directly sends a current output signal to the power management chip after receiving the synchronization signal from the computing chip, thereby realizing voltage drop compensation, thereby reducing the resource consumption of the controller.

[0078] In accordance with the above-mentioned embodiments, please refer to Figure 6 , Figure 6 is a structural block diagram of a voltage drop compensation device provided in an embodiment of the present application, and the device is applied to Figure 1 In the controller 11 shown, the voltage drop compensation device 60 includes: a receiving unit 601, which is used to receive a feedback signal from the computing chip, and the feedback signal is used to indicate that the computing chip starts to execute a target computing program, and the target computing program includes multiple computing tasks, and the multiple computing tasks include at least one high-power computing task; a first acquisition unit 602, which is used to obtain the current output delay of the power management chip, and the current output delay refers to the time required for the power management chip to output the peak current from receiving the current output signal; a second acquisition unit 603, which is used to obtain the running state of the target computing program; a sending unit 604, which is used to send the current output signal to the power management chip when the running state of the target computing program is the target state, and the target state is used to indicate that the time interval between the current time point and the target time point is equal to the current output delay, and the target time point refers to the time point when the computing chip next executes a high-power computing task and generates a voltage drop.

[0079] In one possible example, in terms of obtaining the running status of the target computing program, the second obtaining unit 603 is specifically used to: send a status query instruction to the computing chip, the status query instruction is used to obtain the running time, preset execution information and actual execution information of the target computing program, the running time is used to indicate the current time point, the preset execution information includes the preset execution order, preset execution start time point and preset execution end time point of each computing task in the multiple computing tasks, and the actual execution information is used to characterize the execution progress of the target computing program at the current time point; determine the target computing program according to the actual execution information and the preset execution order of each computing task A target computing task, wherein the target computing task refers to the next high-power computing task to be executed by the computing chip; judging whether there is a reference computing task according to the preset execution order of each computing task and the target computing task, wherein the reference computing task refers to a computing task whose preset execution order is one position before the preset execution order of the target computing task; if so, determining the running state of the target computing program according to the actual execution information and the reference computing task; if not, determining the preset execution start time point of the target computing task as the target time point; and determining the running state of the target computing program according to the current time point, the target time point and the current output delay.

[0080] In one possible example, in terms of determining the running state of the target computing program based on the actual execution information and the reference computing task, the second acquisition unit 603 is specifically used to: determine whether the reference computing task is a computing task that has been executed based on the actual execution information; if so, determine the running state of the target computing program based on the preset execution information and the actual execution information; if not, determine that the running state of the target computing program is not the target state.

[0081] In one possible example, the actual execution information includes the actual execution end time point of the reference computing task. In terms of determining the running status of the target computing program based on the preset execution information and the actual execution information, the second acquisition unit 603 is specifically used to: determine the task execution time interval based on the preset execution end time point of the reference computing task and the preset execution start time point of the target computing task; determine the running status of the target computing program based on the actual execution end time point of the reference computing task, the task execution time interval and the current output delay.

[0082] In one possible example, in terms of determining the running status of the target computing program based on the actual execution end time point of the reference computing task, the task execution time interval and the current output delay, the second acquisition unit 603 is specifically used to: determine the task start execution time point of the target computing task based on the actual execution end time point of the reference computing task and the task execution time interval; if the task execution time interval is greater than or equal to the current output delay, determine the task start execution time point of the target computing task as the target time point; if the task execution time interval is less than the current output delay, determine the target time point based on the actual execution end time point of the reference computing task and the current output delay; determine the running status of the target computing program based on the current time point, the target time point and the current output delay.

[0083] In one possible example, in terms of determining the target time point based on the actual execution end time point of the reference computing task and the current output delay, the second acquisition unit 603 is specifically used to: determine a time point that is after the actual execution end time point of the reference computing task and whose time interval with the actual execution end time point of the reference computing task is the current output delay as the target time point.

[0084] In one possible example, when the task execution time interval is less than the current output delay, after sending the current output signal to the power management chip, the voltage drop compensation device 60 is further used to: send a frequency reduction instruction to the computing chip, wherein the frequency reduction instruction is used to instruct the computing chip to reduce the clock frequency at the task execution start time point of the target computing task and restore the clock frequency at the target time point.

[0085] It can be understood that since the method embodiment and the device embodiment are different presentation forms of the same technical concept, the content of the method embodiment part in this application should be synchronously adapted to the device embodiment part and will not be repeated here.

[0086] In the case of integrated units, such as Figure 7 As shown, Figure 7 is a structural block diagram of another voltage drop compensation device provided in an embodiment of the present application. Figure 7In the embodiment, the voltage drop compensation device 60 includes: a processing module 62 and a communication module 61. The processing module 62 is used to control and manage the actions of the voltage drop compensation device, for example, to execute the steps of the receiving unit 601, the first acquisition unit 602, the second acquisition unit 603 and the sending unit 604, and / or to execute other processes of the technology described herein. The communication module 61 is used to support the interaction between the voltage drop compensation device and other devices. Figure 7 As shown, the voltage drop compensation device may further include a storage module 63, and the storage module 63 is used to store program codes and data of the voltage drop compensation device.

[0087] Among them, all relevant contents of each scenario involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here. The above voltage drop compensation device 60 can execute the above Figure 2 The voltage drop compensation method shown.

[0088] See also Figure 8 , Figure 8 is a structural block diagram of a controller provided in an embodiment of the present application. Figure 8 As shown, the controller may include one or more of the following components: a processor 801, and a memory 802 coupled to the processor 801, wherein the memory 802 may store one or more computer programs, and the one or more computer programs may be configured to implement the methods described in the above embodiments when executed by one or more processors 801.

[0089] The processor 801 may include one or more processing cores. The processor 801 uses various interfaces and lines to connect various parts of the entire controller, and executes various functions of the controller and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 802, and calling data stored in the memory 802.

[0090] The memory 802 may be used to store instructions, programs, codes, code sets or instruction sets. The memory 802 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the above-mentioned various method embodiments, etc. The data storage area may also store data created by the controller during use, etc.

[0091] It can be understood that the controller may include more or fewer structural elements than those in the above structural block diagram, which is not limited here.

[0092] An embodiment of the present application also provides a computer storage medium, on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, part or all of the steps of any method recorded in the above method embodiments are implemented.

[0093] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0094] In the several embodiments provided in the present application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0095] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0096] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions without departing from the spirit and scope of the present invention, and can make various changes and modifications, including the combination of the above-mentioned different functions and implementation steps, including software and hardware implementation methods, all of which are within the scope of protection of the present invention.

Claims

1. A voltage drop compensation method, characterized in that: A controller applied to a target board, wherein the target board is provided with the controller, a computing chip and a power management chip, and the method comprises: receiving a feedback signal from the computing chip, wherein the feedback signal is used to indicate that the computing chip starts to execute a target computing program, wherein the target computing program includes a plurality of computing tasks, wherein the plurality of computing tasks include at least one high-power computing task; Obtaining a current output delay of the power management chip, where the current output delay refers to the time required for the power management chip to output a peak current from receiving a current output signal; Obtaining the running status of the target computing program; When the running state of the target computing program is the target state, the current output signal is sent to the power management chip. The target state is used to characterize that the time interval between the current time point and the target time point is equal to the current output delay. The target time point refers to the time point when the computing chip next executes a high-power computing task and generates a voltage drop.

2. The method according to claim 1, characterized in that The obtaining the running status of the target computing program includes: Sending a status query instruction to the computing chip, the status query instruction is used to obtain the running time, preset execution information and actual execution information of the target computing program, the running time is used to indicate the current time point, the preset execution information includes the preset execution order, the preset execution start time point and the preset execution end time point of each computing task in the multiple computing tasks, and the actual execution information is used to characterize the execution progress of the target computing program at the current time point; Determining a target computing task according to the actual execution information and a preset execution order of each computing task, wherein the target computing task refers to a next high-power consumption computing task to be executed by the computing chip; Determining whether there is a reference computing task according to the preset execution order of each computing task and the target computing task, wherein the reference computing task refers to a computing task whose preset execution order is one position before the preset execution order of the target computing task; If so, determining the running state of the target computing program according to the actual execution information and the reference computing task; If not, determining the preset execution start time point of the target computing task as the target time point; and determining the running state of the target computing program according to the current time point, the target time point and the current output delay.

3. The method according to claim 2, characterized in that The determining the running state of the target computing program according to the actual execution information and the reference computing task includes: Determining whether the reference computing task is a computing task that has been completed according to the actual execution information; If yes, determining the running state of the target computing program according to the preset execution information and the actual execution information; If not, it is determined that the running state of the target computing program is not the target state.

4. The method according to claim 3, characterized in that: The actual execution information includes the actual execution end time point of the reference computing task, and the determining the running state of the target computing program according to the preset execution information and the actual execution information includes: Determining a task execution time interval according to a preset execution end time point of the reference computing task and a preset execution start time point of the target computing task; The running state of the target computing program is determined according to the actual execution end time point of the reference computing task, the task execution time interval and the current output delay.

5. The method according to claim 4, characterized in that The determining the running state of the target computing program according to the actual execution end time point of the reference computing task, the task execution time interval and the current output delay includes: Determine the task execution start time point of the target computing task according to the actual execution end time point of the reference computing task and the task execution time interval; If the task execution time interval is greater than or equal to the current output delay, determining the task execution start time point of the target computing task as the target time point; If the task execution time interval is less than the current output delay, determining the target time point according to the actual execution end time point of the reference calculation task and the current output delay; The running state of the target computing program is determined according to the current time point, the target time point and the current output delay.

6. The method according to claim 5, characterized in that The step of determining the target time point according to the actual execution end time point of the reference computing task and the current output delay includes: A time point that is after the actual execution end time point of the reference computing task and whose time interval with the actual execution end time point of the reference computing task is the current output delay is determined as the target time point.

7. The method according to claim 5 or 6, characterized in that: The task execution time interval is less than the current output delay, and after sending the current output signal to the power management chip, the method further includes: A frequency reduction instruction is sent to the computing chip, wherein the frequency reduction instruction is used to instruct the computing chip to reduce the clock frequency at a task execution start time point of the target computing task and to restore the clock frequency at the target time point.

8. A voltage drop compensation device, characterized in that: A controller applied to a target board, wherein the target board is provided with the controller, a computing chip and a power management chip, and the device comprises: A receiving unit, configured to receive a feedback signal from the computing chip, wherein the feedback signal is used to indicate that the computing chip starts to execute a target computing program, wherein the target computing program includes a plurality of computing tasks, wherein the plurality of computing tasks include at least one high-power computing task; A first acquisition unit, used to acquire the current output delay of the power management chip, where the current output delay refers to the time required for the power management chip to output the peak current from receiving the current output signal; A second acquisition unit, used to acquire the running status of the target computing program; A sending unit is used to send the current output signal to the power management chip when the running state of the target computing program is the target state, and the target state is used to characterize that the time interval between the current time point and the target time point is equal to the current output delay, and the target time point refers to the time point when the computing chip next executes a high-power computing task and generates a voltage drop.

9. A controller, characterized in that: The method comprises a processor, a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for executing the steps in the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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