Voltage drop compensation method and related apparatus

Abstract

The application provides a voltage drop compensation method and related device, the method comprises the following steps: receiving a feedback signal from a computing chip, the feedback signal is used for representing that the computing chip starts to execute a target computing program; obtaining a current output delay of a power management chip; obtaining a running state of the target computing program; when the running state of the target computing program is a target state, sending a current output signal to the power management chip, the target state is used for representing that a time interval between a current time point and a target time point is equal to the current output delay, and the target time point refers to a time point at which the computing chip executes a next large-power-consumption computing task and generates a voltage drop. In this way, when the computing chip executes the next large-power-consumption computing task and generates the voltage drop, the generated large voltage drop can be compensated by output peak current, so that the chip can be prevented from running failure.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electric digital data processing, and particularly relates to a voltage drop compensation method and a related device. BACKGROUND

[0002] At present, a large voltage drop is generated on a computing chip of a computing device during the running of a large computing program, and the excessive voltage drop can cause the chip to malfunction.

[0003] In order to avoid the above situation, the voltage drop of the chip needs to be compensated for. The traditional method is to compensate for the capacitance by modifying the circuit design, but this method involves the increase and modification of hardware, occupies a large area of a printed circuit board (PCB), and increases the cost of board manufacturing. SUMMARY

[0004] The embodiments of the present application provide a voltage drop compensation method and a related device, so as to reduce the voltage drop through a software program and avoid the malfunction of the chip.

[0005] In a first aspect, the embodiments of the present application provide a voltage drop compensation method applied to a controller on a target board card, wherein the target board card is provided with the controller, a computing chip and a power management chip, and the method comprises the following steps.

[0006] Receiving a feedback signal from the computing chip, wherein the feedback signal is used to represent that the computing chip starts to execute a target computing program, the target computing program comprises a plurality of computing tasks, and at least one high-power computing task is contained in the plurality of computing tasks;

[0007] Obtaining a current output delay of the power management chip, wherein the current output delay refers to a time length required by the power management chip from receiving a current output signal to outputting a peak current;

[0008] Obtaining a running state of the target computing program;

[0009] When the running state of the target computing program is a target state, sending the current output signal to the power management chip, wherein the target state is used to represent that a time interval between a current time point and a target time point is equal to the current output delay, and the target time point refers to a time point at which the computing chip executes a high-power computing task next time to generate a voltage drop.

[0010] In a second aspect, the embodiments of the present application provide a voltage drop compensation device applied to a controller on a target board card, wherein the target board card is provided with the controller, a computing chip and a power management chip, and the device comprises the following steps.

[0011] a receiving unit, configured to receive a feedback signal from the computing chip, the feedback signal being used to represent that the computing chip starts to execute a target computing program, the target computing program including a plurality of computing tasks, at least one of the plurality of computing tasks being a high-power-consumption computing task;

[0012] a first obtaining unit, configured to obtain a current output delay of the power management chip, the current output delay being a time length required by the power management chip from receiving a current output signal to outputting a peak current;

[0013] a second obtaining unit, configured to obtain a running state of the target computing program;

[0014] a sending unit, configured to send the current output signal to the power management chip when the running state of the target computing program is a target state, the target state being used to represent that a time interval between a current time point and a target time point is equal to the current output delay, the target time point being a time point at which the computing chip next executes the high-power-consumption computing task to generate a voltage drop.

[0015] In a third aspect, an embodiment of the present application provides a controller, including a processor, a memory, and one or more programs, the one or more programs being stored in the memory and configured to be executed by the processor, and the program including instructions for performing the steps in the first aspect of the embodiments of the present application.

[0016] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, having a computer program / instruction stored thereon, the computer program / instruction being executed by a processor to implement the steps in the first aspect of the embodiments of the present application.

[0017] It can be seen that, in the embodiments of the present application, the controller can obtain the current output delay of the power management chip and obtain the running state of the target computing program when determining that the computing chip starts to execute the target computing program, so that the current output signal is sent to the power management chip when the running state of the target computing program is the target state, and the power management chip can successfully output the peak current when the computing chip next executes the high-power-consumption computing task to generate the voltage drop, and the peak current is used to compensate for the large voltage drop. In this way, the voltage drop generated by the computing chip due to execution of the high-power-consumption computing task can be reduced without modifying the circuit design, and the running failure of the chip can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description only show some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.

[0019] Figure 1 is a structural block diagram of a target board card provided by an embodiment of the present application;

[0020] Figure 2 is a flowchart of a voltage drop compensation method provided by an embodiment of the present application;

[0021] Figure 3 is an oscilloscope waveform diagram without voltage drop compensation;

[0022] Figure 4 is an oscilloscope waveform diagram without adjusting the monitoring path delay time;

[0023] Figure 5 is an oscilloscope waveform diagram after adjusting the monitoring path delay time;

[0024] Figure 6 is a structural block diagram of a voltage drop compensation device provided by an embodiment of the present application;

[0025] Figure 7 is a structural block diagram of another voltage drop compensation device provided by an embodiment of the present application;

[0026] Figure 8 is a structural block diagram of a controller provided by an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0028] The terms "first", "second", and the like in the description and in the claims of the present application and above-described drawings are used to distinguish between similar objects, not to describe a particular sequential order. Moreover, the terms "include", and "have", and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a list of steps or units is not limited to the listed steps or units, but can optionally further include additional steps or units not listed, or can optionally further include other steps or units inherent to such process, method, product, or device.

[0029] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to one of skill in the art, embodiments described herein can be combined with other embodiments.

[0030] Please refer to Figure 1 , Figure 1 is a structural block diagram of a target board card provided by an embodiment of the application. As shown in Figure 1 , the target board card 10 is provided with a controller 11, a computing chip 12, and a power management chip 13. The computing chip 12 is configured to run a computing program and execute various computing tasks in the computing program; the power management chip 13 is configured to supply power to the entire system and can output a peak current after a certain time delay when receiving a current output signal. In general, the computing chip 12 will generate voltage drops of different amplitudes when starting to execute computing tasks, and the greater the power consumption required by the computing tasks, the higher the amplitude of the voltage drop generated by the computing tasks. When the voltage drop drops to a certain extent, it may cause the running failure of the chip. Therefore, the tester usually marks the computing tasks that generate large voltage drops as large-power-consumption computing tasks, and designs accordingly to minimize the impact of large voltage drops generated when executing such computing tasks on the chip. Specifically, the computing chip 12 can be an RPP (Reconfigurable Parallel Processing) chip.

[0031] Next, a voltage drop compensation method provided by an embodiment of the application is introduced.

[0032] Please refer to Figure 2 , Figure 2 is a flowchart of a voltage drop compensation method provided by an embodiment of the application, which is applied to the controller 11 as shown in Figure 1 , and as shown in Figure 2 , the method comprises:

[0033] S201, receiving a feedback signal from the computing chip.

[0034] The feedback signal is used to represent that the computing chip starts to execute a target computing program, and the target computing program includes a plurality of computing tasks, and at least one high-power consumption computing task is included in the plurality of computing tasks. That is, when the computing chip starts to execute the target computing program including the high-power consumption computing task, a feedback signal is sent to the controller, and the controller triggers the voltage drop compensation mechanism involved in the embodiment of the application after receiving the feedback signal. Specifically, the high-power consumption computing task can be a Kernel task.

[0035] S202, obtaining a current output delay of the power management chip.

[0036] The current output delay refers to the time length required for the power management chip to output a peak current after receiving a current output signal, and the current output signal is specifically a pulse. Therefore, if a pulse is applied only when it is detected that the chip starts to execute a high-power consumption computing task, the peak current cannot arrive at the starting time point of the execution of the high-power consumption computing task due to the current output delay, and when the peak current arrives subsequently, the charge stored in the capacitor cannot support such a large current.

[0037] The current output delay can be specifically data artificially written after testing. Specifically, a tester artificially gives a PMIC (Power Management IC, power management chip) a feedback signal with an oscilloscope, the feedback signal is a pulse, and the width of the pulse is continuously adjusted. At this time, the greater the width of the pulse, the higher the output current peak. The time interval between the time point at which the pulse is given and the time point at which the current peak is the largest is the current output delay, and this data can be obtained from the oscilloscope.

[0038] S203, obtaining a running state of the target computing program.

[0039] S204, when the running state of the target computing program is a target state, sending the current output signal to the power management chip.

[0040] In the embodiment of the application, the obtaining of the running state of the target computing program can be that the controller monitors the running state of the target computing program until the running state of the target computing program is the target state. In other embodiments, the obtaining of the running state of the target computing program can also be that the computing chip sends a signal to the controller to inform the controller that the running state of the target computing program is the target state when it is detected that the running state of the target computing program is the target state, which is not uniquely limited here.

[0041] In the embodiments of the present application, the running state of the target computing program includes a target state and a non-target state. The target state indicates that the time interval between the current time point and a target time point is equal to the current output delay of the power management chip, and the target time point refers to the time point at which the computing chip performs a next high-power computing task and causes a voltage drop.

[0042] As can be seen, in the embodiments of the present application, the controller can obtain the current output delay of the power management chip and the running state of the target computing program when it is determined that the computing chip starts to execute the target computing program, so that the current output signal is sent to the power management chip when the running state of the target computing program is the target state, so that the power management chip can successfully output the peak current when the computing chip performs a next high-power computing task and causes a voltage drop, and the peak current is used to compensate for the large voltage drop. In this way, the voltage drop caused by the computing chip when performing a high-power computing task can be reduced without modifying the circuit design, and the running failure of the chip can be avoided.

[0043] In one possible example, the obtaining of the running state of the target computing program includes: sending a state query instruction to the computing chip, the state query instruction being used to obtain a running duration of the target computing program, preset execution information and actual execution information, the running duration being used to indicate the current time point, the preset execution information including a preset execution sequence, a preset execution start time point and a preset execution end time point of each computing task in the plurality of computing tasks, and the actual execution information being used to indicate the execution progress of the target computing program at the current time point; determining a target computing task according to the actual execution information and the preset execution sequence of each computing task, the target computing task being a next high-power computing task to be executed by the computing chip; determining whether there is a reference computing task according to the preset execution sequence of each computing task and the target computing task, the reference computing task being a computing task whose preset execution sequence is one position before the preset execution sequence of the target computing task; if there is, determining the running state of the target computing program according to the actual execution information and the reference computing task; if there is not, determining that the preset execution start time point of the target computing task is the target time point; and determining the running state of the target computing program according to the current time point, the target time point and the current output delay.

[0044] In the present example, the controller obtains the running state of the target computing program by monitoring. Specifically, monitoring the running state of the target computing program depends on a monitoring path delay, which refers to the time interval required for the controller to access the computing chip twice in succession. In each access, the controller obtains the running time, preset execution information and actual execution information of the target computing program by sending a state query instruction to the computing chip. The running time is used to determine the current time point, i.e., in the present embodiment, the starting time of the target computing program is taken as the reference origin, and the running state of the target computing program is represented by the running time. For example, if the monitoring path delay is 1 microsecond, the controller can obtain the running state of the target computing program at 1 microsecond, 2 microseconds, 3 microseconds, etc. of the program running; if the monitoring path delay is 0.5 microseconds, the controller can obtain the running state of the target computing program at 0.5 microseconds, 1 microsecond, 1.5 microseconds, etc. of the program running.

[0045] The target computing program to be executed by the computing chip is known, i.e., each computing task in the target computing program has corresponding preset execution information, i.e., preset execution sequence, preset execution start time point and preset execution end time point, which are stored in the storage unit of the computing chip. After receiving the state query instruction from the controller, the computing chip calls up these data and sends them to the controller.

[0046] Generally, if the program running process is normal, each computing task will be executed according to the preset execution information, in which case the time point at which the high-power computing task starts to execute, i.e., the time point at which a large voltage drop occurs, can be clearly determined, and thus the running state of the target computing program can be clearly determined. In particular, if it is determined at the current time point that there is no reference computing task, it indicates that the target computing task is the first computing task of the target computing program, in which case it is determined that the program running is normal, and it is determined that the target computing task can start to execute at the preset execution start time point corresponding to the target computing task, and thus the preset execution start time point of the target computing task is determined as the target time point, and then it is determined whether the running state of the target computing program is the target state according to the current time point, the target time point and the current output delay. For example, taking B task as the target computing task, assuming that B task is the first computing task of the target computing program, the preset execution start time point corresponding to B task is 5 microseconds of the program running, and the current output delay is 3 microseconds, then 2 microseconds of the program running is the target state, and at this time a current output signal is sent to the power management chip, so that the peak current reaches the computing chip at 5 microseconds of the program running, to compensate for the voltage drop generated.

[0047] However, during the actual operation of the program, there may be various problems that lead to the early or delayed execution of the computing task, and the time point at which the high-power computing task starts execution may also change, resulting in inconsistency with the preset execution start time point. At this time, the running status of the target computing program cannot be accurately determined based on the preset execution start time point of the target computing task. In response to this problem, the embodiment of the present application determines the running status of the target computing program based on the actual execution information of the target computing program and the reference computing task that precedes the target computing task in the preset execution order, and comprehensively considers the actual running situation of the target computing program to determine the running status of the target computing program. Among them, the actual execution information is used to characterize the execution progress of the target computing program at the current time point, and can specifically include the execution information of the computing tasks that have been executed, such as the actual execution start time point, the actual execution end time point, the actual execution duration, etc.

[0048] It can be seen that in this example, the controller obtains the running time, preset execution information and actual execution information of the target computing program by sending a status query instruction to the computing chip, and then determines the target computing task that will produce a large voltage drop. When there is a reference computing task, the running status of the target computing program is determined based on the actual execution information and the reference computing task. When there is no reference computing task, the preset execution start time point of the target computing task is directly determined as the target time point, thereby determining the running status of the target computing program based on the current time point, the target time point and the current output delay. In this way, when the first computing task of the target computing program is a high-power computing task, the controller can directly determine the target time point and then determine the running status of the target computing program, which simplifies the calculation process, reduces the amount of calculation of the system, improves the accuracy of the calculation results, and thus improves the compensation effect of the voltage drop.

[0049] In one possible example, determining the running status of the target computing program based on the actual execution information and the reference computing task includes: judging whether the reference computing task is a computing task that has been executed based on the actual execution information; if so, determining the running status of the target computing program based on the preset execution information and the actual execution information; if not, determining that the running status of the target computing program is not the target status.

[0050] Exemplarily, the following describes the scheme with reference to a task A as a reference computing task and a task B as a target computing task. Each computing task in the target computing program has a preset execution sequence, i.e., each computing task is serial. The task A is a previous task of the task B. At this time, the controller sends a state query instruction to the computing chip at a current time point, and takes whether the task A is executed completely as a detection standard. The target computing program includes three cases: the task A is not started to be executed, the task A is being executed, and the task A has been executed completely. The task A is not started to be executed and the task A is being executed can be summarized as the task A is not executed completely. In this case, it is unable to determine whether the execution process of the task A is accelerated or delayed, i.e., it is unable to determine when the task A can be executed completely, and it is also unable to determine the task start execution time point of the task B, i.e., the target time point, and further unable to determine the running state of the target computing program. Based on the above case, in the present example, if the task A is not executed completely, it is determined that the running state of the target computing program is not the target state. Only when the task A is executed completely, the running state of the target computing program is further determined according to the preset execution information and the actual execution information, so as to avoid the case that the target time point cannot be accurately determined due to the execution delay or advance of other computing tasks, and further the case that the running state of the target computing program cannot be accurately determined.

[0051] It can be seen that in the present example, when the reference computing task exists in the target computing program, the controller determines whether the reference computing task has been executed completely according to the actual execution information. If the reference computing task is not executed completely at the current time point, it is directly determined that the running state of the target computing program is not the target state. If the reference computing task has been executed completely at the current time point, the running state of the target computing program is further determined according to the preset execution information and the actual execution information, so as to avoid the case that the running state of the target computing program cannot be accurately determined due to the execution delay or advance of other computing tasks, improve the accuracy of the computing result, and further improve the compensation effect of the voltage drop.

[0052] In one possible example, the actual execution information includes an actual execution end time point of the reference computing task. The determining the running state of the target computing program according to the preset execution information and the actual execution information includes: determining a task execution time interval according to a preset execution end time point of the reference computing task and a preset execution start time point of the target computing task; and determining the running state of the target computing program according to the actual execution end time point of the reference computing task, the task execution time interval, and the current output delay.

[0053] In the design of the computing program, the tester or the designer can design a time interval between two continuous computing tasks, which is usually used to make the previous computing task completely write the computing result into the memory, so as to avoid the data inconsistency of the subsequent computing task when the computing result of the previous computing task is needed for the computation. The task execution time interval can be calculated according to the preset execution end time point of the reference computing task and the preset execution start time point of the target computing task. Taking A task as the reference computing task and B task as the target computing task as an example, the preset execution end time point of the A task is 50 microseconds of the program running, and the preset execution start time point of the B task is 52 microseconds of the program running. The task execution time interval between the A task and the B task is 2 microseconds. Further, if the A task delays or advances during execution, the actual execution end time point of the A task will be inconsistent with the preset execution end time point corresponding thereto, so that the target time point cannot be determined, and the running state of the target computing program cannot be determined. The task execution time interval can associate the execution start time point of the B task with the A task, so in this example, the running state of the target computing program can be further determined by the actual execution end time point of the A task, the task execution time interval and the current output delay.

[0054] It can be seen that in this example, when the reference computing task is a computing task that has been executed, the controller determines the task execution time interval according to the preset execution end time point of the reference computing task and the preset execution start time point of the target computing task, and determines the running state of the target computing program according to the actual execution end time point of the reference computing task, the task execution time interval and the current output delay. In this way, the target computing task is associated with the reference computing task through the task execution time interval, and in the case that the actual execution information of the reference computing task is known, the execution information of the target computing task, i.e. the high-power computing task, can be determined, so that the running state of the target computing program is determined, the accuracy of the computing result is improved, and the compensation effect of the voltage drop is improved.

[0055] In one possible example, the determining the running state of the target computing program according to the actual end time point of the reference computing task, the task execution time interval and the current output delay comprises: determining a task start execution time point of the target computing task according to the actual end time point of the reference computing task and the task execution time interval; if the task execution time interval is greater than or equal to the current output delay, determining that the task start execution time point of the target computing task is the target time point; if the task execution time interval is less than the current output delay, determining the target time point according to the actual end time point of the reference computing task and the current output delay; and determining the running state of the target computing program according to the current time point, the target time point and the current output delay.

[0056] For example, taking the A task as the reference computing task and the B task as the target computing task, it is assumed that the preset end execution time point of the A task is 50 microseconds of program running, and the preset start execution time point of the B task is 52 microseconds of program running, and the task execution time interval is 2 microseconds. It is assumed that the actual end execution time point of the A task is 55 microseconds of program running, and the task start execution time point of the B task can be calculated as 57 microseconds of program running.

[0057] It should be noted that in the present example, the running state of the target computing program is only possible to be the target state after the A task is executed, and the controller sends the current output signal to the PMIC, that is, the earliest time point at which the controller sends the current output signal to the PMIC is the actual end execution time point of the A task, for example, 55 microseconds in the above example.

[0058] In this case, if the task execution time interval is greater than or equal to the current output delay, for example, the task execution time interval is 5 microseconds, and the current output delay is 3 microseconds, the B task will start to execute at 60 microseconds, and the controller can detect that the running state of the target computing program is the target state at 57 microseconds and then send the current output signal to the PMIC, so that the peak current can be output at 60 microseconds to compensate for the voltage drop. That is, in the case where the task execution time interval is greater than or equal to the current output delay, the peak current can be output in time when the B task starts to execute, and at this time, no adjustment is needed, and the task start execution time point of the B task is determined as the target time point.

[0059] However, if the task execution time interval is less than the current output delay, for example, the task execution time interval is 2 microseconds and the current output delay is 3 microseconds, then task B will start executing at 57 microseconds, and task A will be completed at 55 microseconds. That is, the earliest time point when the controller sends the current output signal to the PMIC is 55 microseconds, and the peak current will not be output until 58 microseconds at the earliest, and it is impossible to compensate for the voltage drop generated at 57 microseconds. At this time, it is necessary to modify the target time point at which the computing chip will generate a large voltage drop when executing task B, so that the peak current output can compensate for the large voltage drop generated. In this example, after detecting that the task execution time interval is less than the current output delay, the controller re-determines the target time point based on the actual execution end time point of task A and the current output delay, and then determines the running status of the target computing program.

[0060] As can be seen, in this example, the controller first determines the task execution start time point of the target computing task, then compares the task execution time interval and the current output delay to determine whether it is necessary to modify the target time point when the computing chip generates a large voltage drop when executing the target computing task. If the task execution time interval is greater than or equal to the current output delay, it is determined that the target time point does not need to be modified, and the task execution start time point of the target computing task is determined as the target time point. If the task execution time interval is less than the current output delay, it is determined that the target time point needs to be modified. The target time point is determined based on the actual execution end time point of the reference computing task and the current output delay. Finally, the running status of the target computing program is determined based on the current time point, the target time point, and the current output delay. In this way, the controller can determine the target time point based on the size relationship between the task execution time interval and the current output delay, thereby ensuring that the peak current can be output in time to compensate for the large voltage drop when it occurs, thereby improving the compensation effect for the voltage drop.

[0061] In one possible example, determining the target time point based on the actual execution end time point of the reference computing task and the current output delay includes: determining a time point that is after the actual execution end time point of the reference computing task and whose time interval between the actual execution end time point of the reference computing task and the current output delay is the target time point.

[0062] Wherein, taking the A task as a reference computing task, the B task as a target computing task, the actual execution end time point of the A task as 55 microseconds, the task execution start time point of the B task as 57 microseconds, and the current output delay as 3 microseconds as an example, the task execution time interval is 2 microseconds, at this time, the target time point needs to be determined again so that the peak current can be output in time at the target time point to compensate for the voltage drop. Wherein, the target time point only needs to satisfy that the time interval between the actual execution end time point of the A task is greater than or equal to the current output delay, that is, the target time point only needs to be at 58 microseconds and later, and the peak current can be output in time to compensate. In particular, in the present example, the time point located after the actual execution end time point of the reference computing task and having a time interval between the actual execution end time point of the reference computing task equal to the current output delay is determined as the target time point, that is, 58 microseconds is determined as the target time point at which the computing chip executes the B task to generate a large voltage drop.

[0063] It can be seen that in the present example, in the case that the task execution time interval is less than the current output delay, the controller determines the time point located after the actual execution end time point of the reference computing task and having a time interval between the actual execution end time point of the reference computing task equal to the current output delay as the target time point, so that the peak current can be output in time to compensate for the voltage drop, thereby improving the compensation effect of the voltage drop.

[0064] In one possible example, the task execution time interval is less than the current output delay, and after the sending of the current output signal to the power management chip, the method further includes sending a frequency reduction instruction to the computing chip, the frequency reduction instruction being used to instruct the computing chip to reduce the clock frequency at the task start execution time point of the target computing task and to restore the clock frequency at the target time point.

[0065] Wherein, the computing chip usually generates a large voltage drop when starting to execute a large-power-consumption computing task, and in the case that the task execution time interval is less than the current output delay, the time point at which the large voltage drop is generated needs to be modified, which includes various modification manners, in the present example, after the controller determines that the running state of the target computing program is the target state and sends the current output signal to the PMIC, a frequency reduction instruction is sent to the computing chip, so that the computing chip reduces the clock frequency when starting to execute the target computing task, and does not generate such a large voltage drop in the low-frequency stage, and restores the clock frequency at the target time point. When the clock frequency of the computing chip is restored, the voltage drop is also generated, and at this time, the peak current is output to compensate.

[0066] For example, the current time point, i.e. the time point at which the controller sends the current output signal to the PMIC, is 55 microseconds, the task execution start time point of the B task is 57 microseconds, and the target time point is 58 microseconds. Therefore, the controller sends the frequency reduction instruction to the computing chip at 55 microseconds, so that the computing chip reduces its clock frequency when it starts executing the B task at 57 microseconds, and restores the clock frequency at 58 microseconds, so that the large voltage drop occurs at 58 microseconds, and the peak current is output at 58 microseconds, thereby achieving compensation for the large voltage drop.

[0067] As can be seen, in this example, the controller sends the frequency reduction instruction to the computing chip after sending the current output signal to the power management chip, so that the computing chip reduces the clock frequency when it starts executing the target computing task, and restores the clock frequency at the target time point, thereby ensuring that the peak current is output in time when the large voltage drop occurs, and improving the compensation effect for the voltage drop.

[0068] The scheme related to the embodiments of the application will be described below through specific examples.

[0069] The actual execution end time point of the A task is 60 microseconds, and the current output delay is 3 microseconds. Therefore, the task execution time interval can be divided into the following cases according to the different task execution time intervals:

[0070] (1) The task execution time interval is 2 microseconds, and the B task starts executing at 62 microseconds. In this case, the controller sends the current output signal to the PMIC at 60 microseconds, and sends the frequency reduction instruction to the computing chip, so that the computing chip reduces the frequency at 62 microseconds, and restores the frequency at 63 microseconds. At this time, the large voltage drop and the peak current are generated at 63 microseconds, thereby achieving compensation.

[0071] (2) The task execution time interval is 3 microseconds, and the B task starts executing at 63 microseconds. In this case, the controller sends the current output signal to the PMIC at 60 microseconds, and the large voltage drop and the peak current are generated at 63 microseconds, thereby achieving compensation.

[0072] (3) The task execution time interval is 4 microseconds, and the B task starts executing at 64 microseconds. In this case, the controller sends the current output signal to the PMIC at 61 microseconds, and the large voltage drop and the peak current are generated at 64 microseconds, thereby achieving compensation.

[0073] It should be noted that the controller monitoring the running state of the target computing program depends on the monitoring path delay, which refers to the time interval required for the controller to send a state query instruction to the computing chip twice in succession. Due to the influence of the monitoring path delay, the controller may not be able to obtain the time point corresponding to the target state of the running state of the target computing program. For example, let the target time point be at 30.5 microseconds of program running, and the current output delay be 3 microseconds. In this scenario, the time point corresponding to the target state should be at 27.5 microseconds of program running. If the monitoring path delay is 1 microsecond at this time, the controller can only obtain the running states at 27 microseconds and 28 microseconds of program running, and cannot obtain the time point corresponding to the target state. Although the controller can send a current output signal to the power management chip at 27 microseconds and 28 microseconds of program running, so that the peak current reaches at the closest time point to the target time point, the compensation effect is not good, and there is an error.

[0074] Based on this, after the controller determines the target time point, it can further calculate the time point corresponding to the target state according to the target time point and the current output delay, and then adjust the monitoring path delay according to the time point, so that the controller can obtain the running state of the target computing program at the corresponding time point and send a current output signal to the power management chip, to achieve the effect of timely compensation.

[0075] Specifically, the monitoring path delay can be shortened by increasing the clock frequency of the monitoring path; the monitoring path delay can also be shortened by adjusting the programmed monitoring loop algorithm. Taking the while(1) loop as an example, the irrelevant program can be deleted to achieve the effect of shortening the monitoring path delay.

[0076] Please refer to Figures 3-5 , Figure 3 is an oscilloscope waveform diagram without voltage drop compensation, Figure 4 is an oscilloscope waveform diagram without adjusting the monitoring path delay, Figure 5 is an oscilloscope waveform diagram after adjusting the monitoring path delay. The horizontal axis in the figure is the time axis, and the vertical axis is the operating voltage of the parallel computing chip. The C3 reference line represents the voltage applied to the parallel computing chip, which is 810 mV. From Figure 3 , it can be seen that under an input voltage of 810 mV, the core operating voltage of the parallel computing chip is about 800 mV, and a large voltage drop is generated between 90us and 100us, with a minimum of 760 mV to 770 mV, about 763 mV. In Figure 4 , due to the unadjusted monitoring path delay, the waveform diagram after applying the pulse is chaotic and has a large error. In Figure 5 , after adjusting the monitoring path delay, the operating voltage is about 778 mV, which is lower than that inFigure 3 The voltage increased by about 15mV, which is in line with expectations.

[0077] It can be understood that the process of determining the running state of the target computing program in the above-mentioned embodiments can also be completed by the computing chip and synchronized to the controller when the running state of the target computing program is the target state, so that the controller directly sends the current output signal to the power management chip after receiving the synchronization signal from the computing chip, realizes compensation of the voltage drop, and further can reduce the resource consumption of the controller.

[0078] In line with the above-mentioned embodiments, please refer to Figure 6 , Figure 6 is a structural block diagram of a voltage drop compensation device provided by the embodiment of the present application, which is applied to the controller 11 as shown in Figure 1 The voltage drop compensation device 60 comprises: a receiving unit 601, configured to receive a feedback signal from the computing chip, the feedback signal being used to represent that the computing chip starts to execute a target computing program, the target computing program comprising a plurality of computing tasks, and at least one high-power consumption computing task being contained in the plurality of computing tasks; a first obtaining unit 602, configured to obtain a current output delay of the power management chip, the current output delay being a time length required by the power management chip from receiving a current output signal to outputting a peak current; a second obtaining unit 603, configured to obtain a running state of the target computing program; and a sending unit 604, configured to send the current output signal to the power management chip when the running state of the target computing program is a target state, the target state being used to represent that a time interval between a current time point and a target time point is equal to the current output delay, and the target time point being a time point at which the computing chip next executes a high-power consumption computing task to generate a voltage drop.

[0079] In a possible example, in the obtaining of the running state of the target computing program, the second obtaining unit 603 is specifically configured to: send a state query instruction to the computing chip, the state query instruction being used to obtain a running duration of the target computing program, preset execution information, and actual execution information, the running duration being used to indicate the current time point, the preset execution information including preset execution sequences, preset execution start time points, and preset execution end time points of each computing task in the plurality of computing tasks, the actual execution information being used to represent an execution progress of the target computing program at the current time point; determining a target computing task according to the actual execution information and the preset execution sequence of each computing task, the target computing task being a next high-power computing task to be executed by the computing chip; determining whether there is a reference computing task according to the preset execution sequence of each computing task and the target computing task, the reference computing task being a computing task whose preset execution sequence is one position before the preset execution sequence of the target computing task; if there is, determining the running state of the target computing program according to the actual execution information and the reference computing task; if there is not, determining the preset execution start time point of the target computing task as the target time point; and determining the running state of the target computing program according to the current time point, the target time point, and the current output delay.

[0080] In a possible example, in the determining of the running state of the target computing program according to the actual execution information and the reference computing task, the second obtaining unit 603 is specifically configured to: determine whether the reference computing task is a computing task that has been executed according to the actual execution information; if yes, determine the running state of the target computing program according to the preset execution information and the actual execution information; and if no, determine that the running state of the target computing program is not the target state.

[0081] In a possible example, the actual execution information includes an actual execution end time point of the reference computing task, and in the determining of the running state of the target computing program according to the preset execution information and the actual execution information, the second obtaining unit 603 is specifically configured to: determine a task execution time interval according to the preset execution end time point of the reference computing task and the preset execution start time point of the target computing task; and determine the running state of the target computing program according to the actual execution end time point of the reference computing task, the task execution time interval, and the current output delay.

[0082] In a possible example, in the determining of the running state of the target computing program according to the actual execution end time point of the reference computing task, the task execution time interval and the current output delay, the second acquisition unit 603 is specifically configured to: determine a task start execution time point of the target computing task according to the actual execution end time point of the reference computing task and the task execution time interval; if the task execution time interval is greater than or equal to the current output delay, determine that the task start execution time point of the target computing task is the target time point; if the task execution time interval is less than the current output delay, determine the target time point according to the actual execution end time point of the reference computing task and the current output delay; and determine the running state of the target computing program according to the current time point, the target time point and the current output delay.

[0083] In a possible example, in the determining of the target time point according to the actual execution end time point of the reference computing task and the current output delay, the second acquisition unit 603 is specifically configured to: determine a time point located between the actual execution end time point of the reference computing task and the actual execution end time point of the reference computing task and having a time interval equal to the current output delay as the target time point.

[0084] In a possible example, in the case that the task execution time interval is less than the current output delay, after the sending of the current output signal to the power management chip, the voltage drop compensation apparatus 60 is further configured to: send a frequency reduction instruction to the computing chip, where the frequency reduction instruction is used to instruct the computing chip to reduce the clock frequency at the task start execution time point of the target computing task and restore the clock frequency at the target time point.

[0085] It can be understood that, since the method embodiment and the device embodiment are different presentation forms of the same technical concept, the content of the method embodiment part in the present application should be synchronously adapted to the device embodiment part, which will not be repeated here.

[0086] In the case of using an integrated unit, as shown in Figure 7 , the voltage drop compensation apparatus 60 is an integrated unit. Figure 7 is a structural block diagram of another voltage drop compensation apparatus provided by the embodiment of the present application, in the case of using an integrated unit, as shown in Figure 7In specific embodiments, the voltage drop compensation apparatus 60 comprises a processing module 62 and a communication module 61. The processing module 62 is configured to control and manage the operations of the voltage drop compensation apparatus, for example, to perform the steps of the receiving unit 601, the first obtaining unit 602, the second obtaining unit 603 and the sending unit 604, and / or to perform other processes of the techniques described herein. The communication module 61 is configured to support the interaction between the voltage drop compensation apparatus and other devices. As Figure 7 As shown in FIG. 6, the voltage drop compensation apparatus can further comprise a storage module 63, which is configured to store the program codes and data of the voltage drop compensation apparatus.

[0087] The above method embodiments involve all related contents of each scenario, which can be cited to the function description of the corresponding functional module, and will not be repeated here. The above voltage drop compensation apparatus 60 can perform the above Figure 2 The voltage drop compensation method shown in FIG. 6.

[0088] Please refer to Figure 8 , Figure 8 is a structural block diagram of a controller provided by an embodiment of the present application. As shown in FIG. 8, the controller can comprise one or more of the following components: a processor 801, a memory 802 coupled to the processor 801, wherein the memory 802 can store one or more computer programs, and the one or more computer programs can be configured to be executed by the one or more processors 801 to implement the method described in the above embodiments. Figure 8 The controller can comprise one or more of the following components: a processor 801, a memory 802 coupled to the processor 801, wherein the memory 802 can store one or more computer programs, and the one or more computer programs can be configured to be executed by the one or more processors 801 to implement the method described in the above embodiments.

[0089] The processor 801 can comprise one or more processing cores. The processor 801 connects various parts of the controller through various interfaces and lines, and performs various functions of the controller and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 802, and calling data stored in the memory 802.

[0090] The memory 802 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 802 can comprise a program storage area and a data storage area, wherein the program storage area can store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the above various method embodiments, etc. The data storage area can also store data created by the controller in use, etc.

[0091] It can be understood that the controller can comprise more or fewer structural elements than the above structural block diagram, which is not limited here.

[0092] The embodiment of the present application further provides a computer storage medium, wherein a computer program / instruction is stored in the computer storage medium, and the computer program / instruction is executed by a processor to implement part or all steps of any method described in the above method embodiment.

[0093] It should be understood that the size of the sequence number of each process described above does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0094] In several embodiments provided in the present application, it should be understood that the disclosed method and device can be implemented in other ways. For example, the above-described device embodiment is only schematic; for example, the division of the units is only a logical function division, and actual implementation can have another division manner; for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0095] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment of the present application.

[0096] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically included separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0097] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements without departing from the spirit and scope of the present application, and can make various changes and modifications, including the combination of different functions and implementation steps, including the software and hardware implementation, which are all within the protection scope of the present application.

Claims

1. A method of voltage drop compensation, characterized by, The application relates to a method for controlling a controller applied to a target board card, wherein the controller, a computing chip and a power management chip are arranged on the target board card, and the method comprises the following steps: receiving a feedback signal from the computing chip, wherein the feedback signal is used for representing that the computing chip starts to execute a target computing program, the target computing program comprises a plurality of computing tasks, and at least one high-power consumption computing task is contained in the plurality of computing tasks; obtaining a current output delay of the power management chip, wherein the current output delay refers to a time length required by the power management chip from receiving a current output signal to outputting a peak current; obtaining a running state of the target computing program; when the running state of the target computing program is a target state, sending the current output signal to the power management chip, wherein the target state is used for representing that a time interval between a current time point and a target time point is equal to the current output delay, and the target time point refers to a time point at which the computing chip executes a next high-power consumption computing task and generates a voltage drop.

2. The method of claim 1, wherein, The step of obtaining the running state of the target computing program comprises the following steps: sending a state query instruction to the computing chip, wherein the state query instruction is used for obtaining a running time length of the target computing program, preset execution information and actual execution information, the running time length is used for indicating the current time point, the preset execution information comprises a preset execution sequence, a preset execution start time point and a preset execution end time point of each computing task in the plurality of computing tasks, and the actual execution information is used for representing an execution progress of the target computing program at the current time point; determining a target computing task according to the actual execution information and the preset execution sequence of each computing task, wherein the target computing task refers to a next high-power consumption computing task to be executed by the computing chip; judging whether a reference computing task exists according to the preset execution sequence of each computing task and the target computing task, wherein the reference computing task refers to a computing task whose preset execution sequence is one position before the preset execution sequence of the target computing task; if the reference computing task exists, determining the running state of the target computing program according to the actual execution information and the reference computing task; if the reference computing task does not exist, determining that the preset execution start time point of the target computing task is the target time point, and determining the running state of the target computing program according to the current time point, the target time point and the current output delay.

3. The method of claim 2, wherein, The step of determining the running state of the target computing program according to the actual execution information and the reference computing task comprises the following steps: judging whether the reference computing task is a computing task that has been executed according to the actual execution information; if the reference computing task is the computing task that has been executed, determining the running state of the target computing program according to the preset execution information and the actual execution information; if the reference computing task is not the computing task that has been executed, determining that the running state of the target computing program is not the target state.

4. The method of claim 3, wherein, The actual execution information comprises an actual execution end time point of the reference computing task, and the step of determining the running state of the target computing program according to the preset execution information and the actual execution information comprises the following steps: determine a task execution time interval according to the preset execution end time point of the reference computing task and the preset execution start time point of the target computing task; determine a running state of the target computing program according to the actual execution end time point of the reference computing task, the task execution time interval and the current output delay.

5. The method of claim 4, wherein, The method further comprises: determine a task start execution time point of the target computing task according to the actual execution end time point of the reference computing task and the task execution time interval; if the task execution time interval is greater than or equal to the current output delay, determine that the target time point is the task start execution time point of the target computing task; if the task execution time interval is less than the current output delay, determine that a time point located after the actual execution end time point of the reference computing task and between the actual execution end time point of the reference computing task and the target time point is the current output delay; determine a running state of the target computing program according to the current time point, the target time point and the current output delay.

6. The method of claim 5, wherein, The task execution time interval is less than the current output delay, and the method further comprises: send a frequency reduction instruction to the computing chip, the frequency reduction instruction being used to instruct the computing chip to reduce a clock frequency at the task start execution time point of the target computing task and restore the clock frequency at the target time point.

7. A voltage drop compensation device, characterized by The controller is applied to a target board card, the target board card being provided with the controller, a computing chip and a power management chip, and the device comprises: a receiving unit configured to receive a feedback signal from the computing chip, the feedback signal being used to represent that the computing chip starts to execute a target computing program, the target computing program comprising a plurality of computing tasks, and the plurality of computing tasks comprising at least one high-power-consumption computing task; a first obtaining unit configured to obtain a current output delay of the power management chip, the current output delay being a time length required by the power management chip from receiving a current output signal to outputting a peak current; a second obtaining unit configured to obtain a running state of the target computing program; a sending unit configured to send the current output signal to the power management chip when the running state of the target computing program is a target state, the target state being used to represent that a time interval between a current time point and a target time point is equal to the current output delay, and the target time point being a time point at which the computing chip next executes a high-power-consumption computing task and generates a voltage drop.

8. A controller characterized by comprising: A computer program product comprising a processor, a memory and one or more programs stored in the memory and configured to be executed by the processor, the program comprising instructions for performing the steps in the method of any one of claims 1-6. A computer program product comprising a processor, a memory and one or more programs stored in the memory and configured to be executed by the processor, the program comprising instructions for performing the steps in the method of any one of claims 1-6.

9. A computer readable storage medium having stored thereon computer programs / instructions, characterized in that, The computer program / instructions, when executed by the processor, implement the steps of the method according to any one of claims 1-6.

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