Atomic operation processing system and method, display card and computer equipment

Abstract

The invention discloses an atomic operation processing system and method, a display card and computer equipment, and belongs to the field of chips. The atomic operation processing system comprises a processor, a storage unit and an atomic operation processing unit which is independent of the processor, the processor is connected with the atomic operation processing unit; the atomic operation processing unit is connected with the storage unit through a straight-through path; the processor is used for sending an atomic operation instruction to the atomic operation processing unit; the atomic operation processing unit is used for reading read data from the storage unit based on the atomic operation instruction; executing atomic operation based on the atomic operation instruction and the read data to obtain an atomic operation result; and writing the atomic operation result into the storage unit. The atomic operation unit is arranged independent of the processor, read data does not need to return to the processor and then enter the atomic operation processing unit, but directly enter the atomic processing unit outside the processor, so that the transmission path of the read data is shortened, and the transmission delay of the read data is reduced.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to an atomic operation processing system, method, graphics card and computer equipment. Background Art

[0002] Atomic operations are operations that cannot be interrupted during execution and are one of the important operations in GPU (Graphics Processing Unit). The atomic operation processing unit (such as ALU, Arithmetic Logic Unit) used to perform atomic operations is one of the important units in GPU. The atomic operation processing unit is located inside the GPU and is connected to the memory through the on-chip network. During the execution of atomic operations, data needs to be read from or written to the memory.

[0003] In the related art, when reading data, the GPU needs to initiate a read request. After the read request reaches the memory through the on-chip network, the memory returns the read data to the ALU in the GPU through the on-chip network according to the read request. The data transmission process when writing data is similar to that of reading data, and both need to pass through the on-chip network multiple times. This causes a large delay in the atomic operation process. Summary of the invention

[0004] The present application provides an atomic operation processing system, method, graphics card and computer equipment, and the technical solution is as follows:

[0005] According to one aspect of the present application, an atomic operation processing system is provided, the atomic operation processing system comprising a processor, a storage unit, and an atomic operation processing unit independently provided from the processor; the processor is connected to the atomic operation processing unit; the atomic operation processing unit is connected to the storage unit via a direct path;

[0006] The processor is used to send an atomic operation instruction to the atomic operation processing unit;

[0007] The atomic operation processing unit is used to read the read data from the storage unit based on the atomic operation instruction; perform the atomic operation based on the atomic operation instruction and the read data to obtain the atomic operation result; and write the atomic operation result into the storage unit.

[0008] According to one aspect of the present application, an atomic operation processing method is provided, the method is performed by an atomic operation system, the atomic operation processing system comprises a processor, a storage unit, and an atomic operation processing unit independently provided from the processor; the processor is connected to the atomic operation processing unit; the atomic operation processing unit is connected to the storage unit via a direct path;

[0009] The method comprises:

[0010] The processor sends an atomic operation instruction to the atomic operation processing unit;

[0011] The atomic operation processing unit reads read data from the storage unit based on the atomic operation instruction; performs an atomic operation based on the atomic operation instruction and the read data to obtain an atomic operation result; and writes the atomic operation result into the storage unit.

[0012] According to one aspect of the present application, a graphics card is provided, comprising an atomic operation processing system.

[0013] According to one aspect of the present application, a computer device is provided, wherein the computer device includes an atomic operation processing system.

[0014] The beneficial effects of the technical solution provided by this application include at least:

[0015] The atomic operation unit that supports atomic operations is set independently from the processor. When performing atomic operations, the atomic operation processing unit only needs to interact with the storage unit. The read data does not need to return to the processor and then enter the atomic operation processing unit, but directly enters the atomic processing unit outside the processor, shortening the transmission path of the read data and thus reducing the transmission delay of the read data. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic diagram of an atomic operation processing system in the related art is shown;

[0018] Figure 2 A schematic diagram of an atomic operation processing system provided by an exemplary embodiment of the present application is shown;

[0019] Figure 3 A schematic diagram of an atomic operation processing system provided by an exemplary embodiment of the present application is shown;

[0020] Figure 4 A schematic diagram of an atomic operation processing system provided by an exemplary embodiment of the present application is shown;

[0021] Figure 5 A schematic diagram of an atomic operation processing system provided by an exemplary embodiment of the present application is shown;

[0022] Figure 6 A schematic diagram of an atomic operation processing system provided by an exemplary embodiment of the present application is shown;

[0023] Figure 7 A schematic diagram of an atomic operation processing system provided by an exemplary embodiment of the present application is shown;

[0024] Figure 8 A flowchart of an atomic operation processing method provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0026] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0027] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0028] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the information such as setting operations involved in this application is obtained with full authorization.

[0029] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0030] First, the relevant terms involved in this application are introduced:

[0031] Instruction: It is a command that instructs a computer to perform a certain operation. It is the smallest functional unit of a computer. An instruction is a statement in machine language, and an instruction is a group of meaningful binary codes. The collection of all instructions of a computer constitutes the instruction system of the computer, also known as the instruction set.

[0032] Instruction format: A readable representation of an instruction. An instruction usually includes an opcode and an operand. The opcode is used to describe the type of operation to be performed by the instruction, and the operand provides the data or address of the data required to execute the instruction. The opcode is indispensable in the instruction, but the operand can be absent, one, or two.

[0033] Atomic operation: refers to an operation or a group of operations that only have two states: unexecuted and fully executed. There is no intermediate state for atomic operations. It can also be understood that an atomic operation is an independent and indivisible operation composed of multiple steps. In a single-core environment, threads cannot be switched when performing atomic operations. Thread switching can only be performed before atomic operations or after atomic operations are completed. In a multi-core environment, it can be reflected in that when a core performs an atomic operation on a certain storage unit, it is necessary to ensure that other cores do not change the data of the same storage unit at the same time. In other words, an atomic operation refers to one or more operations that must be completed as a whole. If an atomic operation is interrupted when any step of the operation is not completed, all completed operations must be rolled back to ensure that all operations are not completed or all operations are completed.

[0034] In GPU, the hardware unit that performs atomic operations can be called Arithmetic Logic Unit (ALU), Atomic Operation Processing Unit, Data Processing Unit, etc., and usually requires the input of several atomic operands. For example, atomic operations include xchg, add, sub, and, or, xor, inc, dec, cmp, cmpxchg (Compare and Exchange, also known as cas, the full name of which is Compare-And-Swap), etc.

[0035] Among them, xchg represents a swap operation, which requires the input of an atomic operand. This operation means using the input atomic operand to replace the data at a certain address in a storage unit (such as memory or video memory, etc.).

[0036] Add represents an addition operation, which requires two atomic operands. This operation represents the addition of two input atomic operands.

[0037] sub represents a subtraction operation, which requires two atomic operands. This operation represents subtracting the two input atomic operands.

[0038] and represents an AND operation, which requires two atomic operands. This operation represents the logical AND of the two input atomic operands.

[0039] or represents an OR operation, which requires two atomic operands. This operation represents the logical OR of the two input atomic operands.

[0040] xor represents an exclusive OR operation, which requires two atomic operands. This operation represents performing a logical exclusive OR on the two input atomic operands.

[0041] inc represents a self-increment operation, which requires two atomic operands. This operation first compares the atomic operand passed in from the bus with the atomic operand read from the storage unit. If the atomic operand passed in from the bus is greater than the atomic operand read, it will not be incremented; if the atomic operand passed in from the bus is less than or equal to the atomic operand read, it will be incremented. It should be noted that the above example uses the case where the atomic operand passed in from the bus is equal to the atomic operand read as an example of self-increment. In actual use, if the atomic operand passed in from the bus is less than or equal to the atomic operand read, it may not be incremented. The following decrement is the same and will not be repeated here.

[0042] dec represents a decrement operation, which requires two atomic operands. This operation first compares the atomic operand passed in from the bus with the atomic operand read from the storage unit. If the atomic operand passed in from the bus is less than the atomic operand read, it will not be decremented; if the atomic operand passed in from the bus is greater than or equal to the atomic operand read, it will be incremented.

[0043] cmp represents a comparison operation, which requires two atomic operands. This operation is used to compare the sizes of the two atomic operands.

[0044] float represents floating-point sum and requires two atomic operands. This operation is used to add two atomic operands based on the precision of floating-point numbers.

[0045] cas represents a compare and exchange operation, which requires three atomic operands. Atomic operand 1 and atomic operand 2 are passed in from the bus, and atomic operand 3 is read from the storage unit. This operation is used to compare atomic operand 1 with atomic operand 3. If atomic operand 1 is equal to atomic operand 3, atomic operand 2 is used to replace atomic operand 3 in the storage unit; if atomic operand 1 is not equal to atomic operand 3, no replacement is made.

[0046] Among them, each type of atomic operation can be divided into 16 bits, 32 bits and 64 bits according to the bit width of the atomic operand.

[0047] It should be noted that the above atomic operations and their functions are for illustration only and can be adjusted according to the requirements of different processors during actual use.

[0048] Atomic operation instruction: An instruction used to instruct the execution of an atomic operation.

[0049] Among them, the atomic operands of atomic operations can be divided into original data and read data according to their sources.

[0050] Original data: the atomic operand carried in the atomic operation instruction, or the atomic operand read from the storage unit based on the address carried in the atomic operation instruction but not modified in the atomic operation.

[0051] Read data: The atomic operand that needs to be modified by the atomic operation is read from the storage unit based on the address carried in the atomic operation instruction. In other words, the atomic operand is read from the storage unit based on the address carried in the atomic operation instruction, and the address is the address where the atomic operation result needs to be written after the atomic operation is completed. In other words, the atomic operand is read from the storage unit based on the address carried in the atomic operation instruction, and the address is both a read address and a write address.

[0052] Network-on-Chip (NoC): A communication subsystem based on network design located in an integrated circuit. It is usually used for data transmission and communication between different modules in a system-on-chip (SoC). NoC technology connects processor cores, memory, and various peripherals through routers to form a highly parallel communication architecture, effectively improving data transmission efficiency and communication bandwidth. Compared with the traditional shared bus method, NoC technology can provide higher scalability and better performance, especially for multi-core systems.

[0053] The schematic diagram of the architecture of the atomic operation processing system in the related art is as follows: Figure 1 As shown. Take the processor as GPU and the atomic operation processing unit for performing atomic operations as ALU as an example for explanation. The atomic operation processing system includes GPU 10, on-chip network 20 and storage unit.

[0054] The GPU 10 includes one or more GPU cores, and each GPU core includes at least one ALU 11 .

[0055] The GPU 10 is connected to the storage unit via the on-chip network 20. In other words, each GPU core in the GPU 10 is connected to the storage unit via the on-chip network 20.

[0056] For example, when performing an atomic operation, if data needs to be read, GPU core 0 (or ALU 11) sends a read request, which is sent to storage unit 0 through on-chip network 20. After receiving the read request, storage unit 0 reads read data 12 and returns read data 12 to GPU core 0 through on-chip network 20. If data needs to be written, GPU core 0 (or ALU 11) sends a write request and write data 13, which are sent to storage unit 0 through on-chip network 20, and storage unit 0 writes write data 13 based on the write request.

[0057] It should be noted that the transmission paths of the read data 12 and write data 13 involved in the above process are only for illustration. For GPU core 0, read data 12 can be read from storage unit 1 or write data 13 can be written to storage unit 1, and read data 12 can be read from storage unit N or write data 13 can be written to storage unit 1, and so on.

[0058] In addition, in order to reduce latency, a cache 14 is also provided inside the GPU core. The cache 14 is used to store data frequently accessed by the GPU core, thereby reducing the processing efficiency caused by the GPU core's frequent reading requirements for the data.

[0059] In some embodiments, the atomic operation processing system also includes other hosts, which generally refer to the CPU (Central Processing Unit) working in conjunction with the GPU and the system environment in which it is located. These other hosts (or CPUs) are used to execute tasks that cannot be executed on the GPU and manage GPU resources and task scheduling.

[0060] However, for atomic operations, in addition to reading the read data from the storage unit, after performing the atomic operation on the read data, the result of the atomic operation needs to be written to the address corresponding to the read data in the storage unit, that is, the atomic operation usually changes the data at the same address. Therefore, the cache cannot reduce the delay caused by reading and writing data in atomic operations.

[0061] Figure 2 The schematic diagram of the architecture of an atomic operation processing system provided by an exemplary embodiment of the present application is shown. The atomic operation processing system 100 includes a processor 110 , an atomic operation processing unit 120 and a storage unit 130 .

[0062] Among them, the atomic operation processing unit 120 is set independently of the processor 110, that is, the atomic operation processing system 100 includes an atomic operation processing unit 120 set independently of the processor 110; the processor 110 is connected to the atomic operation processing unit 120; the atomic operation processing unit 120 is connected to the storage unit 130 through a direct path.

[0063] Among them, the processor 110 is used to send atomic operation instructions to the atomic operation processing unit 120; the atomic operation processing unit 120 is used to read read data from the storage unit 130 based on the atomic operation instruction; perform atomic operations based on the atomic operation instruction and the read data to obtain atomic operation results; and write the atomic operation results into the storage unit 130.

[0064] Optionally, the processor 110 is a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) or an AI (Artificial Intelligence) processor, and the AI ​​processor is used to process computing operations related to machine learning. This application takes the processor 110 as a GPU as an example for explanation, but does not limit the specific type of the processor.

[0065] Optionally, the direct path is a path for connecting the atomic operation processing unit 120 and the storage unit 130; or, the direct path is a path that only connects the atomic operation processing unit 120 and the storage unit 130. If the path between the processor 110 and the atomic operation processing unit 120 is called the first path, the delay of the signal transmission on the first path is higher than the delay of the signal transmission on the direct path, that is, the transmission delay of the first path is higher than the transmission delay of the direct path. The path is a signal transmission path based on hardware implementation, and the signal transmission path includes: at least one of the circuits, caches, and other possible electronic devices in the chip. That is, the path is a signal transmission path composed of at least one of the metal lines, caches, and other possible electronic devices on the chip.

[0066] Optionally, the atomic operation instruction includes at least one of an atomic operation code, an atomic operand, and an address of the atomic operand. The atomic operation code is used to indicate to the atomic operation processing unit 120 the atomic operation to be performed, such as the atomic operation is an atomic addition operation (add), an atomic subtraction operation (sub), an atomic logical sum operation (and), an atomic logical or operation (or), etc. Generally speaking, the atomic operation code is required in the atomic operation instruction, the atomic operand and the address of the atomic operand are optional, and there may be one or more atomic operands and the addresses of the atomic operands.

[0067] Optionally, the atomic operation processing unit 120 reads read data from the storage unit 130 and writes the atomic operation result to the storage unit 130 through a direct path.

[0068] To summarize, the system provided in the embodiment of the present application sets the atomic operation unit supporting atomic operations independently from the processor. When executing atomic operations, the atomic operation processing unit only needs to interact with the storage unit through a direct path. Compared with the atomic operation processing unit located in the processor in the related technology, which needs to communicate with the storage unit through a second path, the direct path is a path connecting the atomic operation processing unit and the storage unit, and the second path is a path connecting the processor and the storage unit. Since the transmission delay of the direct path is usually lower than the transmission delay of the second path, the transmission delay of the system is lower than the transmission delay in the related technology, and the lower transmission delay can indirectly improve the operating efficiency of the atomic operation processing system.

[0069] Next, each module in the atomic operation processing unit 120 is introduced.

[0070] Read data processing module and atomic operation processing module:

[0071] In some embodiments, Figure 3As shown, the atomic operation processing unit 120 includes a read data processing module 50 and an atomic operation processing module 40 ; the direct path includes a read path 80 and a write path 81 .

[0072] The read data input terminal 54 of the read data processing module 50 is connected to the storage unit 130 through the read path 80; the read data output terminal 52 of the read data processing module 50 is connected to the first input terminal 42 of the atomic operation processing module 40. The output terminal 43 of the atomic operation processing module 40 is connected to the storage unit 130 through the write path 81.

[0073] Optionally, the read path 80 is used to transmit read data; the write path 81 is used to transmit write data (ie, the above-mentioned atomic operation result).

[0074] Optionally, the read data processing module 50 is used to read the read data from the storage unit 130 based on the atomic operation instruction. For example, the atomic operation instruction carries the address of the read data (or the address of the atomic operand).

[0075] Optionally, the atomic operation processing module 40 is used to perform an atomic operation based on the atomic operation instruction and the read data to obtain an atomic operation result, and write the atomic operation result into the storage unit 130. The read data is sent from the read data processing module 50 to the first input terminal 42 of the atomic operation processing module 40 through the read data output terminal 52.

[0076] In summary, the system provided by the embodiment of the present application further illustrates the internal structure of the atomic operation processing unit. The atomic operation processing unit includes a read data processing module for obtaining read data and an atomic operation processing module for performing atomic operations. According to the different functions of the read data processing module and the atomic operation processing module, there are different paths between them and the storage unit, namely, a read path and a write path. The read data processing module directly reads the read data from the storage unit through the read path, and the atomic operation processing module also directly writes the atomic operation result to the storage unit through the write path. Compared with the atomic operation processing system in the related art, in which the read data and the atomic operation result need to reach the storage unit via the on-chip network, the atomic operation processing system shown in the embodiment of the present application can reduce the delay of interacting with the storage unit during the atomic operation, thereby improving the efficiency of the atomic operation processing system in performing atomic operations.

[0077] Request scheduling module:

[0078] exist Figure 3 In the atomic operation processing unit 120 shown, both the read data processing module 50 and the atomic operation processing module 40 need to parse the atomic operation instruction to obtain the information they need. Therefore, a separate module for assisting in parsing the atomic operation instruction can be designed, such as Figure 4 shown.

[0079] The atomic operation processing unit 120 further includes a request scheduling module 30 .

[0080] Among them, the atomic operation instruction input terminal 31 of the request scheduling module 30 is connected to the processor 110; the original data output terminal 32 of the request scheduling module 30 is connected to the second input terminal 41 of the atomic operation processing module 40; the read request output terminal 33 of the request scheduling module 30 is connected to the read request input terminal 51 of the read data processing module 50.

[0081] Optionally, the atomic operation instruction may be referred to as an atomic operation request, an atomic write request, etc. Since the atomic operation of reading data usually requires the atomic operation result to overwrite the read data in the storage unit 130, or the address of the read data indicated in the atomic operation instruction is actually both the read address and the write address of the atomic operation instruction, the atomic operation instruction may also be considered as an atomic write request.

[0082] Optionally, the request scheduling module 30 is used to receive atomic operation instructions sent by the processor 110; obtain at least one original data and a read data request based on the atomic operation instruction, and the read data request is used to instruct the read data processing module 50 to obtain read data; input at least one original data into the atomic operation processing module 40, and send the read data request to the read data processing module 50.

[0083] That is, the request scheduling module 30 is responsible for parsing the information required by the read data processing module 50 and the atomic operation processing module 40 from the atomic operation instruction.

[0084] Optionally, the request scheduling module 30 is further used to indicate an operation code of the atomic operation to the atomic operation processing module 40 based on the atomic operation instruction. The operation code and at least one original data are sent to the atomic operation processing module 40 through the same path; or, the operation code and at least one original data are sent to the atomic operation processing module 40 through different paths, such as the operation code is sent through the control path, and at least one original data is sent using the data path.

[0085] When the operation code and at least one original data are sent to the atomic operation processing module 40 through the same path, the operation code and at least one original data are sent in the same clock cycle, that is, the operation code and at least one original data are spliced ​​and sent; or, the operation code and at least one original data are sent in different clock cycles.

[0086] Optionally, the operation code and at least one original data are both received at the second input terminal 41 of the atomic operation processing module 40; or, the atomic operation processing module 40 also includes an operation code input terminal, and the operation code input terminal is connected to the original data output terminal 32 of the request scheduling module 30; or, the atomic operation processing module 40 also includes an operation code input terminal, and the request scheduling module 30 also includes an operation code output terminal, and the operation code output terminal of the request scheduling module 30 is connected to the operation code input terminal of the atomic operation processing module 40.

[0087] It should be noted that the input and output shown above are logical concepts, that is, ports distinguished by function. In actual implementation, they can be integrated into one or more ports according to the needs of the module, device or unit. For example, the original data output terminal 32 and the read request output terminal 33 can be collectively referred to as the output terminal of the request scheduling module 30. In actual implementation, the original data output terminal 32 can be implemented as a physical pin, a physical interface, a physical connection point, etc. of the request scheduling module 30, and the read request output terminal 33 can be implemented as a physical pin, a physical interface, a physical connection point, etc. of the request scheduling module 30; that is, the original data output terminal 32 and the read request output terminal 33 are respectively implemented as different physical pins or physical interfaces or physical connection points, etc. In other embodiments, the original data output terminal 32 and the read request output terminal 33 are implemented as the same physical pin or physical interface or physical connection point; that is, the original data 34 and the read request 35 can be output by the same output terminal. The multiple input terminals and output terminals of other modules (or units or devices) shown in the embodiments of the present application are similarly referred to as an input terminal or an output terminal. That is, the input and output shown in the embodiments of the present application are logical concepts, and the functions are used as the basis for division, but the specific physical structure of the module is not limited. In other embodiments, the above-mentioned input and output can exist as a physical pin or a physical interface or a physical connection point, that is, the functions of input and output are encapsulated as a physical pin or a physical interface or a physical connection point. The embodiments of the present application are not limited to this.

[0088] In summary, the system provided by the embodiment of the present application adds a request scheduling module in the atomic operation processing unit, and the request scheduling module is responsible for receiving and parsing atomic operation instructions, thereby scheduling other modules in the atomic operation processing unit (such as the read data processing module and the atomic operation processing module) to complete the atomic operation. Scheduling is implemented by the request scheduling module, which can reduce the complexity of other modules in the atomic operation processing unit (that is, other modules do not need to perform the step of parsing the atomic operation instructions at this time), realize a more reasonable modular design of the atomic operation processing unit, and improve the maintainability and scalability of the atomic operation processing unit.

[0089] Same address processing path:

[0090] In some embodiments, the atomic operation processing module 40 also includes a same address processing path for connecting its own output terminal 43 and the first input terminal 42. The same address processing path is used to return the i-th atomic operation result corresponding to the i-th instruction to the first input terminal 42 when the i-th instruction and the i+1-th instruction correspond to the same address, and participate in the execution of the i+1-th instruction. The above-mentioned same address means that the i-th instruction and the i+1-th instruction correspond to the same write address (which can also be understood as the same read address, that is, the address corresponding to the read data is the same).

[0091] Optionally, the i-th instruction is one of n atomic operation instructions received by the atomic operation processing module 40, i is a positive integer, n is an integer greater than 1, and the n atomic operation instructions correspond to the same write address;

[0092] When i is equal to 1, the atomic operation processing module 40 is used to perform an atomic operation based on the i-th instruction to obtain the i-th atomic operation result. That is, the atomic operation processing module 40 performs an atomic operation based on at least one original data and read data corresponding to the i-th instruction to obtain the i-th atomic operation result.

[0093] When i is greater than 1 and i is less than n, the atomic operation processing module 40 is used to perform an atomic operation based on the i-th instruction and the i-1-th atomic operation result to obtain the i-th atomic operation result, and output the i-th atomic operation result to the first input terminal 42 through the same address processing path, and the i-1-th atomic operation result is obtained by performing an atomic operation based on the first i-1 instructions among the n atomic operation instructions. It can also be understood that the atomic operation processing module 40 performs an atomic operation based on at least one original data corresponding to the i-th instruction and the i-1-th atomic operation result to obtain the i-th atomic operation result.

[0094] In the case where i is equal to n, the atomic operation processing module 40 is used to perform an atomic operation based on the nth instruction and the n-1th atomic operation result to obtain the nth atomic operation result, where the n-1th atomic operation result is obtained by performing an atomic operation based on the first n-1 instructions among the n instructions; and write the nth atomic operation result into the storage unit 130. It can also be understood that the atomic operation processing module 40 performs an atomic operation based on at least one original data corresponding to the nth instruction and the n-1th atomic operation result to obtain the nth atomic operation result.

[0095] Optionally, after the atomic operation corresponding to the i-th instruction is executed, the atomic operation processing module 40 returns the i-th atomic operation result to the first input terminal 42 through the same address processing path, and writes the i-th atomic operation result to the storage unit 130; or, after the atomic operation corresponding to the i-th instruction is executed, the atomic operation processing module 40 only returns the i-th atomic operation result to the first input terminal 42 through the same address processing path, but does not write the i-th atomic operation result to the storage unit 130; until the atomic operation corresponding to the j-th instruction is executed, the j-th atomic operation result is written into the storage unit 130. The i-th instruction to the j-th instruction all correspond to the same address, but the j+1-th instruction and the j-th instruction correspond to different addresses, i and j are both positive integers, j>i.

[0096] Exemplarily, the atomic operation processing module 40 will process four atomic operation instructions, namely instruction 1, instruction 2, instruction 3 and instruction 4, wherein instruction 1, instruction 2 and instruction 3 correspond to the same address, and instruction 4 corresponds to different addresses from instruction 3. Then, when performing an atomic operation, the atomic operation processing module 40 first obtains atomic operation result 1 based on instruction 1. Since instruction 2 corresponds to the same address as instruction 1, the atomic operation result 1 is returned to the first input terminal 42 through the same address processing path; the atomic operation processing module 40 performs an atomic operation based on instruction 2 and atomic operation result 1 to obtain atomic operation result 2. Since instruction 3 corresponds to the same address as instruction 2, the atomic operation result 2 is returned to the first input terminal 42 through the same address processing path; the atomic operation processing module 40 performs an atomic operation based on instruction 3 and atomic operation result 2 to obtain atomic operation result 3. Since instruction 4 corresponds to different addresses from instruction 3, the atomic operation processing module 40 writes atomic operation result 3 into the storage unit 130; the atomic operation processing module 40 performs an atomic operation based on instruction 4 to obtain atomic operation result 4.

[0097] To summarize, the system provided by the embodiment of the present application shows two atomic operation processing processes based on the same address processing path. After each atomic operation is executed, the atomic operation result is written into the storage unit, but the atomic operation result will be returned to the first input end along with the same address processing path, so that the atomic operation processing unit does not need to read the atomic operation result from the storage unit again, thereby reducing a certain delay; on the other hand, the final atomic operation result is written into the storage unit only after all atomic operation instructions with the same address are executed, which also saves the multi-step writing process and can further save the atomic operation delay.

[0098] Figure 5 A schematic diagram of an atomic operation processing system provided by an exemplary embodiment of the present application is shown.

[0099] The atomic operation processing unit 120 includes a request scheduling module 30, an atomic operation processing module 40 and a read data processing module 50. Next, the entire atomic operation system is introduced in modules.

[0100] 1. Request scheduling module.

[0101] Optionally, the processor 110 is connected to the request scheduling module 30. Exemplarily, the processor 110 is connected to the request scheduling module 30 via an on-chip network 20.

[0102] Among them, the processor 110 is used to send an atomic operation instruction 21 to the request scheduling module 30. The atomic operation instruction 21 is used to instruct the atomic operation processing unit 120 to perform an atomic operation. Optionally, the atomic operation instruction 21 includes at least one of an atomic operation code, an atomic operand, and an address of the atomic operand. The atomic operation code is used to indicate to the atomic operation processing unit 120 the atomic operation to be performed, such as the atomic operation is an atomic addition operation (add), an atomic subtraction operation (sub), an atomic logical operation and operation (and), an atomic logical or operation (or), etc. Generally speaking, the atomic operation code in the atomic operation instruction 21 is required, the atomic operand and the address of the atomic operand are optional, and the atomic operand and the address of the atomic operand can be one or more.

[0103] Optionally, the request scheduling module 30 is used to schedule the atomic operation processing unit 120 to perform atomic operations based on the atomic operation instruction 21; or, the request scheduling module 30 is used to schedule the atomic operation processing module 40 and the read data processing module 50 to perform atomic operations based on the atomic operation instruction 21.

[0104] Optionally, the request scheduling module 30 is connected to the processor 110 ; the request scheduling module 30 is connected to the atomic operation processing module 40 ; the request scheduling module 30 is connected to the read data processing module 50 .

[0105] Optionally, the request scheduling module 30 includes an atomic operation instruction input terminal 31, an original data output terminal 32 and a read request output terminal 33. The atomic operation instruction input terminal 31 is connected to the processor 110; the original data output terminal 32 is connected to the atomic operation processing module 40; and the read request output terminal 33 is connected to the read data processing module 50.

[0106] Optionally, the functions of the request scheduling module 30 using the above-mentioned connection relationship (or interface design) are introduced as follows: the request scheduling module 30 is used to receive the atomic operation instruction 21 sent by the processor 110; based on the atomic operation instruction 21, at least one original data and a read data request are obtained, and the read data request is used to instruct the read data processing module 50 to obtain the read data, and at least one original data is the data required to perform the atomic operation; at least one original data is input into the atomic operation processing module 40, and the read data request is sent to the read data processing module 50.

[0107] That is, the request scheduling module 30 determines the original data 34 according to the atomic operation instruction 21 (such as the original data 34 is the atomic operand carried in the atomic operation instruction 21), or the request scheduling module 30 receives the original data 34 according to the atomic operation instruction 21, that is, the atomic operation instruction 21 does not carry the atomic operand, but indicates how to receive the original data 34. And the request scheduling module 30 determines the read request 35 according to the atomic operation instruction 21, such as the atomic operation instruction 21 carries the address of the read data, the request scheduling module 30 determines the read request 35 according to the address of the read data, or the request scheduling module 30 extracts the read request 35 from the atomic operation instruction 21, that is, the atomic operation instruction 21 carries the read request 35, and the request scheduling module 30 only needs to perform the extraction operation.

[0108] It should be noted that the original data output terminal 32 and the read request output terminal 33 can be collectively referred to as the output terminal of the request scheduling module 30. In actual implementation, the original data output terminal 32 can be implemented as a physical pin, a physical interface, a physical connection point, etc. of the request scheduling module 30, and the read request output terminal 33 can be implemented as a physical pin, a physical interface, a physical connection point, etc. of the request scheduling module 30; that is, the original data output terminal 32 and the read request output terminal 33 are respectively implemented as different physical pins or physical interfaces or physical connection points, etc. In other embodiments, the original data output terminal 32 and the read request output terminal 33 are implemented as the same physical pin or physical interface or physical connection point; that is, the original data 34 and the read request 35 can be output by the same output terminal. Similarly, the multiple input terminals and output terminals of other modules (or units or devices) shown in the embodiments of the present application can be collectively referred to as one input terminal or one output terminal. That is, the input terminals and output terminals shown in the embodiments of the present application are logical concepts, with functions as the basis for division, but do not limit the specific physical structure of the module. In other embodiments, the input and output terminals may exist as a physical pin, a physical interface, or a physical connection point, that is, the functions of the input and output are encapsulated as a physical pin, a physical interface, or a physical connection point. This embodiment of the present application does not limit this.

[0109] 2. Read data processing module.

[0110] Optionally, the read data processing module 50 is connected to the storage unit 130 ; and the read data processing module 50 is connected to the atomic operation processing module 40 .

[0111] The read data processing module 50 is used to read the read data from the storage unit 130 based on the read request 35 ; and send the read data to the atomic operation processing module 40 .

[0112] Optionally, the read data processing module 50 includes a read request input terminal 51, a read data output terminal 52, a read data request output terminal 53 and a read data input terminal 54. The read data input terminal 54 of the read data processing module 50 is connected to the storage unit 130 through a read path; the read request input terminal 51 is connected to the request scheduling module 30, or it can be said that the read request input terminal 51 of the read data processing module 50 is connected to the read request output terminal 33 of the request scheduling module 30; and the read data request output terminal 53 is connected to the storage unit 130.

[0113] The read data processing module 50 is used to read the read data 56 from the storage unit 130 based on the read request 35 and send the read data 56 to the atomic operation processing module 40. The process of reading the read data 56 from the storage unit 130 based on the read request can be called read request and data interaction 55.

[0114] In some embodiments, the read data request output terminal 53 and the read data input terminal 54 can be implemented as a port, such as a read port, which is connected to the storage unit 130 through a read path. The read data processing module 50 is used to read the read data 56 from the storage unit 130 through the read port.

[0115] 3.Atomic operation processing module.

[0116] Optionally, the atomic operation processing module 40 includes a second input terminal 41, a first input terminal 42 and an output terminal 43, and the atomic operation processing module 40 is further provided with a same address processing path 44 for connecting the first input terminal 42 and the output terminal 43. The second input terminal 41 is connected to the request scheduling module 30, or it can be said that the second input terminal 41 is connected to the original data output terminal 32 of the request scheduling module 30; the first input terminal 42 is connected to the read data processing module 50, or it can be said that the first input terminal 42 is connected to the read data output terminal 52 of the read data processing module 50; and the output terminal 43 is connected to the storage unit 130.

[0117] Optionally, the output terminal 43 of the atomic operation processing module 40 is connected to the storage unit 130 through a write path.

[0118] The atomic operation processing module 40 is used to perform an atomic operation based on at least one original data 34 and read data 56 to obtain an atomic operation result 45 ; and write the atomic operation result 45 into the storage unit 130 .

[0119] In some embodiments, a design for multiple atomic operation instructions with the same address is added. The same address processing path 44 is used to return the i-th atomic operation result corresponding to the i-th instruction to the first input terminal 42 when the i-th instruction and the i+1-th instruction correspond to the same address, and participate in the execution of the i+1-th instruction. Therefore, a selection unit 46 is added before the first input terminal 42 of the atomic operation processing module 40, and the selection unit 46 is used to select one of the data outputs from the multiple input data. Optionally, the selection unit 46 selects from the multiple data according to the selection signal, and the selection signal comes from the request scheduling module 30 or the atomic operation processing module 40 or the read data processing module 50 or other modules not shown in the atomic operation processing unit 120.

[0120] Exemplarily, the selection signal is sent by the request scheduling module 30 to the selection unit 46. The request scheduling module 30 is used to determine the selection signal based on the atomic operation instruction 21. For example, the selection signal "1" indicates that the read data 56 sent from the read data output terminal 52 is selected for output, and the selection signal "0" indicates that the atomic operation result 45 sent through the same address processing path 44 is selected. The overall process is as follows: the request scheduling module 30 receives the j-th instruction, determines that the j-th instruction and the j-1-th instruction correspond to different addresses, and therefore sends the selection signal "1" to the selection unit 46. At this time, the first input terminal 42 inputs the read data 56 read from the storage unit 130 by the read data processing module 50. The atomic operation processing module 40 performs an atomic operation based on the original data 34 and the read data 56 to obtain the jth atomic operation result; the request scheduling module 30 receives the j+1th instruction, determines that the j+1th instruction corresponds to the same address as the jth instruction, and therefore sends a selection signal "0" to the selection unit 46. At this time, the first input terminal 42 inputs the jth atomic operation result returned through the same address processing path 44. The atomic operation processing module 40 performs an atomic operation based on the original data 34 and the jth atomic operation result to obtain the j+1th atomic operation result.

[0121] For the specific functions of the same address processing path 44, please refer to the above embodiments and will not be described again here.

[0122] Optionally, the processor 110 is connected to the atomic operation processing unit 120 via an on-chip network; or, the processor 110 is connected to the atomic operation processing unit 120 via a bus; or, the processor 110 is connected to the atomic operation processing unit 120 via a first path. Figure 6As shown, the processor 110 is connected to the atomic operation processing unit 120 via the on-chip network 20. The on-chip network and bus provide a more flexible way to expand the atomic operation processing system 100. When adding more units (such as processors, storage units, etc.) to the atomic operation processing system 100, it is only necessary to connect them to the on-chip network or bus without redesigning the circuits in the entire atomic operation system, which is conducive to improving the flexibility and scalability of the entire atomic operation processing system 100.

[0123] It should be noted that the above description is based on an example of a processor, an atomic operation processing unit and a storage unit. In a specific implementation, the atomic operation processing system may include multiple processors, multiple atomic operation processing units and multiple storage units.

[0124] Exemplarily, there are multiple atomic operation processing units 120 and storage units 130 in the atomic operation processing system 100, and there is a one-to-one correspondence between the atomic operation processing units 120 and the storage units 130.

[0125] There is a one-to-one correspondence between the atomic operation processing unit 120 and the storage unit 130, which means that each atomic operation processing unit 120 corresponds to one storage unit 130. Optionally, one atomic operation processing unit 120 corresponds to only one storage unit 130. One storage unit 130 corresponds to zero or one atomic operation processing unit 120.

[0126] For example, Figure 7 The figure shows an atomic operating system of a multi-core processor 110, multiple atomic operation processing units 120 and multiple storage units 130. The atomic operating system can actually include multiple single-core or multiple multi-core processors, multiple atomic operation processing units and multiple storage units. During the atomic operation process, the corresponding relationship between the processor 110 (or processor core), the atomic operation processing unit 120 and the storage unit 130 can be allocated by the on-chip network 20, which is not limited in the embodiment of the present application. Figure 1 In the solution used in the related technology, for the atomic operation processing unit, the paths for reading and writing data are shortened. However, since the atomic operation instructions sent by the processor core still need to be received, the path for scheduling the atomic operation processing unit becomes longer. However, the shortened paths for reading and writing data can improve the execution efficiency of atomic operations. Especially for scenes with frequent reading and writing, the delay caused by the long reading and writing paths can be reduced.

[0127] Figure 8A flowchart of an atomic operation processing method provided by an exemplary embodiment of the present application is shown. The method is executed by the atomic operation processing system provided by each of the above embodiments, the atomic operation processing system includes a processor, a storage unit, and an atomic operation processing unit independently provided from the processor; the processor is connected to the atomic operation processing unit; the atomic operation processing unit is connected to the storage unit via a direct path.

[0128] The method includes:

[0129] Step 1: The processor sends an atomic operation instruction to the atomic operation processing unit.

[0130] Step 2: The atomic operation processing unit reads data from the storage unit based on the atomic operation instruction.

[0131] Step 3: The atomic operation processing unit performs the atomic operation based on the atomic operation instruction and the read data to obtain the atomic operation result.

[0132] Step 4: The atomic operation processing unit writes the atomic operation result into the storage unit.

[0133] Next, the functions of each unit or device in the above-mentioned atomic operation processing system are introduced.

[0134] Optionally, the atomic operation processing unit includes a read data processing module and an atomic operation processing module; the direct path includes a read path and a write path; the read data input end of the read data processing module is connected to the storage unit through the read path; the read data output end of the read data processing module is connected to the first input end of the atomic operation processing module; the output end of the atomic operation processing module is connected to the storage unit through the write path;

[0135] Wherein, the read data processing module reads the read data from the storage unit based on the atomic operation instruction;

[0136] The atomic operation processing module performs atomic operations based on the atomic operation instructions and read data to obtain atomic operation results; and writes the atomic operation results into the storage unit.

[0137] exist Figure 3 In the atomic operation processing unit shown, both the read data processing module and the atomic operation processing module need to parse the atomic operation instruction to obtain the information they need. Therefore, a separate module for assisting in parsing the atomic operation instruction can be designed.

[0138] Optionally, the atomic operation processing unit further includes a request scheduling module; the request scheduling module includes an atomic operation instruction input terminal, a read request output terminal and an original data output terminal; the read data processing module further includes a read request input terminal; the atomic operation processing module further includes a second input terminal; the atomic operation instruction input terminal of the request scheduling module is connected to the processor; the original data output terminal of the request scheduling module is connected to the second input terminal of the atomic operation processing module; the read request output terminal of the request scheduling module is connected to the read request input terminal of the read data processing module;

[0139] The request scheduling module receives an atomic operation instruction sent by the processor; obtains at least one original data and a read data request based on the atomic operation instruction, and the read data request is used to instruct the read data processing module to obtain the read data; inputs at least one original data into the atomic operation processing module, and sends the read data request to the read data processing module;

[0140] The read data processing module reads the read data from the storage unit based on the read data request; inputs the read data into the atomic operation processing module;

[0141] The atomic operation processing module performs an atomic operation based on at least one original data and read data to obtain an atomic operation result; and writes the atomic operation result into a storage unit.

[0142] In some embodiments, the atomic operation processing unit also includes a same address processing path for connecting its own output terminal and the first input terminal. The same address processing path is used to return the i-th atomic operation result corresponding to the i-th instruction to the first input terminal when the i-th instruction and the i+1-th instruction correspond to the same address, and participate in the execution of the i+1-th instruction. The above-mentioned same address means that the i-th instruction and the i+1-th instruction correspond to the same write address (which can also be understood as the same read address, that is, the address corresponding to the read data is the same).

[0143] Optionally, the atomic operation processing module includes a same address processing path for connecting its own output terminal and the first input terminal; the i-th instruction is one of n atomic operation instructions received by the atomic operation processing unit, i and n are integers greater than 1, and the n atomic operation instructions correspond to the same write address;

[0144] Wherein, when i is greater than 1 and i is less than n, the atomic operation processing module is used to perform an atomic operation based on the i-th instruction and the i-1-th atomic operation result to obtain the i-th atomic operation result; output the i-th atomic operation result to the first input terminal through the same address processing path, and the i-1-th atomic operation result is obtained by performing an atomic operation based on the first i-1 instructions among the n atomic operation instructions;

[0145] When i is equal to n, the atomic operation processing module is used to perform an atomic operation based on the nth instruction and the n-1th atomic operation result to obtain the nth atomic operation result, where the n-1th atomic operation result is obtained by performing an atomic operation based on the first n-1 instructions among the n instructions; and write the nth atomic operation result into a storage unit.

[0146] To summarize, the method provided in the embodiment of the present application sets the atomic operation unit supporting atomic operations independently from the processor. When executing atomic operations, the atomic operation processing unit only needs to interact with the storage unit through a direct path. Compared with the atomic operation processing unit located in the processor in the related technology, which needs to communicate with the storage unit through a second path, the direct path is a path connecting the atomic operation processing unit and the storage unit, and the second path is a path connecting the processor and the storage unit. Since the transmission delay of the direct path is usually lower than the transmission delay of the second path, the transmission delay of the system is lower than the transmission delay in the related technology, and the lower transmission delay can indirectly improve the operating efficiency of the atomic operation processing system.

[0147] On the other hand, an embodiment of the present application provides a graphics card, which includes the atomic operation processing system described in the above embodiments.

[0148] On the other hand, an embodiment of the present application provides a computer device, wherein the computer device includes the atomic operation processing system as described above. The computer device may be at least one of a portable computer, a desktop computer, a server, a server cluster, an artificial intelligence (AI) computing cluster, and a cloud computing cluster. Among them, the AI ​​computing cluster may also be referred to as an intelligent computing cluster or a smart computing cluster.

[0149] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0150] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An atomic operation processing system, characterized in that: The atomic operation processing system comprises a processor, a storage unit, and an atomic operation processing unit independently provided from the processor; the processor is connected to the atomic operation processing unit; the atomic operation processing unit is connected to the storage unit via a direct path; The processor is used to send an atomic operation instruction to the atomic operation processing unit; The atomic operation processing unit is used to read the read data from the storage unit based on the atomic operation instruction; An atomic operation is performed based on the atomic operation instruction and the read data to obtain an atomic operation result; and the atomic operation result is written into the storage unit.

2. The system according to claim 1, characterized in that The atomic operation processing unit includes a read data processing module and an atomic operation processing module; the direct connection path includes a read path and a write path; The read data input terminal of the read data processing module is connected to the storage unit through the read path; the read data output terminal of the read data processing module is connected to the first input terminal of the atomic operation processing module; The output end of the atomic operation processing module is connected to the storage unit through the write path.

3. The system according to claim 2, characterized in that The read data processing module is used to read the read data from the storage unit based on the atomic operation instruction; The atomic operation processing module is used to perform the atomic operation based on the atomic operation instruction and the read data to obtain the atomic operation result; The atomic operation result is written into the storage unit.

4. The system according to any one of claims 1 to 3, characterized in that: The atomic operation processing unit also includes a request scheduling module; The atomic operation instruction input terminal of the request scheduling module is connected to the processor; The original data output terminal of the request scheduling module is connected to the second input terminal of the atomic operation processing module; The read request output terminal of the request scheduling module is connected to the read request input terminal of the read data processing module.

5. The system according to claim 4, characterized in that The request scheduling module is used to receive the atomic operation instruction sent by the processor; obtain at least one original data and a read data request based on the atomic operation instruction, and the read data request is used to instruct the read data processing module to obtain the read data; input the at least one original data into the atomic operation processing module, and send the read data request to the read data processing module; The read data processing module is used to read the read data from the storage unit based on the read data request; and input the read data into the atomic operation processing module; The atomic operation processing module is used to perform an atomic operation based on the at least one original data and the read data to obtain the atomic operation result; and write the atomic operation result into the storage unit.

6. The system according to any one of claims 1 to 3, characterized in that: The atomic operation processing module includes a same address processing path for connecting its own output terminal and the first input terminal; the i-th instruction is one of n atomic operation instructions received by the atomic operation processing unit, i and n are integers greater than 1, and the n atomic operation instructions correspond to the same write address; In the case where i is greater than 1 and i is less than n, the atomic operation processing module is used to perform an atomic operation based on the i-th instruction and the i-1-th atomic operation result to obtain the i-th atomic operation result; output the i-th atomic operation result to the first input end through the same address processing path, and the i-1-th atomic operation result is obtained by performing an atomic operation based on the first i-1 instructions among the n atomic operation instructions; When i is equal to n, the atomic operation processing module is used to perform an atomic operation based on the nth instruction and the n-1th atomic operation result to obtain the nth atomic operation result, wherein the n-1th atomic operation result is obtained by performing an atomic operation based on the first n-1 instructions among the n instructions; and write the nth atomic operation result into the storage unit.

7. The system according to any one of claims 1 to 3, characterized in that: The processor is connected to the atomic operation processing unit via an on-chip network.

8. The system according to claim 7, characterized in that There are multiple atomic operation processing units and multiple storage units in the atomic operation processing system, and there is a one-to-one correspondence between the atomic operation processing units and the storage units.

9. An atomic operation processing method, characterized in that: The method is performed by an atomic operation system, wherein the atomic operation processing system includes a processor, a storage unit, and an atomic operation processing unit independently provided from the processor; The processor is connected to the atomic operation processing unit; The atomic operation processing unit is connected to the storage unit via a direct connection path; The method comprises: The processor sends an atomic operation instruction to the atomic operation processing unit; The atomic operation processing unit reads read data from the storage unit based on the atomic operation instruction; performs an atomic operation based on the atomic operation instruction and the read data to obtain an atomic operation result; and writes the atomic operation result into the storage unit.

10. The method according to claim 9, characterized in that The atomic operation processing unit includes a read data processing module and an atomic operation processing module; The atomic operation processing unit reads read data from the storage unit based on the atomic operation instruction; Perform an atomic operation based on the atomic operation instruction and the read data to obtain an atomic operation result; Writing the atomic operation result into the storage unit comprises: The read data processing module reads the read data from the storage unit based on the atomic operation instruction; The atomic operation processing module performs an atomic operation based on the atomic operation instruction and the read data to obtain the atomic operation result; and writes the atomic operation result into the storage unit.

11. The method according to claim 9 or 10, characterized in that: The atomic operation processing unit also includes a request scheduling module; The atomic operation processing unit reads read data from the storage unit based on the atomic operation instruction; Perform an atomic operation based on the atomic operation instruction and the read data to obtain an atomic operation result; Writing the atomic operation result into the storage unit comprises: The request scheduling module receives the atomic operation instruction sent by the processor; obtains at least one original data and a read data request based on the atomic operation instruction, wherein the read data request is used to instruct the read data processing module to obtain the read data; inputs the at least one original data into the atomic operation processing module, and sends the read data request to the read data processing module; The read data processing module reads the read data from the storage unit based on the read data request; and inputs the read data into the atomic operation processing module; The atomic operation processing module performs an atomic operation based on the at least one original data and the read data to obtain the atomic operation result; and writes the atomic operation result into the storage unit.

12. The method according to claim 9 or 10, characterized in that: The atomic operation processing module includes a same address processing path for connecting its own output terminal and the first input terminal; the i-th instruction is one of n atomic operation instructions received by the atomic operation processing unit, i and n are integers greater than 1, and the n atomic operation instructions correspond to the same write address; The atomic operation processing unit reads read data from the storage unit based on the atomic operation instruction; Perform an atomic operation based on the atomic operation instruction and the read data to obtain an atomic operation result; Writing the atomic operation result into the storage unit comprises: In the case where i is greater than 1 and i is less than n, the atomic operation processing module is used to perform an atomic operation based on the i-th instruction and the i-1-th atomic operation result to obtain the i-th atomic operation result; output the i-th atomic operation result to the first input end through the same address processing path, and the i-1-th atomic operation result is obtained by performing an atomic operation based on the first i-1 instructions among the n atomic operation instructions; When i is equal to n, the atomic operation processing module is used to perform an atomic operation based on the nth instruction and the n-1th atomic operation result to obtain the nth atomic operation result, wherein the n-1th atomic operation result is obtained by performing an atomic operation based on the first n-1 instructions among the n instructions; and write the nth atomic operation result into the storage unit.

13. A graphics card, characterized in that: The graphics card includes the atomic operation processing system as described in any one of claims 1 to 8.

14. A computer device, characterized in that: The computer device comprises an atomic operation processing system as described in any one of claims 1 to 8.

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