Voltage-conductance point distribution for artificial neural networks

Abstract

Updating a voltage-conductance point distribution of an artificial neural network may include receiving, at an accelerator of, for example, a MAC unit, information of a memory array corresponding to the MAC unit. A plurality of parameters of the ANN may be received. The voltage-conductance point distribution may be identified using the plurality of parameters and based on the information corresponding to the memory array. The voltage-conductance point distribution corresponds to a discernible conductance level and a subset of the plurality of parameters. The ANN may be stored in the MAC unit based on the discernible level of electrical conductivity.

Description

Technical Field

[0001] The present disclosure generally relates to apparatus, non-transitory machine-readable media, and methods associated with updating voltage-conductance point distributions of artificial neural networks. Background Art

[0002] The computing device may be, for example, a personal laptop computer, a desktop computer, a smart phone, smart glasses, a tablet computer, a wrist-worn device, a mobile device, a digital camera, and / or redundant combinations thereof, as well as other types of computing devices.

[0003] A computing device may be used to perform an operation. Performing an operation may utilize resources of the computing device. For example, performing an operation may utilize memory resources, processing resources, and power resources. The performed operation may be affected by the characteristics of the memory device. Summary of the invention

[0004] One aspect of the present disclosure relates to a method for updating a voltage-conductance point distribution of an artificial neural network, comprising: receiving, at an accelerator, information corresponding to a memory array of the accelerator; receiving, at the accelerator, a plurality of parameters of an artificial neural network (ANN); identifying, at the accelerator, a voltage-conductance point distribution using the plurality of parameters and based on the information corresponding to the memory array, wherein the voltage-conductance point distribution corresponds to a discernible conductance level and a subset of the plurality of parameters; and storing the ANN in the accelerator based on the discernible conductance level.

[0005] Another aspect of the present disclosure relates to an apparatus for updating a voltage-conductance point distribution of an artificial neural network, comprising: an accelerator including a multiply and accumulate (MAC) unit having a plurality of memory arrays; a controller coupled to the accelerator and configured to: receive information corresponding to the plurality of memory arrays of the MAC unit; receive a plurality of parameters of an artificial neural network (ANN); identify a voltage-conductance point distribution using the plurality of parameters and based on the information corresponding to the plurality of memory arrays, wherein the voltage-conductance point distribution corresponds to a discernible conductance level and a subset of the plurality of parameters; and provide the voltage-conductance point distribution to the accelerator to store the ANN in the MAC unit based on the voltage-conductance point distribution.

[0006] Yet another aspect of the present disclosure relates to a non-transitory machine-readable medium having computer-readable instructions for updating a voltage-conductance point distribution of an artificial neural network, the computer-readable instructions, when executed by a computer, cause the computer to: access a voltage-conductance point distribution; receive a plurality of parameters of an artificial neural network (ANN); store the plurality of parameters in a memory array of a multiply and accumulate (MAC) unit of an accelerator; and read the plurality of parameters from the memory array using the voltage-conductance point distribution to interpret a signal received from reading the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 An example computing system for updating a voltage-conductance point distribution of an artificial neural network is described according to some embodiments of the present disclosure.

[0008] Figure 2 A diagram showing a quantization profile according to some embodiments of the present disclosure is illustrated.

[0009] Figure 3 The illustration shows a graph showing the distribution of quantization profiles and parameters of an artificial neural network according to some embodiments of the present disclosure.

[0010] Figure 4 is a functional block diagram for updating voltage-conductance point distribution according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart corresponding to a method for updating a voltage-conductance point distribution according to some embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Apparatus, machine-readable media, and methods related to updating a voltage-conductance point distribution of an artificial neural network (ANN) are described. An accelerator including a multiply and accumulate (MAC) unit may receive information corresponding to a memory array of the MAC unit. The accelerator may also receive a plurality of parameters of the ANN. The accelerator may utilize the plurality of parameters and identify a voltage-conductance point distribution based on the information corresponding to the memory array. The voltage-conductance point distribution may have distinguishable conductance levels corresponding to a subset of the plurality of parameters. The ANN may be stored in the MAC unit based on the distinguishable conductance levels. As used herein, a MAC unit is hardware that calculates the product of two values ​​and adds the product to an accumulator.

[0014] The values ​​generated in the digital domain may be converted to the analog domain to store the values ​​in memory. In some approaches, the conversion of values ​​may assume that voltage levels are uniformly distributed to the conductance levels (e.g., uniform voltage-conductance points) for reading and storing values ​​in a multi-level cell (MLC). As described in more detail herein, the voltage-conductance point refers to the voltage that makes the MLC conductive for a particular data state. MLCs programmed to different data states will conduct in response to different corresponding voltages being applied thereto. There are many factors that may affect the distribution of voltage levels to the conductance levels for reading and storing to the MLCs. The presence of these factors may cause errors when storing or reading values ​​stored in the MLCs.

[0015] Aspects of the present disclosure address the above and other shortcomings by updating the voltage-conductance point distribution of the ANN. The ANN may include weights, biases, and / or activation functions. The weights, biases, and / or activation functions of the ANN may be referred to as parameters of the ANN. The parameters may also be referred to as values. The parameters may be stored in a MAC unit of an accelerator configured to execute the ANN. The voltage-conductance points used to store and / or read parameters from the MAC unit may be updated based on information associated with the memory array of the MAC unit. The information associated with the memory array of the MAC unit may describe various noise sources present in the MAC unit implemented in the analog domain. The information associated with the memory array of the MAC unit may not only describe the noise sources, but also describe their modeling. The noise sources may be operational noise sources.

[0016] As used herein, a voltage-conductance point is a related voltage level and a corresponding conductance level. The voltage-conductance point is associated with the parameters of the ANN to produce a quantized profile. As used herein, the ANN can provide learning by forming a probability weight association between the input and the output. The probability weight association can be provided by a plurality of nodes that constitute the ANN. The nodes, together with weights, biases and / or activation functions, can be used to generate the output of the ANN based on the input of the ANN. A plurality of nodes of the ANN can be grouped to form a layer of the ANN. The ANN can be implemented using an accelerator, such as a deep learning accelerator. As used herein, a deep learning accelerator can include hardware configured to perform machine learning operations including operations used to implement the ANN.

[0017] Figure 1 An example computing system for updating the voltage-conductance point distribution of an ANN according to some embodiments of the present disclosure is illustrated. The computing system may include a computing device 102. The computing device 102 may include a processor 104 and a memory subsystem 111. The memory subsystem includes a memory array 105, an accelerator 109, and a controller 114.

[0018] The memory subsystem 111 may be hardware, firmware, and / or software configured to implement the ANN 106 using the accelerator 109. The memory subsystem 111 (e.g., a non-transitory MRM) may store instructions and / or data (e.g., the ANN 106, the voltage-conductance point distribution 107, and the operational information 108). Although the following description refers to one processing device and one memory device, the description may also be applicable to systems having multiple processing devices and multiple memory devices. In such examples, the instructions may be distributed across (e.g., stored by) multiple memory devices and the instructions may be distributed across (e.g., executed by) multiple processing devices.

[0019] The memory subsystem 111 may include a memory device. The memory device may be an electronic, magnetic, optical or other physical storage device that stores executable instructions. One or both of the memory devices may be, for example, non-volatile or volatile memory. In some examples, one or both of the memory devices are non-temporary MRMs including RAM, electrically erasable programmable ROM (EEPROM), storage drives, optical disks, and the like. In this example, the quantization circuit system 110 may be disposed in the accelerator 109. The accelerator 109 may also include a MAC unit 112. The MAC unit 112 may include an array 113 (e.g., a memory array) including a multi-level cell (MLC). Although the MAC unit 112 is shown to include an array 113, the MAC unit 112 may include multiple arrays. The accelerator 109 may be hardware, firmware, and / or software configured to implement the ANN 106 using the MAC unit 112. The MLC may be a memory cell that can be programmed to any of three or more data states, where each data state represents a different value.

[0020] The memory subsystem 111 may be, for example, a portable, external, or remote storage medium that allows the computing device 102 to download the ANN 106, the voltage-conductance point distribution 107, and / or the operational information 108 from the portable / external / remote storage medium. In various examples, the ANN 106, the voltage-conductance point distribution 107, and / or the operational information 108 may be part of an “installation package.” As described herein, the memory subsystem 111 may be encoded with executable instructions for updating the voltage-conductance point distribution 107, which may be used to implement the ANN 106 using the MAC unit 112.

[0021] In various examples, ANN 106, voltage-conductance point distribution 107, and / or operation information 108 may be provided to accelerator 109. ANN 106, voltage-conductance point distribution 107, and / or operation information 108 may be read from memory array 105 before ANN 106, voltage-conductance point distribution 107, and / or operation information 108 are provided to accelerator 109. Figure 1 105, the voltage-conductance point distribution 107 may also be stored in the accelerator 109. For example, the voltage-conductance point distribution 107 may be stored in a register of the accelerator 109. In such an example, the voltage-conductance point distribution 107 may be accessed by the accelerator 109 without transmitting the voltage-conductance point distribution 107 to the accelerator 109.

[0022] ANN 106 may include weights, biases and / or activation functions along with other values ​​used to implement ANN 106. ANN can be trained, which may include updating weights, biases and / or activation functions. ANN 106 may be deployed at accelerator 109. ANN 106 may be trained in a binary environment, which may have very little or no adverse effect on the output of ANN 106, due to, for example, that the operational binary environment is more reliable than the corresponding simulation environment. ANN 106 may be implemented (e.g., run) in a simulation environment (e.g., accelerator 109). In order to implement ANN 106 in a simulation environment, weights, biases and / or activation functions of ANN 106 may be converted from the digital domain to the analog domain.

[0023] If the conversion of weights, biases and / or activation functions (e.g., ANN 106) does not take into account the various noise sources present in the analog domain, the conversion may be inaccurate. Inaccurate conversion of weights, biases and / or activation functions may lead to inaccuracies in the inferences generated using ANN 106.

[0024] The conversion process may be accompanied by a quantization process because representing high-bit values ​​per parameter is an energy and power intensive operation in the analog domain and may increase the sensitivity of the computation to noise. The quantization process may be used to associate the values ​​of weights, biases, and / or activation functions with conductance levels and / or voltage levels (e.g., voltage-conductance points) used to program or read memory cells of the array 113. Noise sources and / or modeling of noise sources may be utilized to facilitate the quantization process. The quantization process may also be performed using the effects of noise sources and / or their modeling on the accuracy of the ANN 106.

[0025] Noise sources and / or their modeling may be referred to as operating characteristics or operating information corresponding to the operation of the array 113, accelerator 109, memory subsystem 111, and / or computing device 102. The conversion of values ​​(e.g., weights, biases, and / or activation functions) may be susceptible to the operating characteristics of the array 113. The operating characteristics may include, for example, the operating temperature, power state, and / or current-voltage characteristics of the array 113, accelerator 109, memory subsystem 111, and / or computing device 102. The operating temperature, power state, and / or current-voltage characteristics of the array 113 may increase the thermal noise and / or shot noise experienced by the memory cells of the array 113, which may affect the programming of the memory cells of the array 113 and / or the reading of the memory cells of the array 113. The operating temperature, power state, and / or current-voltage characteristics, etc., may be used to dynamically adjust the voltage-conductance point distribution, which allows the weights, biases, and / or activation functions of the ANN 106 to be accurately programmed using the memory cells of the array 113. Accurately programming memory cells of array 113 in light of operational noise experienced by array 113 may allow for improved inference accuracy of ANN 106, as opposed to programming memory cells without updating the voltage-conductance point distribution. The voltage-conductance point distribution may be updated without retraining ANN 106 (e.g., weights, biases, and / or activation functions).

[0026] Figure 2 The illustration shows graphs 220-1, 220-2, 220-3 showing quantization profiles according to some embodiments of the present disclosure.As used herein, a quantization profile is a voltage-conductance point distribution that may be selected based on a number of criteria.

[0027] Graph 220-1 shows a quantized profile that may include voltage-conductance points V1-G1, V2-G2, V3-G3, V4-G4, V5-G5, V6-G6, V7-G7, V8-G8. Graph 220-1 also shows a voltage-conductance characteristic 221-1 of a memory cell (e.g., MLC) of a MAC unit of an accelerator. As used herein, voltage-conductance characteristics 221-1, 221-2, 221-3 are the conductance of a memory cell when a voltage is applied to the memory cell. Voltage-conductance characteristics 221-1, 221-2, 221-3 may be affected by operating characteristics. For example, operating characteristics of a memory subsystem and / or a memory cell of a MAC unit may be particularly affected by aging of the memory subsystem and / or the memory cell of the MAC unit. As memory cells of the memory subsystem and / or MAC unit age, the voltage-conductance characteristics 221 - 1 , 221 - 2 , 221 - 3 of the memory cells may change.

[0028] The voltage-conductance points V1-G1, V2-G2, V3-G3, V4-G4, V5-G5, V6-G6, V7-G7, V8-G8 of the graph 220-1 are shown as being uniformly distributed. The voltages V1, V2, V3, V4, V5, V6, V7, and V8 are uniformly distributed and the conductances G1, G2, G3, G4, G5, G6, G7, and G8 of the graph 220-1 are uniformly distributed, so that the voltage-conductance points V1-G1, V2-G2, V3-G3, V4-G4, V5-G5, V6-G6, V7-G7, and V8-G8 are uniformly distributed. The voltage-conductance points V1-G1, V2-G2, V3-G3, V4-G4, V5-G5, V6-G6, V7-G7, and V8-G8 of the graph 220-1 are different and distinguishable, so that the memory cells can be programmed and read with accuracy above the threshold using the voltage-conductance points V1-G1, V2-G2, V3-G3, V4-G4, V5-G5, V6-G6, V7-G7, and V8-G8. Each of the voltage-conductance points V1-G1, V2-G2, V3-G3, V4-G4, V5-G5, V6-G6, V7-G7, and V8-G8 can correspond to a different value that can be used to program the memory cells. The memory cell may be programmed with different values ​​and may be read from the memory cell using the voltage-conductance points V1-G1, V2-G2, V3-G3, V4-G4, V5-G5, V6-G6, V7-G7, and V8-G8 of graph 220-1.

[0029] Graph 220-2 shows voltage-conductance characteristic 221-2. Voltage-conductance characteristic 221-2 indicates that uniform selection of voltage levels V1, V2, V3, V4, V5, V6, V7, and V8 results in selection of non-uniform conductance levels G1, G2, G3, G4, G5, G6, G7, and G8, such that voltage-conductance points V1-G1, V2-G2, V3-G3, V4-G4, V5-G5, V6-G6, V7-G7, and V8-G8 of graph 220-2 are non-uniform. As shown in graph 220-2, selection of uniform voltage levels and non-uniform conductance levels may result in indistinguishable voltage-conductance points 224 (e.g., V5-G5, V6-G6, V7-G7, and V8-G8). Programming and / or reading memory cells using indistinguishable voltage-conductance points 224 may cause errors when reading or programming the memory cells, which may cause errors in the inferences generated by the memory cells using ANN and MAC units. For example, when programming or reading from memory cells using voltage-conductance points 224, the values ​​assigned to voltage-conductance points 224 may be indistinguishable from each other.

[0030] In various examples, non-uniform voltage levels 222-1, 222-2, 222-3, 222-4, 222-5, 222-6, 222-7, 222-8 (referred to as voltage levels 222) and non-uniform conductance levels 223-1, 223-2, 223-3, 223-4, 223-5, 223-6, 223-7, 223-8 (referred to as conductance levels 223) may be selected, as shown in graph 220-3. Voltage levels 222 and conductance levels 223 may be selected in view of the voltage-conductance characteristics 221-3 of the memory cells and based on the values ​​of the ANN (e.g., weights, biases, and / or activation functions).

[0031] For example, a value including more information than other values ​​may be identified. A voltage-conductance point including voltage level 222 and conductance level 223 may be selected to make values ​​including more information distinguishable and to make the information available for accurate inference in the ANN. For example, a voltage-conductance point including voltage levels 222-1, 222-2, 222-3, 222-6, 222-7, 222-8 and conductance levels 223-1, 223-2, 223-3, 223-6, 223-7, 223-8 may be selected to make conductance levels 223-1, 223-2, 223-3, 223-6, 223-7, 222-8 distinguishable from each other, which has the benefit of making corresponding values ​​distinguishable from each other.

[0032] Selecting distinguishable conductance levels may also have the result of selecting indistinguishable conductance levels 223-3, 223-4, 223-5, 223-6 and corresponding voltage levels 222-3, 222-4, 222-5, 222-6. Utilizing indistinguishable conductance levels means that when programming or reading memory cells using voltages 222-3, 222-4, 222-5, 222-6, corresponding values ​​may be indistinguishable from each other. Figure 3 The selection of distinguishable voltage-conductance points and indistinguishable voltage-conductance points is further described.

[0033] Figure 3 Graphs 320, 330 showing a quantization profile and a distribution 332 of parameters of an ANN according to some embodiments of the present disclosure are illustrated. Graph 330 shows the distribution 332 of parameters. Graph 320 shows a quantization profile including voltage-conductance points. The voltage-conductance points include conductance levels and voltage levels.

[0034] Graph 330 shows a distribution 332 of parameters (e.g., weights, biases, and / or activation functions) of the ANN. Distribution 332 may be based on the number of parameters (e.g., occurrence rates) and / or different characteristics of the parameters. For example, graph 330 shows a distribution 332 based on the number of parameters and based on the values ​​of the parameters (e.g., weight value ranges). The values ​​of the parameters may be represented based on bits. For example, the values ​​of the parameters may be graphically represented using the least significant bit (LSB) and the most significant bit (MSB), respectively.

[0035] In various examples, the parameters may be analyzed to divide the parameters into minimum values ​​334-1 and maximum values ​​334-2 (e.g., a range of weight values) and the remainder of the values ​​333. Although the chart 330 shows that the parameters are divided into three groups (e.g., minimum values ​​334-1, maximum values ​​334-2 (collectively referred to as peripheral values ​​334), and remaining values ​​333), the parameters may be divided into a greater number or a smaller number of groups than the number of groups shown. The division of the parameters may be based on the type of distribution 332 and / or on the grouping of parameters that preserve the most information (e.g., learning) and / or the least information. In various examples, the weight values ​​with the highest occurrence rate may be determined to preserve the least information, while the weight values ​​with the lowest occurrence rate (e.g., parameters) may be determined to preserve the most information.

[0036] The quantization circuitry of the accelerator may process the parameters to determine a distribution 332 of the parameters. The distribution 332 may follow a bell curve pattern as shown in graph 330. However, the parameters may adopt a different type of distribution 332 other than a bell curve pattern.

[0037] The grouping of parameters and / or the mapping of parameters to voltage-conductance points may be based on the distribution and grouping of parameters. For example, parameters 334 and 333 (e.g., values ​​of parameters) may be mapped to conductance levels, as shown in chart 320. The mapped conductance levels may correspond to respective voltage-conductance points. The grouping of parameters and / or the mapping of parameters to conductance levels may make portions of the conductance levels discernible from one another and different portions of the conductance levels indistinguishable from one another. The conductance level mapped to parameter 334 is discernible, while the conductance level mapped to parameter 333 is indistinguishable. Indistinguishable conductance levels may be clustered together such that the distance between the indistinguishable conductance levels is less than a threshold. Reading a memory cell using an indistinguishable conductance level makes it impossible to accurately discern the read value compared to different values ​​corresponding to other indistinguishable conductance levels.

[0038] Mapping the parameters with the most information content to discernible conductivity levels allows the least amount of read or programming errors to be encountered compared to mapping the parameters with the least information content to indiscernible conductivity levels. Mapping parameter 333 to indiscernible conductivity levels sacrifices read and / or programming errors of parameter 333 in order to limit read and / or programming errors of parameter 334. This sacrifice allows the ANN to use the parameters with the most information content for inference, which will result in fewer inference errors than using the parameters with the least information content for inference.

[0039] Figure 4 is a functional block diagram for updating voltage-conductance point distribution according to some embodiments of the present disclosure. Figure 4 Quantization circuitry 410 , input model 406 , and output model 446 are shown.

[0040] Quantization circuit system 410 is hardware and / or firmware configured to update the voltage-conductance point distribution. The quantization circuit system may receive operation information 408. Operation information 408 may include current-voltage characteristics 441-1, operating temperature 441-2, and operating voltage 441-3. Current-voltage characteristics 441-1 represent the relationship between the current through the memory subsystem, array, MAC, and / or memory cell and the corresponding voltage across the memory subsystem, array, MAC, and / or memory cell. The current-voltage characteristics 441-1 of the memory cell may change over time and aging (e.g., with use). Operating temperature 441-2 is the temperature of the memory cell, the array including the memory cell, the MAC unit including the array, the accelerator including the MAC unit, and / or the memory subsystem including the accelerator. The voltage-conductance characteristics of the memory cell may change based on the operating temperature 441-2. Operating voltage 441-3 may describe the supply voltage used to operate the memory cell, array, MAC unit, accelerator, and / or memory subsystem. The operational information 408, along with parameters input to a model (eg, input to an ANN), can be used to update a voltage-conductance point distribution used to store or read parameters in a memory cell.

[0041] Operation information 408 and input model 406 may be received by quantization circuit system 410 from the main memory array of the memory subsystem. Operation information 408 and input model 406 may be received by quantization circuit system 410 before input model 406 and / or quantized model 446 are stored in the memory array of the MAC unit of the accelerator. For example, when input model 406 is stored in the main memory of the memory subsystem, input model 406 may be provided to quantization circuit system 410 for processing. In various examples, input model 406 may be provided to quantization circuit system 410 before input model 406 is stored in the main memory of the memory subsystem. Input model 406 may be converted to quantized model 446 without storing input model 406 in main memory. Alternatively, quantized model 446 may be stored in main memory.

[0042] At 442, input model 406 may be analyzed to determine whether the accuracy of inferences generated using input model 406 is greater than a threshold (eg, an accuracy threshold). Input model 406 may also be analyzed by quantization circuitry 410 to determine whether an error of an output of input model 406 is greater than a threshold.

[0043] At 442, the input model 406 can be analyzed using the voltage-conductance distribution points accessed by the quantization circuit system 410. The voltage-conductance distribution points can be default voltage-conductance distribution points before being updated. The voltage-conductance distribution points can also be associated with different ANNs before being updated. The input model 406 can be analyzed using sample input data. For example, the input model 406 can be used to perform operations using the input data to generate inferences (e.g., output data).

[0044] The input model 406 may be analyzed by, for example, storing weights, biases, and / or activation functions in an array of MAC units and utilizing the MAC units to perform operations of the ANN represented by the input model 406. Default voltage-conductance points may be used to store weights, biases, and / or activation functions in memory cells of the array. Default voltage-conductance points may also be used to read weights, biases, and / or activation functions from memory cells of the array.

[0045] Sample data (eg, input data) may be stored in a main memory of a memory subsystem. The sample data may be read from the main memory and provided to the quantization circuitry 410. The sample data may be used as input to the input model 406 to generate inferences.

[0046] At 443, it may be determined whether the accuracy of the inferences generated using the input model 406 is greater than a threshold. If the accuracy of the inferences generated using the input model 406 is greater than the threshold or the error of the output of the input model 406 is less than a different threshold, the input model 406 may be converted to a quantized model 446 without making any changes to the input model 406. If the accuracy of the inferences generated using the input model 406 is less than a threshold or the error of the output of the input model 406 is greater than a different threshold, the voltage-conductance point distribution may be modified.

[0047] In various examples, when the input model 406 is received by the quantization circuit system 410, a voltage-conductance point distribution corresponding to the input model 406 may be accessed. For example, the voltage-conductance point distribution may be stored in a main memory. The voltage-conductance point distribution may be provided to the quantization circuit system 410 along with the input model 406. In various examples, the voltage-conductance point distribution may be considered as part of the input model 406.

[0048] The voltage-conductance point distribution may also be stored in the accelerator. For example, the voltage-conductance point distribution may be stored in registers and other locations of the accelerator. The quantization logic 410 may access the voltage-conductance point distribution from the accelerator.

[0049] At 444, the most informative parameter value from the plurality of parameter values ​​of the input model 406 may be identified and selected in response to determining that the target / error accuracy of the input model 406 is not met. The selected parameter value may be divided into Figure 4 The medium represents a low parameter value n l and high parameter value n L The selected parameter value can distinguish the low value 334-1 from the remaining values ​​333 and distinguish the high value 334-2 from the remaining values ​​333, such as Figure 3 As shown in Figure 3 The parameter values ​​are selected as described in .

[0050] At 445, a voltage-conductance point may be identified. The voltage-conductance point may be assigned to a plurality of parameter values ​​such that n l and n L Assigned to discernible conductivity levels, such as Figure 3 320 in . The identified voltage-conductance point may be used to update a previous voltage-conductance point (eg, a default value). For example, a register of an accelerator storing a previous voltage-conductance point may be updated using the identified voltage-conductance point to update the voltage-conductance point distribution.

[0051] In response to identifying the voltage-conductance point, the input model 406 may again be analyzed for error / accuracy at 442. A second iteration of 442 may be performed using the updated voltage-conductance point.l and n L The selection of and updating of the voltage-conductance points may be performed multiple times based on the accuracy of the input model 406 until a threshold of accuracy is reached.

[0052] Once the accuracy threshold is reached, a quantized model 446 may be generated. The quantized model 446 may include the same weights, biases, and / or activation functions as the input model 406, but may be stored in the MLC array of the MAC using updated voltage-conductance points. The voltage-conductance point distribution associated with the quantized model 446 may be stored in a register of the accelerator or in the main memory of the memory subsystem. Storing the updated voltage-conductance point distribution in the main memory allows the updated voltage-conductance points to be utilized without having to re-identify the updated voltage-conductance points the next time the input model 406 is implemented in the accelerator.

[0053] If the updated voltage-conductance point distribution is not stored, the quantized model 446 may exist during execution of the quantized model 446, but may cease to exist after execution of the quantized model 446. For example, the updated voltage-conductance point distribution may be used to store and read memory cells of an array of MAC units of an accelerator, but may not be available after execution of the quantized model 446, which would revert to the input model 406 because the voltage-conductance point distribution is not available.

[0054] Figure 5 is a flow chart corresponding to a method 580 for updating a voltage-conductance point distribution according to some embodiments of the present disclosure. In some examples, the method 580 may use a computing system (e.g., Figure 1 The computing system described herein is used to perform the above steps.

[0055] At 581, information corresponding to a memory array of the accelerator is received at the accelerator. For example, the memory array may be implemented in a MAC unit of the accelerator. The accelerator may be implemented in a memory subsystem. The accelerator may be coupled to a controller of the memory subsystem and a main memory (e.g., a memory array) of the memory subsystem. At 582, a plurality of parameters of the ANN may be received at the accelerator. The parameters of the ANN may include weights, biases, and / or activation functions of the ANN.

[0056] At 583, a voltage-conductance point may be identified at the accelerator using multiple parameters and based on information corresponding to a memory array. The voltage-conductance point may correspond to a subset of discernible conductance levels and multiple parameters. For example, the voltage-conductance point may associate a parameter with a conductance level. The conductance level may be discernible because the associated parameters may be accurately read and written to a memory array of a MAC unit of the accelerator. At 584, the ANN may be stored in the accelerator based on the discernible conductance level. Storing the ANN may include storing multiple parameters using the voltage-conductance point. Parameters of the ANN may also be read using the voltage-conductance point. For example, the ANN may be stored in a MAC unit of the accelerator and / or a memory array of the MAC unit.

[0057] A quantized profile corresponding to a plurality of parameters is generated based on the voltage-conductance point distribution. The quantized profile may include the voltage-conductance point distribution. The quantized profile may also map the voltage-conductance point distribution to the plurality of parameters.

[0058] The accuracy of the ANN may be analyzed using the sample set, the quantized profile, and the voltage-conductance point distribution. In response to determining that the accuracy of the ANN is greater than a threshold, the ANN may be stored in a memory array of the MAC unit using the voltage-conductance point distribution. In response to determining that the accuracy of the ANN is not greater than the threshold, different voltage-conductance points are identified using multiple parameters and based on information corresponding to the memory array.

[0059] In various examples, a controller of a memory subsystem may receive information corresponding to a plurality of memory arrays of a MAC unit. An accelerator of the memory subsystem may include a plurality of MAC units, each of the MAC units including one or more memory arrays. The controller may receive a plurality of parameters of an ANN. The parameters may be received from a main memory of the memory subsystem. The controller may utilize the plurality of parameters and identify a voltage-conductance point based on information corresponding to the plurality of memory arrays. The voltage-conductance point corresponds to a subset of discernible conductance levels and a plurality of parameters. Each of the parameters in the subset may be associated with a different one of the discernible conductance levels. The voltage-conductance point may be provided to the accelerator to store the ANN in the MAC unit based on the voltage-conductance point. The ANN may be stored in the MAC unit by storing the plurality of parameters in the memory array of the MAC unit.

[0060] The information of the memory array corresponding to the MAC unit includes the current-voltage characteristics of the memory array. The information may also include the operating temperature and / or operating voltage of the memory array.

[0061] The controller may also identify at least two or more voltage-conductance points corresponding to a distinguishable conductivity level group. The distinguishable conductivity level group may have a certain number of conductivity levels equal to a certain number of parameters from a subset of multiple parameters. The distinguishable conductivity level group corresponds to parameters with an occurrence rate below a threshold. The parameters with an occurrence rate below a threshold store an amount of information that affects the accuracy of the ANN above a different threshold. The occurrence rate may be the number of times a certain parameter (e.g., a parameter value) is included in the multiple parameters.

[0062] The controller may identify two or more voltage-conductance points corresponding to an indistinguishable conductivity level group. An indistinguishable conductivity level is a conductivity level used to store or read a corresponding parameter with an accuracy below a threshold. An indistinguishable conductivity level group is indistinguishable compared to at least one adjacent conductivity level. Adjacent conductivity levels are discernible conductivity levels. The indistinguishable conductivity levels may be grouped so that the distance between the conductivity levels causes an error when reading or storing data when used to read or store data in a memory cell. An indistinguishable conductivity level group corresponds to a parameter having an incidence rate above a threshold. For example, the most commonly used parameters may be associated with an indistinguishable conductivity level. Parameters having an incidence rate above a threshold store an amount of information that affects the accuracy of the ANN below a threshold (e.g., a different threshold).

[0063] In various examples, a voltage-conductance point distribution may be accessed. The accelerator may access the voltage-conductance point distribution from a register of the accelerator or from a main memory of a memory subsystem hosting the accelerator. The accelerator may receive a plurality of parameters for the ANN. The plurality of parameters may be received from a main memory of the memory subsystem. The accelerator may store the plurality of parameters in a memory array of a MAC unit of the accelerator. The accelerator may store the plurality of parameters in preparation for executing the ANN and generating inferences. The accelerator may read the plurality of parameters from the memory array using the voltage-conductance point distribution to interpret a signal received from reading the memory array. As part of executing the ANN, the accelerator may read the plurality of parameters.

[0064] The voltage-conductance point distribution may correspond to a parameter from a plurality of parameters represented using LSBs. The voltage-conductance point distribution may correspond to a parameter from a plurality of parameters represented using MSBs. The accelerator may determine the parameter represented using LSBs and MSBs.

[0065] Figure 6 is a block diagram of an example computer system 690 in which embodiments of the present disclosure may operate. For example, Figure 6 An example machine illustrating a computer system 690 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 690 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The computer system 690 may be used to perform the operations described herein (eg, to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, the Internet, and / or a wireless network. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0066] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0067] The example computer system 690 includes a processing device (e.g., a processor) 691, a main memory 693 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 697 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 698, which communicate with each other via a bus 696.

[0068] The processing device 691 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device 691 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 691 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 691 is configured to execute instructions 692 for performing the operations and steps discussed herein. The computer system 690 may further include a network interface device 694 for communicating over a network 695.

[0069] The data storage system 698 may include a machine-readable storage medium 699 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 692 or software embodying any one or more of the methodologies or functionality described herein. The instructions 692 may also reside, completely or at least partially, within the main memory 693 and / or within the processing device 691 during execution by the computer system 690, the main memory 693 and the processing device 691 also constituting machine-readable storage media. The machine-readable storage medium 699, the data storage system 698, and / or the main memory 693 may correspond to Figure 1 Memory subsystem 111.

[0070] In one embodiment, instructions 692 include instructions for (e.g., using Figure 1 The quantized circuit system of the present invention (or the quantized circuit system of the present invention) implements the instructions corresponding to the functionality of the examples described herein. Although the machine-readable storage medium 699 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0071] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Mainly for common purposes, it sometimes proves convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0072] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0073] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0074] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures of a variety of these systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0075] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0076] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for updating the voltage-conductance point distribution of an artificial neural network, comprising: Receiving, at an accelerator (109), information (108, 408) corresponding to a memory array (113) of the accelerator; Receiving a plurality of parameters of an artificial neural network ANN (106, 406) at the accelerator; identifying a voltage-conductance point distribution (107) at the accelerator using the plurality of parameters and based on the information corresponding to the memory array, wherein the voltage-conductance point distribution corresponds to a subset of discernible conductance levels (223-1, 223-2, 223-3, 223-4, 223-5, 223-6, 223-7, 223-8) and the plurality of parameters; and The ANN is stored in the accelerator based on the discernible conductivity level.

2. The method of claim 1, further comprising generating a quantized profile corresponding to the plurality of parameters based on the voltage-conductance point distribution.

3. The method of claim 2, further comprising analyzing the accuracy of the ANN using a sample set, the quantized profile, and the voltage-conductance point distribution.

4. The method of claim 3, further comprising, in response to determining that the accuracy of the ANN is greater than a threshold, utilizing the voltage-conductance point distribution to store the ANN in the memory array of a MAC unit (112) of the accelerator.

5. The method of claim 3, further comprising identifying, in response to determining that the accuracy of the ANN is not greater than a threshold, utilizing the plurality of parameters and based on the information corresponding to the memory array a different voltage-conductance point distribution (107).

6. A device for updating the voltage-conductance point distribution of an artificial neural network, comprising: An accelerator (109) comprising a multiply-and-accumulate MAC unit (112) having a plurality of memory arrays (113); A controller (114) coupled to the accelerator and configured to: receiving information corresponding to the plurality of memory arrays of the MAC unit (108, 408); receiving a plurality of parameters of an artificial neural network ANN (106, 406); identifying a voltage-conductance point distribution (107) using the plurality of parameters and based on the information corresponding to the plurality of memory arrays, wherein the voltage-conductance point distribution corresponds to a subset of discernible conductance levels (223-1, 223-2, 223-3, 223-4, 223-5, 223-6, 223-7, 223-8) and the plurality of parameters; and The voltage-conductance point distribution is provided to the accelerator to store the ANN in the MAC unit based on the voltage-conductance point distribution.

7. The apparatus of claim 6, wherein the information corresponding to the memory array of the MAC unit includes one or more of a group of characteristics including: Current-voltage characteristics (441-1) of the memory array; the operating temperature of the memory array (441-2); and The operating voltage (441-3) of the memory array.

8. The apparatus of claim 6, wherein the controller is further configured to identify two or more voltage-conductance points corresponding to at least a discernible group of conductance levels (224).

9. The apparatus of claim 8, wherein the discernible groups of conductivity levels correspond to parameters having an occurrence rate below a threshold.

10. The apparatus of claim 9, wherein the parameters having the incidence below the threshold hold an amount of information that affects the accuracy of the ANN above a different threshold.

11. The apparatus of any one of claims 6 to 10, wherein the controller is further configured to identify two or more voltage-conductance points (224) corresponding to a group of indistinguishable conductance levels (223-1, 223-2, 223-3, 223-4, 223-5, 223-6, 223-7, 223-8).

12. The apparatus of claim 11, wherein the group of indistinguishable electrical conduction levels are indistinguishable from at least one adjacent electrical conduction level.

13. The apparatus of claim 11, wherein the group of indistinguishable electrical conduction levels corresponds to parameters having an occurrence rate above a threshold.

14. The apparatus of claim 13, wherein the parameters having the incidence above the threshold hold an amount of information that affects the accuracy of the ANN below a different threshold.

15. A non-transitory machine-readable medium having computer-readable instructions for updating a voltage-conductance point distribution of an artificial neural network, the computer-readable instructions, when executed by a computer, cause the computer to: Access voltage-conductance point distribution (107); receiving a plurality of parameters of an artificial neural network ANN (106, 406); storing the plurality of parameters in a memory array (113) of a multiply and accumulate MAC unit (112) of the accelerator (109); and The plurality of parameters are read from the memory array using the voltage-conductance point distribution to interpret signals received from reading the memory array.

16. The non-transitory machine-readable medium of claim 15, wherein the voltage-conductance point distribution corresponds to a parameter from the plurality of parameters represented using: LSB; or Most significant bit MSB.

17. The non-transitory machine-readable medium of claim 16, wherein the instructions are further executable to determine the parameter represented using LSBs and MSBs.

Images