Clamping circuit and in-memory computing device

Abstract

Embodiments of this disclosure provide a clamping circuit and an in-memory computing device. The clamping circuit includes a clamping branch module, an amplifier module, a feedforward sampling module, and a feedback sampling module. The feedback sampling module is configured to sample a first voltage difference between a clamping reference voltage and an ideal clamping voltage received in a first operating state to generate a feedback output. The amplifier module is configured to amplify the feedback output received from the feedback sampling module and output it to the feedforward sampling module. The feedforward sampling module is configured to sample a second voltage difference between the voltage at the output of the amplifier module and the first reference voltage to generate a feedforward output. The clamping branch module is configured to clamp the clamping node to the ideal clamping voltage according to the feedforward output in a second operating state. This clamping circuit can eliminate quiescent current errors caused by input voltage offset and voltage mismatch in the clamping mechanism itself.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a clamping circuit and a memory computing device. Background Technology

[0002] Analog In-Memory Computation (CIM) based on resistive switching memory cell arrays has shown great potential for accelerating high-performance neural network hardware. By storing network weights with non-volatile adjustable conductance based on the device and applying voltage pulses representing the input values, matrix-vector multiplication results represented by analog current values ​​can be obtained. To achieve high parallelism with multi-bit input, the CIM array requires numerous analog voltage drive circuits to apply input voltages to the bit lines (BL) of the CIM array. Simultaneously, the readout circuitry needs to precisely clamp the connected source lines (SL), ultimately quantizing the current on the source lines to obtain accurate matrix multiplication and addition results. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a clamping circuit, including: a clamping branch module, an amplifier module, a feedforward sampling module, and a feedback sampling module, wherein the feedback sampling module is coupled to the clamping branch module and a clamping node, and the feedback sampling module is configured to sample a first voltage difference between a clamping reference voltage and an ideal clamping voltage received in a first operating state to generate a feedback output, wherein the ideal clamping voltage is a floating voltage; the input terminal of the amplifier module is coupled to the feedback sampling module, the output terminal of the amplifier module is coupled to the feedforward sampling module, and the amplifier module is configured to amplify the feedback output received from the feedback sampling module and output it to the feedforward sampling module; the feedforward sampling module is coupled to the clamping branch module and is configured to sample a second voltage difference between the voltage at the output terminal of the amplifier module and the first reference voltage to generate a feedforward output, and provide the feedforward output to the clamping branch module; the clamping branch module is configured to clamp the clamping node to the ideal clamping voltage according to the feedforward output in a second operating state.

[0004] For example, at least one embodiment of this disclosure provides a clamping circuit that further includes: a first reference voltage generation module, coupled to the feedforward sampling module via a third node, coupled to the feedback sampling module via the clamping node, and configured to generate the first reference voltage.

[0005] For example, in at least one embodiment of this disclosure, a clamping circuit is provided, wherein the first reference voltage generating module includes a first current generating unit, a second current generating unit, and a second transistor, wherein the control terminal of the second transistor is coupled to a first terminal of the second transistor, and the control terminal of the second transistor is coupled to the feedforward sampling module through the third node; the first current generating unit is coupled to a second terminal of the second transistor through the clamping node and is configured to generate a first current; and the second current generating unit is coupled to a first terminal of the second transistor and is configured to generate a second current, wherein the second current is equal to the first current.

[0006] For example, in at least one embodiment of this disclosure, a clamping circuit is provided, wherein the clamping branch module includes a third current generating unit and a first transistor, the control terminal of the first transistor is coupled to the feedforward sampling module through a first node, and the second terminal of the first transistor is coupled to the feedback sampling module through a second node; the third current generating unit is coupled to the second terminal of the first transistor and is configured to generate a third current, wherein the ratio of the third current to the first current is equal to the ratio of the width-to-length ratio of the first transistor to the width-to-length ratio of the second transistor, and the gate length of the first transistor is equal to the gate length of the second transistor.

[0007] For example, in at least one embodiment of this disclosure, a clamping circuit is provided, wherein the feedback sampling module includes a first switch, a third switch, and a first capacitor, and the feedforward sampling module includes a second switch and a second capacitor. According to the closed state of the first switch, the second switch, and the third switch, the first capacitor samples the first voltage difference, and the second capacitor samples the second voltage difference.

[0008] For example, in at least one embodiment of this disclosure, a clamping circuit is provided in which the amplifier module includes a differential amplifier or a single-ended amplifier.

[0009] For example, in at least one embodiment of this disclosure, a clamping circuit is provided in which the positive input terminal of the differential amplifier is coupled to a first terminal of the first switch and configured to receive the clamping reference voltage, the negative input terminal of the differential amplifier is coupled to a second terminal of the first switch, and the output terminal of the differential amplifier is coupled to a first terminal of the second capacitor.

[0010] For example, in at least one embodiment of this disclosure, a clamping circuit is provided in which the single-ended amplifier includes a first resistor, a third transistor, and a fifth transistor. The control terminal of the third transistor is coupled to the second terminal of the first switch, the first terminal of the third transistor is coupled to the second terminal of the fifth transistor, the first terminal of the fifth transistor is coupled to the first resistor, and the first terminal of the fifth transistor serves as the output terminal of the amplifier module and is coupled to the first terminal of the second capacitor.

[0011] For example, in at least one embodiment of this disclosure, a clamping circuit is provided, the clamping circuit further comprising a second reference voltage generating module, the second reference voltage generating module being coupled to a first terminal of the second switch and configured to provide the clamping reference voltage.

[0012] For example, in at least one embodiment of this disclosure, a clamping circuit is provided in which the second reference voltage generating module includes a fourth current generating unit, a fourth transistor, and a sixth transistor. The fourth current generating unit is coupled to a first terminal of the sixth transistor and configured to generate a fourth current. The second terminal of the sixth transistor is coupled to the first terminal of the fourth transistor. The control terminal of the fourth transistor is coupled to the first terminal of the sixth transistor and is coupled to the first terminal of the first switch. The ratio of the current flowing through the third transistor to the fourth current is equal to the ratio of the width-to-length ratio of the fourth transistor to the width-to-length ratio of the third transistor, and the gate length of the fourth transistor is equal to the gate length of the third transistor.

[0013] For example, at least one embodiment of this disclosure provides a clamping circuit that further includes a low-resistance path module and a fourth switch, wherein a first terminal of the low-resistance path module and the fourth switch is coupled to the clamping node, and the low-resistance path module is configured to provide the ideal clamping voltage to the clamping node when the fourth switch is closed.

[0014] At least one embodiment of this disclosure also provides an in-memory computing device, including: a memristor array, an input circuit, and an output circuit, wherein the output circuit includes a plurality of clamping circuits as described in any of the above embodiments, the input circuit is coupled to the memristor array and configured to provide a plurality of input voltages to the memristor array, the memristor array is coupled to a plurality of clamping circuits through a plurality of clamping nodes of the plurality of clamping circuits respectively, and is configured to provide the floating voltage to the plurality of clamping circuits respectively as the ideal clamping voltage when the plurality of input voltages are zero. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0016] Figure 1 This illustrates a current-mode in-memory computing circuit structure;

[0017] Figure 2 A self-zeroing input drive and clamping structure is shown;

[0018] Figure 3A A schematic diagram of a clamping circuit provided in at least one embodiment of this disclosure is shown;

[0019] Figure 3B A schematic diagram of another clamping circuit provided in at least one embodiment of this disclosure is shown;

[0020] Figure 4 A schematic diagram of a clamping circuit based on differential amplification provided in at least one embodiment of this disclosure is shown;

[0021] Figure 5 This disclosure shows a schematic diagram of a clamping circuit based on single-ended amplification according to at least one embodiment; and

[0022] Figure 6 A schematic diagram of the structure of an in-memory computing device provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0024] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0025] Memristors (such as resistive switching memory cells, phase-change memory cells, and conductive bridge memory cells) are non-volatile devices whose conductance can be adjusted by applying an external stimulus. As a two-terminal device, memristors have the characteristics of adjustable and non-volatile resistance, and are therefore widely used in in-memory computing (or in-memory arithmetic).

[0026] Analog in-memory computing (CIM) based on resistive switching memory cell arrays has shown great potential in accelerating high-performance neural network hardware. By using the non-volatile adjustable conductivity memory network weights of the device and applying voltage pulses representing the input values, the matrix-vector multiplication results represented by analog current values ​​can be obtained.

[0027] However, due to factors such as process variations and layout parasitic effects, a large amount of offset voltage caused by mismatch exists in the circuit. For example, under the influence of mismatch, the unity-gain buffers used in the bit line (BL) drive circuit and the source line (SL) clamp circuit exhibit a deviation between the actual output voltage and the ideal voltage of the reference input, resulting in errors between the calculated and ideal results. To address the mismatch problem, dynamic self-calibration or static calibration can be used to separately calibrate the error of the clamping current on the BL drive circuit and the source line. However, the additional overhead of the calibration circuit leads to a decrease in computational density, and frequent calibration refreshes cause a decrease in system efficiency.

[0028] For example, Figure 1 A current-mode in-memory computing circuit structure is shown.

[0029] like Figure 1As shown, the weights are stored in the memristor array in the form of the conductance G[i,j] of the storage cells (also called "memristors" or "weight cells"). The storage cells can be 2T2R or 1T1R structures. A 1T1R weight cell includes one switching transistor and one memristor, while a 2T2R weight cell includes two switching transistors and two memristors. For example, a 2T2R structure can be arranged as a differential type to characterize positive and negative weight values. For example, memristors can be resistive random access memory, phase-change memory, or bridge memory, and are non-volatile devices whose conductance can be adjusted.

[0030] like Figure 1 As shown, the digital-to-analog converter (DAC) applies an analog voltage VCM+VIN[i] representing the input data to the bit line BL[i] of the memristor array (e.g., set horizontally), while the source line SL of the memristor array (e.g., set vertically) is clamped to a fixed voltage VCM. With all zeros input (i.e., VIN[i] = 0), the voltage difference across all memory cells in the memristor array is zero, and current flows through the source line SL. After applying the input voltage VIN[i], the current on SL[j] represents the result of the matrix multiplication operation:

[0031]

[0032] This represents the result of vector dot product, and the current is ultimately quantized and read out by the readout circuit to obtain the calculation result.

[0033] However, due to process variations and layout parasitic effects, circuit mismatch issues exist, leading to static deviations between the input voltage of BL and the clamping voltage of SL and their ideal values. For example, ... Figure 1 As shown, the analog voltage output by the DAC changes from VCM+VIN[i] to VCM+VIN[i]+ΔV[i], while the clamping voltage on SL changes to VCM+ΔVC[j]. Due to the circuit mismatch problem, in the case of all-zero input (i.e., VIN[i]=0), the current of SL[j] is no longer the ideal zero current, but rather:

[0034]

[0035] Subsequently, when the input voltage is applied, according to the linear current superposition theorem, there will always be a static error ΔI between the actual current and the ideal current on SL. SL[j] .

[0036] To eliminate mismatches in in-memory computing circuits, for example, one can use... Figure 2 The self-zeroing input drive and clamping structure shown is used to eliminate input mismatch errors in unity-gain buffers used for input drive and SL clamping in in-memory computing circuits.

[0037] First, switches SW.1 and SW.2 are closed, and switch SW.3 is open, sampling the mismatch between the positive and negative inputs across zero-adjustment capacitor C1. Then, switch SW.1 is opened to end sampling. Afterward, switch SW.2 is opened and switch SW.3 is closed, compensating the sampled mismatch voltage in the loop so that the amplifier output voltage (the voltage applied to bit line BL) is the ideal voltage. Based on a similar principle, the clamping voltage on the source line SL can be the ideal clamping voltage.

[0038] The inventors of this disclosure have noted that high-parallelism in-memory computing arrays require a large number of input drive circuits, which in turn require a large number of self-zeroing input drivers and clamping structures. The use of zeroing capacitors reduces circuit density, thereby leading to a decrease in computational density. Furthermore, due to leakage current in the zeroing capacitors, the in-memory computing circuits need to be refreshed frequently, resulting in a decrease in system efficiency.

[0039] To address the above shortcomings, one or more embodiments of this disclosure propose a clamping circuit and a memory computing device including the clamping circuit.

[0040] The clamping circuit of at least one embodiment of this disclosure includes: a clamping branch module, an amplifier module, a feedforward sampling module, and a feedback sampling module. The feedback sampling module is coupled to the clamping branch module and the clamping node, and is configured to sample a first voltage difference between a clamping reference voltage and an ideal clamping voltage received in a first operating state phase to generate a feedback output, wherein the ideal clamping voltage is a floating voltage. The input terminal of the amplifier module is coupled to the feedback sampling module, and the output terminal of the amplifier module is coupled to the feedforward sampling module. The amplifier module is configured to amplify the feedback output received from the feedback sampling module and output it to the feedforward sampling module. The feedforward sampling module is coupled to the clamping branch module and is configured to sample a second voltage difference between the voltage at the output terminal of the amplifier module and the first reference voltage to generate a feedforward output, and to provide the feedforward output to the clamping branch module. The clamping branch module is configured to clamp the clamping node to the ideal clamping voltage according to the feedforward output in a second operating state.

[0041] This clamping circuit adaptively changes the clamping voltage of SL, so that the current of SL is 0 when all inputs are zero. This eliminates the static current error caused by input voltage misalignment and the voltage mismatch of the clamp itself, improving robustness to input circuit mismatch and thus improving system efficiency and density.

[0042] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0043] Figure 3A A schematic diagram of a clamping circuit provided in at least one embodiment of the present disclosure is shown.

[0044] like Figure 3A As shown, the clamping circuit includes: a clamping branch module 310, an amplifier module 320, a feedforward sampling module 330, and a feedback sampling module 340. The feedback sampling module 340 is coupled to the clamping branch module 310 and the clamping node SLC, and is configured to sample a first voltage difference between the clamping reference voltage and the ideal clamping voltage (hereinafter referred to as "V_SLC") received by the feedback sampling module 340 from the clamping node SLC during a first operating phase to generate a feedback output. The input of the amplifier module 320 is coupled to the feedback sampling module 340, and the output of the amplifier module 320 is coupled to the feedforward sampling module 330. The amplifier module 320 is configured to amplify the feedback output received from the feedback sampling module 340 and output it to the feedforward sampling module 330. The feedforward sampling module 330 is coupled to the clamping branch module 310 and configured to sample the second voltage difference between the voltage at the output terminal AOUT of the amplifier module 320 and the first reference voltage to generate a feedforward output, and to provide the feedforward output to the clamping branch module 310. The clamping branch module 310 is configured in a second operating state to clamp the clamping node SLC to the ideal clamping voltage according to the feedforward output.

[0045] In the embodiments of this disclosure, the first operating state is a sampling stage, in which the external array provides an ideal clamping voltage to the feedback sampling module 340 through the clamping node; the second operating state is a clamping operating state, in which the clamping branch 310 clamps the clamping node SLC to the ideal clamping voltage. The ideal clamping voltage is a floating voltage, that is, the voltage of the external array's bit line BL with all zeros input and the source line SL in a floating state. The feedback sampling module 340 is also configured to receive the clamping reference voltage VCM.

[0046] For example, the amplifier module 320 described above may include a differential amplifier (such as...) Figure 3A (as shown) or single-ended amplifier (such as Figure 3B (As shown). When the amplifier module 320 includes a differential amplifier, the positive input terminal of the amplifier module 320 receives the clamping reference voltage VCM, and the negative input terminal receives the feedback output from the feedback sampling module 340.

[0047] Figure 3B A schematic diagram of another clamping circuit provided in at least one embodiment of this disclosure is shown. For example... Figure 3B As shown, amplifier module 320 includes a single-ended amplifier, and the input of amplifier module 320 receives the feedback output from feedback sampling module 340. Figure 3B The structure and function of the clamping branch module, feedforward sampling module, and feedback sampling module in the clamping circuit shown can be referred to Figure 3A The clamping branch module 310, feedforward sampling module 330 and feedback sampling module 340 shown will not be described in detail here.

[0048] Figure 4 A schematic diagram of a differential amplification-based clamping circuit is shown, according to at least one embodiment of the present disclosure.

[0049] like Figure 4 As shown, the clamping circuit 400 includes a clamping branch module 410, a feedforward sampling module 430, a feedback sampling module 440, and an amplifier module 420, wherein the amplifier module 420 includes a differential amplifier.

[0050] like Figure 4 As shown, the clamping circuit 400 also includes a reference voltage generation module G1, which is coupled to the feedforward sampling module 430 via node N3 and to the feedback sampling module 440 via clamping node SLC. The reference voltage generation module G1 is configured to generate a reference voltage REFG and provide it to the feedforward sampling module 430.

[0051] For example, the reference voltage generation module G1 includes a current generation unit I.G1, a current generation unit I.G2, and a transistor NM2. The control terminal (e.g., gate) of transistor NM2 is coupled to a first terminal (e.g., source) of transistor NM2, and the control terminal of transistor NM2 is coupled to the feedforward sampling module 430 via node N3. Current generation unit I.G1 is coupled to a second terminal (e.g., drain) of transistor NM2 via a clamping node SLC and is configured to generate a first current I1. Current generation unit I.G2 is coupled to the first terminal (e.g., source) of transistor NM2 and is configured to generate a second current I2, wherein the second current I2 is equal to the first current I1.

[0052] For example, clamping branch module 410 includes a current generation unit I.C1 and a transistor NM1. The control terminal (e.g., gate) of transistor NM1 is coupled to feedforward sampling module 430 via node N1, and the second terminal (e.g., source) of transistor NM1 is coupled to feedback sampling module 440 via node N2. The current generation unit I.C1 is coupled to the second terminal of transistor NM1 via node N2 and is configured to generate a third current I3. The ratio of the third current I3 to the first current I1 is equal to the ratio of the width-to-length ratio of transistor NM1 to the width-to-length ratio of transistor NM2, i.e., I3 / I2 = (W / L). NM1 / (W / L) NM2 Furthermore, the gate length of transistor NM1 is equal to the gate length of transistor NM2.

[0053] It is important to note the matching relationship between the clamping branch and the reference voltage generation module G1 (i.e., I3 / I2 = (W / L)). NM1 / (W / L) NM2 And the gate length of the first transistor NM1 is equal to the gate length of the second transistor NM2), the first reference voltage REFG is the ideal clamping gate voltage that makes the voltage at the second terminal (i.e. the source) of the transistor NM1 equal to the ideal clamping voltage V_SLC.

[0054] For example, the feedback sampling module 440 includes switches SW.1 and SW.3 and capacitor C1, and the feedforward sampling module 430 includes switch SW.2 and capacitor C2. Based on the closed states of switches SW.1, SW.2, and SW.3, capacitor C1 samples the first voltage difference, and capacitor C2 samples the second voltage difference. As mentioned earlier, the first voltage difference is the voltage difference between the clamping reference voltage VCM and the ideal clamping voltage V_SLC received by the feedback sampling module 340 from the clamping node SLC during the first operating phase; the second voltage difference is the voltage difference between the output terminal AOUT of the amplifier module 320 and the first reference voltage REFG.

[0055] For example, the positive input of differential amplifier 420 is coupled to the first terminal of switch SW.1 and is configured to receive clamp reference voltage VCM, the negative input of differential amplifier is coupled to the second terminal of switch SW.1, and the output terminal AOUT of differential amplifier is coupled to the first terminal of capacitor C2.

[0056] For example, the clamping circuit 400 may further include a low-impedance path module 450 and a switch SW.4. The first terminals of the low-impedance path module 450 and the switch SW.4 are coupled to the clamping node SLC, and the low-impedance path module 450 is configured to provide an ideal clamping voltage V_SLC to the clamping node SLC when the switch SW.4 is closed. The second terminal of the switch SW.4 is coupled to the source line SL of a memristor array (e.g., a resistive random access memory (RRAM) array 460). For example, the switch SW.4 may be a high-voltage switch.

[0057] For example, the low-resistance path module 450 includes a switch SW.5 and a resistor R2. The first terminal of the switch SW.5 is equipped with a clamping reference voltage VCM. The second terminal of the switch SW.5 is coupled to the first terminal of the resistor R2. The second terminal of the resistor R2 is coupled to the first terminal of the switch SW.4. That is, the second terminal of the resistor R2 is coupled to the clamping node SLC.

[0058] In the clamping circuit provided in the above embodiments of this disclosure, based on the low-resistance path module 4 controlled by switch SW.5, the problem of unstable floating voltage on the source line and slow charging speed of capacitor C1 caused by the memory cells in the RRAM array 460 being in an unformed (or initialized or preprocessed) state (i.e., unformed state) or a state where most devices are high-resistance can be avoided. Figure 4 and Figure 5 A low-impedance path controlled by SW.4 was added to the structure and connected to VCM to provide the ideal clamping voltage VCM when the array is a high-impedance load.

[0059] When multiple memory cells in the RRAM array 460 are in an unformed state, switch SW.5 is closed, and the source line voltage SL of the RRAM array 460 is clamped to the clamping reference voltage VCM. At this time, due to the input circuit ( Figure 4 Not shown in the image, please refer to the following: Figure 6 There is a mismatch, and a fixed current deviation still exists on the source line SL. Therefore, during the programming verification process, the output circuit ( Figure 4 Not shown in the image, please refer to the following: Figure 6 First, read the current I under the condition of all zero input. OS Then, read the current I after applying the read voltage to the memory cell corresponding to the programmed row. DAT Then, the actual cell current (i.e., the current passing through the storage cell) under the ideal read voltage is I. DAT -I OS Iterative programming and reading verification are performed based on the actual unit current.

[0060] After multiple memory cells are shaped, the load impedance of the RRAM array 460 becomes low. At this time, clamping the source line SL voltage to the clamping reference voltage VCM will cause excessive deviation current, resulting in range saturation of the analog-to-digital converter (ADC) and reducing the ADC dynamic range. Therefore, switch SW.5 is opened, and the voltage of the source line SL after the array is floating is used as the ideal clamping voltage, after which clamping and quantization can be performed normally.

[0061] It is important to note that Figure 4 The clamping reference voltage VCM is the zero input voltage under no mismatch conditions, and it is also the input voltage at the positive input terminal of the differential amplifier 420.

[0062] For example, the operation of the clamping circuit 400 when reading the source line current of the RRAM array 460 is as follows.

[0063] In the first operating state phase: the RRAM array 460 is in computation mode, switch SW.5 is closed, and all bit lines BL of the array are 0 inputs (i.e., Figure 1 (VIN[i] = 0). Switches SW.1 and SW.2 are closed, and switch SW.3 is open. The source line SL of the RRAM array 460 is coupled only to the reference voltage generation module G1. The current generated by the current generation unit I.G1 is equal to the current generated by the current generation unit I.G2. The source line SL is in a floating state. The voltage on the source line SL is used as the ideal clamping voltage V_SLC so that the current on the source line SL is 0 when all inputs of BL are 0. At this time, capacitor C1 in the feedback sampling module 440 samples the voltage difference (i.e., the first voltage difference) between the clamping reference voltage VCM and the ideal clamping voltage V_SLC. At the same time, capacitor C2 in the feedforward sampling module 430 samples the voltage difference (i.e., the second voltage difference) between the voltage at the output terminal AOUT of the differential amplifier 420 and the reference voltage REFG.

[0064] In the second operating phase: Switch SW.1 is first opened, and after a period of time (i.e., after the voltage at the output terminal AOUT of the differential amplifier 420 stabilizes), switch SW.2 is opened, and capacitors C1 and C2 stop sampling sequentially. Then switch SW.3 is closed, establishing a closed loop, for example, between the feedforward sampling module 430, the clamping branch module 410, the feedback sampling module 440, and the amplifier module 420 (a schematic diagram of the closed loop can also be found). Figure 3A At this point, the voltage of the clamping node SLC is clamped to the ideal clamping voltage V_SLC.

[0065] In the third working state stage: multiple rounds of reading and calculation are performed. Until capacitors C1 and C2 leak current, C1 and C2 are refreshed, and the process returns to the first working state stage to resample.

[0066] In the above embodiments, the clamping circuit 400 eliminates the deviation between the clamping reference voltage VCM (i.e., the actual clamping voltage) and the ideal clamping voltage V_SLC through the feedback sampling module (e.g., the sampling operation of capacitor C1), thereby eliminating the effect of input (drive) circuit mismatch; and eliminates the deviation between the output voltage of the amplifier module and the standard clamping gate voltage REFG through the feedforward sampling module (e.g., the sampling operation of capacitor C2), thereby eliminating the mismatch of the clamping structure itself.

[0067] Figure 5 A schematic diagram of a clamping circuit based on single-ended amplification provided in at least one embodiment of this disclosure is shown.

[0068] like Figure 5 As shown, the clamping circuit 500 includes a clamping branch module 510, a feedforward sampling module 530, a feedback sampling module 540, an amplifier module 520, and a reference voltage generation module G1. The amplifier module 520 includes a single-ended amplifier, and the matching relationship between the clamping branch module 510 and the reference voltage generation module G1 is... Figure 4 The matching relationship between the clamping branch module 410 and the reference voltage generation module G1 is the same.

[0069] For example, a single-ended amplifier includes a resistor R1, a transistor NM3, and a control terminal of transistor NM3 coupled to the second terminal NBIAS of switch SW.1. The first terminal of transistor NM3 is coupled to the second terminal of transistor NM3, and the first terminal of transistor NM3 is coupled to resistor R1. The first terminal of transistor NM5 in amplifier module 520 serves as the output terminal AOUT of amplifier module 520 and is coupled to the first terminal of capacitor C2 of feedforward sampling module 530.

[0070] For example, the clamping circuit 500 also includes a reference voltage generation module G2, which is coupled to the first terminal of the switch SW.1 in the feedback sampling module 540 and is configured to provide a clamping reference voltage REFB (equivalent to Figure 3A , Figure 3B and Figure 4 (Clamping reference voltage VCM in the middle).

[0071] For example, the reference voltage generation module G2 includes a current generation unit I.B1, a transistor NM4, and a transistor NM6. The current generation unit I.B1 is coupled to the first terminal of transistor NM6 and configured to generate a fourth current I4. A terminal of transistor NM6 is coupled to the first terminal of transistor NM4. Both the control terminal of transistor NM4 and the first terminal of transistor NM6 are coupled to the first terminal of switch SW.1 in the feedback sampling module 540. The ratio of the current flowing through transistor NM3 to the fourth current I4 is equal to the ratio of the width-to-length ratio of transistor NM4 to the width-to-length ratio of transistor NM3, i.e., I(NM3) / I4 = (W / L). NM3 / (W / L) NM4 =k, and the gate length of transistor NM4 is equal to the gate length of transistor NM3.

[0072] In addition, for Figure 5 The structure and function of other modules in the clamping circuit 500 shown, such as clamping branch module 510, feedforward sampling module 530, feedback sampling module 540, and reference voltage generation module G1, can be referred to the above. Figure 4The clamping branch module 410, feedforward sampling module 430, feedback sampling module 440 and reference voltage generation module G1 in the clamping circuit 400 shown will not be described in detail here.

[0073] For example, the operation of clamp circuit 500 when reading source line current of RRAM array 560 is as follows.

[0074] In the first operating state phase: the RRAM array 560 is in computation mode, switch SW.5 is closed, and all bit lines BL of the array are 0 inputs (i.e., Figure 1 (VIN[i] = 0). Switches SW.1 and SW.2 are closed, and switch SW.3 is open. The source line SL of the RRAM array 560 is only coupled to the reference voltage generation module G1. The current generated by the current generation unit I.G1 is equal to the current generated by the current generation unit I.G2. The source line SL is in a floating state. The voltage on the source line SL is used as the ideal clamping voltage V_SLC so that the current on the source line SL is 0 when all inputs of BL are 0. At this time, the first reference voltage REFG is the ideal clamping gate voltage that makes the source voltage of transistor NM1 V_SLC. The clamping reference voltage REFB is equivalent to Figure 3A , Figure 3B and Figure 4 The clamping reference voltage VCM is used in the feedback sampling module 540. The capacitor C1 samples the voltage difference (i.e., the first voltage difference) between the clamping reference voltage REFB and the ideal clamping voltage V_SLC. At the same time, the capacitor C2 of the feedforward sampling module 530 samples the voltage difference (i.e., the second voltage difference) between the voltage at the output terminal AOUT of the single-ended common source amplifier 520 and the first reference voltage REFG.

[0075] In the second operating phase: Switch SW.1 is open. After a period of time (i.e., after the voltage at the output terminal AOUT of the single-ended common-source amplifier 520 stabilizes), switch SW.2 is opened, and capacitors C1 and C2 stop sampling sequentially. Then switch SW.3 is closed, establishing a closed loop, for example, between the feedforward sampling module 530, the clamping branch module 510, the feedback sampling module 540, and the amplifier module 520 (a schematic diagram of the closed loop can also be found). Figure 3B At this time, the voltage of the clamping node SLC is clamped to the ideal clamping voltage V_SLC. The gate voltage of transistor NM3 (i.e. the voltage at node N1) still maintains the clamping reference voltage REFB under the action of the closed loop. The current flowing through transistor NM3 satisfies the relationship I(NM3)=k×I4.

[0076] In the third working state stage: multiple rounds of reading and calculation are performed. Until capacitors C1 and C2 leak current, C1 and C2 are refreshed, and the process returns to the first working state stage to resample.

[0077] In the above embodiments, the clamping circuit 500 eliminates the deviation between the clamping reference voltage REFB (i.e., the actual clamping voltage) and the ideal clamping voltage V_SLC through the feedback sampling module 540 (e.g., the sampling operation of capacitor C1), thereby eliminating the effect of input (drive) circuit mismatch; and eliminates the deviation between the output voltage of the amplifier module 520 and the standard clamping gate voltage REFG through the feedforward sampling module 530 (e.g., the sampling operation of capacitor C2), thereby eliminating the mismatch of the clamping structure itself.

[0078] Figure 6 A schematic diagram of the structure of an in-memory computing device provided in at least one embodiment of the present disclosure is shown.

[0079] like Figure 6 As shown, the in-memory computing device 600 includes a memristor array, an input circuit, and an output circuit, wherein the output circuit (such as...) Figure 5 The "clamping / readout circuit" includes multiple such circuits. Figure 3A , Figure 3B , Figure 4 or Figure 5 The clamping circuit is shown. The input circuit is coupled to the memristor array and configured to provide multiple input voltages to the memristor array. The memristor array is coupled to multiple clamping circuits via multiple clamping nodes and is configured to provide floating voltages to the multiple clamping circuits as ideal clamping voltages when the multiple input voltages are zero. The multiple clamping circuits sample this ideal clamping voltage and clamp the source line SL of the memristor array to this ideal clamping voltage under any calculated load condition via a feedback sampling module.

[0080] For example, the in-memory computing device in any embodiment of this disclosure can be used to implement a data processing device, such as to prepare a neural network processor chip, or to cooperate with a central processing unit as a coprocessor to achieve data processing functions, etc. This disclosure does not limit it.

[0081] In addition to the illustrative examples described above, the following points also need to be noted:

[0082] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0083] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0084] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A clamping circuit, comprising: The system includes a clamping branch module, an amplifier module, a feedforward sampling module, a feedback sampling module, a low-impedance path module, and a fourth switch. The feedback sampling module is coupled to the clamping branch module and the clamping node, and the feedback sampling module is configured to sample the first voltage difference between the clamping reference voltage and the ideal clamping voltage received in the first operating state phase to generate a feedback output, wherein the ideal clamping voltage is a floating voltage. The input terminal of the amplifier module is coupled to the feedback sampling module, the output terminal of the amplifier module is coupled to the feedforward sampling module, and the amplifier module is configured to amplify the feedback output received from the feedback sampling module and output it to the feedforward sampling module. The feedforward sampling module is coupled to the clamping branch module and is configured to sample the second voltage difference between the voltage at the output of the amplifier module and the first reference voltage to generate a feedforward output, and to provide the feedforward output to the clamping branch module. The clamping branch module is configured to clamp the clamping node to the ideal clamping voltage according to the feedforward output in the second operating state. The low-impedance path module and the first terminal of the fourth switch are coupled to the clamping node, and the low-impedance path module is configured to provide the ideal clamping voltage to the clamping node when the fourth switch is closed; the second terminal of the fourth switch is coupled to the source line of the memristor array.

2. The clamping circuit as described in claim 1 further includes: The first reference voltage generation module is coupled to the feedforward sampling module through the third node, coupled to the feedback sampling module through the clamping node, and is configured to generate the first reference voltage.

3. The clamping circuit as described in claim 2, wherein, The first reference voltage generation module includes a first current generation unit, a second current generation unit, and a second transistor. The control terminal of the second transistor is coupled to the first terminal of the second transistor, and the control terminal of the second transistor is coupled to the feedforward sampling module through the third node; The first current generating unit is coupled to the second terminal of the second transistor through the clamping node and is configured to generate a first current; as well as The second current generating unit is coupled to the first terminal of the second transistor and is configured to generate a second current, wherein the second current is equal to the first current.

4. The clamping circuit as described in claim 3, wherein, The clamping branch module includes a third current generating unit and a first transistor. The control terminal of the first transistor is coupled to the feedforward sampling module through a first node, and the second terminal of the first transistor is coupled to the feedback sampling module through a second node. The third current generating unit is coupled to the second terminal of the first transistor and is configured to generate a third current. Wherein, the ratio of the third current to the first current is equal to the ratio of the width-to-length ratio of the first transistor to the width-to-length ratio of the second transistor, and the gate length of the first transistor is equal to the gate length of the second transistor.

5. The clamping circuit as described in claim 1, wherein, The feedback sampling module includes a first switch, a third switch, and a first capacitor; the feedforward sampling module includes a second switch and a second capacitor. Based on the closed states of the first switch, the second switch, and the third switch, the first capacitor samples the first voltage difference, and the second capacitor samples the second voltage difference.

6. The clamping circuit as described in claim 5, wherein, The amplifier module includes a differential amplifier or a single-ended amplifier.

7. The clamping circuit as described in claim 6, wherein, The positive input terminal of the differential amplifier is coupled to the first terminal of the first switch and is configured to receive the clamping reference voltage. The negative input terminal of the differential amplifier is coupled to the second terminal of the first switch. The output terminal of the differential amplifier is coupled to the first terminal of the second capacitor.

8. The clamping circuit as described in claim 6, wherein, The single-ended amplifier includes a first resistor, a third transistor, and a fifth transistor. The control terminal of the third transistor is coupled to the second terminal of the first switch, and the first terminal of the third transistor is coupled to the second terminal of the fifth transistor. The first terminal of the fifth transistor is coupled to the first resistor, and the first terminal of the fifth transistor serves as the output terminal of the amplifier module and is coupled to the first terminal of the second capacitor.

9. The clamping circuit as described in claim 8, wherein, The clamping circuit further includes a second reference voltage generation module, which is coupled to a first terminal of the second switch and configured to provide the clamping reference voltage.

10. The clamping circuit as described in claim 9, wherein, The second reference voltage generation module includes a fourth current generation unit, a fourth transistor, and a sixth transistor. The fourth current generating unit is coupled to the first terminal of the sixth transistor and configured to generate a fourth current. The second terminal of the sixth transistor is coupled to the first terminal of the fourth transistor. The control terminal of the fourth transistor is coupled to the first terminal of the sixth transistor and is also coupled to the first terminal of the first switch. The ratio of the current flowing through the third transistor to the fourth current is equal to the ratio of the width-to-length ratio of the fourth transistor to the width-to-length ratio of the third transistor, and the gate length of the fourth transistor is equal to the gate length of the third transistor.

11. A memory computing device, comprising: Memristor array, input circuit and output circuit, among which, The output circuit includes a plurality of clamping circuits as described in any one of claims 1-10. The input circuit is coupled to the memristor array and configured to provide multiple input voltages to the memristor array. The memristor array is coupled to multiple clamping circuits via multiple clamping nodes, and is configured to provide the floating voltage to the multiple clamping circuits as the ideal clamping voltage when the multiple input voltages are zero.

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