Memory system and operating method thereof

Abstract

The invention provides a memory system and an operating method thereof. A memory system includes a memory and a memory controller coupled to the memory. The memory controller is configured to read data from a data page of the memory, perform a first stage error correction code test on the read data in accordance with first error correction code data associated with the data, and, in response to determining that the read data does not pass the first stage error correction code test, perform a second stage error correction code test on the read data. And performing a second-stage error correction code test on the part of the read data according to the second error correction code data. And storing the first error correction code data and the data in the data page. The second error correction code data is associated with a portion of the data corresponding to the portion of the read data, and is stored in a redundant page different from the data page.

Description

Technical Field

[0001] The present disclosure relates to a memory system, and more particularly to error correction of the memory system. Background Art

[0002] Once memory cells in a data storage device (e.g., a memory system) are programmed, data can be read from the memory cells by comparing the cell threshold voltage to one or more read voltages to sense the programming state of each memory cell. However, the cell threshold voltage may change due to one or more factors such as read disturbance or data retention, which may cause the sensed programming state to be different from the written programming state and result in a read output failure bit (error bit) of the data. Summary of the invention

[0003] According to one aspect of the present disclosure, a memory system is provided, comprising a memory and a memory controller. The memory controller is coupled to the memory and configured to: read a data from a data page of the memory. A first-stage error correction code test is performed on the read data according to a first error correction code data associated with the data, and the first error correction code data is stored together with the data in the data page. In response to determining that the read data does not pass the first-stage error correction code test, a second-stage error correction code test is performed on a portion of the read data according to a second error correction code data, wherein the second error correction code data is associated with the portion of the read data, and the portion of the read data is stored in a redundant page different from the data page.

[0004] In one embodiment, the data includes multiple parts, which include a first part of the data and a second part of the data, and the read data includes multiple parts, which include a first part of the read data and a second part of the read data, the second part of the read data corresponds to the second part of the data, and wherein the memory controller is configured to: in response to determining that the first part of the read data passes the second stage error correction code test, perform the first stage error correction code test on the second part of the read data and a corrected data of the first part of the read data according to the first error correction code data.

[0005] In one embodiment, the memory controller includes a redundant array of independent disks circuit, and the memory controller is configured to: in response to determining that the portion of the read data fails the second stage error correction code test, perform an error correction on the read data using the redundant array of independent disks circuit.

[0006] In one embodiment, the memory controller includes an ECC decoder, and the memory controller is configured to use the ECC decoder to perform the first-stage ECC test and the second-stage ECC test.

[0007] In one embodiment, the memory controller is configured to: in response to determining that the read data fails the first stage error correction code test, read the second error correction code data from the redundant page; and use the second error correction code data to perform an error correction code decoding operation on the portion of the read data and a combination of multiple predetermined values, wherein the total size of the portion of the read data and the predetermined values ​​is equal to the read data.

[0008] In one embodiment, the memory controller includes an error correction code encoder configured to: generate the first error correction code data according to the data; and generate the second error correction code data according to the portion of the data and the predetermined values.

[0009] In one embodiment, the predetermined values ​​include at least one of 0 or 1.

[0010] In one embodiment, the data size of the portion of the data is half of the data size.

[0011] In one embodiment, the memory controller is configured to: perform an error correction code decoding operation on the read data according to the first error correction code data; determine whether a number of error bits in the read data after the error correction code decoding operation is performed is less than a predetermined threshold; if the number of error bits is less than the predetermined threshold, determine that the read data passes the first stage error correction code test; and if the number of error bits is equal to or greater than the predetermined threshold, determine that the read data fails the first stage error correction code test.

[0012] In one embodiment, the redundant page includes an error correction code parity data associated with the second error correction code data, and the memory controller is configured to: perform an error correction code decoding operation on the second error correction code data according to the error correction code parity data to generate a corrected second error correction code data; and perform the second stage error correction code test on the portion of the read data according to the corrected second error correction code data.

[0013] In one embodiment, wherein the memory includes a plurality of data pages including the data page as a first data page, the redundant page is different from each of the data pages, and wherein the redundant page includes a plurality of second error correction code data associated with a specific portion of a page of data in the data pages.

[0014] In one embodiment, the data amount of the specific portion of the page data in each of the data pages is the same, and the memory controller is configured to: for each of the data pages, generate the corresponding first error correction code data according to the page data in the data page, and store the corresponding first error correction code data in the data page; and for each of the data pages, generate the corresponding second error correction code data and a plurality of predetermined values ​​according to the specific portion of the page data in the data page, and store the corresponding second error correction code data of the data page in the redundant page, wherein the total data amount of the specific portion of the page data in the data page and the predetermined values ​​are equal to the data amount of the page data in the data page.

[0015] In one embodiment, the memory includes one or more memory chips, each of the memory chips has multiple blocks, and wherein the data pages are located in the same block of one of the memory chips, and the redundant page is located in the same block or different blocks of one of the memory chips, or wherein at least two of the data pages are located in different blocks of one of the memory chips, and the redundant page is located in one of the memory chips or different chips, or wherein at least two of the data pages are located in different memory chips of the memory, and the redundant page is located in the memory.

[0016] In one embodiment, the memory controller is configured to: generate a corresponding first error correction code data based on the page data of each data page of at least two data pages among the data pages, and store the corresponding first error correction code data in each data page of the at least two data pages; generate a synthetic data based on multiple specific parts of the at least two data pages, the data amount of the synthetic data is equal to the data amount of each specific part of the at least two data pages; and generate a corresponding second error correction code data based on the synthetic data and multiple predetermined values, and store the second error correction code data corresponding to the at least two data pages in the redundant page.

[0017] In one embodiment, the memory controller is configured to: read a first page of data from a first data page among the at least two data pages; perform a first stage error correction code test on the read first page of data according to a first error correction code data corresponding to the first data page; in response to determining that the read first page of data fails the first stage error correction code test, read another page of data from at least one other data page among the at least two data pages; read the second error correction code data corresponding to the at least two data pages from the redundant page; and perform a second stage error correction code test on a first data portion of the read first page of data and the predetermined values ​​according to the corresponding second error correction code data and the other page data from the at least one other data page.

[0018] According to one aspect of the present disclosure, a memory system is provided, including a memory and a memory controller, wherein the memory controller is coupled to the memory and configured to: generate a first error correction code data based on a data in a data page of the memory; store the first error correction code data and the data in the data page; generate a second error correction code data based on a portion of the data in the data page; and store the second error correction code data of the data page in a redundant page different from the data page.

[0019] In one embodiment, the memory controller is configured to generate the second error correction code data based on the portion of the data of the data page and multiple predetermined values, wherein the total data amount of the portion of the data of the data page and the multiple predetermined values ​​is equal to the data amount of the data in the data page.

[0020] In one embodiment, the memory controller is configured to: read the data from the data page of the memory; perform a first stage error correction code test on the read data according to the first error correction code data in the data page; and in response to determining that the read data fails the first stage error correction code test, read the second error correction code data from the redundant page, and perform a second stage error correction code test on a portion of the read data according to the second error correction code data, wherein the portion of the read data corresponds to the portion of the data.

[0021] In one embodiment, the memory includes multiple data pages, which include the data page, the redundant page is different from each of the data pages, and the memory controller is configured to: generate a corresponding first error correction code data for the page data of each of at least two data pages among the data pages, and store the corresponding first error correction code data and the page data in each of the at least two data pages; generate a synthetic data according to multiple specific parts of the page data of the at least two data pages, the data amount of the synthetic data is equal to the data amount of each of the specific parts of the page data of the at least two data pages; and generate a corresponding second error correction code data according to the synthetic data, and store the second error correction code data corresponding to the at least two data pages in the redundant page.

[0022] In one embodiment, the memory controller is configured to: read a first page of data from a first data page of the at least two data pages; perform a first stage error correction code test on the read first page of data according to a first error correction code data corresponding to the first data page; in response to determining that the read first page of data fails the first stage error correction code test, read at least one other specific portion of a page of data from at least one other data page of the at least two data pages; read a second error correction code data corresponding to the at least two data pages from the redundant page; and perform a second stage error correction code test on a first data portion of the read first page of data and the predetermined values ​​according to the corresponding second error correction code data and the at least one other specific portion of the at least one other data page.

[0023] According to one aspect of the present disclosure, a method for operating a memory system is provided, comprising: reading a data from a data page of a memory; performing a first-stage error correction code test on the read data according to a first error correction code data associated with the data, the first error correction code data being stored together with the data in the data page; and in response to determining that the read data fails the first-stage error correction code test, performing a second-stage error correction code test on a portion of the read data according to a second error correction code data, wherein the second error correction code data is associated with the portion of the read data, and storing the portion of the read data in a redundant page different from the data page.

[0024] In one embodiment, the operating method further includes: generating the first error correction code data according to the data in the data page, and storing the first error correction code data in the data page; and generating a second error correction code data according to a portion of the data in the data page and a plurality of predetermined values, and storing the second error correction code data of the data page in the redundant page, wherein the total data amount of the portion of the data in the data page and the predetermined values ​​is equal to the data amount of the data in the data page.

[0025] Other aspects and advantages of the present disclosure will become apparent from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A An example of a memory system with error correction capability is shown.

[0027] Figure 1B An example configuration of a memory chip including a plurality of blocks is shown.

[0028] Figure 2 An example of generating multi-stage error correction code data for error correction in a memory system is shown.

[0029] Figure 3 Another example of generating multi-stage error correction code data for error correction of a memory system is shown.

[0030] Figure 4A is a flow chart of an example process for generating multi-stage error correction code data for error correction of a memory system.

[0031] Figure 4B is a flow diagram of an example process for managing error correction in a memory system.

[0032] Description of Reference Numerals

[0033] 100: Memory System

[0034] 120: Host device

[0035] 122: Host controller

[0036] 110: Installation

[0037] 112: Device controller

[0038] 113: Processor

[0039] 114: Internal memory

[0040] 130: Error correction code circuit

[0041] 132: Error Correction Code Encoder

[0042] 134: Error correction code decoder

[0043] 140: Redundant Array of Independent Disks Circuit

[0044] 150: Memory

[0045] 152: Memory chip

[0046] 154: Block

[0047] 156: Page

[0048] 200,300: Example

[0049] 400,450: Process

[0050] 402,404,452,454,456: Steps

[0051] 202,302: Data page

[0052] 202-0,302-0: Page 0

[0053] 202-1,302-1: Page 1

[0054] 202-2,302-2: Page 2

[0055] 202-3,302-3: Page 3

[0056] 302-(N-1): Page N-1

[0057] 202-(M-1): Page M-1

[0058] 204: Page M

[0059] 304: Page N

[0060] 222,224,226,322,322-0,322-1,322-2,322-3,322-(N-1), 326,320: Error correction code data

[0061] 212,312,312-1,312-2,312-3,322-(N-1): User data

[0062] 220,322-1: Error Correction Code Encoder

[0063] 214,314,314-0: Data section

[0064] 230,330: Cache pages

[0065] 216,318: Fixed data

[0066] 316: Synthetic Data

[0067] 224,: Error correction code data

[0068] 324: Second stage error correction code data

[0069] 304 redundant page

[0070] 315: XOR Operation DETAILED DESCRIPTION

[0071] The technical terms in this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art in this technical field may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0072] Due to frequent read operations, data stored in the memory may be subject to read disturbance, where the state of the memory cell (e.g., erased state and one or more programmed states) of the memory may have an increased threshold voltage. Read disturbance may cause a fail bit (or error bit) to appear when the read data is output. The error correction code decoder can be configured to perform decoding on the data read from the memory to detect and correct any bit errors that may exist in the data, which can exceed the error correction capability of the error correction code mechanism.

[0073] Redundant array of independent disks (RAID) is a data storage virtualization technology that combines multiple physical disk drive elements into one or more logical units for data redundancy, improved performance, or both. Data is distributed across the disk drives in one of a number of ways, called RAID levels, depending on the desired redundancy / performance level. Different mechanisms or data distribution layouts may be named with the word "RAID" followed by a number, for example, RAID 0, RAID 1, RAID 2, ..., RAID 9, or more. Each mechanism or RAID level provides a different balance between key objectives, including reliability, availability, performance, and capacity. RAID levels greater than RAID 0 can provide protection against unrecoverable sector read errors as well as failure of entire physical disk drives.

[0074] Instead of storing ECC data in the same page as user data, RAID redundancy data is stored across different physical disk drive elements. Therefore, RAID can provide inter-page RAID or inter-disk RAID protection to recover data that cannot be corrected by ECC as an additional protection. However, to perform inter-page RAID or inter-disk RAID protection, all pages need to be read to find failed data, which will take longer to recover data than ECC.

[0075] Embodiments of the present disclosure provide systems, methods, and techniques for managing error correction of memory systems, such as protection with multi-stage error correction codes (or error correction with multi-stage error correction codes). These techniques can enhance the protection (or error correction) capabilities of error correction codes and recover uncorrectable data via conventional error correction code mechanisms. These techniques can use the same error correction code hardware (e.g., error correction code encoders and decoders) to implement similar functions of independent disk redundant arrays without using independent disk redundant array circuits and / or without changing existing hardware configurations. The above techniques can also be implemented via independent disk redundant array circuits or independent disk redundant array technology for additional / further enhanced data correction and protection.

[0076] In some implementations, for protection of the first stage error correction code, for example Figure 2 as well as Figure 4A As discussed in further detail, the error correction code encoder performs encoding on the data in each data page of the memory to generate first error correction code data. The first error correction code data is stored together with the data in the data page. For the protection of the second stage error correction code, the error correction code encoder performs encoding on a portion of the data (e.g., half of the data) and a predetermined value (e.g., 1 or 0) together to generate second error correction code data. The second error correction code data is stored separately from the data in a redundant page. The redundant page can store the second error correction code data of some parts of the data from multiple pages. Since the predetermined value is fixed, the second error correction code data is only used to correct a portion of the data (e.g., half of the data), and therefore, the second error correction code data can provide a higher error correction capability than the first error correction code data. For example, if this portion of the data is half of the data, and the second error correction code data includes an error correction code check bit (ECC check bits) of the same length as the first error correction code data, the second error correction code data can have double the error correction capability compared to the first error correction code data.

[0077] In a read operation, for example, Figure 4BAs discussed in further detail, when the first error correction code data in the data page fails to correct the data, for example, the protection of the first stage error correction code fails, the controller can extract the second error correction code data of the data page from the redundant page. Since the second error correction code data has a higher error correction capability, the second error correction code data can be used to correct this portion of the data. After this portion of the data is corrected, the corrected portion of the data can replace this portion of the data, and then the first error correction code data can be used to correct the remaining portion of the data. Since the amount of data in the remaining portion of the data is less than the data, the first error correction code data can have a higher error correction capability for the remaining portion of the data. Therefore, the protection of the second stage error correction code can recover the uncorrectable data protected by the first stage error correction code. In the protection of the second stage error correction code, only two pages (the data page and the redundant page) are read to implement the protection of the error correction code. Compared to the RAID technology using inter-page RAID protection, which requires reading all pages (eg, 8 to 128 pages) once the first stage ECC protection fails, the technology implemented by the present disclosure provides faster speed and faster response.

[0078] In some implementations, the second stage error correction code protection utilizes independent disk redundant array technology to further improve performance. Figure 3 As discussed in further detail, if a large number of data pages need to be protected with a small number of available redundant pages, the same second error correction code data can be used to protect portions of multiple data pages. Portions of multiple data pages can be used to generate synthetic data, for example, using one or more logical / mathematical functions, such as XOR. The synthetic data can have the same amount of data as each portion, such as half of a data page. The synthetic data can then be encoded to generate the second error correction code data to be stored in the redundant pages. As described above, the redundant pages can provide second-stage error correction code protection for more data pages. In a read operation, multiple data pages used to generate the synthetic data and the second error correction code data are read out to perform second-stage error correction code protection on any one of the multiple data pages.

[0079] The above techniques can be applied to different situations. In some embodiments, multiple data pages are located in the same block of a memory chip, and redundant pages for storing the second error correction code data of the multiple data pages can be located in the same block or different blocks in the same memory chip. In some embodiments, at least two of the multiple data pages are located in different blocks in the memory chip, and the redundant pages can be located in the blocks of the memory chip or in different memory chips. In some embodiments, at least two of the multiple data pages are located in different memory chips of a memory device, and the redundant pages can be located in the memory chips of the memory device or in different memory devices. In some embodiments, at least two of the multiple data pages are located in different memory devices, such as a solid state drive (SSD) of a memory system, and the redundant pages can be located in a memory device of a different memory device, or in another memory device of the memory system. These techniques can be applied alone or in combination with independent disk redundant array technology.

[0080] These techniques can be applied to various types of semiconductor devices, volatile memory devices or non-volatile memory devices (NVM), such as NAND flash memory (NAND flash), NOR flash memory (NOR flash), resistive random access memory (RRAM), phase change memory (PCM), such as phase change random access memory (PCRAM). And, spin transfer torque (STT) magnetoresistive random access memory (MRAM), etc. The above techniques can also be applied to memory devices based on charge capture, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating gate-based memory devices. The above techniques can be applied to two-dimensional memory devices or three-dimensional memory devices. The above techniques can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (such as two-level cell devices), TLC (three-level cell) devices, QLC (four-level cell) devices or PLC (five-level cell) devices. Furthermore, the above technology may be applied to various types of devices and systems, such as a secure digital (SD) card, an embedded multimedia card (eMMC) or a solid state drive (SSD), an embedded system, and the like.

[0081] Figure 1A An example of a memory system 100 with error correction capability is shown. The memory system 100 includes a device 110 and a host device 120. The host device 120 includes a host controller 122, which may include at least one processor and at least one memory, the at least one memory being coupled to the at least one processor and storing program instructions for execution by the at least one processor to perform one or more corresponding operations.

[0082] In some embodiments, device 110 is a storage device. For example, device 110 may be an embedded multimedia card, a secure digital card, a solid state drive, or other suitable storage device. In some embodiments, device 110 is a smart watch, a digital camera, or a media player. In some embodiments, device 110 is a client device coupled to host device 120. For example, device 110 is a secure digital card in a digital camera or a media player as host device 120.

[0083] In some embodiments, the host device 120 is coupled to one or more devices 110 (eg, solid state drives). Each of the devices 110 may include a device controller 112 and a memory 150. The memory 150 may include one or more memory chips 152, each of which is coupled to the device controller 112. Figure 1B An example configuration of a memory chip 152 including a plurality of blocks 154 (e.g., block 0, block 1, ..., block m-1, and block m) is shown. Each block may include the same number of pages 156, e.g., page 0, page 1, ..., page n. Each page has a unique number in the block. Data is stored in the pages of the block in the order of the unique numbers of the pages in the block. Each page can be read or written separately, and the pages in the block can be erased together.

[0084] Device controller 112 is a general-purpose microprocessor or an application-specific microcontroller. In some implementations, device controller 112 is a memory controller of device 110. The following paragraphs of this document describe various techniques based on implementations where device controller 112 is a memory controller. However, the techniques described in the following paragraphs are also applicable to implementations where device controller 112 is another type of controller other than a memory controller.

[0085] In some embodiments, the device controller 112 includes a processor 113 and an internal memory 114. The processor 113 is configured to execute instructions and process data. These instructions include firmware instructions and / or other program instructions stored in the auxiliary memory as firmware program code and / or other program code, respectively. This data includes program data corresponding to the firmware and / or other programs executed by the processor and other suitable data. In some embodiments, the processor 113 is a general-purpose microprocessor or a dedicated microcontroller. The processor 113 is also referred to as a central processing unit (CPU).

[0086] The processor 113 accesses instructions and data from the internal memory 114. In some embodiments, the internal memory 114 is a static random access memory (SRAM) or a dynamic random access memory (DRAM). For example, in some embodiments, when the device 110 is a secure digital card, an embedded multimedia card, or a smart watch, the internal memory 114 is a static random access memory. In some embodiments, when the device 110 is a digital camera or a media player, the internal memory 114 is a dynamic random access memory.

[0087] In some implementations, such as Figure 1A As shown, the internal memory 114 is a cache memory included in the device controller 112. The internal memory 114 stores instruction program codes corresponding to instructions executed by the processor 113 and / or data requested by the processor 113 during operation.

[0088] The device controller 112 transfers the instruction program code and / or data from the memory 150 to the internal memory 114. In some embodiments, the memory 150 is a storage device or non-volatile memory configured to store instructions and / or data for a long time, such as a NAND flash memory device or some other suitable non-volatile storage device. In an embodiment where the memory 150 is a NAND flash memory, the device 110 is a flash memory device, such as a flash memory card. And, the device controller 112 is a NAND flash controller. For example, in some embodiments, when the device 110 is a secure digital card or an embedded multimedia card, the memory 150 is a NAND flash memory. In some embodiments, when the device 110 is a digital camera, the memory 150 is a secure digital card. In some embodiments, when the device 110 is a media player, the memory 150 is a hard disk.

[0089] In some embodiments, the device controller 112 is configured to receive data and instructions from the host device 120, and to send data to the host device 120. The device controller 112 is further configured to send data and commands to the memory 150, and to receive data from the host device 120. For example, the device controller 112 is used to send data and write commands to instruct the memory 150 to store data at a specific address. In another example, the device controller 112 is configured to receive a read request (or read command) from the host device 120, and to send a corresponding read command to the memory 150 to read data from a specific address in the memory 150.

[0090] In some embodiments, Figure 1AAs shown, the device controller 112 includes an ECC circuit 130. The ECC circuit 130 may include an ECC encoder 132 and an ECC decoder 134. In some embodiments, the ECC circuit 130 may be arranged to be externally coupled to the device controller 112.

[0091] The error correction code encoder 132 can be configured to receive data to be stored in the memory 150 and generate check bits. The check bits are generated, for example, by encoding the data using an error correction code encoding mechanism. The check bits can be called error correction code data. The error correction code encoder 132 can include a "Reed Solomon encoder", a "Bose-Chaudhuri-Hocquenghem (BCH) encoder", a "low-density parity check (LDPC) encoder" or any combination of the above three. The error correction code decoder 134 can be configured to perform decoding on the data read from the memory 150 to detect and correct any bit errors that may exist in the data, which can reach the error correction capability of the error correction code mechanism. The error correction code decoder 134 can perform BCH decoding or LDPC decoding.

[0092] In some embodiments, the error correction code encoder 132 is configured to perform encoding for data having a predetermined length or data amount (e.g., 4KB) to generate error correction code data having a predetermined data amount (e.g., 512B). The error correction code decoder 134 is configured to perform decoding for data having a predetermined length or data amount (e.g., 4KB) using error correction code data having a predetermined data amount (e.g., 512B). For the same amount of data, the error correction code data of a larger data amount can provide a higher error correction capability relative to the error correction code data of a smaller data amount. For the same amount of error correction code data, the error correction code data can provide a higher error correction capability for the data of a smaller data amount relative to the data of a larger data amount. For example, an error correction code encoder with a data amount of 4KB generates error correction code data with a data amount of 512B. If the error correction code encoder is used to encode data with a data amount of 2KB and a predetermined (or fixed) value (e.g., 1 or 0) with a data amount of 2KB to generate 512B error correction code data, when the error correction code decoder decodes the data using the error correction code data, the 512B error correction code data generated from the 2KB data can provide a higher error correction capability than the 512B error correction code data generated from the 4KB data. Figure 2 , Figure 3 as well as Figure 4A , 4B As discussed in further detail, the ECC encoder 132 and the ECC decoder 134 may be used to provide multiple stages of ECC protection.

[0093] In some embodiments, the device controller 112 includes an independent disk redundant array circuit 140 configured to use independent disk redundant array technology to protect data. The independent disk redundant array circuit 140 can distribute the data on different disk drives of an independent disk redundant array level (e.g., RAID 0, RAID 1, RAID 2, ..., RAID 9, or any combination thereof). The independent disk redundant array circuit 140 can be configured to provide a further stage of error protection if the protection using the multi-stage error correction code of the error correction code circuit 130 fails.

[0094] Figure 2 An example 200 of generating multi-stage error correction code data for error correction in a memory system is shown. The memory system may include: a memory controller (e.g., Figure 1A device controller 112) and a memory (e.g., Figure 1A Memory 150) of the memory device (e.g., Figure 1A The memory may include one or more memory chips (e.g., Figure 1A and Figure 1B Each memory chip includes a plurality of blocks (e.g., Figure 1B Each block includes a plurality of pages (eg, Figure 1B 156 of the ).

[0095] For ease of explanation, the protection of the multi-stage error correction code is implemented for multiple data pages. For example, page 0 202-0, page 1 202-1, page 2 202-2, page 3 202-3, ..., page M-1 202-(M-1), which can be collectively referred to as multiple data pages 202 (and individually referred to as data pages 202), where M is an integer equal to or greater than 1, for example, M is 7. Each data page 202 stores corresponding user data 212 in the data page 202.

[0096] For the protection of the first stage error correction code, the error correction code encoder 220 (eg, Figure 1A The error correction code encoder 132) is for the data from the plurality of data pages 202 (eg, Figure 2 2-0) to generate error correction code data 222. As described above, the error correction code encoder 220 may include: a Reed Solomon encoder, a BCH encoder, an LDPC encoder, or any combination thereof. The error correction code data 222 may include: an error correction code check bit (or an error correction code protection bit) of the user data 212. The error correction code data 222 may be stored in the same data page 202 as the user data 212, for example, appended to the user data 212 in the data page 202.

[0097] The error correction code encoder 220 is configured to perform encoding on data having a predetermined length or data amount to generate error correction code data having a predetermined data amount. For example, the error correction code encoder 220 may be a 4KB error correction code encoder configured to perform encoding on 4KB of data. The data amount of the user data 212 may be 4KB, and the data amount of the error correction code data 222 may be 512B. In some examples, the data page 202 stores 16KB of user data. The error correction code encoder 220 may perform encoding on each 4KB of user data 212 to generate corresponding error correction code data 222 having a data amount of 512B, and store the corresponding error correction code data 222 in the data page 202 adjacent to the user data 212. The error correction code encoder 220 may repeat encoding 4 times to perform encoding on all 16KB of user data in the data page 202. The corresponding error correction code data 222 may be referred to as "first stage error correction code data" or "first error correction code data". In the present disclosure, the terms “first stage error correction code data” and “first error correction code data” may be used interchangeably.

[0098] For the protection of the second stage error correction code, such as Figure 2 As shown, the controller (e.g., Figure 1A The device controller 112 of the device 112 may extract the data portion 214 of the user data 212 from the data page 202 and place the data portion 214 into the cache page 230 as an input to the error correction code encoder 220. The cache page 230 may be located in a cache area (or data buffer) of the controller, such as a cache area of ​​the controller. Figure 1A a cache area in the internal memory 114, or a cache area for the error correction code encoder 220).

[0099] In some embodiments, for example Figure 2 As shown, the controller fills the remaining space of the cache page 230 with fixed data 216 (e.g., a plurality of predetermined values), so that the total data amount of the data portion 214 and the fixed data 216 is compatible with (e.g., equal to) the predetermined data amount of the error correction code encoder 220. The controller may be configured to execute the following steps: Figure 1A The processor 113 or the controller of the processor 113 is configured to execute a specific circuit to fill the data, and the fixed data 216 is filled in the cache page 230. The fixed data 216 may include at least one of 1 and 0 or any fixed value.

[0100] In some examples, the error correction code encoder 220 is a 4KB error correction code encoder 220, and the data size of the user data 212 is 4KB. If the data size of the data portion 214 is half of the user data 212, for example, a data size of 2KB, then the data size of the fixed data 216 filled in the cache page is 2KB. In this way, the encoder 220 can still be used to perform encoding on the data in the cache page 230 (for example, the data portion 214 and the predetermined value 216) to generate the error correction code data 224. The data size of the error correction code data 224 can be equal to the error correction code data 222, for example, 512B.

[0101] Compared to the ECC data 222 of the user data 212, the ECC data 224 is used for the data portion 214 and the fixed data 216. Since the fixed data 216 includes a predetermined / fixed value and does not have an error bit, the ECC data 224 can be used to decode and correct the data portion 214 (e.g., by using Figure 1A The error correction capability of the error correction code data 222 for the user data 212 is performed by the error correction code decoder of the error correction code decoder 134 of the embodiment of the present invention. Since the data portion 214 is a part of the user data 212, and the data amount of the data portion 214 is smaller than the user data 212, if the data amount of the error correction code data 224 is equal to the error correction code data 222, the error correction code data 224 may have a higher error correction capability for the data portion 214 than the error correction capability of the error correction code data 222 for the user data 212. For example, if the data amount of the data portion 214 is half of the user data 212, and the data amount of the error correction code data 224 is equal to the error correction code data 222, the error correction code data 224 has double the error correction capability compared to the error correction code data 222.

[0102] The error correction code data 224 may be referred to as "second stage error correction code data" or "second error correction code data". The above terms "second stage error correction code data" or "second error correction code data" may be used interchangeably in the present disclosure. If the first stage error correction code data 222 fails to correct the user data 212, the second stage error correction code data 224 may be used to correct the data portion 214 as well as the user data 212. For example, after the second stage error correction code has corrected the data portion 214, the corrected data portion 214 may replace the data portion in the user data 212, and the first stage error correction code data 222 may be used again to decode and correct the remaining portion of the user data 212 based on the corrected data portion 214. In this way, the first stage error correction code data 222 and the second stage error correction code data 224 may correct the entire user data 212.

[0103] In some implementations, the data portion 214 has an amount of half the amount of the user data 212. That is, the data portion 214 is 50% of the user data 212. The data portion 214 may also be less than or greater than 50% of the user data 212.

[0104] The fixed data 216 may be populated in the cache page 230 in any suitable manner. In some implementations, the fixed data 216 is arranged adjacent to the data portion 214 in the cache page 230. In some implementations, the values ​​(e.g., 1 or 0) in the fixed data 216 are distributed or inserted between bits in the data portion 214. In some implementations, the fixed data 216 is divided into at least two parts, which are populated at different locations in the data portion 214.

[0105] like Figure 2 As shown, the error correction code data 224 may be stored in the redundant page 204 (e.g., page M). The controller (e.g., the error correction code encoder 220) may generate corresponding error correction code data 224 for each of the plurality of data pages 202. Therefore, the redundant page 204 may store M error correction code data 224 for the plurality of data pages 202. The data amount of the redundant page 204 may be equal to the data amount of the plurality of data pages 202. The total data amount of the M error correction code data 224 may be no greater than the data amount of the redundant page 204. The redundant page 204 may be configured for the M data pages 202. In some examples, M is equal to 7. In some implementations, the redundant page 204 may be selectively encoded by the error correction code encoder 220 to generate the error correction code data 226 of the redundant page 204 itself and stored in a position adjacent to the second error correction code data 224 in the redundant page 204. The ECC data 226 may be optionally used to correct error bits in the redundant page 204 , for example, before extracting the second stage ECC data 224 for the second ECC protection.

[0106] Redundant page 204 may be different from each of the plurality of data pages 202. In some embodiments, the plurality of data pages 202 are located in the same block of a memory chip, and redundant page 204 may be located in the same block or a different block in the memory chip. In some embodiments, at least two of the plurality of data pages 202 are located in different blocks of a memory chip, and redundant page 204 may be located in the same memory chip or a different memory chip of the same memory. In some embodiments, at least two of the plurality of data pages 202 are located in at least two memory chips of a memory system, and redundant page 204 may be located in a memory chip different from the at least two memory chips of the memory system.

[0107] In some implementations, at least two of the plurality of data pages 202 are located in at least two memory devices (eg, SSDs) in a memory system, and redundant page 204 may be located in a memory device other than the at least two memory devices of the memory system.

[0108] In some embodiments, the controller includes a second error correction code encoder, which may be different from the error correction code encoder 220. The second error correction code encoder may be configured to encode data of the same amount of data as the data portion 214 (e.g., 2KB). The controller may include a corresponding second error correction code decoder, which is configured to decode data of the same amount of data as the data portion 214 (e.g., 2KB). In the cache page, there is no need to add additional data (e.g., fixed data 216) to the data portion 214. Alternatively, the data portion 214 may be directly used as an input to the second error correction code encoder. In some examples, the amount of data of the error correction code data generated by the second error correction code encoder may be equal to the error correction code data 224 or the error correction code data 222. In this way, the error correction code data generated by the second error correction code encoder may have a higher error correction capability than the error correction code data 222 for the user data 212. If the first stage error correction code protection using the first stage error correction code data 222 fails, the error correction code data generated by the second error correction code encoder can also be used as the second stage error correction code data (or second error correction code data) to provide second stage protection.

[0109] In some examples, the amount of data of the error correction code data generated by the second error correction code encoder may be greater than the amount of data of the error correction code data 222. In some examples, the amount of data of the error correction code data generated by the second error correction code encoder may be less than the amount of data of the error correction code data 222, but greater than a threshold. For example, if the amount of data portion 214 is half of the amount of user data 212, the amount of data of the threshold may be half of the amount of error correction code data 222.

[0110] Figure 3 Another example 300 of generating multi-stage error correction code data for error correction of a memory system is shown. Figure 2 In example 200, each data page has corresponding second-stage error correction code data, and example 300 uses one or more logical and / or mathematical operations (e.g., XOR) on data portions of multiple data pages to obtain a single second-stage error correction code data for multiple data pages, which can save space in redundant pages and / or reduce the number of redundant pages used to store second-stage error correction code data for a large number of data pages protected by multi-stage error correction codes.

[0111] Similar to Figure 2 In example 200, a memory system may include a memory controller (e.g., Figure 1Adevice controller 112) and a memory (e.g., Figure 1A Memory 150) of the memory device (e.g., Figure 1A The memory may include one or more memory chips (e.g., the memory chip 152 of FIGS. 1A and 1B). Each memory chip includes a plurality of blocks (e.g., Figure 1B Each block includes a plurality of pages (eg, Figure 1B 156 of page 156). The memory controller may include an error correction code encoder 320 (e.g., Figure 1A The error correction code encoder 132) and the error correction code decoder (e.g., Figure 1A Error correction code decoder 134).

[0112] For ease of explanation, protection of a multi-stage error correction code (or error correction of a multi-stage error correction code) is implemented for multiple data pages (e.g., page 0 302-0, page 1 302-1, page 2 302-2, page 3 302-3, ..., page N-1 302-(N-1)), which can generally be referred to as data page 302, which can be a single or multiple data pages. N is an integer equal to or greater than 2. In some examples, N is a value of 15, 31, 63, 127, 255, or more.

[0113] Data page 302 may be similar to or the same as Figure 2 Each data page 302 stores corresponding user data 312 in the data page 302. Figure 2 In the example 200 of the example 300, in the protection of the first stage error correction code, the error correction code encoder 320 (for example, Figure 1A The error correction code encoder 132 or Figure 2 The ECC encoder 220 may generate corresponding first-stage ECC data (or first ECC data) 322 for the user data 312 of each data page 302, and the first-stage ECC data 322 may be stored in a position adjacent to the user data 312 in the data page 302. Figure 3 As shown, page 0 (data page 302-0) stores user data 312-0 and first-stage error correction code data 322-0, page 1 (data page 302-1) stores user data 312-1 and first-stage error correction code data 322-1, page 2 (data page 302-2) stores user data 312-2 and first-stage error correction code data 322-2, page 3 (data page 302-3) stores user data 312-3 and first-stage error correction code data 322-3, ..., page N-1 (data page 302-(N-1)) stores user data 312-(N-1) and first-stage error correction code data 322-(N-1).

[0114] The protection of the second stage error correction code is different from Figure 2 Each data page 202 of example 200 has corresponding second stage error correction code data 224 in redundant page 204 (page M), and example 300 uses one or more logical or mathematical operations (e.g., XOR) on data portions of multiple data pages to obtain a single second stage error correction code data for multiple data pages in redundant page 304 (page N). The one or more logical or mathematical operations may be similar to or the same as the logical or mathematical operations used in redundant array of independent disks technology.

[0115] For example, Figure 3 The data portion 314-0 of the user data 312-0 in page 0 (data page 302-0), the data portion 314-1 of the user data 312-1 in page 1 (data page 302-1), and one or more other data portions of the user data 312 in one or more other data pages 302, can be operated using an XOR operation 315 to generate a synthesized data 316. The XOR operation 315 can be performed by a memory controller (e.g., an error correction code encoder 320 or a specific logic gate or circuit) before encoding. The data portions 314-0, 314-1, ..., etc. can be collectively or individually referred to as data portions 314, that is, the data portion 314 can be a single data portion or multiple data portions. The data amount of the synthesized data 316 is the same as each of the data portions 314. For example, if the data amount of the data portion 314 is 2KB, the data amount of the synthesized data 316 is also 2KB. In the above manner, the data portion 314 of the user data 312 of the plurality of data pages 302 can be represented by a single synthetic data 316, which can be used to generate the second-stage error correction code data 324 of the plurality of data pages 302. The data amount of the second-stage error correction code data 324 can be the same as the first-stage error correction code data 322, for example, 512B.

[0116] In some implementations, similar to Figure 2 The synthesized data 316 of example 300 is stored in the flash page 330 as an input to the error correction code encoder 320. The fixed data 318 may be filled in the flash page 330. The fixed data 318 may be similar or identical to Figure 2The fixed data 318 may include a plurality of predetermined values, such as 1 or 0. The total data volume of the synthetic data 316 and the fixed data 318 is the same as the user data 312. In a specific example, the data volume of each user data 312 is 4KB, and the data volume of each data portion 314 is half of the user data 312 (i.e., 2KB), then the data volume of the synthetic data 316 is 2KB, and the data volume of the fixed data 318 is 2KB. In the above manner, the error correction code encoder 320 can be used to generate the first-stage error correction code data 322 and the second-stage error correction code data 324.

[0117] The plurality of data pages 302 may be divided into a plurality of groups of data pages 302. Each group of data pages 302 may be associated with corresponding second-stage error correction code data 324. The second-stage error correction code data 324 groups corresponding to the plurality of groups may be stored in the redundant page 304. The total amount of data of each second-stage error correction code data 324 may not be greater than the amount of data of the user data 312 or the space capacity of the redundant page 304. In some implementations, similar to Figure 2 In the example 200, in the example 300, the second stage ECC data 324 stored in the redundant page 304 can be encoded by, for example, the ECC encoder 320 to generate the ECC data 326 and stored together with the second stage ECC data 324 in the redundant page 304. During a read operation, before the second stage ECC data 324 is used to perform the second stage ECC protection, the ECC data 326 can be selectively used to correct bit errors in the second stage ECC data 324 stored in the redundant page 304.

[0118] The number of the plurality of data pages 302 may be an integer greater than 1, and the number of the plurality of groups may be n (i.e., an integer greater than 1). In some examples, if the data size of the user data 312 is 4 KB and the data size of each second-stage error correction code data 324 is 512B, then n may be 8.

[0119] In some examples, if the number of the plurality of data pages 302 is 15, that is, N=15, there may be 7 groups of single or two data pages 302. Each group is used to generate the synthetic data 316, and to generate the second stage error correction code data 324 of the group. In addition, the single data page 302 itself is used to generate the second stage error correction code data 324 of the single data page 302. The redundant page 304 stores 8 second stage error correction code data 324 for 15 data pages 302. Therefore, using the XOR operation, one redundant page can provide the second stage error correction code protection for 15 data pages 302.

[0120] In some examples, if the number of the plurality of data pages 302 is 31, that is, N=31, there may be 7 groups of 4 data pages 302 or 1 group of 3 data pages 302. Each group is used to generate the synthesized data 316 and to generate the second stage error correction code data 324 of the group. The redundant page 304 also stores 8 second stage error correction code data 324 of the 31 data pages 302. Therefore, using the XOR operation, one redundant page can provide the second stage error correction code protection for the 31 data pages 302.

[0121] In some examples, if the number of the plurality of data pages 302 is 63, that is, N=63, there may be 7 groups of 8 data pages 302 and 1 group of 7 data pages 302. Each group is used to generate the synthesized data 316 and to generate the second stage error correction code data 324 of the group. The redundant page 304 stores 8 second stage error correction code data 324 for 63 data pages 302. Therefore, using the XOR operation, one redundant page can provide the second stage error correction code protection for 63 data pages 302.

[0122] Similar to Figure 2 In some embodiments, the redundant page 204 of the plurality of data pages 302 may be different from each data page of the plurality of data pages 302. In some embodiments, the plurality of data pages 302 are located in the same block of a memory chip, and the redundant page 304 may be located in the same or different blocks in the memory chip. In some embodiments, at least two of the plurality of data pages 302 are located in different blocks of a memory chip, and the redundant page 304 may be located in the same memory chip, or in different memory chips of the same memory. In some embodiments, at least two of the plurality of data pages 302 are located in at least two memory chips of the same memory, and the redundant page 304 may be located in another memory chip different from the at least two memory chips of the above-mentioned memory. In some implementations, at least two of the plurality of data pages 302 are located in at least two memory devices (e.g., SSD) in a memory system, and the redundant page 304 may be located in another memory device different from the at least two memory devices in the memory system.

[0123] Figure 4A 4 is a flow chart of an example process 400 for generating multi-stage error correction code data for error correction of a memory system. The memory system may include a memory controller (e.g., Figure 1A device controller 112) and a memory (e.g., Figure 1A Memory 150) of the memory device (e.g., Figure 1A The memory may include one or more memory chips (e.g., the memory chip 152 of FIGS. 1A and 1B). Each memory chip includes a plurality of blocks (e.g., Figure 1B Each block includes a plurality of pages (eg, Figure 1B 156 of ). The memory controller may include an error correction code encoder (e.g., Figure 1A The error correction code encoder 132, Figure 2 The error correction code encoder 220 or Figure 3 The error correction code encoder 320) and the error correction code decoder (e.g., Figure 1A Error correction code decoder 134). Figure 4A Process 400 of the method may be performed by a memory system (eg, a memory controller).

[0124] The memory system can be from a host device (e.g., Figure 1A The host device 120 receives the data and stores the data in a plurality of data pages in the memory system. The memory system can provide protection for data errors for the stored data, for example, Figure 2 or Figure 3 The data pages can be protected by multi-stage error correction codes, and optionally by redundant array of independent disks. Figure 2 Multiple data pages 202, or Figure 3 A plurality of data pages 302 .

[0125] In step 402, first error correction code data (or first stage error correction code data) is generated according to the data stored in each of the plurality of data pages, and the first error correction code data is stored together with the data in the data page. The first error correction code data may be generated by an error correction code encoder. The data stored in each of the plurality of data pages may be Figure 2 User data 212 or Figure 3 The first error correction code data may be Figure 2 The first error correction code data 222 or Figure 3 The first error correction code data 322.

[0126] In step 404, second error correction code data (or second-stage error correction code data) is generated according to a portion of the data stored in each of the plurality of data pages, and the second error correction code data is stored in a redundant page different from the data page. The redundant page may be Figure 2 Redundant page 204 or Figure 3 The redundant page 304. The portion of the stored data may be Figure 3 Data portion 314 or Figure 2 data portion 214.

[0127] In some embodiments, for example Figure 2 The memory controller shown in FIG. 1 stores a portion of data in a data page and a plurality of predetermined values ​​(eg, Figure 2The plurality of predetermined values ​​may include at least one of 1 or 0. The portion of the stored data may be extracted and stored in a cache page (e.g., Figure 2 The portion may be half of the stored data. A plurality of predetermined values ​​may be filled in the cache page. The portion of the data stored in the data page and the total amount of the plurality of predetermined values ​​are equal to the amount of data stored in the data page. The error correction code encoder may perform encoding on the data in the cache page to generate second error correction code data for the data page. The amount of data of the second error correction code data for the portion of the data stored in the data page may be equal to the first error correction code data for the data stored in the data page.

[0128] In some embodiments, a plurality of data pages are divided into a plurality of groups. Each group may include one or more data pages. Figure 3 As shown, for a group including at least two data pages, an operation (eg, via an XOR operation) may be performed on specific portions of the page data of the at least two data pages to generate composite data (eg, Figure 3 The synthesized data 316 is then processed based on the synthesized data and a plurality of predetermined values ​​(e.g., Figure 3 The fixed data 318) generates the second error correction code data (for example, Figure 3 The term "page data" refers to data stored in a data page. Then, the second error correction code data of this group can be stored in a redundant page. The data amount of the synthesized data can be the same as each specific portion of the page data of at least two data pages. The total data amount of the synthesized data and the plurality of predetermined values ​​can be the same as the data amount of the page data in the data page. The data amount of the second error correction code data for the specific portion of the page data of at least two data pages can be the same as the first error correction code data for the page data of each of the at least two data pages.

[0129] In some embodiments, if the memory system includes a redundant array of independent disks circuit (e.g., Figure 1A If a redundant array of independent disks circuit 140 is used, the memory system can use a redundant array of independent disks circuit to protect data, for example, to store data across multiple disk drive elements (such as memory chips) in the memory system.

[0130] In some embodiments, multiple data pages are located in the same block of a memory chip of a memory, and the redundant page may be located in the same block or different blocks in the same memory chip. In some implementations, at least two of the multiple data pages are located in different blocks of a memory chip of a memory, and the redundant page may be located in the same memory chip or different memory chips of the memory. In some embodiments, at least two of the multiple data pages are located in at least two memory chips of a memory, and the redundant page may be located in another memory chip different from the at least two memory chips of the memory. In some implementations, at least two of the multiple data pages are located in at least two memory devices (e.g., SSD) in a memory system, and the redundant page may be located in another memory device different from the at least two memory devices in the memory system.

[0131] Figure 4B is a flow diagram of an example process 450 of managing error correction in a memory system. Figure 4B The memory system used in the process of Figure 4A The memory system may include a memory controller (e.g., Figure 1A device controller 112) and a memory (e.g., Figure 1A Memory 150) of the memory device (e.g., Figure 1A The memory may include one or more memory chips (e.g., Figure 1A-1B Each memory chip includes a plurality of blocks (e.g., Figure 1B Each block includes a plurality of pages (eg, Figure 1B 156 of ). The memory controller may include an error correction code encoder (e.g., Figure 1A The error correction code encoder 132, Figure 2 The error correction code encoder 220 or Figure 3 The error correction code encoder 320) and the error correction code decoder (e.g., Figure 1A Error correction code decoder 134). Figure 4B Process 450 may be performed by a memory system (eg, a memory controller).

[0132] The memory system can be from a host device (e.g., Figure 1A The host device 120 of the memory system receives the request. The request may be a read request for reading data stored in the memory system. As discussed above, the data may be stored in multiple data pages with multi-stage error correction code protection.

[0133] At step 452, from a plurality of data pages (eg Figure 2 Data page 202 or Figure 3Each of the data pages 302 reads data (eg Figure 2 User data 212 or Figure 3 In step 454, a first stage error correction code test is performed on the read data according to first error correction code data associated with the data, the first error correction code data being stored together with the data in the data page. The first error correction code data may be Figure 2 The first stage error correction code data 222 or Figure 3 The first stage error correction code data 322.

[0134] In some embodiments, the memory controller performs an error correction code decoding operation on the read data according to the first error correction code data, performs a first stage error correction code test via the error correction code decoding operation, and determines whether the number of error bits in the read data after the error correction code decoding operation is less than a predetermined threshold. If the number of error bits is less than the predetermined threshold, the memory controller determines that the read data passes the first stage error correction code test. The memory controller can then output the read data as output data to the host device. If the number of error bits is equal to or greater than the predetermined threshold, the memory controller determines that the read data does not pass the first stage error correction code test.

[0135] At step 456, if the read data fails the first stage ECC test, a second stage ECC test is performed on a portion of the read data according to the second ECC data. The second ECC data is data associated with the portion corresponding to the read data and is stored in a redundant page different from each of the plurality of data pages. The second ECC data may be Figure 2 The second error correction code data 224 or Figure 3 The second error correction code data 324. The amount of data of the second error correction code data may be the same as the amount of data of the first error correction code data. This portion of the data may be Figure 2 Data section 214 or Figure 3 The data portion 314 of the data. The amount of data in this portion of the data may be one-half of the amount of data in this data. The redundant page may be Figure 2 Redundant page 204 or Figure 3 Redundant page 304.

[0136] In some embodiments, the memory controller performs an error correction code decoding operation on the portion of the read data according to the second error correction code data (e.g., by, for example, Figure 1AThe memory controller may use the same error correction code decoder to perform the first stage error correction code test and the second stage error correction code test. If the number of error bits is less than the predetermined threshold, the memory controller determines that the portion of the read data passes the second stage error correction code test. If the number of error bits is greater than or equal to the predetermined threshold, the memory controller determines that the portion of the read data fails the second stage error correction code test.

[0137] The data may include a plurality of parts, including: a part as a first part of the data, and a second part of the data (e.g., a remaining part). The read data may include a plurality of parts, including: a part as a first part of the read data, and a second part of the read data, which corresponds to the second part of the data. If the first part of the read data passes the second stage error correction code test, the memory controller may perform a first stage error correction code test on the second part of the read data and the corrected data of the first part of the read data according to the first error correction code data. If the second part of the read data and the corrected data of the first part of the read data pass the first stage error correction code test, the memory controller may output the corrected data of the second part of the read data and the corrected data of the first part of the read data as the read data of the data.

[0138] In some embodiments, the memory controller includes a redundant array of independent disks circuit (e.g., Figure 1A Array of Independent Disks redundant array circuit 140)~If this portion of the read data fails the second stage error correction code test, the memory controller may use the array of independent disks redundant array circuit to perform error correction on the read data, for example, as a third stage data protection.

[0139] In some embodiments, in response to determining that the read data does not pass the first stage error correction code test, the memory controller reads second error correction code data from the redundant page, and uses the second error correction code data to perform an error correction code decoding operation on the combination of the portion of the read data and the plurality of predetermined values. The total amount of data of the portion of the read data and the plurality of predetermined values ​​is the same as the read data. The plurality of predetermined values ​​may be the same as the plurality of predetermined values ​​used to generate the second error correction code data. The plurality of predetermined values ​​may be Figure 2 Fixed data 216 or Figure 3 The plurality of predetermined values ​​may include at least one of 0 or 1.

[0140] In some implementations, the redundant page includes error correction code parity data associated with the second error correction code data (eg, Figure 2 Error correction code data 226 or Figure 3 The memory controller may perform an error correction code decoding operation on the second error correction code data according to the error correction code parity data to generate corrected second error correction code data, and perform a second stage error correction code test on the portion of the read data according to the corrected second error correction code data.

[0141] In some embodiments, Figure 2 or Figure 3 As shown, the redundant page includes: a plurality of second error correction code data associated with a specific portion of the page data in the plurality of data pages. The total data amount of the plurality of second error correction code data is less than or equal to the data amount of the data. The data amount of the specific portion of the page data in each of the plurality of data pages can be the same.

[0142] In some implementations, such as Figure 3 As shown, multiple data pages are divided into multiple groups. Each group may include one or more data pages. Figure 3 As shown, for a group including at least two data pages, an operation (eg, via an XOR operation) may be performed on specific portions of the page data of the at least two data pages to generate composite data (eg, Figure 3 The synthesized data 316 is then processed based on the synthesized data and a plurality of predetermined values ​​(e.g., Figure 3 The fixed data 318) is used to generate the second error correction code data ( Figure 3 The second error correction code data 324 of the group can then be stored in the redundant page. The amount of the synthesized data can be the same as each specific portion of the page data of each of the one or more data pages.

[0143] In some embodiments, in a read operation, the memory controller reads a first page of data from a first data page of at least two data pages (e.g., at step 452) and, based on first error correction code data corresponding to the first data page, performs a first stage error correction code test on the read first page of data (e.g., at step 454). In response to determining that the read first page of data fails the first stage error correction code test (e.g., at step 456), the memory controller reads other page data from one or more other data pages other than the first data page (which fails the first stage error correction code test) among the at least two data pages, and reads corresponding second error correction code data of at least two data pages from redundant pages. And, based on the corresponding second error correction code data and other page data from one or more other data pages, performs a second stage error correction code test on a first data portion of the read first page of data and a plurality of predetermined values.

[0144] A plurality of predetermined values ​​are fixed data without error bits. The error correction code decoder may perform decoding on the synthesized data using the corresponding second error correction code data. Furthermore, the decoded synthesized data may be used together with other page data from one or more other data pages for a reverse XOR operation to derive a first data portion of the first page data, which may be used to correct the first data portion of the first page data that has been read. Furthermore, as discussed above, the corrected first data portion may be used to correct the remaining portion of the first page data that has been read using the first error correction code data of the first page data. Further, after performing correction on the read first page data in the first data page, the corrected first page data may be used to perform error correction on the read page data of one or more other data pages.

[0145] The present disclosure and other examples may be implemented as one or more computer program products, such as one or more module blocks of computer program instructions, which are stored on a computer-readable medium and executed or controlled by a data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a storage device, or a combination of one or more of the above. The term "data processing device" covers all devices and machines for processing data, including, for example, a programmable processor, a calculator, or a multiprocessor. In addition to hardware, the device may also include program code for an execution environment created by a computer program, such as program code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more thereof.

[0146] The system may include all devices, equipment and machines for processing data, such as programmable processors, computers or multiple processors. In addition to hardware, the system may also include program code for the execution environment created by the computer program, such as program code constituting processor firmware, protocol stack, database management system, operating system, or one or more combinations thereof.

[0147] A computer program (also referred to as a program, software, software application, script, or program code) may be written in any form of programming language (including compiled or interpreted languages) and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored as part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language file), in a single file dedicated to the program, or in multiple collaborative files (e.g., files that store one or more modules, subroutines, or portions of program code). A computer program may be deployed for execution on one or more computers located at one site or distributed across multiple sites and interconnected via a communications network.

[0148] The processes and logic flows described herein can be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The processes and logic flows can also be performed by special purpose logic circuits, and the apparatus can also be implemented by special purpose logic circuits, such as FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits).

[0149] For example, processors suitable for executing computer programs include general-purpose and special-purpose microprocessors, and any one or more processors of any type of digital calculator. Generally speaking, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a calculator may include: a processor for executing instructions, and one or more memory devices for storing instructions and data. Generally speaking, a calculator may also include (or be operably coupled to) receiving data from or transmitting data to one or more large-capacity storage devices (such as disks or optical disks) for storing data, or performing both reception and transmission. Computer-readable media suitable for storing computer program instructions and data may include: all forms of non-volatile memory, media and storage devices, such as semiconductor storage devices (such as EPROM, EEPROM, flash devices and disks). The processor and memory may be supported by special-purpose logic circuits or incorporated into special-purpose logic circuits.

[0150] Although the present disclosure has been disclosed in detail with preferred embodiments and examples as above, it is to be understood that these examples are intended to be illustrative rather than restrictive. It is contemplated that a person skilled in the art may conceive of various modifications and combinations, which fall within the spirit of the present disclosure and the scope of the appended claims.

Claims

1. A memory system, comprising: a memory; as well as A memory controller is coupled to the memory and is configured to: Reading data from a data page of the memory; performing a first stage error correction code test on the read data according to a first error correction code data associated with the data, the first error correction code data being stored together with the data in the data page; and In response to determining that the read data fails the first stage ECC test, a second stage ECC test is performed on a portion of the read data according to a second ECC data associated with the portion of the read data, and the portion of the read data is stored in a redundant page different from the data page.

2. The memory system of claim 1 , wherein the data comprises a plurality of parts including a first part of the data and a second part of the data, and the read data comprises a plurality of parts including a first part of the read data and a second part of the read data, the second part of the read data corresponding to the second part of the data, and in, The memory controller is configured as: In response to determining that the first portion of the read data passes the second stage ECC test, the first stage ECC test is performed on the second portion of the read data and a corrected data of the first portion of the read data according to the first ECC data.

3. The memory system of claim 1 , wherein the memory controller comprises a redundant array of independent disks circuit, and The memory controller is configured to: in response to determining that the portion of the read data fails the second stage error correction code test, use the independent disk redundant array circuit to perform an error correction on the read data.

4. The memory system of claim 1 , wherein the memory controller comprises an error correction code decoder, and The memory controller is configured to use the error correction code decoder to perform the first-stage error correction code test and the second-stage error correction code test.

5. The memory system according to claim 1, wherein the memory controller is configured to: In response to determining that the read data fails the first stage ECC test, reading the second ECC data from the redundant page; and An error correction code decoding operation is performed on the portion of the read data and a combination of a plurality of predetermined values ​​using the second error correction code data, wherein the total data amount of the portion of the read data and the predetermined values ​​is equal to the read data.

6. The memory system according to claim 5, wherein the memory controller comprises an error correction code encoder, the error correction code encoder being configured to: Generate the first error correction code data according to the data; and The second error correction code data is generated according to the portion of the data and the predetermined values.

7. The memory system of claim 5, wherein the predetermined values ​​include at least one of 0 or 1. 8 . The memory system according to claim 1 , wherein a data amount of the portion of the data is half a data amount of the data.

9. The memory system according to claim 1, wherein the memory controller is configured to: performing an error correction code decoding operation on the read data according to the first error correction code data; Determining whether an error bit number in the read data after the error correction code decoding operation is performed is less than a predetermined threshold; If the number of error bits is less than the predetermined threshold, determining that the read data passes the first stage error correction code test; as well as If the number of error bits is equal to or greater than the predetermined threshold, it is determined that the read data fails the first stage error correction code test.

10. The memory system of claim 1, wherein the redundant page comprises an ECC parity data associated with the second ECC data, and in, The memory controller is configured as: performing an error correction code decoding operation on the second error correction code data according to the error correction code parity check data to generate a corrected second error correction code data; and The second stage ECC test is performed on the portion of the read data according to the corrected second ECC data.

11. The memory system of claim 1 , wherein the memory comprises a plurality of data pages, the data pages including the data page as a first data page, the redundant page being different from each of the data pages, and The redundant page includes a plurality of second error correction code data associated with a specific portion of a page of data in the data pages.

12. The memory system according to claim 11, wherein the data amount of the specific portion of the page data in each of the data pages is the same, and in, The memory controller is configured as: For each of the data pages, generating the corresponding first error correction code data according to the page data in the data page, and storing the corresponding first error correction code data in the data page; as well as For each of the data pages, the corresponding second error correction code data and a plurality of predetermined values ​​are generated according to the specific portion of the page data in the data page, and the corresponding second error correction code data of the data page is stored in the redundant page. The total data volume of the specific portion of the page data in the data page and the predetermined values ​​are equal to the data volume of the page data in the data page.

13. The memory system according to claim 11, wherein the memory comprises one or more memory chips, each of the memory chips having a plurality of blocks, and wherein the data pages are located in the same block of one of the memory chips, and the redundant page is located in the same block or a different block of one of the memory chips, or At least two of the data pages are located in different blocks of one of the memory chips, and the redundant page is located in one of the memory chips or in a different chip, or At least two of the data pages are located in different memory chips of the memory, and the redundant page is located in the memory.

14. The memory system according to claim 11, wherein the memory controller is configured to: Generate a corresponding first error correction code data according to the page data of each data page of at least two data pages among the data pages, and store the corresponding first error correction code data in each data page of the at least two data pages; generating a composite data according to the specific portions of the at least two data pages, wherein the data amount of the composite data is equal to the data amount of each specific portion of the specific portions of the at least two data pages; as well as A corresponding second error correction code data is generated according to the synthesized data and a plurality of predetermined values, and the second error correction code data corresponding to the at least two data pages is stored in the redundant page.

15. The memory system according to claim 14, wherein the memory controller is configured to: Reading a first page of data from a first data page among the at least two data pages; Performing a first-stage error correction code test on the read first page data according to a first error correction code data corresponding to the first data page; The at least two data pages further include at least one other data page other than the first data page, and in response to determining that the read first page data fails the first-stage error correction code test, reading another page of data from the at least one other data page; Reading the second error correction code data corresponding to the at least two data pages from the redundant page; as well as A second stage ECC test is performed on a first data portion of the read first page data and the predetermined values ​​according to the corresponding second ECC data and the other page data from the at least one other data page.

16. A memory system comprising: a memory; as well as A memory controller is coupled to the memory and is configured to: Generate a first error correction code data according to a data in a data page of the memory; storing the first error correction code data and the data in the data page; Generate a second error correction code data according to a portion of the data in the data page; and The second error correction code data of the data page is stored in a redundant page different from the data page.

17. The memory system according to claim 16, wherein the memory controller is configured to: generating the second error correction code data according to the portion of the data of the data page and a plurality of predetermined values, The total data amount of the portion of the data in the data page and a plurality of predetermined values ​​is equal to the data amount of the data in the data page.

18. The memory system according to claim 16, wherein the memory controller is configured to: Reading the data from the data page of the memory; Performing a first stage ECC test on the read data according to the first ECC data in the data page; and In response to determining that the read data fails the first stage ECC test, the second ECC data is read from the redundant page, and a second stage ECC test is performed on a portion of the read data according to the second ECC data, wherein the portion of the read data corresponds to the portion of the data.

19. The memory system of claim 16, wherein the memory comprises a plurality of data pages, the data pages comprising the data page, the redundant page being different from each of the data pages, and in, The memory controller is configured as: Generate a corresponding first error correction code data for the page data of each of at least two data pages among the data pages, and store the corresponding first error correction code data and the page data in each of the at least two data pages; Generating a composite data according to a plurality of specific portions of the page data of the at least two data pages, wherein the data amount of the composite data is equal to the data amount of each of the specific portions of the page data of the at least two data pages; as well as A corresponding second error correction code data is generated according to the synthesized data, and the second error correction code data corresponding to the at least two data pages is stored in the redundant page.

20. The memory system of claim 19, wherein the memory controller is configured to: Reading a first page of data from a first data page of the at least two data pages; Performing a first-stage error correction code test on the read first page data according to a first error correction code data corresponding to the first data page; The at least two data pages further include at least one other data page other than the first data page, and in response to determining that the read first page data fails the first-stage error correction code test, reading at least one other specific portion of the page data from the at least one other data page; Reading a second error correction code data corresponding to the at least two data pages from the redundant page; as well as A second stage ECC test is performed on a first data portion of the read first page data and the predetermined values ​​according to the corresponding second ECC data and the at least one other specific portion of the page data in the at least one other data page.

21. A method for operating a memory system, comprising: Reading data from a data page of a memory; performing a first stage error correction code test on the read data according to a first error correction code data associated with the data, the first error correction code data being stored together with the data in the data page; and In response to determining that the read data fails the first stage ECC test, a second stage ECC test is performed on a portion of the read data according to a second ECC data associated with the portion of the read data, and the portion of the read data is stored in a redundant page different from the data page.

22. The operating method according to claim 21, further comprising: Generate the first error correction code data according to the data in the data page, and store the first error correction code data in the data page; as well as generating a second error correction code data according to a portion of the data in the data page and a plurality of predetermined values, and storing the second error correction code data of the data page in the redundant page, The total data amount of the portion of the data in the data page and the predetermined values ​​is equal to the data amount of the data in the data page.

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