Semiconductor die stacked structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor die stack structure and a manufacturing method thereof. A method of manufacturing a semiconductor die stack structure includes: preparing a base die including a base die substrate and a base die interlayer dielectric layer; forming a base die front side bonding pad structure; preparing a bottom tube core with a bottom tube core substrate and a bottom tube core through electrode; forming a bottom die front-side bond pad structure in the bottom die substrate; forming a base bottom die stack structure in which the bottom die front-side bond pad structure is in direct contact with the base die front-side bond pad structure; forming a base die through electrode vertically through the base die substrate and electrically connected to the base die front side bond pad structure; forming a base die backside bump structure electrically connected to the base die through electrode; laminating the intermediate die and the top die in the base bottom die stack structure; and forming a bottom die backside bump structure electrically connected to the bottom die through electrode.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to semiconductors, and more particularly, to semiconductor die stack structures and methods of manufacturing semiconductor die stack structures. Background Art

[0002] A semiconductor die stack structure including a plurality of semiconductor dies is disclosed. Summary of the invention

[0003] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor die stacking structure includes the following steps: preparing a base die including a base die substrate and a base die interlayer dielectric layer; forming a base die front side bonding pad structure above the base die interlayer dielectric layer; preparing a bottom die having a bottom die substrate and a bottom die through-electrode; forming a bottom die front side bonding pad structure above the front side of the bottom die substrate; forming a base bottom die stacking structure in which the bottom die front side bonding pad structure and the base die front side bonding pad structure are in direct contact with each other by bonding the bottom die and the base die; forming a base die through-electrode that vertically passes through the base die substrate and is electrically connected to the base die front side bonding pad structure; forming a base die back side bump structure electrically connected to the base die through-electrode above the back side of the base die substrate; stacking a plurality of intermediate die above the base die of the base bottom die stacking structure; stacking a top die above the plurality of intermediate die; and forming a bottom die back side bump structure electrically connected to the bottom die through-electrode.

[0004] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor die stacking structure includes the following steps: preparing a base die having a base die substrate and a base die interlayer dielectric layer; forming a base die front side bonding pad structure above the base die interlayer dielectric layer; preparing a bottom die having a bottom die substrate and a bottom die through-electrode; forming a bottom die front side bonding pad structure above the front side of the bottom die substrate; forming a base bottom die stacking structure in which the bottom die front side bonding pad structure and the base die front side bonding pad structure are in direct contact with each other by bonding the bottom die and the base die; forming a base die through-electrode that vertically passes through the base die substrate and is electrically connected to the base die front side bonding pad structure; forming a base die back side bump structure that is electrically connected to the base die through-electrode above the back side of the base die substrate; forming a bottom die back side bump structure above the basic bottom die stacking structure; stacking an intermediate die above the bottom die of the basic bottom die stacking structure; and stacking a top die above the intermediate die.

[0005] According to another embodiment of the present disclosure, a semiconductor die stacking structure includes: a bottom die; a base die stacked above the bottom die; and an intermediate die and a top die stacked above the base die, wherein the bottom die includes: a bottom die substrate; a bottom die front side bonding pad structure, which is arranged above the front side of the bottom die substrate; a bottom die back side bump structure, which is arranged above the back side of the bottom die substrate; and a bottom die through electrode, which passes through the bottom die substrate and connects the bottom die front side bonding pad structure. The base die is electrically connected to the bottom die back side bump structure, and the base die includes: a base die substrate; a base die front side bonding pad structure, which is arranged above the front side of the base die substrate; a base die back side bump structure, which is arranged above the back side of the base die substrate; and a base die through-electrode, which passes through the base die substrate and electrically connects the base die front side bonding pad structure and the bottom die back side bump structure, and the bottom die front side bonding pad structure and the base die front side bonding pad structure are bonded by direct contact with each other.

[0006] According to another embodiment of the present disclosure, a semiconductor die stacking structure includes: a base die; a bottom die stacked above the base die; and an intermediate die and a top die stacked above the base die, wherein the base die includes: a base die substrate; a base die front side bonding pad structure, which is arranged above the front side of the base die substrate; a base die back side bump structure, which is arranged above the back side of the base die substrate; and a base die through electrode, which passes through the base die substrate and connects the base die front side bonding pad structure. The bottom die is electrically connected to the back side bump structure of the base die, and the bottom die includes: a bottom die substrate; a bottom die front side bonding pad structure, which is arranged above the front side of the bottom die substrate; a bottom die back side bump structure, which is arranged above the back side of the bottom die substrate; and a bottom die through-electrode, which passes through the bottom die substrate and electrically connects the bottom die front side bonding pad structure and the bottom die back side bump structure, and the bottom die front side bonding pad structure and the base die front side bonding pad structure are bonded by directly contacting each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E , Fig.8F , Figure 8G , Figure 8H , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E , Fig.10F , Fig.11A and Fig. 11B A method of manufacturing a semiconductor die stack structure according to various embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0008] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments described herein. Throughout the present disclosure, similar reference numerals throughout the various drawings and embodiments of the present disclosure represent similar parts.

[0009] The accompanying drawings are not necessarily to scale, and in some cases, the scale may be exaggerated in order to clearly illustrate the features of the embodiments. When the first layer is referred to as being "on" the second layer or "on" the substrate, it refers not only to the situation where the first layer is directly formed on the second layer or the substrate, but also to the situation where the third layer exists between the first layer and the second layer or the substrate. It will be understood that when an element or layer, etc. is referred to as being "on", "connected to" or "coupled to" another element or layer, etc., it may be directly on, connected to or coupled to another element or layer, etc., or there may be an intermediate element or layer, etc. On the contrary, when an element or layer, etc. is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, etc., there is no intermediate element or layer, etc. In this article, for ease of description, spatial relative terms such as "below", "below", "below", "below", "above", "on", etc. may be used to describe the relationship between an element or feature and another element or feature, as shown in the figure. It will be understood that, in addition to the orientations depicted in the figure, these spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, the elements described as being "below" or "beneath" other elements or features will be oriented as being "above" the other elements or features. Therefore, examples of the term "below" can cover both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly. Embodiments of the present disclosure relate to a semiconductor die stacking structure including a plurality of semiconductor dies stacked therein and a method for manufacturing the semiconductor die stacking structure. Embodiments of the present disclosure relate to a basic bottom die stacking structure in which a base die and a bottom die are bonded and a method for manufacturing the basic bottom die stacking structure. Embodiments of the present disclosure relate to a method for stacking an intermediate die and a top die above a basic bottom die stacking structure. Embodiments of the present disclosure relate to a semiconductor stacking structure including an intermediate die and a top die stacked above a basic bottom die stacking structure.

[0010] Figures 1A to 6G 1 and 102 (respectively) according to an embodiment of the present disclosure. Fig. 5F and Figure 6G ) method. Figures 1A to 6G , a method for manufacturing semiconductor die stacking structures 101 and 102 may include: preparing a base die 10; preparing a bottom die 20; preparing a base bottom die stacking structure 30 by bonding the base die 10 and the bottom die 20; preparing an intermediate die 50 and a top die 60; stacking the intermediate die 50 and the top die 60 above the base bottom die stacking structure 30; and performing a dicing process.

[0011] Figure 1A and Figure 1BFIG. 1 shows a method for manufacturing a semiconductor die stack structure ( Fig. 5F 101 and Figure 6G The base die 10 is manufactured and prepared in the method 102).

[0012] Reference Figure 1A The method may include: forming a base die circuit element 12 and a base die interlayer dielectric layer 13 above the front side (active side) FS1 of the base die substrate 11; and forming a base die front side bonding dielectric layer 15 above the base die circuit element 12 and the base die interlayer dielectric layer 13.

[0013] The base die substrate 11 may include a silicon wafer. The base die circuit element 12 may include a base die transistor 12a, a base die metal interconnect 12b, a base die metal via 12c, and a base die metal pad 12d. For example, the base die circuit element 12 may include a memory peripheral logic circuit. The base die metal interconnect 12b may extend in a horizontal direction and transmit an electrical signal. The base die metal via 12c may extend in a vertical direction to electrically connect the base die transistor 12a, the base die metal interconnect 12b, and the base die metal pad 12d. A base die interlayer dielectric layer 13 may be formed over the base die substrate 11 to cover the base die circuit element 12. The base die interlayer dielectric layer 13 may include a silicon oxide-based or silicon nitride-based dielectric material.

[0014] The base die front side bonding dielectric layer 15 may include an inorganic dielectric layer. For example, the base die front side bonding dielectric layer 15 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and other inorganic dielectric materials containing silicon, oxygen, and / or nitrogen. The base die front side bonding dielectric layer 15 may have a hole H1 exposing the surface of the base die metal pad 12d.

[0015] Reference Figure 1B, the method may further include forming a base die front side bonding pad structure 18. The base die front side bonding pad structure 18 may include a base die front side bonding pad seed layer 16 conformally formed on the side surface of the base die front side bonding dielectric layer 15 exposed in the hole H1 and on the surface of the exposed base die metal pad 12d, and a base die front side bonding pad metal 17 formed above the base die front side bonding pad seed layer 16 to fill the hole H1. The base die front side bonding pad seed layer 16 may be conformally formed by performing a deposition process such as a physical vapor deposition (PVD) process. According to one embodiment of the present disclosure, each base die front side bonding pad seed layer 16 may include a lower base die front side bonding pad seed layer including titanium (Ti), titanium nitride (TiN) or titanium tungsten (TiW) and an upper base die front side bonding pad seed layer including copper (Cu). The base die front side bonding pad metal 17 may be formed by performing a plating process. According to one embodiment of the present disclosure, the base die front side bonding pad metal 17 may include a metal such as copper (Cu) and / or nickel (Ni). The base die front side bonding pad seed layer 16 may surround the lower surface and the side surface of the base die front side bonding pad metal 17 in a U shape.

[0016] FIG. 2A to FIG. 2D FIG. 1 shows a method for manufacturing a semiconductor die stack structure ( Fig. 5F 101 and Figure 6G The bottom die 20 is manufactured and prepared in the method 102).

[0017] Reference Figure 2A , the method may include: performing a deposition process such as a chemical vapor deposition (CVD) process to form a bottom die front side passivation layer 22 over the front side FS2 of the bottom die substrate 21 in a wafer state; and forming a hole H2. The bottom die substrate 21 may include a silicon wafer. The bottom die front side passivation layer 22 may include an inorganic dielectric layer based on silicon nitride or silicon oxide. The hole H2 may be formed by performing a photolithography process and an etching process. The hole H2 may completely penetrate the bottom die front side passivation layer 22 and may partially penetrate the bottom die substrate 21. For example, the bottom surface of the hole H2 may be set in the bottom die substrate 21.

[0018] Reference Figure 2B, the method may further include forming a bottom die through electrode 23 in the hole H2. Each bottom die through electrode 23 may include a bottom die through electrode plug, a bottom die through electrode seed layer surrounding the side surface of the bottom die through electrode plug, and a bottom die through electrode dielectric layer covering the side surface of the bottom die through electrode seed layer. The bottom die through electrode dielectric layer may be conformally formed on the inner wall and bottom surface of the hole H2 by performing a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The bottom die through electrode dielectric layer may include a silicon oxide-based or silicon nitride-based inorganic dielectric layer. The bottom die through electrode seed layer may include a metal or a metal compound formed by performing a CVD process or a PVD process. The bottom die through electrode seed layer may be conformally formed above the bottom die through electrode dielectric layer. According to one embodiment of the present disclosure, the bottom die through electrode seed layer may include a lower bottom die through electrode seed layer and an upper bottom die through electrode seed layer. The lower bottom die through electrode seed layer may include titanium (Ti), titanium nitride (TiN) or titanium tungsten (TiW). The upper bottom die through electrode seed layer may include copper (Cu). The bottom die through electrode plug may be formed above the bottom die through electrode seed layer to completely fill the hole H2. The bottom die through electrode plug may include copper (Cu) formed by performing a plating process. The upper surface of the bottom die through electrode 23 may be exposed. The upper surface of the bottom die through electrode 23 and the upper surface of the bottom die front side passivation layer 22 may be coplanar.

[0019] Reference Figure 2C The method may further include forming a bottom die front side bonding dielectric layer 25 having a hole H3 over the bottom die front side passivation layer 22. The bottom die front side bonding dielectric layer 25 may include a silicon oxide-based or silicon nitride-based inorganic dielectric layer (e.g., silicon oxide, silicon nitride, or silicon carbonitride) formed by performing a deposition process such as CVD. The surface of the upper end of the bottom die through electrode 23 may be exposed in the hole H3.

[0020] Reference Figure 2D, the method may further include forming a bottom die front side bonding pad structure 28. Each bottom die front side bonding pad structure 28 may include a bottom die front side bonding pad seed layer 26 and a bottom die front side bonding pad metal 27. The bottom die front side bonding pad seed layer 26 may be conformally formed on the upper surface of the bottom die front side bonding dielectric layer 25 exposed in the hole H3 and the upper surface of the exposed bottom die through electrode 23 and the side surface of the bottom die front side bonding dielectric layer 25. Each bottom die front side bonding pad seed layer 26 may include a multilayer metal layer having a lower bottom die front side bonding pad seed layer and an upper bottom die front side bonding pad seed layer. The lower bottom die front side bonding pad seed layer may include titanium (Ti), titanium nitride (TiN) or titanium tungsten (TiW). The upper bottom die front side bonding pad seed layer may include copper (Cu). The bottom die front side bonding pad metal 27 may be formed to fill the hole H3 over the bottom die front side bonding pad seed layer 26. The bottom die front side bonding pad metal 27 may include copper (Cu). The bottom die front side bonding pad seed layer 26 may surround the lower surface and the side surface of the bottom die front side bonding pad metal 27 in a U shape, respectively.

[0021] FIG. 3A to FIG. 3E FIG. 1 shows a method for manufacturing a semiconductor die stack structure ( Fig. 5F 101 and Figure 6G In the method 102) in the embodiment, a plurality of base bottom die stack structures 30 are manufactured and prepared by bonding the base die 10 and the bottom die 20 and forming a base die through-electrode 33.

[0022] Reference Figure 3A The method may include bonding a plurality of base dies 10 and a plurality of bottom dies 20 in a wafer-to-wafer manner. For example, the method may include bonding a bottom die 20 facing upward and a base die 10 facing downward. In other words, the base die 10 and the bottom die 20 may be bonded as shown in FIG. Figure 3A The bottom dies 20 and the base dies 10 may correspond to each other one by one. The base dies 10 and the bottom dies 20 may be bonded using a hybrid bonding method. The base die front side bonding pad structures 18 and the bottom die front side bonding pad structures 28 may be in direct contact with each other and may be bonded to each other. The base die front side bonding dielectric layer 15 and the bottom die front side bonding dielectric layer 25 may be in direct contact with each other and may be bonded to each other through a surface activation process.

[0023] Reference Figure 3B, the method may further include thinning the back side (inactive surface) BS1 of the base die substrate 11 by performing a back grinding process as indicated by the arrow. In an embodiment, the base die substrate 11 may be thinned while being bonded to the bottom die substrate 21 in a wafer state. In an embodiment, because the bonded bottom die substrate 21 has sufficient resistance, the base die substrate 11 may be maintained during the thinning process without bending or curling. In one embodiment, the thickness Tw of the base die substrate 11 may be as thin as about 20 μm or less.

[0024] Reference Figure 3C The method may further include forming a base die backside passivation layer 32 and forming a hole H4 on the backside BS1 of the base die substrate 11. The hole H4 may vertically penetrate the thinned base die substrate 11 to selectively expose the surface of the base die metal interconnect 12b.

[0025] Reference Figure 3D , the method may further include forming a basic die through electrode 33 in the hole H4. Each basic die through electrode 33 may include a basic die through electrode plug, a basic die through electrode seed layer surrounding the side surface of the basic die through electrode plug, and a basic die through electrode dielectric layer surrounding the side surface of the basic die through electrode seed layer. The basic die through electrode dielectric layer may be conformally formed on the inner wall and bottom surface of the hole H4 by performing a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The basic die through electrode dielectric layer may include an inorganic dielectric layer based on silicon oxide or silicon nitride. The basic die through electrode seed layer may include a metal or a metal compound formed by performing a CVD process or a PVD process. The basic die through electrode seed layer may be conformally formed on the basic die through electrode dielectric layer. In one embodiment, the basic die through electrode seed layer may include a lower basic die through electrode seed layer and an upper basic die through electrode seed layer. The lower base die through electrode seed layer may include titanium (Ti), titanium nitride (TiN) or titanium tungsten (TiW). The upper base die through electrode seed layer may include copper (Cu). The base die through electrode plug may be formed above the base die through electrode seed layer to completely fill the hole H4. The base die through electrode plug may include copper (Cu) formed by performing a plating process. The surface of the upper end of the base die through electrode 33 may be exposed on the base die back side passivation layer 32. The surface of the upper end of the base die through electrode 33 and the upper surface of the base die back side passivation layer 32 may be coplanar.

[0026] Reference Figure 3E, the method may further include forming a base die backside bump structure 37. Forming the base die backside bump structure 37 may include: forming an under-bump metallurgy (UBM) layer and a plating mask pattern on the base die backside passivation layer 32 and the base die through-electrode 33; forming a bump by performing a plating process; and removing the plating mask pattern. The bump may include a bump metal and a bump capping layer. Each base die backside bump structure 37 may include a base die backside UBM layer 34 and base die backside bumps 35 and 36. The base die backside bumps 35 and 36 may include a base die backside bump metal 35 and a base die backside bump capping layer 36. The base die backside UBM layer 34 may include a lower base die backside UBM layer including titanium (Ti) or titanium tungsten (TiW) and an upper base die backside UBM layer including copper (Cu). The base die backside bump metal 35 may include a single metal layer or multiple metal layers including a metal such as nickel (Ni) or copper (Cu). The base die backside bump capping layer 36 may include an oxidation and corrosion resistant metal such as gold (Au).

[0027] Figure 4A and Figure 4B It is shown that the middle die 50 and the top die 60 are prepared in the method of manufacturing the semiconductor die stack structures 101 and 102 according to an embodiment of the present disclosure.

[0028] Reference Figure 4A , the method may further include preparing an intermediate die 50. The intermediate die 50 may include an intermediate die substrate 51, an intermediate die through-electrode 52 passing through the intermediate die substrate 51, an intermediate die front side bump structure 55 disposed on the front side FS3 of the intermediate die substrate 51, and an intermediate die back side bump structure 57 disposed on the back side BS3 of the intermediate die substrate 51. The intermediate die substrate 51 may include the intermediate die substrate 51, an intermediate die circuit element formed above the intermediate die substrate 51, an intermediate die dielectric layer, an intermediate die front side passivation layer, and an intermediate die back side passivation layer. The intermediate die through-electrode 52 may include an intermediate die through-electrode dielectric layer, an intermediate die through-electrode seed layer, and an intermediate die through-electrode plug. The structure of the intermediate die through-electrode 52 may be referred to as the structure of the bottom die through-electrode 23. Each intermediate die front side bump structure 55 may include an intermediate die front side bump metal 53 and an intermediate die front side bump solder 54. The middle die front side bump metal 53 may include a metal such as copper (Cu) or nickel (Ni). The middle die front side bump solder 54 may include a solder material. Each middle die front side bump structure 55 may also include a middle die front side metal pad and a middle die front side bump UBM layer disposed between the middle die substrate 51 and the middle die front side bump metal 53 and between the middle die through-electrode 52 and the middle die front side bump metal 53. The middle die front side metal pad may correspond to the base die metal pad ( Figure 1A 12d in the figure). The front side bump UBM layer of the intermediate die may have a similar structure to the back side UBM layer of the base die ( Figure 3E For example, the intermediate die backside bump structure 57 may include the same structure as the base die backside bump structure ( Figure 3E The structure of 37) is the same as the structure of 37).

[0029] Reference Figure 4B , the method may further include preparing a top die 60. The top die 60 may include a top die substrate 61 and a top die front side bump structure 65 disposed on the front side FS4 of the top die substrate 61. The top die substrate 61 may be substantially the same as the middle die substrate 51. The top die 60 may include a top die circuit element, a top die dielectric layer, and a top die front side passivation layer. Each top die front side bump structure 65 may include a top die front side bump metal 63 and a top die front side bump solder 64. Each top die front side bump structure 65 may also include a top die front side metal pad and a top die front side bump UBM layer. The top die front side bump structure 65 may have the same structure as the middle die front side bump structure ( Figure 4A The structure of 55) is the same as the structure of 55).

[0030] FIG. 5A to FIG. 5E A semiconductor die stack structure 101 is shown prepared using a base bottom die stack structure 30 , a middle die 50 , and a top die 60 in accordance with an embodiment of the present disclosure.

[0031] Reference Figure 5A and Figure 5B The method may further include: stacking a plurality of intermediate tube cores 50 (such as by Figure 5A 90; and molding the middle die 50 and the top die 60 with an encapsulant 90. The middle die 50 and the top die 60 may be stacked on the back side of the base die 10 of the base bottom die stack structure 30. The encapsulant 90 may include an epoxy molding compound (EMC). The preliminary semiconductor die stack structure may be formed and manufactured by performing the described processes.

[0032] Reference Figure 5C The method may include mounting the preliminary semiconductor die stack structure upside down on a wafer support system (WSS) and thinning the back side of the bottom die substrate 21 (eg Figure 5C ). The upper end of the bottom die through electrode 23 may protrude upward from the thinned back side BS2 of the bottom die substrate 21.

[0033] Reference Figure 5D, the method may further include forming a bottom die backside passivation layer 72 on the backside of the base bottom die stack structure 30 (i.e., on the backside BS2 of the thinned bottom die 20). The bottom die backside passivation layer 72 may include a silicon nitride-based dielectric layer formed by performing a CVD process. The method may further include planarizing the bottom die backside passivation layer 72 by performing a planarization process (e.g., CMP) to expose the upper surface of the bottom die through-electrode 23. The upper surface of the bottom die through-electrode 23 and the upper surface of the bottom die backside passivation layer 72 may be coplanar.

[0034] Reference Figure 5E , the method may further include forming a bottom die backside bump structure 77. Each bottom die backside bump structure 77 may include a bottom die backside UBM layer 74 and bottom die backside bumps 75 and 76. The bottom die backside bumps 75 and 76 may include a bottom die backside bump metal 75 and a bottom die backside bump solder 76. For example, the method may include: forming a UBM layer over the bottom die backside passivation layer 72; forming a plating mask pattern; performing a plating process to form a bump; and removing the plating mask. The bottom die backside UBM layer 74 may include a lower bottom die backside UBM layer (e.g., titanium (Ti) or titanium nitride (TiN)) and an upper bottom die backside UBM layer (e.g., copper (Cu)). The bottom die backside bump metal 75 may include a single metal layer or multiple metal layers, which include a metal (e.g., copper (Cu) or nickel (Ni)). According to one embodiment of the present disclosure, the bottom die back bump metal 75 may include a lower bottom die back bump metal including copper (Cu), a middle bottom die back bump metal including nickel (Ni), and an upper bottom die back bump metal including a copper (Cu) layer. A preliminary basic die stack structure may be formed and manufactured by performing the described processes.

[0035] Reference Fig. 5F , the method may further include manufacturing a plurality of semiconductor die stacking structures 101 by dicing the preliminary base die stacking structure. Each semiconductor die stacking structure 101 may include a base bottom die stacking structure 30, and the base bottom die stacking structure 30 includes a base die 10 and a bottom die 20 bonded face to face. For example, the base bottom die stacking structure 30 may include a bottom die 20 bonded in a face-up manner and a base die 10 bonded in a face-down manner. The bottom die 20 and the base die 10 may be bonded by a hybrid bonding method.

[0036] The semiconductor die stack structure 101 may include a plurality of middle dies 50 and a top die 60 stacked over a base bottom die stack structure 30. The middle dies 50 and the top die 60 may be stacked on a back side of the base die 10 of the base bottom die stack structure 30 facing downward.

[0037] The bottom die 20 may be disposed at the lowest portion of the semiconductor die stack structure 101. The bottom die 20 may include a bottom die substrate 21, a bottom die front side passivation layer 22, a bottom die through electrode 23, a bottom die front side bonding dielectric layer 25, a bottom die front side bonding pad structure 28, a bottom die back side passivation layer 72, and a bottom die back side bump structure 77. The bottom die 20 may not include active circuit elements. In other words, transistors may not be formed on the upper surface or the lower surface of the bottom die substrate 21. The bottom die substrate 21 may include a silicon wafer. The bottom die front side passivation layer 22 may be uniformly disposed on the upper surface of the bottom die substrate 21. The bottom die back side passivation layer 72 may be uniformly disposed below the lower surface of the bottom die substrate 21. The bottom die front side passivation layer 22 and the bottom die back side passivation layer 72 may include an inorganic dielectric layer based on silicon nitride or an inorganic dielectric layer based on silicon oxide. The bottom die through electrode 23 may vertically penetrate or pass through the bottom die substrate 21, the bottom die front side passivation layer 22, and the bottom die back side passivation layer 72. The bottom die through electrode 23 may include copper (Cu). The upper surface of the bottom die through electrode 23 may be exposed. The upper surface of the bottom die through electrode 23 and the upper surface of the bottom die front side passivation layer 22 may be coplanar. The bottom die front side passivation layer 22 may surround the side surface of the upper end of the bottom die through electrode 23. The lower surface of the bottom die through electrode 23 may be exposed. The lower surface of the bottom die through electrode 23 and the lower surface of the bottom die back side passivation layer 72 may be coplanar. The bottom die back side passivation layer 72 may surround the side surface of the lower end of the bottom die through electrode 23. The bottom die front side bonding dielectric layer 25 and the bottom die front side bonding pad structure 28 may be disposed above the bottom die front side passivation layer 22. The bottom die front side bonding dielectric layer 25 may cover the side surface of the bottom die front side bonding pad structure 28. The upper surface of the bottom die front side bonding dielectric layer 25 and the upper surface of the bottom die front side bonding pad structure 28 may be coplanar. The bottom die front side passivation layer 22 may include at least one of a silicon oxide-based inorganic dielectric layer, a silicon nitride-based inorganic dielectric layer, or a silicon carbonitride-based inorganic dielectric layer. The bottom die front side bonding pad structure 28 may include a bottom die front side bonding pad seed layer 26 and a bottom die front side bonding pad metal 27. The bottom die front side bonding pad seed layer 26 may include a lower bottom die front side bonding pad seed layer including at least one of titanium (Ti), titanium nitride (TiN), or titanium tungsten (TiW), and an upper bottom die front side bonding pad seed layer including copper (Cu). The bottom die front side bonding pad metal 27 may include copper (Cu). The bottom die front side bonding pad seed layer 26 may surround the bottom die front side bonding pad metal 27 in a U-shape or a bowl shape. The bottom die front side bonding pad structure 28 may be electrically connected to the bottom die through electrode 23. The bottom die back side bump structure 77 may be disposed under the lower surface of the bottom die back side passivation layer 72.The bottom die backside bump structure 77 may be electrically connected to the bottom die through-electrode 23. The bottom die backside bump structure 77 may include a bottom die backside UBM layer 74 and bottom die backside bumps 75 and 76. The bottom die backside bumps 75 and 76 may include a bottom die backside bump metal 75 and a bottom die backside bump solder 76. The bottom die backside UBM layer 74 may be disposed directly below the lower surface of the bottom die backside passivation layer 72. The bottom die backside bump metal 75 may be disposed below the bottom die backside UBM layer 74. The bottom die backside bump solder 76 may be disposed below the bottom die backside bump metal 75.

[0038] The base die 10 may be stacked face-down over the bottom die 20. In other words, the active surface (i.e., the front side of the base die 10) may be disposed downward to face the bottom die 20. The base die 10 may include a base die substrate 11, a base die circuit element 12, a base die interlayer dielectric layer 13, a base die front side bonding dielectric layer 15, a base die front side bonding pad structure 18, a base die back side passivation layer 32, a base die through electrode 33, and a base die back side bump structure 37. The base die front side bonding pad structure 18 may include a base die front side bonding pad seed layer 16 and a base die front side bonding pad metal 17. The base die back side bump structure 37 may include a base die back side UBM layer 34 and base die back side bumps 35 and 36. The base die back side bumps 35 and 36 may include a base die back side bump metal 35 and a base die back side bump capping layer 36 .

[0039] The base die substrate 11 may include a silicon wafer. The base die circuit element 12 may include a base die transistor 12a, a base die metal interconnect 12b, a base die metal via 12c, and a base die metal pad 12d. For example, the base die circuit element 12 may include a memory peripheral logic circuit. The base die transistor 12a may be disposed on the active side of the base die substrate 11. The base die metal interconnect 12b may transmit an electrical signal by extending in a horizontal direction. The base die metal interconnect 12b may be connected to the base die through electrode 33. The base die metal via 12c may extend in a vertical direction to electrically connect the base die substrate 11, the base die transistor 12a, the base die metal interconnect 12b, and the base die metal pad 12d. The base die interlayer dielectric layer 13 may cover the base die circuit element 12. The base die interlayer dielectric layer 13 may include at least one of a silicon oxide-based dielectric layer or a silicon nitride-based dielectric layer. The base die metal pad 12d may be disposed adjacent to the upper surface of the base die interlayer dielectric layer 13. For example, the base die interlayer dielectric layer 13 may expose a portion of the surface of the base die metal pad 12d. The base die front side bonding dielectric layer 15 may be disposed below the unexposed surface of the base die interlayer dielectric layer 13 and the base die metal pad 12d. The base die front side bonding dielectric layer 15 may include at least one of a silicon oxide-based inorganic dielectric layer, a silicon nitride-based inorganic dielectric layer, or a silicon carbonitride-based inorganic dielectric layer. The base die front side bonding dielectric layer 15 and the bottom die front side bonding dielectric layer 25 may be in direct contact with each other. The base die front side bonding pad structure 18 may include a base die front side bonding pad seed layer 16 and a base die front side bonding pad metal 17. The base die front side bonding pad seed layer 16 may surround the lower surface (front side) and side surface of the base die front side bonding pad metal 17 in a (flipped) U-shape, n-shape or (flipped) bowl shape. The base die front side bonding pad seed layer 16 may include a lower base die front side bonding pad seed layer including at least one of titanium (Ti), titanium nitride (TiN) or titanium tungsten (TiW) and an upper base die front side bonding pad seed layer including copper (Cu). The base die front side bonding pad metal 17 may include a metal, such as copper (Cu) or nickel (Ni). The base die front side bonding pad structure 18 and the bottom die front side bonding pad structure 28 may be in direct contact with each other. The base die back side passivation layer 32 may be conformally disposed on the back side of the base die substrate 11. The base die back side passivation layer 32 may include a silicon oxide-based inorganic dielectric layer or a silicon nitride-based inorganic dielectric layer. The base die through electrode 33 may completely pass through or penetrate the base die substrate 11 and the base die backside passivation layer 32 and partially pass through or penetrate the base die interlayer dielectric layer 13 to be electrically connected to the base die metal interconnect 12b of the base die circuit element 12. The base die through electrode 33 may include copper (Cu).The base die backside bump structure 37 may be disposed above the base die backside passivation layer 32. The base die backside bump structure 37 may be electrically connected to the base die through-electrode 33. The base die backside UBM layer 34 may include a lower base die backside UBM layer including titanium (Ti) or titanium tungsten (TiW) and an upper base die backside UBM layer including copper (Cu). The base die backside bump metal 35 may include a single metal layer or multiple metal layers of a metal such as nickel (Ni) or copper (Cu). The base die backside bump capping layer 36 may include an oxidation-resistant and corrosion-resistant metal such as gold (Au). The base die 10 and the bottom die 20 may be stacked and bonded by a hybrid bonding method.

[0040] The intermediate die 50 may be stacked above the base die 10. Each intermediate die 50 may include an intermediate die substrate 51, an intermediate die through-electrode 52, an intermediate die front side bump structure 55, and an intermediate die rear side bump structure 57. The intermediate die front side bump structure 55 may include an intermediate die front side bump metal 53 and an intermediate die front side bump solder 54. The intermediate die 50 may be a memory die. For example, the intermediate die 50 may include a memory core circuit. The intermediate die substrate 51 may include a silicon wafer. The intermediate die through-electrode 52 may vertically pass through or penetrate the intermediate die substrate 51 to electrically connect the intermediate die front side bump structure 55 and the intermediate die rear side bump structure 57 to each other. The intermediate die through-electrode 52 may include a conductive metal, such as copper (Cu). The intermediate die front side bump structure 55 may be disposed below the lower surface (front side) of the intermediate die substrate 51. The middle die front side bump structure 55 may include a middle die front side bump metal 53 and a middle die front side bump solder 54. The middle die front side bump metal 53 may include a metal. The middle die front side bump solder 54 may include a solder material. The base die back side bump structure 37 of the base die 10 and the middle die front side bump structure 55 of the lowest middle die 50 may be bonded and joined to each other. For example, the base die back side bump capping layer 36 of the base die back side bump structure 37 of the base die 10 and the middle die front side bump metal 53 of the lowest middle die 50 may be bonded by the middle die front side bump solder 54. The middle die front side bump structure 55 and the middle die back side bump structure 57 of the stacked middle die 50 may contact and join to each other. The middle die front side metal pad may have the same structure as the base die metal pad 12d. For example, the middle die front side metal pad may be disposed adjacent to the upper surface of the middle die interlayer dielectric layer over the middle die substrate 51. The middle die front side bump UBM layer may have the same structure as the base die back side UBM layer 34. For example, the middle die back side bump structure 57 may include the same structure as the base die back side bump structure 37.

[0041] The top die 60 may include a top die substrate 61 and a top die front side bump structure 65. The top die substrate 61 may have the same structure as the structure of the middle die substrate 51. For example, the top die substrate 61 may also be a memory die. Therefore, the top die 60 may also include a memory core circuit. The top die front side bump structure 65 may be disposed below the lower surface (front side) of the top die substrate 61. The top die front side bump structure 65 may include a top die front side bump metal 63 and a top die front side bump solder 64. The top die front side bump structure 65 may be the same as the middle die front side bump structure 55. The top die front side bump structure 65 of the top die 60 may directly contact and bond to the middle die back side bump structure 57 of the middle die 50 stacked on the uppermost portion of the middle die 50.

[0042] The semiconductor die stack structure 101 may further include an encapsulant 90 surrounding the middle die 50 and the top die 60 over the base die backside passivation layer 32 of the base die 10. The encapsulant 90 may include an epoxy molding compound. The base die 10 and the bottom die 20 may have the same horizontal width W1. The middle die 50 and the top die 60 may have the same horizontal width W2. The horizontal width W1 of the base die 10 and the bottom die 20 may be greater than the horizontal width W2 of the middle die 50 and the top die 60. Therefore, the molding material 90 may be formed over the base die backside passivation layer 32 over the back side BS1 of the base die substrate 11 to encapsulate the side surfaces of the middle die 50 and the top die 60. The two side surfaces of the base die 10, the two side surfaces of the bottom die 20, and the two side surfaces of the molding material 90 may be vertically coplanar.

[0043] FIG. 6A to FIG. 6G A method of manufacturing a semiconductor die stack structure 102 according to another embodiment of the present disclosure using a base bottom die stack structure 30 , a middle die 50 , and a top die 60 according to an embodiment of the present disclosure is shown.

[0044] Reference Fig. 6A The method may further include: executing reference FIG. 5A to FIG. 5C The process described above includes forming a preliminary bottom die backside pad UBM layer 78p over the bottom die backside passivation layer 72; forming a plating mask pattern M1 over the preliminary bottom die backside pad UBM layer 78p; and forming a bottom die backside pad 79. The plating mask pattern M1 may have a hole H5 exposing the upper end of the bottom die through-electrode 23. The bottom die backside pad 79 may be formed over the preliminary bottom die backside pad UBM layer 78p to fill the lower portion of the hole H5. The bottom die backside pad 79 may include copper (Cu) or nickel (Ni) formed by performing a plating process.

[0045] Reference Figure 6BThe method may further include removing the plating mask pattern M1 and removing the exposed preliminary bottom die backside pad UBM layer 78p. A portion of the preliminary bottom die backside pad UBM layer 78p may form a remaining bottom die backside pad UBM layer 78 below the bottom die backside pad 79. A portion of the upper surface of the bottom die backside passivation layer 72 may be exposed.

[0046] Reference Figure 6C The method may further include forming a bottom die top backside passivation layer 73 over the bottom die backside passivation layer 72. The bottom die top backside passivation layer 73 may include an inorganic dielectric material such as silicon oxide or silicon nitride and / or a polymer organic material such as polyimide-isoindene-quinazolinedione (PIQ). The bottom die top backside passivation layer 73 may have a hole H6 exposing the surface of the bottom die backside pad 79.

[0047] Reference Fig.6D The method may further include: forming a preliminary bottom die backside UBM layer 74p over the exposed surface of the bottom die top backside passivation layer 73 and the bottom die backside pad 79; and forming a plating mask pattern M2 having a hole H7 vertically overlapping the bottom die backside pad 79.

[0048] Reference Fig. 6E , the method may include forming a bottom die back bump metal 75 by performing a plating process. The bottom die back bump metal 75 may have a multilayer structure. For example, the bottom die back bump metal 75 may include a lower bottom die back bump metal 75a, an intermediate bottom die back bump metal 75b, and an upper bottom die back bump metal 75c, respectively. According to one embodiment of the present disclosure, the lower bottom die back bump metal 75a and the upper bottom die back bump metal 75c may include the same metal. For example, the lower bottom die back bump metal 75a and the upper bottom die back bump metal 75c may include copper (Cu). The intermediate bottom die back bump metal 75b may include a metal different from the lower bottom die back bump metal 75a and the upper bottom die back bump metal 75c. For example, the intermediate bottom die back bump metal 75b may include nickel (Ni). In an embodiment, a multi-layered bump structure including a copper (Cu) layer and a nickel (Ni) layer may be suitable for forming a bump structure having a sufficient thickness. In an embodiment, nickel (Ni) may provide hardness and anti-corrosion properties to the bump structure.

[0049] Reference Fig. 6F, the method may further include: forming a bottom die backside bump solder 76 over the bottom die backside bump metal 75; removing the plating mask pattern M2; and forming a preliminary bottom die backside UBM layer 74p exposed under the plating mask pattern M2. A bottom die backside bump structure 77 including a bottom die backside UBM layer 74 and bottom die backside bumps 75 and 76, respectively, may be formed. The bottom die backside bumps 75 and 76 may include a bottom die backside bump metal 75 and a bottom die backside bump solder 76.

[0050] Reference Figure 6G The method may further include manufacturing the semiconductor die stack structure 102 by performing a singulation process.

[0051] The semiconductor die stack structure 102 may include a plurality of middle dies 50 and top dies 60 stacked over a base bottom die stack structure 30. The middle dies 50 and top dies 60 may be stacked on a back side of the base die 10 of the base bottom die stack structure 30 facing downward.

[0052] The bottom die 20 may be disposed at the lowest portion of the semiconductor die stack structure 102. The bottom die 20 may include a bottom die substrate 21, a bottom die front side passivation layer 22, a bottom die through electrode 23, a bottom die front side bonding dielectric layer 25, a bottom die front side bonding pad structure 28, a bottom die back side passivation layer 72, a bottom die top back side passivation layer 73, a bottom die back side pad UBM layer 78, a bottom die back side pad 79, and a bottom die back side bump structure 77.

[0053] The bottom die top backside passivation layer 73 may be disposed below the lower surface of the bottom die backside passivation layer 72. The bottom die top backside passivation layer 73 may include an inorganic dielectric material such as silicon oxide or silicon nitride and / or a polymer organic material such as polyimide-isoindene-quinazolinedione (PIQ). The bottom die top backside passivation layer 73 may surround the sides of the bottom die backside pad UBM layer 78 and the bottom die backside pad 79.

[0054] The bottom die backside pad UBM layer 78 and the bottom die backside pad 79 may be disposed below the lower surface of the bottom die backside passivation layer 72. The bottom die backside pad UBM layer 78 and the bottom die backside pad 79 may be electrically connected to the bottom die through-electrode 23. The bottom die backside pad UBM layer 78 may include a lower bottom die backside pad UBM layer including titanium (Ti) or titanium tungsten (TiW) and an upper bottom die backside pad UBM layer including copper (Cu). The bottom die backside pad 79 may include copper (Cu) or nickel (Ni). According to one embodiment of the present disclosure, the bottom die backside pad 79 may include a copper (Cu) layer and a nickel (Ni) layer formed above the copper (Cu) layer. According to one embodiment of the present disclosure, the bottom die backside pad 79 may include a copper (Cu) layer and a capping metal layer above the copper (Cu) layer. The capping metal layer may include an oxidation-resistant or corrosion-resistant metal. For example, the capping metal layer may include gold (Au).

[0055] The bottom die backside bump structure 77 may be disposed below the bottom die backside pad 79 and the lower surface of the bottom die top backside passivation layer 73. The bottom die backside bump structure 77 may contact the bottom die backside pad 79. The bottom die backside bump structure 77 may include a bottom die backside UBM layer 74 and bottom die backside bumps 75 and 76. The bottom die backside bumps 75 and 76 may include a bottom die backside bump metal 75 and a bottom die backside bump solder 76. The bottom die backside UBM layer 74 may include a lower bottom die backside UBM layer such as titanium (Ti) or titanium nitride (TiN) and an upper bottom die backside UBM layer such as copper (Cu). The bottom die backside bump metal 75 may include a single metal layer or multiple metal layers including a metal such as copper (Cu) or nickel (Ni). According to one embodiment of the present disclosure, the bottom die back bump metal 75 may include a lower bottom die back bump metal 75a including copper (Cu), a middle bottom die back bump metal 75b including nickel (Ni), and an upper bottom die back bump metal 75c including copper (Cu). The bottom die back bump solder 76 may be disposed under the bottom die back bump metal 75. The bottom die back bump solder 76 may include a solder material. The constituent elements of the undescribed reference numerals may refer to Fig. 5F Come to understand.

[0056] 7A to 10F A method for manufacturing a semiconductor die stack structure according to an embodiment of the present disclosure is shown. Fig. 9B 103 and Fig.11A 104) method. 7A to 10F , manufacturing semiconductor die stacking structure ( Fig. 9B 103 and Fig.11AThe method 104) in may include: preparing a base die 10; preparing a bottom die 40; forming and preparing a base bottom die stacking structure 80 by bonding the base die 10 and the bottom die 40; preparing an intermediate die 50 and a top die 60; stacking the intermediate die 50 and the top die 60 above the base bottom die stacking structure 80; and performing a dicing process.

[0057] Fig. 7A and Figure 7B FIG. 1 shows a method for manufacturing a semiconductor die stack structure ( Fig. 9B The bottom tube core 40 is manufactured and prepared in the method of 103). Fig. 7A , the method may include: forming a bottom die circuit element 42, a bottom die interlayer dielectric layer 43, and a bottom die through-electrode 49 above the front side (active surface) FS5 of the bottom die substrate 41 in a wafer state; and forming a bottom die front side bonding dielectric layer 45 above the bottom die circuit element 42 and the bottom die interlayer dielectric layer 43. The bottom die substrate 41 may include a silicon wafer. The bottom die circuit element 42 may include a bottom die transistor 42a, a bottom die metal interconnect 42b, a bottom die metal via 42c, and a bottom die metal pad 42d. According to one embodiment of the present disclosure, the bottom die circuit element 42 may include a memory cell circuit, such as a memory core circuit (such as a cell group and a decoder circuit block). The bottom die through-electrode 49 may completely pass through the bottom die interlayer dielectric layer 43 and partially pass through the bottom die substrate 41. For example, the first end of the bottom die through electrode 49 may contact some bottom die metal interconnects 42b, and the second end of the bottom die through electrode 49 may be disposed in the bottom die substrate 41. The bottom die front side bonding dielectric layer 45 may include an inorganic dielectric material based on silicon oxide, silicon nitride, or silicon carbonitride. The bottom die front side bonding dielectric layer 45 may include silicon carbonitride. The bottom die front side bonding dielectric layer 45 may have a hole H8 exposing the surface of the bottom die metal pad 42d.

[0058] Reference Figure 7B , the method may further include forming a bottom die front side bonding pad structure 48 on the surface of the bottom die metal pad 42d exposed in the hole H8. The bottom die front side bonding pad structure 48 may be vertically aligned with the bottom die metal pad 42d and the bottom die through electrode 49 above the bottom die metal pad 42d, respectively. Each bottom die front side bonding pad structure 48 may include a bottom die front side bonding pad seed layer 46 and a bottom die front side bonding pad metal 47. Each bottom die front side bonding pad seed layer 46 may surround the bottom surface and the side surface of each bottom die front side bonding pad metal 47 in a U-shape.

[0059] FIG. 8A to FIG. 8HIn the method of manufacturing the semiconductor die stack structure 103 according to an embodiment of the present disclosure, the base die 10 and the bottom die 40 are bonded (eg, Fig. 8A A plurality of basic bottom die stack structures 80 are formed and prepared (as indicated by the arrows in FIG. 8 ).

[0060] Reference Fig. 8A , the method may also include bonding a plurality of base tube cores 10 and a plurality of bottom tube cores 40 in a wafer-to-wafer manner. For example, the method may also include placing the bottom tube core 40 face up and bonding the base tube core 10 facing down to the bottom tube core 40. The base tube core 10 and the bottom tube core 40 can be connected to each other by a hybrid bonding method. Each base tube core front side bonding pad structure 18 and each bottom tube core front side bonding pad structure 48 can be directly contacted and bonded to each other by heat. The base tube core front side bonding dielectric layer 15 and the bottom tube core front side bonding dielectric layer 45 can be directly contacted and bonded to each other by surface activation treatment.

[0061] Reference Figure 8B The method may further include thinning the back side (inactive surface) of the base die substrate 11 of the base bottom die stack structure 80 by performing a back grinding process (as indicated by the arrows shown).

[0062] Reference Figure 8C (and Figure 8B ), the method may further include forming a base die backside passivation layer 32 and forming a hole H9 over the thinned backside BS1 of the base die substrate 11. The hole H9 may vertically penetrate the thinned base die substrate 11 to selectively partially expose the base die metal interconnect 12b.

[0063] Reference Fig.8D The method may further include forming a base die through electrode 33 in the hole H9.

[0064] Reference Fig. 8E , the method may further include forming a base die backside bump structure 37'. The method may further include forming a base die backside UBM layer 34 and base die backside bumps 35 and 36' so that the base die backside bump structure 37' is coupled to the base die through-electrode 33 over the base die backside passivation layer 32. Forming the base die backside bumps 35 and 36' may include forming a base die backside bump metal 35 and a base die backside bump solder 36'.

[0065] Reference Fig.8F The method may also include mounting the base bottom die stack structure 80 above the wafer support system WSS so that the base die 10 is disposed underneath, and performing a back grinding process (as indicated by the arrow) to thin the back side of the bottom die 40 and expose the end of the bottom die through-electrode 49.

[0066] Reference Figure 8G The method may further include forming a bottom die backside passivation layer 82 over the thinned back side BS4 of the bottom die 40, and co-planarizing an upper surface of the bottom die backside passivation layer 82 and an upper end of the bottom die through-electrode 49. The bottom die backside passivation layer 82 may include a dielectric material including silicon nitride or silicon oxide.

[0067] Reference Figure 8H , the method may further include forming a bottom die back side bump structure 87 on the upper surface of the bottom die back side passivation layer 82 and above the upper end of the bottom die through electrode 49. Each bottom die back side bump structure 87 may include a bottom die back side UBM layer 84 and bottom die back side bumps 85 and 86. The bottom die back side bumps 85 and 86 may include a bottom die back side bump metal 85 and a bottom die back side bump capping layer 86. The bottom die back side UBM layer 84 may include a lower bottom die UBM layer including titanium (Ti) or titanium tungsten (TiW) and an upper bottom die UBM layer including copper (Cu). The bottom die back side bump metal 85 may include nickel (Ni) and / or copper (Cu). The bottom die back side bump capping layer 86 may include an oxidation resistant metal such as gold (Au).

[0068] Fig. 9A A semiconductor die stack structure 103 is shown fabricated using a base bottom die stack structure 80 , a middle die 50 , and a top die 60 in accordance with an embodiment of the present disclosure.

[0069] Reference Fig. 9A The method may further include stacking a plurality of middle dies 50 and top dies 60 over the base bottom die stack structure 80 in a chip-to-wafer manner as indicated by arrows.

[0070] Reference Fig. 9B, the method may further include forming a preliminary base bottom die stacking structure by molding the intermediate die 50 and the top die 60 with the encapsulant 90, and manufacturing a semiconductor die stacking structure 103 by dicing the preliminary base bottom die stacking structure. The semiconductor die stacking structure 103 may include a plurality of intermediate dies 50 and a top die 60 stacked above the base die 10 and the bottom die 40 bonded face to face. The semiconductor die stacking structure 103 may include a bottom die 40, an intermediate die 50, and a top die 60 stacked directly face-down above the base die 10 disposed face-up. The base die 10 and the bottom die 40 may have the same horizontal width W3. The intermediate die 50 and the top die 60 may have the same horizontal width W4. The horizontal width W3 of the base die 10 and the bottom die 40 may be greater than the horizontal width W4 of the intermediate die 50 and the top die 60. Therefore, the molding material 90 may be formed over the bottom die backside passivation layer 82 of the backside BS5 of the bottom die 40 to encapsulate the side surfaces of the middle die 50 and the top die 60. Both side surfaces of the base die 10, both side surfaces of the bottom die 40, and both side surfaces of the molding material 90 may be vertically coplanar.

[0071] The base die 10 may be disposed at the lowest portion of the semiconductor die stack structure 103 in a face-up manner. The base die 10 may include a base die substrate 11, a base die circuit element 12, a base die interlayer dielectric layer 13, a base die front side bonding dielectric layer 15, a base die front side bonding pad structure 18, a base die back side passivation layer 32, a base die through electrode 33, and a base die back side bump structure 37'. The base die front side bonding pad structure 18 may include a base die front side bonding pad seed layer 16 and a base die front side bonding pad metal 17. The base die back side bump structure 37' may include a base die back side UBM layer 34 and base die back side bumps 35 and 36. The base die back side bumps 35 and 36 may include a base die back side bump metal 35 and a base die back side bump solder 36'. The base die backside bump solder 36 ′ may include a solder material.

[0072] The bottom die 40 may include a bottom die substrate 41, a bottom die circuit element 42, a bottom die interlayer dielectric layer 43, a bottom die front side bonding dielectric layer 45, a bottom die front side bonding pad structure 48, a bottom die through electrode 49, a bottom die back side passivation layer 82, and a bottom die back side bump structure 87. The bottom die front side bonding pad structure 48 may include a bottom die front side bonding pad seed layer 46 and a bottom die front side bonding pad metal 47. The bottom die back side bump structure 87 may include a bottom die back side UBM layer 84 and bottom die back side bumps 85 and 86. The bottom die back side bumps 85 and 86 may include a bottom die back side bump metal 85 and a bottom die back side bump capping layer 86. The bottom die circuit element 42 may include a bottom die transistor 42a, a bottom die metal interconnect 42b, a bottom die metal via 42c, and a bottom die metal pad 42d. For example, the bottom die circuit element 42 may include a memory cell group, a memory core circuit, or a decoder circuit block. The bottom die transistor 42a may be disposed on the active side of the bottom die substrate 41. The bottom die metal interconnect 42b may transmit an electrical signal by extending in a horizontal direction. The bottom die metal interconnect 42b may be connected to the bottom die through electrode 49. The bottom die metal via 42c may extend in a vertical direction to electrically connect the bottom die substrate 41, the bottom die transistor 42a, the bottom die metal interconnect 42b, and the bottom die metal pad 42d to each other. The bottom die interlayer dielectric layer 43 may cover the bottom die circuit element 42. The bottom die interlayer dielectric layer 43 may include a silicon oxide-based dielectric material or a silicon nitride-based dielectric material. The bottom die metal pad 42d may be disposed adjacent to the upper surface of the bottom die interlayer dielectric layer 43. For example, the bottom die interlayer dielectric layer 43 may expose a portion of the surface of the bottom die metal pad 42d. The bottom die front side bonding dielectric layer 45 may be disposed below the unexposed surface of the bottom die interlayer dielectric layer 43 and the bottom die metal pad 42d. The bottom die through electrode 49 may completely vertically pass through or penetrate the bottom die substrate 41 and the bottom die back side passivation layer 82 and partially vertically pass through or penetrate the bottom die interlayer dielectric layer 43 to electrically connect the bottom die metal interconnect 42b to the bottom die back side bump structure 87. The bottom die through electrode 49 may include a metal such as copper (Cu). The bottom die back side passivation layer 82 may be disposed on the inactive surface (back side) of the bottom die substrate 41. The bottom die back side passivation layer 82 may surround the side surface of the upper end of the bottom die through electrode 49. The bottom die backside UBM layer 84 may include a lower bottom die UBM layer including titanium (Ti) or titanium tungsten (TiW) and an upper bottom die UBM layer including copper (Cu). The bottom die backside bump metal 85 may include nickel (Ni) and / or copper (Cu). The bottom die backside bump capping layer 86 may include an oxidation resistant metal such as gold (Au).

[0073] The base die 10 and the bottom die 40 may be bonded by a hybrid bonding method. The base die front side bonding pad structure 18 of the base die 10 and the bottom die front side bonding pad structure 48 of the bottom die 40 may be in direct contact with each other. The base die front side bonding dielectric layer 15 of the base die 10 and the bottom die front side bonding pad structure 48 of the bottom die 40 may be in direct contact with each other. The middle die front side bump structure 55 of the middle die 50 and the bottom die back side bump structure 87 of the bottom die 40 may be bonded. The constituent elements not described by reference numerals may be referred to. Fig. 5F and Figure 6G Come to understand.

[0074] FIG. 10A to FIG. 10F FIG. 1 shows a method for manufacturing a semiconductor die stack structure ( Fig.11A In the method 104) in the embodiment of the present invention, a plurality of base bottom die stack structures 80 are manufactured and prepared by bonding the base die 10 and the bottom die 40.

[0075] Reference Fig. 10A The method may further include: by executing reference FIG. 8A to FIG. 8D The process described above is used to form a preliminary semiconductor stack structure; forming a preliminary base die backside bump pad UBM layer 31p over the base die backside passivation layer 32; forming a plating mask pattern M3; and forming a base die backside bump pad 38. The preliminary base die backside bump pad UBM layer 31p may include a lower preliminary base die backside bump pad UBM layer including titanium (Ti) or titanium tungsten (TiW) and an upper preliminary base die backside bump pad UBM including copper (Cu). The plating mask pattern M3 may have a hole H10 vertically aligned with respect to the bottom die through electrode 33. The base die backside bump pad 38 may be formed by performing a plating process over the preliminary base die backside bump pad UBM layer 31p to fill the lower portion of the hole H10. The base die backside bump pad 38 may include copper (Cu) or nickel (Ni). According to one embodiment of the present disclosure, the base die backside bump pad 38 may be formed of a single layer or multiple layers including a copper (Cu) layer and / or a nickel (Ni) layer. According to another embodiment of the present disclosure, the base die backside bump pad 38 may include a copper (Cu) layer and a capping metal layer formed above the copper (Cu) layer. The capping metal layer may include an anti-oxidation and anti-corrosion metal such as gold (Au). Subsequently, the plating mask pattern M3 may be removed.

[0076] Reference Fig. 10B, the method may further include: removing the plating mask pattern M3; removing the preliminary bottom die backside pad UBM layer 78p exposed under the plating mask pattern M3; and forming a base die top backside passivation layer 39 over the base die backside passivation layer 32. A portion of the preliminary base die backside bump pad UBM layer 31p may form a remaining base die backside bump pad UBM layer 31 under the base die backside bump pad 38. The base die top backside passivation layer 39 may have a hole H11 exposing the base die backside bump pad 38.

[0077] Reference Fig. 10C The method may further include: forming a preliminary base die backside UBM layer 34p over the exposed surface of the base top backside passivation layer 39 and the base die backside bump pad 38; and forming a plating mask pattern M4 having a hole H12 vertically overlapping the base die backside bump pad 38.

[0078] Reference Fig. 10D , the method may further include forming a base die back bump 35 by performing a plating process. The base die back bump 35 may have a multilayer structure. For example, it may include a bottom base die back bump 35a, an intermediate base die back bump 35b, and a top base die back bump 35c. According to one embodiment of the present disclosure, the bottom base die back bump 35a and the top base die back bump 35c may include the same metal. For example, the bottom base die back bump 35a and the top base die back bump 35c may include copper (Cu). The intermediate base die back bump 35b may include a metal different from the bottom base die back bump 35a and the top base die back bump 35c. For example, the intermediate base die back bump 35b may include nickel (Ni).

[0079] Reference Fig. 10E , the method may further include: forming a base die backside bump solder 36' over the base die backside bump 35; removing the plating mask pattern M4; and removing the preliminary base die backside UBM layer 34p exposed under the plating mask pattern M4. A base die backside bump structure 37' including a base die backside UBM layer 34 and base die backside bumps 35 and 36 may be formed. The base die backside bumps 35 and 36 may include a base die backside bump metal 35 and a base die backside bump solder 36'. Some base die backside bump pads 38 may be exposed.

[0080] Reference Fig.10F The method may further include executing a reference FIG. 8F to FIG. 8H The process described is used to form the bottom die backside bump structure 87 .

[0081] Fig.11Ashows a semiconductor die stack structure 104 fabricated using a base bottom die stack structure 80 , a middle die 50 , and a top die 60 , according to one embodiment of the present disclosure, Fig. 11B yes Fig.11A An enlarged view of a portion of semiconductor die stack structure 104 is shown.

[0082] Reference Fig.11A and Fig. 11B The method may further include executing a reference Fig. 9A and Fig. 9B The semiconductor die stacking structure 104 may be fabricated by the process described. The semiconductor die stacking structure 104 may include a plurality of middle dies 50 and a top die 60 stacked over a base die 10 and a bottom die 40 bonded in a face-to-face manner. The semiconductor die stacking structure 104 may include a bottom die 40, middle die 50, and top die 60 stacked in a face-down manner directly over a base die 10 disposed in a face-up manner.

[0083] The base die 10 may be disposed face-up at the lowest portion of the semiconductor die stack structure 104. The base die 10 may include a base die substrate 11, a base die circuit element 12, a base die interlayer dielectric layer 13, a base die front side bonding dielectric layer 15, a base die front side bonding pad structure 18, a base die back side passivation layer 32, a base top back side passivation layer 39, a base die through electrode 33, and a base die back side bump structure 37'. The base die back side bump structure 37' may include a base die back side UBM layer 34 and base die back side bumps 35 and 36'. The base die back side bumps 35 and 36' may include a base die back side bump metal 35 and a base die back side bump solder 36'. The base die backside UBM layer 34 may include a lower base die backside UBM layer such as titanium (Ti) or titanium nitride (TiN) and an upper base die backside UBM layer such as copper (Cu). The base die backside bump metal 35 may include a bottom base die backside bump 35a, an intermediate base die backside bump 35b, and a top base die backside bump 35c. The bottom base die backside bump 35a and the top base die backside bump 35c may include copper (Cu). The intermediate base die backside bump 35b may include nickel (Ni). The base die backside bump solder 36' may include a solder material. The constituent elements of the undescribed reference numerals may refer to Fig. 5F , Figure 6G and Fig. 9B Come to understand.

[0084] According to an embodiment of the present disclosure, a semiconductor die stacking structure manufactured by a wafer-to-wafer bonding process can be provided. In an embodiment, after performing the wafer-to-wafer bonding process, a thinning process can be performed to provide a thin substrate and a short via structure. Therefore, the semiconductor die stacking structure in the embodiment can be provided with processable excellent electrical characteristics.

[0085] While the present disclosure has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the following claims.

[0086] CROSS-REFERENCE TO RELATED APPLICATIONS

[0087] This application claims the benefit of Korean Patent Application No. 10-2023-0090631 filed on July 12, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a semiconductor die stack structure, the method comprising the following steps: Prepare a base tube core including a base tube core substrate and a base tube core interlayer dielectric layer; forming a base die front side bonding pad structure above the base die interlayer dielectric layer; preparing a bottom die having a bottom die substrate and a bottom die through-electrode; forming a bottom die front side bonding pad structure over the front side of the bottom die substrate; forming a base bottom die stack structure in which the bottom die front side bonding pad structure and the base die front side bonding pad structure are in direct contact with each other by bonding the bottom die and the base die; forming a base die through electrode vertically penetrating the base die substrate and electrically connected to the base die front side bonding pad structure; forming a base die backside bump structure electrically connected to the base die through-electrode over the backside of the base die substrate; stacking a plurality of intermediate dies over the base die of the base bottom die stack structure; stacking a top die over the plurality of middle dies; as well as A bottom die backside bump structure electrically connected to the bottom die through-electrode is formed.

2. The method according to claim 1, in, The base die also includes a base die circuit element disposed above the base die substrate, The base die circuit elements include base die transistors, base die metal interconnects, base die metal pads and base die metal vias, and Wherein, the base die front side bonding pad structure is formed above the base die metal pad.

3. The method according to claim 1, further comprising the steps of: forming a base die front side bonding dielectric layer over the base die interlayer dielectric layer; as well as forming a bottom die front side bonding dielectric layer over the front side of the bottom die substrate, Wherein, the base die front side bonding dielectric layer and the bottom die front side bonding dielectric layer are in direct contact with each other.

4. The method according to claim 3, wherein: The steps of forming the base die front side bonding pad structure include: forming a hole in the base die front side bonding dielectric layer to expose a base die metal pad; conformally forming a base die front side bond pad seed layer in the hole; forming a base die front side bond pad metal over the base die front side bond pad seed layer to fill the hole; and An upper surface of the base die front side bonding dielectric layer, an upper surface of the base die front side bonding pad seed layer, and an upper surface of the base die front side bonding pad metal are planarized.

5. The method according to claim 3, wherein: The steps of forming the bottom die front side bonding pad structure include: forming a hole in the bottom die front side bonding dielectric layer exposing the bottom die substrate; forming a bottom die front side bond pad seed layer in the hole; forming a bottom die front side bond pad metal over the bottom die front side bond pad seed layer to fill the hole; and An upper surface of the bottom die front side bonding dielectric layer, an upper surface of the bottom die front side bonding pad seed layer, and an upper surface of the bottom die front side bonding pad metal are planarized.

6. The method according to claim 1, wherein: The steps of forming the backside bump structure of the basic tube die include: exposing ends of the base die through-electrodes by thinning the base die substrate of the base die of the base bottom die stack structure; forming a base die backside under bump metallurgy (UBM) layer over the exposed end of the base die through-electrode; and A base die backside bump is formed over the base die backside UBM layer.

7. The method according to claim 1, wherein: The steps of forming the bottom die backside bump structure include: thinning the bottom die substrate to expose ends of the bottom die through-electrodes; and A bottom die backside bump is formed over the exposed end of the bottom die through-electrode.

8. The method according to claim 1, wherein: The steps of forming the bottom die backside bump structure include: thinning the bottom die substrate to expose ends of the bottom die through-electrodes; forming a bottom die backside pad over the exposed end of the bottom die through-electrode; forming a bottom die top backside passivation layer having a hole exposing an upper surface of the bottom die backside pad over the bottom die backside passivation layer; forming a bottom die backside UBM layer in the hole of the bottom die top backside passivation layer; and A bottom die backside bump is formed over the bottom die backside UBM layer to fill the hole.

9. The method according to claim 1, wherein: The semiconductor die stacking structure comprises: the bottom die disposed face-up; the base die disposed face-down over the bottom die; and The middle die and the top die are disposed face-down over the base die, and Each of the bottom die and the base die has a first horizontal width, and Each of the middle die and the top die has a second horizontal width, and The first horizontal width is greater than the second horizontal width.

10. A method for manufacturing a semiconductor die stack structure, the method comprising the following steps: preparing a base die having a base die substrate and a base die interlayer dielectric layer; forming a base die front side bonding pad structure above the base die interlayer dielectric layer; preparing a bottom die having a bottom die substrate and a bottom die through-electrode; forming a bottom die front side bonding pad structure over the front side of the bottom die substrate; forming a base bottom die stack structure in which the bottom die front side bonding pad structure and the base die front side bonding pad structure are in direct contact with each other by bonding the bottom die and the base die; forming a base die through electrode vertically penetrating the base die substrate and electrically connected to the base die front side bonding pad structure; forming a base die backside bump structure electrically connected to the base die through-electrode over the backside of the base die substrate; forming a bottom die rear bump structure above the base bottom die stack structure; stacking an intermediate die over the bottom die of the base bottom die stack structure; as well as A top die is stacked over the middle die.

11. The method according to claim 10, wherein: The basic tube core also includes: a base die circuit element disposed over the base die substrate, and The base die circuit elements include base die transistors, base die metal interconnects, base die metal pads, and base die metal vias, and Wherein, the base die front side bonding pad structure is formed above the base die metal pad.

12. The method according to claim 10, wherein: The bottom die also includes a bottom die circuit element disposed over the bottom die substrate.

13. The method according to claim 10, further comprising the steps of: forming a base die front side bonding dielectric layer over the base die interlayer dielectric layer; as well as forming a bottom die front side bonding dielectric layer over the front side of the bottom die substrate, Wherein, the base die front side bonding dielectric layer and the bottom die front side bonding dielectric layer are in direct contact with each other.

14. The method according to claim 13, wherein: The steps of forming the base die front side bonding pad structure include: forming a hole in the base die front side bonding dielectric layer to expose a base die metal pad; forming a base die front side bond pad seed layer in the hole; forming a base die front side bond pad metal over the base die front side bond pad seed layer to fill the hole; and An upper surface of the base die front side bonding dielectric layer, an upper surface of the base die front side bonding pad seed layer, and an upper surface of the base die front side bonding pad metal are planarized.

15. The method according to claim 13, wherein: The steps of forming the bottom die front side bonding pad structure include: forming a hole in the bottom die front side bonding dielectric layer exposing the front side of the bottom die substrate; forming a bottom die front side bond pad seed layer in the hole; forming a bottom die front side bond pad metal over the bottom die front side bond pad seed layer to fill the hole; and An upper surface of the bottom die front side bonding dielectric layer, an upper surface of the bottom die front side bonding pad seed layer, and an upper surface of the bottom die front side bonding pad metal are planarized.

16. The method according to claim 10, wherein: The steps of forming the backside bump structure of the basic tube die include: thinning the base die substrate of the base die of the base bottom die stack structure to expose ends of the base die through-electrodes; forming a base die backside under bump metallurgy (UBM) layer over the exposed end of the base die through-electrode; and A base die backside bump is formed over the base die backside UBM layer.

17. The method according to claim 10, wherein: The steps of forming the bottom die backside bump structure include: thinning the bottom die substrate to expose one end of the bottom die through-electrode; forming a bottom die backside UBM layer over the exposed one end of the bottom die through electrode; and A bottom die backside bump is formed over the bottom die backside UBM layer.

18. The method according to claim 10, wherein: The semiconductor die stacking structure comprises: the base die disposed face-up; the bottom die disposed face-down over the base die; and the middle die and the top die disposed face-down over the bottom die, wherein each of the bottom die and the base die has a first horizontal width, wherein each of the middle die and the top die has a second horizontal width, and The first horizontal width is greater than the second horizontal width.

19. A semiconductor die stacking structure, comprising: bottom die; a base die stacked over the bottom die; as well as a middle die and a top die, the middle die and the top die being stacked over the base die, Wherein, the bottom tube core comprises: a bottom die substrate; a bottom die front side bonding pad structure disposed above the front side of the bottom die substrate; a bottom die backside bump structure disposed over a backside of the bottom die substrate; and a bottom die through-electrode that passes through the bottom die substrate and electrically connects the bottom die front side bonding pad structure and the bottom die back side bump structure, and The basic tube core comprises: base die substrate; a base die front side bonding pad structure disposed above the front side of the base die substrate; a base die backside bump structure disposed over the backside of the base die substrate; and a base die through-electrode that passes through the base die substrate and electrically connects the base die front side bonding pad structure and the base die back side bump structure, and The bottom die front side bonding pad structure and the base die front side bonding pad structure are bonded by directly contacting each other.

20. The semiconductor die stack structure according to claim 19, wherein: Each of the intermediate dies comprises: an intermediate die substrate; a middle tube core front side bump structure, the middle tube core front side bump structure is arranged above the front side of the middle tube core substrate; a middle die backside bump structure disposed over the backside of the middle die substrate; and A middle tube die through electrode passes through the middle tube die substrate and electrically connects the middle tube die front side bump structure and the middle tube die back side bump structure.

21. The semiconductor die stack structure according to claim 20, wherein: The middle die front-side bump structure of the middle die stacked in the lowermost portion among the middle dies and the base die back-side bump structure of the base die are bonded by directly contacting each other.

22. The semiconductor die stack structure according to claim 20, wherein: The top die comprises: a top die substrate; and a top die front side bump structure disposed over the front side of the top die substrate, and The middle die backside bump structure of a middle die stacked in an uppermost portion among the middle dies and the top die frontside bump structure of the top die are bonded by directly contacting each other.

23. The semiconductor die stack structure according to claim 19, wherein: The bottom die also includes a bottom die front side bonding dielectric layer disposed over the front side of the bottom die substrate, and wherein the base die further comprises a base die front side bonding dielectric layer disposed above the front side of the base die substrate, and Wherein, the bottom die front side bonding dielectric layer and the base die front side bonding dielectric layer are bonded by directly contacting each other.

24. The semiconductor die stack structure according to claim 19, further comprising: An encapsulant is disposed on the rear side of the base die and surrounds side surfaces of the middle die and side surfaces of the top die.

25. The semiconductor die stack structure according to claim 19, wherein: Each of the bottom die and the base die has a first horizontal width, Each of the middle die and the top die has a second horizontal width, and The first horizontal width is greater than the second horizontal width.

26. The semiconductor die stack structure according to claim 19, wherein: The basic tube core also includes: a base die circuit element disposed over the front side of the base die substrate; and a base inter-die dielectric layer surrounding the base die circuit element, and The basic die circuit element comprises: a base die transistor disposed over a front side of the base die substrate; base die metal interconnects and base die metal vias; and base die metal pad, and The base die front side bonding pad structure is formed over the base die metal pad.

27. The semiconductor die stack structure according to claim 19, wherein: The bottom die comprises: a bottom die back side passivation layer, the bottom die back side passivation layer being disposed above the back side of the bottom die; a bottom die back side pad disposed above the bottom die back side passivation layer; and a bottom die top back side passivation layer disposed above the bottom die back side passivation layer and exposing a surface of the bottom die back side pad, and The bottom die backside bump structure is disposed above the exposed surface of the bottom die top backside passivation layer.

28. The semiconductor die stack structure according to claim 19, wherein: The bottom die is arranged face-up, and The base die, the middle die, and the top die are stacked face-down over the bottom die.

29. A semiconductor die stacking structure, comprising: Basic tube core; a bottom die stacked over the base die; as well as a middle die and a top die, the middle die and the top die being stacked over the base die, Wherein, the basic tube core comprises: base die substrate; a base die front side bonding pad structure disposed above the front side of the base die substrate; a base die backside bump structure disposed over the backside of the base die substrate; and a base die through-electrode that passes through the base die substrate and electrically connects the base die front side bonding pad structure and the base die back side bump structure, and The bottom die comprises: a bottom die substrate; a bottom die front side bonding pad structure disposed above the front side of the bottom die substrate; a bottom die backside bump structure disposed over a backside of the bottom die substrate; and a bottom die through-electrode that passes through the bottom die substrate and electrically connects the bottom die front side bonding pad structure and the bottom die back side bump structure, and Wherein, the bottom die front side bonding pad structure and the base die front side bonding pad structure are bonded by directly contacting each other.

30. The semiconductor die stack structure according to claim 29, wherein: Each of the intermediate dies comprises: an intermediate die substrate; a middle tube core front side bump structure, the middle tube core front side bump structure is arranged above the front side of the middle tube core substrate; a middle die backside bump structure disposed over the backside of the middle die substrate; and a middle tube die through electrode, the middle tube die through electrode passing through the middle tube die substrate and electrically connecting the middle tube die front side bump structure and the middle tube die back side bump structure, and The middle die front side bump structure of the middle die stacked in the lowermost portion among the middle dies and the bottom die back side bump structure of the bottom die are bonded by directly contacting each other.

31. The semiconductor die stack structure according to claim 30, wherein: The top die comprises: a top die substrate; and a top die front side bump structure disposed over the front side of the top die substrate, and The middle die backside bump structure of the middle die stacked in the uppermost portion among the middle dies and the top die frontside bump structure of the top die are bonded by directly contacting each other.

32. The semiconductor die stack structure according to claim 29, wherein: The bottom die also includes a bottom die front side bonding dielectric layer disposed over the front side of the bottom die substrate, and wherein the base die further comprises a base die front side bonding dielectric layer disposed above the front side of the base die substrate, and Wherein, the bottom die front side bonding dielectric layer and the base die front side bonding dielectric layer are bonded by directly contacting each other.

33. The semiconductor die stack structure according to claim 29, wherein: Each of the bottom die and the base die has a first horizontal width, and wherein each of the middle die and the top die has a second horizontal width, and The first horizontal width is greater than the second horizontal width.

34. The semiconductor die stack structure according to claim 29, wherein: The basic tube core also includes: a base die circuit element disposed over the front side of the base die substrate; and a base inter-die dielectric layer surrounding the base die circuit element, and The basic die circuit element comprises: a base die transistor disposed over a front side of the base die substrate; base die metal interconnects and base die metal vias; and base die metal pad, and The base die front side bonding pad structure is formed over the base die metal pad.

35. The semiconductor die stack structure according to claim 29, wherein: The bottom die further comprises: a bottom die circuit element disposed over the front side of the bottom die substrate; and a bottom inter-die dielectric layer surrounding the bottom die circuit element, The bottom die circuit element comprises: a bottom die transistor disposed over a front side of the bottom die substrate; bottom die metal interconnects and bottom die metal vias; and bottom die metal pad, and A bottom die front side bump pad structure is formed over the bottom die metal pad.

36. The semiconductor die stack structure according to claim 29, wherein: The basic tube core comprises: A base die back side passivation layer, the base die back side passivation layer is disposed above the back side of the base die; a base die backside pad, the base die backside pad being disposed above the base die backside passivation layer; and a base die top backside passivation layer, the base die top backside passivation layer being disposed above the base die backside passivation layer and exposing a surface of the base die backside pad, and The base die rear bump structure is arranged above the exposed surface of the rear passivation layer on the top of the base die.

37. The semiconductor die stack structure according to claim 29, wherein: The base die is arranged face-up, and The bottom die, the middle die, and the top die are stacked face-down over the bottom die.

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