Method for measuring metal silicide resistance in semiconductor device, polycrystalline silicon size monitoring method and product electrical property monitoring method

Abstract

The invention discloses a method for measuring metal silicide resistance in a semiconductor device, a polycrystalline silicon size monitoring method and a product electrical property monitoring method. The method comprises the following steps: respectively applying a high potential or a low potential to two ends of a square resistor corresponding to the metal silicide, and measuring the total resistance value of the square resistor of the metal silicide; because the total resistance value of the metal silicide square resistor is interfered by the resistor of the ion implantation layer, the total resistance value of the metal silicide square resistor is used as the metal silicide resistor after the interference of the resistor of the ion implantation layer is removed. According to the method, the interference problem of the ion implantation layer is innovatively proposed and is removed through an accurate calculation method, so that the actual resistance value of the metal silicide which is not interfered by the ion implantation layer can be obtained. Compared with a traditional measurement method, the measurement result of the method is more accurate and reliable, and a solid data basis is provided for subsequent polycrystalline silicon size monitoring and semiconductor device performance evaluation.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and in particular relates to a method for measuring the resistance of metal silicide in a semiconductor device, a method for monitoring the size of polysilicon, and a method for monitoring the electrical properties of a product. Background Art

[0002] In the field of semiconductor manufacturing, metal silicide block resistors are a key monitoring tool used to track key process parameters such as the size of polysilicon or monocrystalline silicon active areas and the thickness of metal silicide. These parameters are critical to the performance and reliability of transistors. In order to ensure real-time monitoring and quality control of the process, the manufacturing process of metal silicide block resistors must include the ion implantation step of polysilicon. This step simulates the ion implantation of the source and drain regions in the actual transistor manufacturing process, ensuring the consistency and accuracy of the process.

[0003] In the actual process of manufacturing transistors, ion implantation in the source and drain regions is inevitable, and this process affects polysilicon and monocrystalline silicon. In order to simulate this actual process, ion implantation of polysilicon is also required in the manufacture of metal silicide block resistors. This step helps ensure that the metal silicide block resistor can accurately reflect process changes under different manufacturing conditions.

[0004] Due to the presence of source and drain ion implantation, the actual metal silicide resistance consists of two parallel resistors: one is the resistance of the metal silicide itself, and the other is the resistance of the polysilicon after ion implantation. This structure makes the measurement of the metal silicide block resistance more complicated because ion implantation changes the electrical properties of polysilicon.

[0005] At present, in the measurement of the metal silicide block resistance on the active area and polysilicon gate of MOS devices (Metal-Oxide-Semiconductor Field-Effect Transistor), it is found that the wafer map (wafer-map) of the metal silicide block resistance on different wafers is inconsistent, especially for different silicon doping types (i.e. N-type and P-type), the wafer-map inconsistency of the metal silicide block resistance is more obvious, and even shows an opposite trend. The main reasons for this phenomenon are as follows:

[0006] ① The non-uniformity of N-type ion implantation and P-type ion implantation; ② The non-uniformity of annealing temperature: During the annealing activation process, N-type ions and P-type ions react differently to the thermal factors in the annealing process; ③ The locations of different test structures are different: the density of patterns around different locations is inconsistent, resulting in inconsistent heat absorption during annealing.

[0007] like Figure 1 The figure in the figure is the wafer-map of the sheet resistance of metal silicide on N-type polysilicon. Figure 2 The figure below shows the wafer-map of the sheet resistance of metal silicide on P-type polysilicon. The redder the color, the larger the sheet resistance. The sheet resistance gradually decreases as it transitions to green. The greener the color, the smaller the sheet resistance. Figure 1 The square resistance in the wafer shows a distribution phenomenon that the square resistance is high in the center of the wafer and low in the surrounding areas. Figure 2 The square resistance in the wafer shows a distribution phenomenon that the square resistance is low in the center of the wafer and high in the periphery. This will make it impossible to accurately determine the square resistance of the metal silicide on the entire wafer, and thus it is impossible to accurately monitor the key process parameters such as the thickness process parameters of the metal silicide and the size of the polysilicon gate and / or silicon active area, as well as the uniformity of these parameters on the wafer.

[0008] Therefore, the main challenge faced by the existing technology is how to accurately measure and evaluate the metal silicide sheet resistance, especially considering the impact of ion implantation on resistance measurement. In order to improve the reliability and performance of semiconductor devices, a new method or technology is needed to accurately evaluate the metal silicide sheet resistance to ensure accurate monitoring of polysilicon size.

[0009] The present invention aims to solve the problems in the existing metal silicide block resistance measurement method and provide a new method that can accurately evaluate the metal silicide resistance and monitor the size of polysilicon, so as to improve the monitoring accuracy of the semiconductor manufacturing process and the reliability of the device. Summary of the invention

[0010] The object of the present invention is to overcome the above-mentioned deficiencies of the prior art and to provide a method for measuring the resistance of metal silicide in a semiconductor device, a method for monitoring the size of polysilicon, and a method for monitoring the electrical properties of a product.

[0011] The present invention is implemented as follows. In a first aspect, the present invention provides a method for measuring the resistance of a metal silicide in a semiconductor device, wherein the metal silicide in the semiconductor device is a metal silicide layer formed by depositing the metal silicide on an ion implanted layer of polysilicon; the method is: By applying a high potential or a low potential to both ends of the block resistor corresponding to the metal silicide, the total resistance value Rsilicide of the metal silicide block resistor is measured; since the total resistance value Rsilicide of the metal silicide block resistor is interfered by the ion implantation layer resistance R2, the total resistance value Rsilicide of the metal silicide block resistor is removed from the interference of the ion implantation layer resistance R2 to obtain the metal silicide resistance R1.

[0012] Preferably, the method specifically comprises the following steps: Applying a high potential or a low potential to both ends of the sheet resistor corresponding to the metal silicide, respectively, to measure the total resistance value of the sheet resistor of the metal silicide; Constructing a mathematical expression for the total resistance of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance; Calculate the total thickness of the metal silicide layer and the ion implantation layer, and then obtain the thickness of the metal silicide layer according to the mathematical expression of the total resistance value of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance; According to the mathematical expression of the resistance of the metal silicide layer, the resistance of the metal silicide layer is finally obtained.

[0013] Preferably, the process of constructing the mathematical expression of the total resistance of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance is as follows: Since the total resistance of the metal silicide block resistance Rsilicide is the metal silicide layer resistance R1 and the ion implantation layer resistance R2 connected in parallel, we get: Formula (1) Substitute the resistance mathematical expressions (2)-(3) of the metal silicide layer and the ion implantation layer into formula (1) to construct the total resistance mathematical expression (4) of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide block resistance: Formula (2) Formula (3) Formula (4) Where L is the length of polysilicon, W is the width of polysilicon, ρ1 and ρ2 are the resistivity of the metal silicide layer and the ion implantation layer, respectively, which are negatively correlated with the carrier concentration; is the thickness of the metal silicide layer, and h1 is the total thickness of the metal silicide layer and the ion implantation layer.

[0014] Preferably, the total thickness of the metal silicide layer and the ion implantation layer is calculated as follows: By performing the same ion implantation method on polysilicon of the same semiconductor device, a test ion implantation layer having a thickness equal to the total thickness of the metal silicide layer and the ion implantation layer is formed; the metal silicide layer and the ion implantation layer are calculated according to a mathematical expression of the resistance of the test ion implantation layer.

[0015] Preferably, the resistance mathematical expression of the test ion implantation layer is: Formula (5) Where L is the length of polysilicon, W is the width of polysilicon, ρ3 is the resistivity of the test ion implantation layer, and h1 is the total thickness of the metal silicide layer and the ion implantation layer.

[0016] Preferably, ρ3=ρ2, where ρ2 is the resistivity of the ion implantation layer in the semiconductor device where the metal silicide resistor to be measured is located.

[0017] Preferably, the thickness of the metal silicide layer is obtained according to the mathematical expression of the total resistance of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide block resistance; and the specific process of finally obtaining the metal silicide layer resistance according to the mathematical expression of the resistance of the metal silicide layer is as follows: Substituting the total thickness of the metal silicide layer and the ion implantation layer into the total resistance value mathematical expression of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance to obtain the thickness of the metal silicide layer; Then, the thickness of the metal silicide layer is substituted into the resistance mathematical expression of the metal silicide layer to obtain the resistance of the metal silicide layer; The resistance mathematical expression of the metal silicide layer is specifically: Formula (6) Where, L is the length of polysilicon, W is the width of polysilicon, and ρ1 is the resistivity of the metal silicide layer; is the thickness of the metal silicide layer.

[0018] Preferably, the ion implantation layer is an N-type doped ion implantation layer or a P-type doped ion implantation layer.

[0019] In a second aspect, the present invention provides a polysilicon size monitoring method, wherein the polysilicon size is monitored using the actual resistance of the metal silicide calculated by the method.

[0020] In a third aspect, the present invention provides a method for product electrical property monitoring of semiconductor devices, and product electrical property monitoring is performed by the method.

[0021] The beneficial effects of the present invention include at least the following: The present invention innovatively proposes the existence of ion implantation layer interference, avoids ion implantation layer interference, and combines the traditional metal silicide block resistance measurement method to obtain the actual resistance value of the metal silicide that is not interfered by the ion implantation layer, thereby ensuring accurate monitoring of the polysilicon size and improving the accuracy of electrical property evaluation of semiconductor device products. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 Wafer image of metal silicide block resistor on N-type polysilicon.

[0024] Figure 2 Wafer image of metal silicide block resistor on P-type polysilicon.

[0025] Figure 3 The present invention provides a metal silicide deposition process for a semiconductor device where a metal silicide resistor to be tested is located.

[0026] Figure 4 yes Figure 3 The corresponding circuit schematic.

[0027] Figure 5 The present invention provides a deposition process for constructing a test ion implantation layer using a semiconductor device having the same metal silicide resistor as the one to be tested.

[0028] Figure 6 yes Figure 5 The corresponding circuit schematic.

[0029] Figure 7 This is a layout of a metal silicide resistor structure provided by an embodiment of the present invention.

[0030] Figure 8 4 is a cross-section of a metal silicide resistor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] As can be seen from the background technology, the traditional metal silicide block resistance measurement method cannot obtain the actual resistance of the metal silicide. It is interfered by the ion implantation layer, resulting in an abnormal trend in the actual measured metal silicide resistance, and cannot ensure accurate monitoring of the polysilicon size. This inaccuracy will affect the evaluation of semiconductor device performance, and further affect the design and optimization of the device.

[0032] In order to solve the technical problem, the present invention provides a method for measuring the real resistance of metal silicide in a semiconductor device, comprising: By applying a high potential or a low potential to both ends of the sheet resistance corresponding to the metal silicide, the total resistance value Rsilicide of the sheet resistance of the metal silicide is measured; Since the total resistance value Rsilicide of the metal silicide block resistance is interfered by the ion implantation layer resistance R2, the total resistance value Rsilicide of the metal silicide block resistance is removed to obtain the metal silicide resistance R1.

[0033] The present invention innovatively proposes the existence of ion implantation layer interference, and by avoiding the ion implantation layer interference, combined with the traditional metal silicide block resistance measurement method, obtains the actual resistance value of the metal silicide that is not interfered by the ion implantation layer, ensures accurate monitoring of the polysilicon size, and improves the accuracy of the electrical evaluation of semiconductor device products. These methods are of key significance for ensuring the high performance, high reliability and precise process control of semiconductor devices, and are directly related to the accuracy of the semiconductor manufacturing process and the quality of the final product.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] refer to Figure 3 , showing a flow chart of an embodiment of a method for measuring metal silicide resistance in a semiconductor device of the present invention.

[0036] The metal silicide in the semiconductor device used in this embodiment is a metal silicide layer formed by depositing the metal silicide on the ion implantation layer of polysilicon; Specifically, the preparation process of depositing metal silicide on the ion implantation layer of polysilicon may be: Obtaining polysilicon and pre-treating it; Performing ion implantation on the pre-treated polysilicon to form an ion implantation layer; Subsequently, metal silicide is deposited on the ion implantation layer to generate a metal silicide layer; wherein the total thickness of the ion implantation layer and the metal silicide layer is set to h1, that is, the thickness of the ion implantation layer is h1-h2, and the thickness of the metal silicide layer is h2.

[0037] Specifically, the ion implantation layer is an N-type doped (NP IMP) ion implantation layer or a P-type doped (PP IMP) ion implantation layer.

[0038] like Figure 8 As shown, the polysilicon provided in this embodiment is a bottom oxide dielectric layer SiO2 grown on the shallow trench isolation STI region of the device, and then polysilicon is arranged on the oxide dielectric layer. Sidewalls are arranged on both sides of the polysilicon, and ions are implanted on the polysilicon to form an ion implantation layer, and then a metal silicide layer is generated on the ion implantation layer.

[0039] The metal silicide resistor structure provided in the embodiment of the present invention may be in the shape of a snake (see Figure 7), and is not limited to the above structure.

[0040] The method for measuring the metal silicide resistance in the semiconductor device of the present invention is to apply a high potential or a low potential to both ends of the block resistance corresponding to the metal silicide, and measure the total resistance value Rsilicide of the metal silicide block resistance; because the total resistance value Rsilicide of the metal silicide block resistance is interfered by the ion implantation layer resistance R2, the total resistance value Rsilicide of the metal silicide block resistance is removed from the interference of the ion implantation layer resistance R2 to obtain the metal silicide resistance R1; More specifically, the method comprises: Step S1, see Figure 4 Device structure, high potential or low potential is applied to both ends of the sheet resistance corresponding to the metal silicide, and the total resistance value Rsilicide of the metal silicide sheet resistance is measured; For example, prepare special test equipment to ensure that it has the function of accurately applying potential and measuring resistance, such as a high-precision source meter (Source - Measure Unit, SMU). Connect the test probes precisely to both ends of the block resistor corresponding to the metal silicide, and set the output parameters of the source meter so that it can stably apply high potential (such as + V) and low potential (such as - V) across the block resistor. During the application of potential, the source meter measures the current I passing through the block resistor. According to Ohm's law R = V / I, the total resistance value Rsilicide of the metal silicide block resistor is calculated by the known applied potential V and the measured current I.

[0041] In order to improve the accuracy of the measurement, multiple measurements can be taken and the average value can be obtained. At the same time, the measurement environment must be stable to avoid external factors (such as temperature, electromagnetic field, etc.) from interfering with the measurement results. Multiple measurements can overcome errors such as equipment accuracy limitations, contact resistance effects, and environmental interference.

[0042] Equipment accuracy limitation: The source meter itself has a certain measurement accuracy error, and the potential value and current value it displays may have a slight deviation from the actual value. For example, the potential measurement accuracy of the source meter may be ±0.1%, and the current measurement accuracy may be ±0.05%. These accuracy errors will be magnified when calculating the resistance value, thus affecting the accuracy of the final measurement result.

[0043] Influence of contact resistance: The contact between the test probe and the two ends of the block resistor is not an ideal zero-resistance connection, and there is a certain contact resistance. The size of the contact resistance will vary depending on factors such as the probe material, contact pressure, and surface cleanliness. If the contact resistance is large and unstable, the total resistance value measured will be too high, resulting in measurement errors.

[0044] Environmental interference: Factors such as temperature, humidity, and electromagnetic fields in the measurement environment may affect the measurement results. For example, temperature changes can cause the resistivity of metal silicide and polysilicon to change, thereby changing the actual resistance value of the block resistor. Generally, for every 1°C increase in temperature, the resistivity may change by about 0.1% - 0.5%. This change will be directly reflected in the measured resistance value, causing measurement errors.

[0045] Step S2: Due to the source-drain ion implantation, the actual metal silicide resistor is composed of two resistors connected in parallel. Figure 4 :One is the metal silicide itself, and the other is the polysilicon resistance after ion implantation, that is, the total resistance of the metal silicide block resistance Rsilicide is the metal silicide layer resistance R1 and the ion implantation layer resistance R2 in parallel. According to the calculation formula of parallel resistance, it can be obtained: Formula (1) Substituting the expressions (2)-(3) of the metal silicide layer resistance R1 and the ion implantation layer resistance R2 into formula (1), we can obtain formula (4): Formula (2) Formula (3) Formula (4) Wherein, L is the length of polysilicon, and W is the width of polysilicon. Under the premise of stable process conditions, both W and L can be considered as fixed constants. is the thickness of the metal silicide layer, h1 is the total thickness of the metal silicide layer and the ion implantation layer; ρ1 and ρ2 are the resistivities of the metal silicide and ion implantation layers, respectively; the carrier concentration of the metal silicide is closely related to the material type. By ensuring that the process parameters such as the metal silicide deposition temperature are stable, ρ1 can remain unchanged; similarly, by keeping the ion implantation energy and dose process parameters stable, ρ2 can also remain unchanged.

[0046] The present invention can also adjust the h2 thickness by adjusting the metal silicide reaction time to obtain a series of Rsilicide values ​​that vary with h2, and use a mathematical regression method to obtain an accurate relationship between Rsilicide and h2, namely, formula (4).

[0047] Step S3, see Figure 5, by performing the same ion implantation method on the polysilicon of the same semiconductor device, a test ion implantation layer with a thickness of h1 is formed, and a high potential or a low potential is applied to both ends of the block resistor corresponding to the test ion implantation layer, and the current test ion implantation layer resistance R3 is obtained by measurement; this operation refers to the SAB resistance (silicide barrier layer resistance), that is, after the ion implantation process, no metal silicide is grown. It should be noted that the ion implantation process of this resistor is the same as that of the metal silicide resistor, and they are carried out at the same time.

[0048] See also Figure 6 , according to the calculation formula (5) of the test ion implantation layer resistance R3, the thickness h1 of the test ion implantation layer is calculated; Formula (5) Where L is the length of polysilicon, W is the width of polysilicon, ρ3 is the resistivity of the test ion implantation layer, and ρ3=ρ2; The current step needs to ensure that the ion implantation process does not change, so as to keep R3 stable, which is sufficient to ensure that the parameter h1 remains unchanged.

[0049] For the polysilicon of the same semiconductor device, the exact same ion implantation method is used to form a test ion implantation layer with a thickness of h1. For the block resistance corresponding to this test ion implantation layer, high-precision test equipment (such as a source meter) is also used to apply high or low potentials at both ends, and measure the current test ion implantation layer resistance R3. The reference here is the SAB resistance (silicide barrier layer resistance), that is, after the ion implantation process, no metal silicide is grown. It should be noted that the ion implantation process of this resistor must be exactly the same as the ion implantation process of the metal silicide resistor, and must be carried out at the same time to ensure that both are formed under the same process conditions, thereby ensuring the accuracy of measurement and calculation.

[0050] Step S4, substituting h1 into formula (4) and solving the equation by mathematical calculation, the thickness of the metal silicide layer can be obtained. ; During the calculation process, ensure that the values ​​entered are accurate, and use appropriate mathematical tools (such as numerical calculation software) to improve the accuracy and efficiency of the calculation.

[0051] Step S5: Substitute h2 obtained in step S4 into formula (2) to calculate the metal silicide layer resistance R1. This step is the ultimate goal of the entire measurement method. The obtained R1 value is the accurate metal silicide resistance value after removing the interference of the ion implantation layer, which can be used for subsequent polysilicon size monitoring and semiconductor device performance evaluation.

[0052] The present invention also provides a polysilicon size monitoring method, which is based on the above-mentioned metal silicide resistance measurement method. By accurately calculating the actual resistance R1 of the metal silicide, effective monitoring of the polysilicon size can be achieved. Since the metal silicide layer resistance R1 is closely related to the size of polysilicon (such as length, width, thickness, etc.) and its electrical properties (such as carrier concentration, etc.), when the size of polysilicon changes, it will directly affect the value of the metal silicide layer resistance R1. Therefore, by real-time monitoring of the change of R1, the fluctuation of the polysilicon size can be discovered in time, so that corresponding measures (such as adjusting process parameters, etc.) can be taken to ensure the stability of the polysilicon size and ensure the manufacturing quality and performance consistency of semiconductor devices.

[0053] The present invention also provides a method for monitoring the electrical properties of semiconductor devices, which is implemented by means of the above-mentioned polysilicon size monitoring method. Since the stability of the polysilicon size has an important influence on the electrical properties of semiconductor devices, the electrical properties of semiconductor devices can be further evaluated by monitoring the polysilicon size (indirectly through the actual resistance R1 of the metal silicide). For example, in the manufacturing process of semiconductor devices, the electrical parameters of the product (such as resistance, capacitance, on-voltage, etc.) are detected in time and compared with the expected standard values. If abnormal changes are found in the electrical parameters, combined with the polysilicon size monitoring data, the problem can be quickly located, which may be caused by changes in the polysilicon size, or problems may occur in other process links. In this way, the manufacturing process can be adjusted in time, the electrical reliability of the product can be improved, and it is ensured that the semiconductor devices finally produced meet the design requirements and performance standards.

[0054] Therefore, the present invention innovatively proposes the problem of interference from the ion implantation layer and removes it through an accurate calculation method, thereby being able to obtain the actual resistance R1 of the metal silicide that is not interfered by the ion implantation layer. Compared with the traditional measurement method, the measurement result of the present invention is more accurate and reliable, providing a solid data foundation for subsequent polysilicon size monitoring and semiconductor device performance evaluation.

[0055] Based on accurate metal silicide resistance measurement, the present invention realizes accurate monitoring of polysilicon size. By real-time monitoring of the change of metal silicide resistance R1, it is possible to timely detect slight changes in polysilicon size and take corresponding measures to adjust it, effectively avoiding the problem of semiconductor device performance degradation caused by uncontrolled polysilicon size, and improving the stability of semiconductor manufacturing process and consistency of product quality.

[0056] In terms of electrical property monitoring of semiconductor device products, the present invention can more accurately evaluate the electrical performance of products through correlation analysis between polysilicon size monitoring and product electrical parameters. When the electrical properties of a product are abnormal, it can be quickly traced back to polysilicon size changes or other potential process problems, providing strong support for product optimization design and quality improvement, and helping to improve the overall reliability and market competitiveness of semiconductor devices.

[0057] In summary, the present invention has important technical value and practical application significance in the field of semiconductor device manufacturing, provides an effective solution to key problems such as metal silicide resistance measurement and polysilicon size monitoring, and helps promote the continuous development and progress of semiconductor manufacturing technology.

[0058] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for measuring the resistance of a metal silicide in a semiconductor device, wherein the metal silicide in the semiconductor device is a metal silicide layer formed by depositing the metal silicide on an ion implanted layer of polysilicon; characterized in that: The method is to apply a high potential or a low potential to both ends of the block resistor corresponding to the metal silicide, and measure the total resistance of the metal silicide block resistor; because the total resistance of the metal silicide block resistor is interfered by the resistance of the ion implantation layer, the total resistance of the metal silicide block resistor is removed from the interference of the ion implantation layer resistance and used as the metal silicide resistance.

2. A method for measuring metal silicide resistance in a semiconductor device according to claim 1, characterized in that: The method specifically comprises the following steps: Applying a high potential or a low potential to both ends of the sheet resistor corresponding to the metal silicide, respectively, to measure the total resistance value of the sheet resistor of the metal silicide; Constructing a mathematical expression for the total resistance of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance; Calculate the total thickness of the metal silicide layer and the ion implantation layer, and then obtain the thickness of the metal silicide layer according to the mathematical expression of the total resistance value of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance; According to the mathematical expression of the resistance of the metal silicide layer, the resistance of the metal silicide layer is finally obtained.

3. A method for measuring metal silicide resistance in a semiconductor device according to claim 2, characterized in that: The construction process of the mathematical expression of the total resistance value of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance is as follows: Since the total resistance of the metal silicide block resistance Rsilicide is the metal silicide layer resistance R1 and the ion implantation layer resistance R2 connected in parallel, we get: Formula (1) Substitute the resistance mathematical expressions (2)-(3) of the metal silicide layer and the ion implantation layer into formula (1) to construct the total resistance mathematical expression (4) of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide block resistance: Formula (2) Formula (3) Formula (4) Where L is the length of polysilicon, W is the width of polysilicon, ρ1 and ρ2 are the resistivities of the metal silicide layer and the ion implantation layer, respectively; is the thickness of the metal silicide layer, and h1 is the total thickness of the metal silicide layer and the ion implantation layer.

4. The method for measuring the resistance of metal silicide in a semiconductor device according to claim 2, characterized in that: The calculation process of the total thickness of the metal silicide layer and the ion implantation layer is: By performing the same ion implantation method on polysilicon of the same semiconductor device, a test ion implantation layer having a thickness equal to the total thickness of the metal silicide layer and the ion implantation layer is formed; the metal silicide layer and the ion implantation layer are calculated according to a mathematical expression of the resistance of the test ion implantation layer.

5. A method for measuring metal silicide resistance in a semiconductor device according to claim 4, characterized in that: The specific mathematical expression of the resistance of the test ion implantation layer is: Formula (5) Where L is the length of polysilicon, W is the width of polysilicon, ρ3 is the resistivity of the test ion implantation layer, and h1 is the total thickness of the metal silicide layer and the ion implantation layer.

6. A method for measuring metal silicide resistance in a semiconductor device according to claim 5, characterized in that: ρ3=ρ2, where ρ2 is the resistivity of the ion implantation layer in the semiconductor device where the metal silicide resistor to be measured is located.

7. The method for measuring the resistance of metal silicide in a semiconductor device according to claim 1, characterized in that: The specific process of obtaining the thickness of the metal silicide layer according to the mathematical expression of the total resistance of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide block resistance and finally obtaining the resistance of the metal silicide layer according to the mathematical expression of the resistance of the metal silicide layer is as follows: Substituting the total thickness of the metal silicide layer and the ion implantation layer into the total resistance value mathematical expression of the metal silicide layer thickness, the ion implantation layer thickness and the metal silicide sheet resistance to obtain the thickness of the metal silicide layer; Then, the thickness of the metal silicide layer is substituted into the resistance mathematical expression of the metal silicide layer to obtain the resistance of the metal silicide layer; The resistance mathematical expression of the metal silicide layer is specifically: Formula (6) Where, L is the length of polysilicon, W is the width of polysilicon, and ρ1 is the resistivity of the metal silicide layer; is the thickness of the metal silicide layer.

8. The method for measuring the resistance of metal silicide in a semiconductor device according to claim 1, characterized in that: The ion implantation layer is an N-type doped ion implantation layer or a P-type doped ion implantation layer.

9. A method for monitoring the size of polysilicon, comprising monitoring the size of polysilicon using the actual resistance of the metal silicide calculated by the method according to any one of claims 1 to 8.

10. A method for monitoring product electrical properties of a semiconductor device, wherein the method according to claim 9 is used to monitor product electrical properties.

Images