Multi-chip packaging element and preparation method thereof

Abstract

A multi-chip packaging component comprises a basic lead frame, a transistor chip, a control circuit chip, a metal frame and a sealing glue layer, wherein the transistor chip and the control circuit chip are positively packaged on a bearing seat of the basic lead frame; the metal frame covers the transistor chip; wherein the metal frame is provided with the main conductive sheet which is electrically connected with a source pad of the transistor chip, and a first conductive section which extends from the main conductive sheet and is not less than the main conductive sheet in height; the first conductive section is connected with the base lead frame, the second conductive section is connected with the first conductive section, extends and bends towards the base lead frame and is provided with a conductive bottom surface which is coplanar with the bottom surface of the bearing seat, and the sealing glue layer covers the transistor chip, the control circuit chip, the main conductive sheet and the first conductive section. And the second conductive section is exposed on the outer side of the sealing glue layer. In addition, the invention also provides a preparation method of the multi-chip packaging element.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging component and a preparation method thereof, and in particular to a multi-chip packaging component and a preparation method thereof. Background Art

[0002] As the functional requirements of electronic products become more and more diverse, the types and quantities of semiconductor components required are also increasing. Therefore, how to stack and package multiple chips or different functions without increasing the volume or increasing the minimum volume has become an important development direction for semiconductor industry players.

[0003] The packaging structure of a general multi-chip package, taking the dual-chip packaging structure of a control chip and a transistor chip as an example, usually uses a wire bonding method, using welding wires to electrically connect the control chip, the transistor chip, and the majority of the pins of the lead frame carrying the control chip and the transistor chip, and then package them, and then electrically connect them to the outside through the pins of the lead frame. However, this electrical connection method is easy to affect the electrical properties because the welding wires are thinner and have a larger resistance. In addition, the solder joints between the welding wires and the pins of the lead frame are easy to fall off / separate during the packaging or process to cause a short circuit. Furthermore, because the packaging structure is formed by bending the pins to form a coplanar bottom surface for the pins to be electrically connected to the outside, however, the bending position of the pins will be located inside the packaging structure (inside the packaging glue) or at the edge of the packaging glue. Therefore, the packaging structure will be damaged due to the stress release caused by the bending of the pins.

[0004] Therefore, how to provide a stable, simpler packaging process that is suitable for different component designs without affecting the packaging yield is the direction that semiconductor packaging companies are constantly working towards. Summary of the invention

[0005] The object of the present invention is to provide a multi-chip packaging component.

[0006] The multi-chip packaging component of the present invention comprises a basic lead frame, a transistor chip, a control circuit chip, a metal frame, and a sealing layer.

[0007] The basic lead frame is made of conductive material, has a bearing seat, and a plurality of pins extending integrally from the bearing seat and spaced from each other, and the bearing seat has a surface and a bottom surface opposite to each other.

[0008] The transistor chip is arranged on the surface of the carrier, and has an active surface and a bottom surface opposite to each other, a plurality of source pads and a gate located on the active surface, and a drain located on the bottom surface of the transistor chip, and the drain is electrically connected to the carrier.

[0009] The control circuit chip is electrically insulated and disposed on the surface of the supporting base, and is electrically connected to the transistor chip and the pins.

[0010] The metal frame has a main conductive sheet and at least one conductive pin extending integrally from the main conductive sheet and used for direct external electrical connection. The main conductive sheet covers the transistor chip and is electrically connected to at least a portion of the source pad of the transistor chip. The conductive pin has a first conductive segment and a second conductive segment. The first conductive segment extends from the main conductive sheet and has a height not less than that of the main conductive sheet. The second conductive segment bends and extends from the first conductive segment toward the direction of the basic lead frame and has a conductive bottom surface coplanar with the bottom surface of the supporting seat.

[0011] The sealing layer covers the basic lead frame, the transistor chip, the control circuit chip, the main conductive sheet of the metal frame, and the first conductive segment, and exposes the support seat to the outside, and the second conductive segment is located outside the sealing layer.

[0012] Preferably, in the multi-chip package component described in the present invention, the transistor chip has three source pads and a gate, one source pad is electrically connected to the main conductive sheet, and the gate and the other two source pads are electrically connected to the control circuit chip.

[0013] Preferably, in the multi-chip package component of the present invention, the transistor chip has four source pads, the main conductive sheet is electrically connected to two of the source pads at the same time, and the two source pads are spaced apart by a gap.

[0014] Preferably, in the multi-chip package component of the present invention, the main conductive sheet has a groove at a position corresponding to the gap.

[0015] Preferably, the multi-chip packaging element described in the present invention, wherein the first conductive segment has an extension portion extending from the main conductive sheet and having a height not less than that of the main conductive sheet, and a parallel portion connected to the extension portion and parallel to the main conductive sheet, the second conductive segment has a first conductive portion connected to the parallel portion and having a bending angle with the parallel portion between 60 and 80°, and a second conductive portion bent from the first conductive portion and having a bending angle with the first conductive portion between 60 and 80°, and the second conductive portion has the conductive bottom surface.

[0016] Preferably, in the multi-chip package component of the present invention, the source pad and the BCPI-240190 Page 3 / 9

[0017] The gate is electrically connected to the control circuit chip via a bonding wire.

[0018] Preferably, the multi-chip packaging component described in the present invention, wherein the basic lead frame also has a partition wall formed on the surface of the carrier seat, and the surface of the carrier seat is defined as a first carrier portion located on opposite sides of the partition wall and for carrying the transistor chip, and a second carrier portion for carrying the control circuit chip.

[0019] Preferably, in the multi-chip package component of the present invention, the basic lead frame has a plurality of pins extending from one side of the second carrier portion and spaced apart from each other, and the control circuit chip is electrically connected to the pins of the basic lead frame via bonding wires.

[0020] Preferably, in the multi-chip packaging component of the present invention, the partition wall and the carrier seat are made of the same material and are integrally formed.

[0021] Preferably, in the multi-chip package component of the present invention, the main conductive sheet covers at least 50% of the surface area of ​​the transistor chip.

[0022] Furthermore, another object of the present invention is to provide a method for preparing a multi-chip package component.

[0023] The method for preparing a multi-chip package component of the present invention comprises a providing step, a first chip setting step, a second chip setting step, a metal frame setting step, an electrical connection step, a packaging step, and a processing step.

[0024] The providing step is to provide a lead frame unit, wherein the lead frame unit has an outer frame, and a plurality of basic lead frames located in the outer frame, connected to the outer frame and arranged in connection with each other, each basic lead frame has a supporting seat and a plurality of pins extending integrally from the supporting seat and spaced from each other.

[0025] The first chip setting step is to set a transistor chip on the surface of each carrier of the basic lead frame in a forward packaging manner, wherein the transistor chip has a drain electrically connected to the carrier, and a plurality of source pads and gates located on the surface of the transistor chip opposite to the carrier.

[0026] The second chip setting step is to set a control circuit chip on the surface of each base support of the basic lead frame in a forward packaging manner, wherein the control circuit chip is electrically isolated from the support and is located on the same surface as the transistor chip and is spaced apart.

[0027] The metal frame setting step is to provide multiple metal brackets, each metal bracket has a main conductive plate and at least one leg extending integrally from the main conductive plate, and the main conductive plates of the metal brackets are respectively covered on the surface of the transistor chip and are each electrically connected to at least one source pad of the corresponding transistor chip.

[0028] The electrical connection step is to electrically connect the control circuit chip disposed on each of the basic lead frames with the other source pads of the transistor chip, the gate, and the pins of the basic lead frame.

[0029] The packaging step is to use a sealing material to cover the metal bracket, the transistor chip, and the control circuit chip to form a sealing layer, and to expose at least a portion of the bottom surface of the carrier opposite to its surface and at least one leg to the outside of the sealing layer to obtain a plurality of semi-finished products.

[0030] The processing step is to obtain any independent semi-finished product, bend the at least one leg of the semi-finished product exposed outside the sealing layer toward the basic lead frame, so that the at least one leg forms a second conductive part with a conductive bottom surface flush with the bottom surface of the supporting seat.

[0031] Preferably, in the method for preparing a multi-chip packaging component described in the present invention, each basic lead frame provided in the providing step also has a partition wall located on the surface of the carrier seat, and the partition wall separates the surface of the carrier seat into a first carrier portion and a second carrier portion located on opposite sides of the partition wall, the transistor chip and the control circuit chip are respectively arranged on the first carrier portion and the second carrier portion, and the pins extend integrally from at least one side edge of the second carrier portion.

[0032] Preferably, in the method for preparing a multi-chip package component of the present invention, the partition wall and the carrier seat are made of the same material and are integrally formed.

[0033] Preferably, in the method for preparing a multi-chip packaging element described in the present invention, the at least one leg has a first conductive segment extending from the main conductive sheet and having a height not less than that of the main conductive sheet, and an extension segment extending from the first conductive segment in a direction away from and parallel to the main conductive sheet, the packaging step is to expose at least a portion of the extension segment to the outside of the sealing layer, and the processing step is to bend the extension segment exposed to the outside of the sealing layer toward the direction of the basic lead frame so that the extension segment forms a parallel portion parallel to the main conductive sheet, a first conductive portion connected to the parallel portion at a bending angle between 60° and 80°, and a second conductive portion bent from the first conductive portion and at a bending angle between 60° and 80° to the first conductive portion.

[0034] Preferably, in the method for preparing the multi-chip package component of the present invention, the electrical connection step is to electrically connect the control circuit chip with other source pads and the gate of the transistor chip respectively by wire bonding.

[0035] The beneficial effect of the present invention is that: by making the external electrical connection of the transistor chip use the metal frame that is electrically connected to the transistor chip and directly extends outward, there is no solder joint that is electrically connected to the pin of the lead frame through a solder wire in the past. In addition, because the bending position of the conductive pin of the metal frame used for external electrical connection is located outside the sealing layer, the packaging component is not easily affected by the stress of the conductive pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a top view schematic diagram, illustrating the multi-chip packaging component of the present invention and is a top view structural schematic diagram of the sealing glue layer covering the top surface being removed;

[0037] Figure 2 is a cross-sectional schematic diagram, along Figure 1 Sectional structure of II-II section line, auxiliary explanation Figure 1 ;

[0038] Figure 3 is a text flow chart illustrating the preparation method of the embodiment of the present invention;

[0039] Figure 4 is a schematic top view, which assists in explaining the preparation method of the embodiment of the present invention;

[0040] Figure 5 It is a schematic flow chart to assist in explaining the preparation method of the embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0042] See also Figure 1 and Figure 2 ,in, Figure 2 is along Figure 1 The embodiment of the multi-chip package component of the present invention comprises a basic lead frame 2, a transistor chip 3, a metal frame 4, a control circuit chip 5, and a sealing layer 6.

[0043] The basic lead frame 2 is made of conductive material, and has a bearing seat 21, a partition wall 22, and a plurality of pins 23 extending from the bearing seat 21 and spaced apart from each other. The bearing seat 21 has a surface 211 and a bottom surface 212 opposite to each other. The partition wall 22 is formed on the surface 211, and is made of the same material as the bearing seat 21 and is formed integrally. The surface 211 of the bearing seat 21 defines a first bearing portion 211A and a second bearing portion 211B located on opposite sides of the partition wall 22, and the pins 23 extend integrally from at least one side of the bearing seat 21 for carrying the control circuit chip 5. In this embodiment, the second bearing portion 211B is used as an example for carrying the control circuit chip 5, so the pins 23 extend integrally from at least one side of the second bearing portion 211B.

[0044] The transistor chip 3 is disposed on the surface 211 of the carrier 21 in a forward packaging manner, and has an active surface and a bottom surface opposite to each other, and a plurality of source pads 31a-31d and a gate 32 located on the active surface, and a drain 33 located on the bottom surface. In this embodiment, the transistor chip 3 is connected to the first carrier portion 211A via the conductive solder 101, and the transistor chip 3 has 4 source pads (respectively represented by 31a to 31d) located on the active surface, a gate 32, and a drain 33 as an example for explanation, but the actual implementation is not limited to this number.

[0045] The metal frame 4 has a main conductive sheet 41, at least one conductive pin 42 integrally extending from the main conductive sheet 41 and used for direct external electrical connection, and a slot 43 penetrating the main conductive sheet 41. It should be noted that the conductive pin 42 of the metal frame 4 can be one or more depending on the electrical connection requirements, or can extend from different sides of the second supporting portion 211B. In this embodiment, the metal frame 4 is taken as an example in which two conductive pins 42 extend from the same side of the first supporting portion 211A. However, in actual implementation, it can be adjusted according to actual requirements and is not limited thereto.

[0046] Specifically, each conductive pin 42 of the metal frame 4 has a width greater than the diameter of a general wire and has a first conductive segment 421 and a second conductive segment 422. The first conductive segment 421 has an extension portion 421A extending from the main conductive sheet 41 and having a height not less than that of the main conductive sheet 41, and a parallel portion 421B connected to the extension portion 421A and substantially parallel to the main conductive sheet 41. The second conductive segment 422 has a first conductive portion 422A connected to the parallel portion 421B and extending from the parallel portion 421B toward the base lead frame 2, and a second conductive portion 422B bent from one end of the first conductive portion 422A away from the first conductive segment 421, and the second conductive portion 422B has a conductive bottom surface 423 coplanar with the bottom surface 212 of the support base 21.

[0047] In order to reduce the stress of post-processing and production, the bending angle θ1 between the first conductive portion 422A and the parallel portion 421B is between 60° and 80°, and the bending angle θ2 between the first conductive portion 422A and the second conductive portion 422B is between 60° and 80°. In this embodiment, the bending angles θ1 and θ2 are 65° as an example, however, the actual implementation is not limited to this.

[0048] The metal frame 4 covers the transistor chip 3 with the main conductive sheet 41 and is electrically connected to two adjacent source pads 31a and 31b of the transistor chip 3 that are spaced apart by a gap, and the groove 43 corresponds to the gap. By forming the source pads 31a and 31b spaced apart by a gap through the source pads of the transistor chip 3 that are electrically connected to the main conductive sheet 41, and arranging the groove 43 of the main conductive sheet 41 corresponding to the gap between the two source pads 31a and 31b, the packaging material of the subsequent packaging can be easily penetrated between the main conductive sheet 41 and the transistor chip 3 to more completely cover the package.

[0049] In some embodiments, the main conductive sheet 41 covers no less than 50% of the surface area of ​​the transistor chip 3 , and the main conductive sheet 41 can provide a better heat dissipation effect and a better electromagnetic interference shielding (EMI Shielding) effect.

[0050] The control circuit chip 5 is packaged in a forward manner using an insulating glue 102 (such as Figure 521) and is electrically insulated and bonded to the second carrier portion 211B, and has a plurality of connection pads 51 for external electrical connection, and is electrically connected to the gate 32 of the transistor chip 3, the other two source pads 31c, 31d, the pin 23, and the second carrier portion 211B through a plurality of wires 52, and can be used as a signal feedback and control of the control circuit chip 5 through the pin 23, the carrier 21, and the transistor chip 3. In this embodiment, the control circuit chip 5 is bonded to the second carrier portion 211B with its bottom, and the connection pad 51 is located on the top of the control circuit chip 5.

[0051] It should be noted that the partition wall 22 is used to isolate the conductive solder 101 and the insulating glue 102 to avoid mutual interference between the conductive solder 101 and the insulating glue 102 during the bonding process of the transistor chip 3 and the control circuit chip 5 with the carrier seat 21. Therefore, in some embodiments, the partition wall 22 may not be required depending on the process.

[0052] The sealing glue layer 6 covers the basic lead frame 2, the transistor chip 3, the main conductive sheet 41 of the metal frame 4, the first conductive segment 421, part of the second conductive segment 422 and the control circuit chip 5, and penetrates between the main conductive sheet 41 and the transistor chip 3 through the groove 43 of the main conductive sheet 41, and makes the bottom surface 212 of the supporting base 21 and the conductive bottom surface 423 of the second conductive segment 422 of the metal frame 4 exposed to the outside, and can be used as the conductive pins of the multi-chip packaging component for external electrical connection through the pins 23 of the basic lead frame 2 and the second conductive segment 422 of the main conductive sheet 41.

[0053] The preparation method of the multi-chip package component according to the embodiment of the present invention is described as follows.

[0054] See also Figure 3 The method for preparing the multi-chip package element includes a providing step 91, a first chip setting step 92, a second chip setting step 93, a metal frame setting step 94, an electrical connection step 95, a packaging step 96, and a processing step 97.

[0055] Related References Figure 4 First, the providing step 91 is performed to provide Figure 4 The lead frame unit 200 is shown.

[0056] The lead frame unit 200 can be obtained by, for example, stamping and forming, and comprises an outer frame 201, and a plurality of basic lead frames 2 located in the outer frame 201 and connected to the outer frame 201 and connected to each other in an array arrangement. The structure of each basic lead frame 2 is the same as the aforementioned basic lead frame 2, and thus will not be described in detail herein.

[0057] Related References Figure 4 , 5 ,in, Figure 5 yes Figure 4 The sectional structure of the AA section line in the figure, and the subsequent steps are explained in conjunction with the sectional structure.

[0058] Next, the first chip arrangement step 92 and the second chip arrangement step 93 are performed to arrange the transistor chip 3 and the control circuit chip 5 on the surface 211 of the support base 21 of each base lead frame 2 .

[0059] Specifically, the first chip setting step 92 is to use the conductive solder 101 to electrically connect the drain 33 of the transistor chip 3 to the corresponding first carrier part 211A. The second chip setting step 93 is to use the insulating glue 102 to bond the control circuit chip 5 to the second carrier part 211B, so that the bottom of the control circuit chip 5 is electrically insulated from the second carrier part 211B. Since the partition wall 22 is provided between the first carrier part 211A and the second carrier part 211B of each of the carrier seats 21, the conductive solder 101 and the insulating glue 102 can be effectively isolated to prevent the electrical characteristics required for the transistor chip 3 and the control circuit chip 5 to be bonded to the carrier seat 21 from being interfered by the conductive solder 101 and the insulating glue 102.

[0060] Next, the metal frame setting step 94 is performed to provide a plurality of metal brackets 400 , and the metal brackets 400 are respectively welded to the active surface of the transistor chip 3 .

[0061] Specifically, each metal bracket 400 has Figure 1The metal frame 4 shown in the figure has the same structure as the main conductive sheet 41 and the slot 43 penetrating the main conductive sheet 41, but the difference is that each metal support 400 has a plurality of legs 402 extending from the main conductive sheet 41, and each leg 402 has a first conductive segment 402A extending from the main conductive sheet 41 and having a height not less than that of the main conductive sheet 41, and an extension segment 402B extending from the first conductive segment 402A in a direction away from and substantially parallel to the main conductive sheet 41. The metal frame setting step 94 is to weld the main conductive sheet 41 of the metal support 400 to the active surface of the transistor chip 3, electrically connect it to two of the source pads 31a and 31b of the transistor chip 3, and allow the slot 43 to be located correspondingly in the gap between the two source pads 31a and 31b.

[0062] Then, the electrical connection step 95 is performed, and the connection pad 51 of the control circuit chip 5 arranged on each of the basic lead frames 2 is electrically connected to the other source pads 31c, 31d of the transistor chip 3, the gate 32, and the corresponding pin 23 of the basic lead frame 2 through the bonding wire 52 by using the wire bonding method.

[0063] Afterwards, the packaging step 96 is performed, and the sealing layer 6 covering the metal bracket 400, the transistor chip 3, and the control circuit chip 5 is formed by molding using a sealing material, and the bottom surface 212 of the supporting base 21 and at least part of the supporting legs 402 are exposed outside the sealing layer 6, thereby forming a plurality of semi-finished products S in the outer frame 201.

[0064] Finally, the processing step 97 is performed, as shown in FIG. Figure 4 The cutting line X is cut to obtain a plurality of independent semi-finished products S, and then the legs 402 of each semi-finished product S are bent into a shape as shown in FIG. Figure 1 The structure of the conductive pins 42 shown in the figure enables the metal bracket 400 to form the metal frame 4, thereby completing the preparation of the multi-chip package component.

[0065] In summary, the multi-chip package component of the present invention uses the conductive pins 42 of the metal frame 4 directly as the conductive pins for the transistor chip 3 to be electrically connected to the outside, and there will be no solder joints that use bonding wires as the electrical connection medium between the transistor chip and the lead frame in the past. Therefore, the problem of the solder joints between the bonding wires used for electrical connection and the pins of the lead frame being easily broken / detached during the packaging or manufacturing process, which is a problem of the packaging component that uses the pins of the lead frame carrying the chip as the pins for external electrical connection, being prone to occur. In addition, the bending structure (second conductive segment 422) of the conductive pins 42 used for external electrical connection of the multi-chip package component of the present invention is obtained by bending the legs 402 located outside the sealing layer 6 after forming the sealing layer 6. Since the bending structure is located outside the sealing layer 6, the influence of the bending stress of the conductive pins 42 on the sealing layer 6 can be effectively reduced, and stress damage can be avoided at the interface between the conductive pins 42 and the sealing layer 6, so that the packaging component has better stability, and thus the purpose of the present invention can be achieved.

Claims

1. A multi-chip package component, characterized in that: Include: The basic lead frame is made of conductive material, has a bearing seat, and a plurality of pins extending from the bearing seat and spaced apart from each other, and the bearing seat has a surface and a bottom surface opposite to each other; A transistor chip is disposed on the surface of the carrier, and has an active surface and a bottom surface opposite to each other, a plurality of source pads and a gate located on the active surface, and a drain located on the bottom surface of the transistor chip, and the drain is electrically connected to the carrier; The control circuit chip is electrically insulated and disposed on the surface of the supporting base. and is electrically connected to the transistor chip and the pin; A metal frame, comprising a main conductive sheet, and at least one conductive pin extending integrally from the main conductive sheet and used for direct external electrical connection, wherein the main conductive sheet covers the transistor chip and is electrically connected to at least a portion of the source pad of the transistor chip, wherein the conductive pin comprises a first conductive segment and a second conductive segment, wherein the first conductive segment extends from the main conductive sheet and has a height not less than that of the main conductive sheet, and the second conductive segment bends and extends from the first conductive segment toward the direction of the basic lead frame and has a conductive bottom surface coplanar with the bottom surface of the supporting seat; and The sealing layer covers the basic lead frame, the transistor chip, the control circuit chip, the main conductive sheet of the metal frame, and the first conductive segment, and exposes the supporting seat to the outside, and the second conductive segment is located outside the sealing layer.

2. The multi-chip package component according to claim 1, wherein: The transistor chip has three source pads and a gate, wherein one source pad is electrically connected to the main conductive sheet, and the gate and the other two source pads are electrically connected to the control circuit chip.

3. The multi-chip package component according to claim 1, wherein: The transistor chip has four source pads, the main conductive sheet is electrically connected to two of the source pads at the same time, and the two source pads are spaced apart by a gap.

4. The multi-chip package component according to claim 3, wherein: The main conductive sheet has a slot at a position corresponding to the gap.

5. The multi-chip package component according to claim 1, wherein: The first conductive segment has an extension portion extending from the main conductive sheet and having a height not less than that of the main conductive sheet, and a parallel portion connected to the extension portion and parallel to the main conductive sheet, the second conductive segment has a first conductive portion connected to the parallel portion and having a bending angle with the parallel portion between 60° and 80°, and a second conductive portion bent from the first conductive portion and having a bending angle with the first conductive portion between 60° and 80°, and the second conductive portion has the conductive bottom surface.

6. The multi-chip package component according to claim 1, wherein: The source pad and the gate are electrically connected to the control circuit chip via bonding wires.

7. The multi-chip package component according to claim 1, wherein: The basic lead frame also has a partition wall formed on the surface of the carrier, and the surface of the carrier is defined as a first carrier part located on opposite sides of the partition wall and used to carry the transistor chip, and a second carrier part used to carry the control circuit chip.

8. The multi-chip package component according to claim 7, wherein: The basic lead frame has a plurality of pins extending from one side of the second carrying portion and spaced apart from each other, and the control circuit chip is electrically connected to the pins of the basic lead frame through bonding wires.

9. The multi-chip package component according to claim 7, wherein: The partition wall and the bearing seat are made of the same material and are integrally formed.

10. The multi-chip package component according to claim 1, wherein: The main conductive sheet covers at least 50% of the surface area of ​​the transistor chip.

11. A method for preparing a multi-chip package component, characterized in that: Include: Providing a lead frame unit, the lead frame unit having an outer frame, and a plurality of basic lead frames located in the outer frame, connected to the outer frame and arranged in connection with each other, each basic lead frame having a bearing seat and a plurality of pins extending integrally from the bearing seat and spaced from each other; A first chip arrangement step is to arrange a transistor chip on the surface of each base of the base lead frame in a forward packaging manner, wherein the transistor chip has a drain electrically connected to the base, and a plurality of source pads and gates located on the surface of the transistor chip opposite to the base; A second chip arrangement step is to arrange a control circuit chip on the surface of each base of the base lead frame in a forward packaging manner, wherein the control circuit chip is electrically isolated from the base and is located on the same surface as the transistor chip and arranged at intervals; A metal frame setting step, providing a plurality of metal brackets, each of which has a main conductive sheet and at least one leg extending from the main conductive sheet, and the main conductive sheets of the metal brackets are respectively covered on the surface of the transistor chip and are respectively electrically connected to at least one source pad of the corresponding transistor chip; An electrical connection step of electrically connecting the control circuit chip disposed on each of the basic lead frames to the other source pads of the transistor chip, the gate, and the pins of the basic lead frame; A packaging step, using a sealing material to cover the metal bracket, the transistor chip, and the control circuit chip to form a sealing layer, and leaving the bottom surface of the carrier opposite to the surface thereof and at least part of the at least one leg exposed outside the sealing layer to obtain a plurality of semi-finished products; and The processing step is to obtain any independent semi-finished product, and bend the at least one leg of the semi-finished product exposed outside the sealing layer toward the basic lead frame, so that the at least one leg forms a second conductive part with a conductive bottom surface flush with the bottom surface of the supporting seat.

12. The method for preparing a multi-chip package component according to claim 11, characterized in that: Each of the basic lead frames provided in the providing step also has a partition wall located on the surface of the carrier seat, and the partition wall separates the surface of the carrier seat into a first carrier portion and a second carrier portion located on opposite sides of the partition wall, the transistor chip and the control circuit chip are respectively arranged on the first carrier portion and the second carrier portion, and the pins extend integrally from at least one side of the second carrier portion.

13. The method for preparing a multi-chip package component according to claim 12, characterized in that: The partition wall and the bearing seat are made of the same material and are integrally formed.

14. The method for preparing a multi-chip package component according to claim 11, characterized in that: The at least one leg comprises a first conductive segment extending from the main conductive sheet and having a height not less than that of the main conductive sheet, and an extension segment extending from the first conductive segment in a direction away from and parallel to the main conductive sheet. The packaging step is to expose at least a portion of the extension segment to the outside of the sealing layer. The processing step is to bend the extension segment exposed to the outside of the sealing layer toward the direction of the basic lead frame so that the extension segment forms a parallel portion parallel to the main conductive sheet, a first conductive portion connected to the parallel portion at a bending angle between 60° and 80°, and a second conductive portion bent from the first conductive portion and at a bending angle between 60° and 80° to the first conductive portion.

15. The method for preparing a multi-chip package component according to claim 11, characterized in that: The electrical connection step is to electrically connect the control circuit chip with other source pads and the gate of the transistor chip respectively by wire bonding.

Images