Wafer and preparation method thereof

Abstract

According to the wafer and the preparation method thereof provided by the invention, the grounding requirement of a semiconductor device obtained by segmenting the wafer can be ensured, the heat dissipation characteristic of the semiconductor device is improved, and the warping degree of the wafer is greatly reduced. The wafer may include a substrate, a patterned metal layer, and a plurality of first electrodes. Wherein the substrate can be provided with a plurality of through holes. The multiple first electrodes can be located on the first surface of the substrate and located at the bottoms of the multiple through holes in a one-to-one correspondence mode. A patterned metal layer may be disposed on the second surface of the substrate and the sidewall and bottom of each of the plurality of vias. The edge of the portion, located on the second surface, of the patterned metal layer can be flush with the edge of the substrate. The first surface is opposite to the second surface.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a wafer and a method for preparing the same. Background Art

[0002] With the rapid development of semiconductor technology, semiconductor devices such as high electron mobility transistors (HEMT) and metal-oxide-semiconductor field-effect transistors (MOSFET) obtained by dividing wafers have been widely used. The wafer may include a stacked substrate and a metal layer. The substrate may be provided with through holes. Although the metal layer can achieve the grounding requirements and good heat dissipation characteristics of the semiconductor device through the through holes, when the thickness of the wafer is thin (such as less than 200um), the stress of the metal layer will cause the wafer to have a large warpage.

[0003] Related technologies usually pattern the metal layer through a dry etching process or a wet etching process to release the stress of the metal layer, thereby reducing the warpage of the wafer. However, the dry etching process or the wet etching process is easy to damage the metal layer at the bottom of the through hole on the substrate, which not only fails to meet the grounding requirements of the semiconductor device, but also causes the heat dissipation characteristics of the semiconductor device to deteriorate.

[0004] Therefore, there is an urgent need for a technical solution that can ensure the grounding requirements of semiconductor devices, improve the heat dissipation characteristics of semiconductor devices and reduce the warpage of wafers. Summary of the invention

[0005] The present application provides a wafer and a preparation method thereof, which can not only ensure the grounding requirements of semiconductor devices obtained by dividing the wafer and improve the heat dissipation characteristics of the semiconductor devices, but also greatly reduce the warping of the wafer.

[0006] In a first aspect, the present application provides a wafer that may include a substrate, a patterned metal layer, and a plurality of first electrodes.

[0007] The substrate may be provided with a plurality of through holes. The plurality of first electrodes may be located on the first surface of the substrate and may be located at the bottom of the plurality of through holes in a one-to-one correspondence. The patterned metal layer may be disposed on the second surface of the substrate and the sidewall and bottom of each through hole in the plurality of through holes. The edge of the portion of the patterned metal layer located on the second surface may be flush with the edge of the substrate. The first surface is disposed opposite to the second surface.

[0008] In the wafer provided by the present application, the patterned metal layer can be arranged on the second surface of the substrate and the sidewalls and bottom of each through hole, and the edge of the portion of the patterned metal layer located on the second surface can be flush with the edge of the substrate, thereby ensuring the grounding requirements of the semiconductor devices obtained by dividing the wafer, improving the heat dissipation characteristics of the semiconductor devices, and greatly reducing the warping of the wafer.

[0009] In a possible implementation, the patterned metal layer may include an adhesion layer, a seed layer, and an electroplating layer that are stacked, wherein the adhesion layer is closer to the second surface than the seed layer and the electroplating layer.

[0010] Optionally, the thickness of the patterned metal layer may be in the micrometer range. More specifically, the thickness of the patterned metal layer may be 2um to 16um. In other words, the thickness of the portion of the patterned metal layer located on the second surface and the portion located on the sidewall and bottom of the through hole may both be 2um to 16um.

[0011] In one example, the adhesion layer may be made of metal materials or alloy materials such as titanium Ti, titanium nitride TiN, tantalum Ta, and tantalum nitride TaN. Of course, the adhesion layer may also be made of other metal materials or alloy materials, which are not limited in this application.

[0012] In another example, the seed layer can be made of metal materials such as copper Cu (Cuprum), gold Au (Aurum), tungsten W (Tungsten), nickel Ni (Nickel), tin Sn (Stannum), etc., and can also be alloy materials such as titanium tungsten TiW (Titanium Tungsten) and titanium gold TiAu (Titanium Aurum). Of course, the seed layer can also be made of other metal materials or alloy materials, which is not limited in this application. The thickness of the seed layer can be 10nm~1um. Of course, the seed layer can also be of other thicknesses, which is not limited in this application.

[0013] In another example, the electroplating layer can be made of metal materials such as copper Cu, gold Au, tin Sn, silver Ag (Argentum), etc. Of course, the electroplating layer can also be made of other metal materials, which is not limited in this application. The thickness of the electroplating layer can be 2um to 16um. Of course, the electroplating layer can also be of other thicknesses, which is not limited in this application.

[0014] Optionally, the aspect ratio of the through hole is 1:5 to 10:1. Of course, the larger the aspect ratio, the deeper the through hole. The thickness of the electroplating layer can be determined according to the aspect ratio of the through hole.

[0015] In another possible implementation, the patterned metal layer may have a plurality of segmentation units. Two adjacent segmentation units among the plurality of segmentation units may be segmented by one or more grooves. It is understood that when two adjacent segmentation units are segmented by one groove, it can be understood that a plurality of grooves are continuously arranged to form one groove. When two adjacent segmentation units are segmented by a plurality of grooves, it can be understood that a plurality of grooves are arranged at intervals and are non-continuous.

[0016] For example, each of the plurality of segmentation units may be a polygon such as a square or a rectangle. The size of each segmentation unit may be less than or equal to 15 mm.

[0017] For example, if the segmentation unit is a square, then the side length of the segmentation unit may be less than or equal to 15 mm.

[0018] For another example, if the segmentation unit is a rectangle, then the width of the segmentation unit may be less than or equal to 15 mm.

[0019] Optionally, the width of the groove may be 5 um to 100 um. Of course, the groove may also be of other widths, which is not limited in this application.

[0020] In one example, the position of the bottom of the groove may satisfy any of the following conditions:

[0021] 1. The bottom of the groove can be located inside the electroplating layer.

[0022] 2. The bottom of the groove can be located at the interface between the electroplating layer and the seed layer.

[0023] 3. The bottom of the groove can be located inside the seed layer.

[0024] 4. The bottom of the groove may be located at the interface between the seed layer and the adhesion layer.

[0025] 5. The bottom of the groove can be located inside the adhesive layer.

[0026] 6. The bottom of the groove may be located at the interface between the adhesion layer and the substrate.

[0027] 7. The bottom of the groove can be located inside the substrate.

[0028] In another example, the depth of the groove may be greater than or equal to 60% of the thickness of the patterned metal layer and less than or equal to 30% of the thickness of the substrate. Since the thickness of the electroplated layer may be greater than the thickness of the seed layer and the thickness of the adhesion layer, when the depth of the groove is equal to 60% of the thickness of the patterned metal layer, it can be considered that the bottom of the groove may be located inside the electroplated layer. When the depth of the groove is equal to 30% of the thickness of the substrate, it can be considered that the bottom of the groove may be located inside the substrate.

[0029] In some possible implementations, the wafer provided in the present application may further include an epitaxial layer, a plurality of second electrodes, and a plurality of third electrodes.

[0030] The epitaxial layer may include a channel layer stacked on the first surface of the substrate. The plurality of second electrodes and the plurality of third electrodes may be located on the first surface, and the plurality of second electrodes and the plurality of third electrodes may be in contact with the channel layer.

[0031] Of course, in addition to the channel layer, the epitaxial layer may also include a nucleation layer, a buffer layer, a barrier layer, and a cap layer. The nucleation layer, the buffer layer, the channel layer, the barrier layer, and the cap layer are sequentially stacked on the first surface. Among them, the nucleation layer is closer to the substrate than the buffer layer, the channel layer, the barrier layer, and the cap layer.

[0032] Optionally, the first electrode may serve as a source electrode, the second electrode may serve as a gate electrode, and the third electrode may serve as a drain electrode.

[0033] In a second aspect, the present application provides a method for preparing a wafer, which may include: forming a plurality of first electrodes on a first surface of a substrate. Photolithography and etching the second surface of the substrate to form a plurality of through holes. The second surface and the first surface may be arranged relative to each other. Metallizing the substrate and each through hole in the plurality of through holes to form a metal layer. Slicing the metal layer to form a patterned metal layer. The edge of the portion of the patterned metal layer located on the second surface may be flush with the edge of the substrate.

[0034] In the wafer preparation method provided in the present application, a patterned metal layer is formed by dividing the metal layer. Due to the division, the stress of the patterned metal layer is released. Therefore, the patterned metal layer can meet the grounding requirements of the semiconductor device obtained by dividing the wafer, improve the heat dissipation characteristics of the semiconductor device, and greatly reduce the warping of the wafer.

[0035] In a possible implementation, metallizing the substrate and each through hole in the plurality of through holes to form a metal layer may include: forming an adhesion layer on the second surface and the sidewall and bottom of each through hole. That is, the adhesion layer may cover the second surface of the substrate and the sidewall and bottom of each through hole. A seed layer and an electroplating layer are sequentially formed on the surface of the adhesion layer. That is, the seed layer may cover the adhesion layer, and the electroplating layer covers the seed layer. It can be seen that the adhesion layer is closer to the second surface than the seed layer and the electroplating layer.

[0036] Optionally, the thickness of the patterned metal layer can be in the micrometer range. More specifically, the thickness of the patterned metal layer can be 2um to 16um. That is, the thickness of the portion of the patterned metal layer located on the second surface (which can be called the first portion) and the portion located on the sidewall and bottom of the through hole (which can be called the second portion) can both be 2um to 16um. In the present application, the thickness of the second portion can be less than or equal to the thickness of the first portion.

[0037] In one example, the adhesion layer may be made of metal materials or alloy materials such as titanium Ti, titanium nitride TiN, tantalum Ta, and tantalum nitride TaN. Of course, the adhesion layer may also be made of other metal materials or alloy materials, which are not limited in this application.

[0038] In another example, the seed layer can be made of metal materials such as copper Cu (Cuprum), gold Au (Aurum), tungsten W (Tungsten), nickel Ni (Nickel), tin Sn (Stannum), etc., and can also be alloy materials such as titanium tungsten TiW (Titanium Tungsten) and titanium gold TiAu (Titanium Aurum). Of course, the seed layer can also be made of other metal materials or alloy materials, which is not limited in this application. The thickness of the seed layer can be 10nm~1um. Of course, the seed layer can also be of other thicknesses, which is not limited in this application.

[0039] In another example, the electroplating layer can be made of metal materials such as copper Cu, gold Au, tin Sn, silver Ag (Argentum), etc. Of course, the electroplating layer can also be made of other metal materials, which is not limited in this application. The thickness of the electroplating layer can be 2um to 16um. Of course, the electroplating layer can also be of other thicknesses, which is not limited in this application.

[0040] Optionally, the aspect ratio of the through hole is 1:5 to 10:1. Of course, the larger the aspect ratio, the deeper the through hole. The thickness of the electroplating layer can be determined according to the aspect ratio of the through hole.

[0041] In another possible implementation, dividing the metal layer to form a patterned metal layer may include: dividing the metal layer using a pulsed laser to form a patterned metal layer. In other words, the patterned metal layer may be obtained by dividing the metal layer.

[0042] Further, the wavelength of the pulsed laser may be 200 nm to 400 nm, the frequency of the pulsed laser may be greater than or equal to 500 Hz, and the power of the pulsed laser may be 2 W to 6 W. Of course, the wavelength, frequency and power of the pulsed laser may also be in other ranges, which are not limited in this application.

[0043] In another possible implementation, the patterned metal layer may have a plurality of segmentation units. Two adjacent segmentation units among the plurality of segmentation units may be segmented by one or more grooves. It is conceivable that when two adjacent segmentation units are segmented by one groove, it can be understood that a plurality of grooves are continuously arranged to form one groove. When two adjacent segmentation units are segmented by a plurality of grooves, it can be understood that a plurality of grooves are arranged at intervals and are non-continuous.

[0044] For example, each of the plurality of segmentation units may be a polygon such as a square or a rectangle. The size of each segmentation unit may be less than or equal to 15 mm.

[0045] For example, if the segmentation unit is a square, then the side length of the segmentation unit may be less than or equal to 15 mm.

[0046] For another example, if the segmentation unit is a rectangle, then the width of the segmentation unit may be less than or equal to 15 mm.

[0047] Optionally, the width of the groove may be 5 um to 100 um. Of course, the groove may also be of other widths, which is not limited in this application.

[0048] In one example, the position of the bottom of the groove may satisfy any of the following conditions:

[0049] 1. The bottom of the groove can be located inside the electroplating layer.

[0050] 2. The bottom of the groove can be located at the interface between the electroplating layer and the seed layer.

[0051] 3. The bottom of the groove can be located inside the seed layer.

[0052] 4. The bottom of the groove may be located at the interface between the seed layer and the adhesion layer.

[0053] 5. The bottom of the groove can be located inside the adhesive layer.

[0054] 6. The bottom of the groove may be located at the interface between the adhesion layer and the substrate.

[0055] 7. The bottom of the groove can be located inside the substrate.

[0056] In another example, the depth of the groove may be greater than or equal to 60% of the thickness of the patterned metal layer and less than or equal to 30% of the thickness of the substrate. Since the thickness of the electroplated layer may be greater than the thickness of the seed layer and the thickness of the adhesion layer, when the depth of the groove is equal to 60% of the thickness of the patterned metal layer, it can be considered that the bottom of the groove may be located inside the electroplated layer. When the depth of the groove is equal to 30% of the thickness of the substrate, it can be considered that the bottom of the groove may be located inside the substrate.

[0057] In some possible implementations, the preparation method provided in the present application may further include: forming an epitaxial layer on the first surface of the substrate, and forming a plurality of second electrodes and a plurality of third electrodes on the surface of the epitaxial layer.

[0058] Optionally, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer are sequentially formed on the first surface of the substrate to form an epitaxial layer. It can be seen that the nucleation layer is closer to the substrate than the buffer layer, the channel layer, the barrier layer and the cap layer.

[0059] Furthermore, the plurality of second electrodes and the plurality of third electrodes may all be in contact with the channel layer, wherein the first electrode may be used as a source electrode, the second electrode may be used as a gate electrode, and the third electrode may be used as a drain electrode.

[0060] Exemplarily, the preparation method provided in the present application may further include: dividing the patterned metal layer and the substrate along the groove to obtain a plurality of semiconductor devices. Alternatively, dividing the substrate along the groove to obtain a plurality of semiconductor devices.

[0061] It is understood that when the bottom of the groove is located inside the patterned metal layer (including when the bottom of the groove is located inside the electroplating layer, at the interface between the electroplating layer and the seed layer, inside the seed layer, at the interface between the seed layer and the adhesion layer, and inside the adhesion layer), it indicates that the patterned metal layer is not completely divided, and the patterned metal layer and the substrate can be divided along the groove. When the bottom of the groove is located at the interface between the patterned metal layer and the substrate or at the back of the substrate, it indicates that the patterned metal layer is completely divided, and the substrate can be divided along the groove.

[0062] Optionally, in the plurality of semiconductor devices, the patterned metal layer of each semiconductor device may have one or more grooves, and the width of the grooves is 5 um to 100 um, which is not limited in the embodiment of the present application.

[0063] Similar to the groove of the wafer, the bottom of the groove of the semiconductor device can also be located inside the electroplating layer, at the interface between the electroplating layer and the seed layer, inside the seed layer, at the interface between the seed layer and the adhesion layer, inside the adhesion layer, at the interface between the adhesion layer and the substrate, or inside the substrate.

[0064] Exemplarily, the semiconductor device may be a high electron mobility transistor (HEMT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-semiconductor field effect transistor (MESFET), etc. Of course, the semiconductor device may also be other devices, which are not limited in this application.

[0065] In a third aspect, the present application further provides a power amplifier, comprising a passive device and a semiconductor device. The passive device can be connected to the semiconductor device.

[0066] Optionally, the passive device may be a capacitor, a resistor, etc., which is not limited in this application.

[0067] In a fourth aspect, the present application further provides a communication system, which may include a radio frequency integrated circuit and a power amplifier provided by the third aspect and possible implementations thereof. The power amplifier may be connected to the radio frequency integrated circuit.

[0068] Optionally, the communication system may further include an antenna. The input end of the power amplifier may be connected to the radio frequency integrated circuit, and the output end of the power amplifier may be connected to the antenna. Thus, the first radio frequency signal output by the radio frequency integrated circuit is amplified by the power amplifier to obtain an amplified first radio frequency signal. The antenna transmits the amplified first radio frequency signal.

[0069] Furthermore, the communication system may also include a filter and a low noise amplifier. The input end of the filter may be connected to the antenna, the output end of the filter may be connected to the input end of the low noise amplifier, and the output end of the low noise amplifier may be connected to the radio frequency integrated circuit. Thus, the second radio frequency signal received by the antenna is filtered by the filter to obtain a filtered second radio frequency signal. The low noise amplifier amplifies the filtered second radio frequency signal and transmits the amplified second radio frequency signal to the radio frequency integrated circuit.

[0070] In a fifth aspect, the present application further provides an electronic device, which may include a power supply and a communication system provided by the fourth aspect and possible implementations thereof. The power supply may be connected to the communication system to supply power to the communication system.

[0071] Optionally, the electronic device may be a mobile phone, a watch, smart glasses, a Bluetooth headset, a router, etc., which is not limited in this application.

[0072] It should be understood that the second to fifth aspects of the present application are consistent with the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0074] Figure 1 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0075] Figure 2 A schematic structural diagram of a patterned metal layer 2 in an embodiment of the present application;

[0076] Figure 3 A schematic structural diagram of a patterned metal layer 2 in an embodiment of the present application;

[0077] Figure 4 A schematic structural diagram of a patterned metal layer 2 in an embodiment of the present application;

[0078] Figure 5 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0079] Figure 6 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0080] Figure 7 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0081] Figure 8 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0082] Fig. 9 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0083] Fig.10 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0084] Fig.11 is another schematic structural diagram of the wafer 10 in the embodiment of the present application;

[0085] Fig.12 A schematic structural diagram of a semiconductor device 100A / 100B in an embodiment of the present application;

[0086] Fig.13 A schematic structural diagram of a semiconductor device 100A / 100B in an embodiment of the present application;

[0087] Fig.14 is a schematic flow chart of the preparation process 20 in the embodiment of the present application;

[0088] Fig.15 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0089] Fig.16 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0090] Fig.17 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0091] Fig.18 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0092] Fig.19 A schematic flow chart of forming a metal layer in an embodiment of the present application;

[0093] Fig. 20 is a schematic flow chart of the preparation process 30 in the embodiment of the present application;

[0094] Fig.21 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0095] Fig. 22 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0096] Fig.23 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0097] Fig.24 is a schematic structural diagram of a wafer 10 in an embodiment of the present application;

[0098] Fig.25 A schematic structural diagram of the wafer 10 after the wafer 10 and the carrier 50 are debonded before the adhesion layer 21, the seed layer 22 and the electroplating layer 23 are separated in an embodiment of the present application;

[0099] Fig.26 A schematic structural diagram of the wafer 10 after the patterned metal layer 2 is formed in the embodiment of the present application and the wafer 10 and the carrier 50 are debonded;

[0100] Fig. 27 is a schematic structural diagram of a communication system 100 in an embodiment of the present application;

[0101] Fig.28 1 is a schematic structural diagram of an electronic device 1000 in an embodiment of the present application. DETAILED DESCRIPTION

[0102] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0103] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0104] The terms "first", "second", etc. in the specification embodiments, claims, and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product, or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0105] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0106] With the rapid development of semiconductor technology, semiconductor devices such as high electron mobility transistor (HEMT) and metal-oxide-semiconductor field-effect transistor (MOSFET) obtained by dividing wafers have been widely used. The wafer may include a stacked substrate and a metal layer. The substrate may be provided with through holes. Although the metal layer can achieve the grounding requirements and good heat dissipation characteristics of the semiconductor device through the through holes, the metal layer often has stress, which will cause a large warping of the wafer.

[0107] Related technologies usually pattern the metal layer through a dry etching process or a wet etching process to release the stress of the metal layer, thereby reducing the warpage of the wafer. However, the dry etching process or the wet etching process is easy to damage the metal layer at the bottom of the through hole on the substrate, which not only fails to meet the grounding requirements of the semiconductor device, but also causes the heat dissipation characteristics of the semiconductor device to deteriorate.

[0108] In order to overcome the above-mentioned shortcomings, the present application embodiment provides a wafer, such as Figure 1 As shown. The wafer 10 may include a substrate 1, a patterned metal layer 2 and a plurality of first electrodes. In the embodiment of the present application, the wafer 10 is introduced by taking the plurality of first electrodes including a first electrode 31 and a first electrode 32 as an example.

[0109] The substrate 1 may be provided with two through holes. The two through holes F may include a through hole F1 and a through hole F2. The first electrode 31 and the first electrode 32 may be located on the lower surface (i.e., the first surface) of the substrate 1 and may be located at the bottom of the through hole F1 and the through hole F2 in a one-to-one correspondence. In other words, the first electrode 31 and the first electrode 32 may be located on the lower surface of the substrate 1, and the first electrode 31 may be located at the bottom of the through hole F1, and the first electrode 32 may be located at the bottom of the through hole F2.

[0110] The patterned metal layer 2 may be disposed on the upper surface (i.e., the second surface) of the substrate 1, the sidewall of the through hole F1, the bottom of the through hole F1, the sidewall of the through hole F2, and the bottom of the through hole F2. The edge of the portion of the patterned metal layer 2 located on the second surface (i.e., the portion located on the upper surface of the substrate 1) may be flush with the edge of the substrate 1. The upper surface and the lower surface of the substrate 1 are disposed opposite to each other.

[0111] In the wafer 10 provided in the embodiment of the present application, the patterned metal layer 2 can be arranged on the upper surface of the substrate 1 and the side wall and bottom of each through hole, and the edge of the portion of the patterned metal layer 2 located on the upper surface can be flush with the edge of the substrate 1, thereby ensuring the grounding requirements of the semiconductor devices obtained by dividing the wafer 10, improving the heat dissipation characteristics of the semiconductor devices, and greatly reducing the warping of the wafer 10.

[0112] In some embodiments, Figure 1 As shown, the patterned metal layer 2 may include an adhesion layer 21, a seed layer 22 and an electroplating layer 23 which are stacked. The adhesion layer 21 is closer to the upper surface of the substrate 1 than the seed layer 22 and the electroplating layer 23.

[0113] Optionally, the thickness of the patterned metal layer 2 may be in the micrometer range. More specifically, the thickness of the patterned metal layer 2 may be 2um to 16um. That is, the thickness of the portion of the patterned metal layer 2 located on the upper surface of the substrate, the portion located on the sidewall and bottom of the through hole F1, and the portion located on the sidewall and bottom of the through hole F2 may all be 2um to 16um. In the present application, the thickness of the portion located on the sidewall and bottom of the through hole F1 and the portion located on the sidewall and bottom of the through hole F2 may be less than or equal to the thickness of the portion located on the upper surface of the substrate 1.

[0114] In one example, the adhesion layer 21 may be made of metal materials or alloy materials such as titanium Ti, titanium nitride TiN, tantalum Ta, and tantalum nitride TaN. Of course, the adhesion layer 21 may also be made of other metal materials or alloy materials, which are not limited in the present embodiment.

[0115] In another example, the seed layer 22 can be made of metal materials such as copper Cu (Cuprum), gold Au (Aurum), tungsten W (Tungsten), nickel Ni (Nickel), tin Sn (Stannum), etc., and can also be alloy materials such as titanium tungsten TiW (Titanium Tungsten) and titanium gold TiAu (Titanium Aurum). Of course, the seed layer 22 can also be made of other metal materials or alloy materials, which is not limited in the embodiment of the present application. The thickness of the seed layer 22 can be 10nm~1um. Of course, the seed layer 22 can also be of other thicknesses, which is not limited in the present application.

[0116] In another example, the electroplating layer 23 may be made of metal materials such as copper Cu, gold Au, tin Sn, silver Ag (Argentum), etc. Of course, the electroplating layer 23 may also be made of other metal materials, which is not limited in the embodiment of the present application. The thickness of the electroplating layer 23 may be 2um to 16um. Of course, the electroplating layer 23 may also be of other thicknesses, which is not limited in the embodiment of the present application.

[0117] Optionally, the aspect ratio of the through hole F1 and the through hole F2 can be 1:5 to 10:1. Of course, the larger the aspect ratio, the deeper the through hole F1 and the through hole F2. The thickness of the electroplating layer 23 can be determined according to the aspect ratio of the through hole F1 and the through hole F2.

[0118] In some other embodiments, the patterned metal layer 2 may have a plurality of segmentation units, such as Figure 2 shown. Figure 2 It can be a top view of the wafer 10. Two adjacent division units among the plurality of division units can be divided by one groove H. It is conceivable that when two adjacent division units are divided by one groove, it can be understood that a plurality of grooves are continuously arranged to form one groove.

[0119] Of course, two adjacent segmentation units in the plurality of segmentation units may also be segmented by a plurality of grooves H, such as Figure 3 It is conceivable that when two adjacent segmentation units are segmented by a plurality of grooves, it can be understood that the plurality of grooves are arranged at intervals and are non-continuous.

[0120] For example, each of the plurality of segmentation units may be a polygon such as a square or a rectangle. The size of each segmentation unit may be less than or equal to 15 mm.

[0121] The present application embodiment is described by taking the segmentation unit as a rectangle as an example. Figure 4 As shown, the segmentation unit is rectangular, and the width W of the segmentation unit may be less than or equal to 15 mm. It is conceivable that the length L of the segmentation unit is also less than or equal to 15 mm.

[0122] Optionally, continue to refer to Figure 4 , the width HW of the groove H may be 5um to 100um. Of course, the groove H may also be of other widths, which is not limited in the embodiment of the present application.

[0123] Combine the following Figures 5 to 10 , taking the case where all the grooves H have the same depth as an example, the position of the bottom of the groove H is introduced.

[0124] 1. If Figure 5 As shown, the bottom of the groove H may be located inside the electroplating layer 23 .

[0125] 2. If Figure 6As shown, the bottom of the groove H may be located at the interface between the electroplating layer 23 and the seed layer 22 .

[0126] 3. If Figure 7 As shown, the bottom of the groove H may be located inside the seed layer 22 .

[0127] 4. If Figure 8 As shown, the bottom of the groove H may be located at the interface between the seed layer 22 and the adhesion layer 21 .

[0128] 5. If Fig. 9 As shown, the bottom of the groove H may be located inside the adhesive layer 21 .

[0129] 6. If Figure 1 As shown, the bottom of the groove H may be located at the interface between the adhesion layer 21 and the substrate 1 .

[0130] 7. If Fig.10 As shown, the bottom of the groove H may be located inside the substrate 1 .

[0131] Exemplarily, the depth of the groove H may be greater than or equal to 60% of the thickness of the patterned metal layer 2 and less than or equal to 30% of the thickness of the substrate 1. Since the thickness of the electroplating layer 23 may be greater than the thickness of the seed layer 22 and the thickness of the adhesion layer 21, when the depth of the groove H is equal to 60% of the thickness of the patterned metal layer 2, it can be considered that the bottom of the groove H may be located inside the electroplating layer 23, which can be referred to Figure 5 When the depth of the groove H is equal to 30% of the thickness of the substrate 1, it can be considered that the bottom of the groove H can be located inside the substrate 1, which can be referred to Fig.10 .

[0132] In some other embodiments, Figure 1 , Figures 5 to 10 As shown, the wafer 10 may further include an epitaxial layer 6 , a plurality of second electrodes and a plurality of third electrodes. The plurality of second electrodes include a second electrode 41 and a second electrode 42 . The plurality of third electrodes include a third electrode 51 and a third electrode 52 .

[0133] Optionally, the epitaxial layer 6 may include a channel layer ( Figure 1 , Figures 5 to 10 (not shown). The second electrode 41, the second electrode 42, the third electrode 51 and the third electrode 52 may be located on the lower surface of the substrate 1, and the second electrode 41, the second electrode 42, the third electrode 51 and the third electrode 52 may be in contact with the channel layer.

[0134] Of course, the epitaxial layer 6 may include a nucleation layer, a buffer layer, a barrier layer, a cap layer, etc. in addition to the channel layer. The nucleation layer, the buffer layer, the channel layer, the barrier layer, and the cap layer are sequentially stacked on the lower surface of the substrate 1. Among them, the nucleation layer is closer to the substrate 1 than the buffer layer, the channel layer, the barrier layer, and the cap layer.

[0135] Optionally, the first electrode 31 and the first electrode 32 can both serve as the source of the semiconductor device, the second electrode 41 and the second electrode 42 can both serve as the gate of the semiconductor device, and the third electrode 51 and the third electrode 52 can both serve as the drain of the semiconductor device.

[0136] The present application also provides another wafer, such as Fig.11 As shown. Figure 1 , Figures 5 to 10 same, Fig.11 The wafer 10 shown may also include a substrate 1, an epitaxial layer 6, a patterned metal layer 2, a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes. The plurality of first electrodes include a first electrode 31, a first electrode 32, a first electrode 33, and a first electrode 34. The plurality of second electrodes include a second electrode 41, a second electrode 42, a second electrode 43, and a second electrode 44. The plurality of third electrodes include a third electrode 51 and a third electrode 52.

[0137] Optionally, the substrate 1 and the epitaxial layer 6 are stacked. The substrate 1 may be provided with four through holes. The four through holes may include a through hole F1, a through hole F2, a through hole F3, and a through hole F4. The patterned metal layer 2 may be provided on the upper surface of the substrate 1, the side walls from the through hole F1 to the through hole F4, the bottom from the through hole F1 to the through hole F4, the side walls from the through hole F1 to the through hole F4, and the bottom from the through hole F1 to the through hole F4. The edge of the portion of the patterned metal layer 2 located on the second surface (that is, the portion located on the upper surface of the substrate 1) may be flush with the edge of the substrate 1. The upper surface and the lower surface of the substrate 1 are arranged opposite to each other.

[0138] The first electrode 31, the first electrode 32, the first electrode 33 and the first electrode 34 may all be located on the lower surface of the substrate 1 and may be located one by one at the bottom of the through holes F1 to F4. That is, the first electrode 31, the first electrode 32, the first electrode 33 and the first electrode 34 may all be located on the lower surface of the substrate 1, and the first electrode 31 may be located at the bottom of the through hole F1, the first electrode 32 may be located at the bottom of the through hole F2, the first electrode 33 may be located at the bottom of the through hole F4, and the first electrode 34 may be located at the bottom of the through hole F4.

[0139] The patterned metal layer 2 can refer to the relevant introduction above, and will not be described in detail in the embodiment of the present application.

[0140] Further, continue to refer to Fig.11The wafer 10 may further include a plurality of second electrodes and a plurality of third electrodes. The plurality of second electrodes include a second electrode 41, a second electrode 42, a second electrode 43, and a second electrode 44. The plurality of third electrodes include a third electrode 51 and a third electrode 53. The second electrode 41, the second electrode 42, the second electrode 43, the second electrode 44, the third electrode 51, and the third electrode 53 may all contact the channel layer in the epitaxial layer 6.

[0141] Optionally, the first electrode 31, the first electrode 32, the first electrode 33 and the first electrode 34 can all serve as the source of the semiconductor device, the second electrode 41, the second electrode 42, the second electrode 43 and the second electrode 44 can all serve as the gate of the semiconductor device, and the third electrode 51 and the third electrode 53 can all serve as the drain of the semiconductor device.

[0142] In some embodiments, the Figure 1 , Figures 5 to 10 The substrate 1 is divided by any groove H between the through hole F1 and the through hole F2 to obtain two semiconductor devices, namely, the semiconductor device 100A and the semiconductor device 100B. The semiconductor device 100A or the semiconductor device 100B can refer to Fig.13 shown.

[0143] In other embodiments, the Fig.11 The substrate 1 is divided by any groove H between the through hole F2 and the through hole F3, and the following is obtained: Fig.13 A semiconductor device 100 is shown.

[0144] because Figure 1 as well as Figures 5 to 11 The bottom of the groove H is located at the interface between the adhesion layer 21 and the substrate 1, and the substrate 1 is divided to obtain the semiconductor device 100A and the semiconductor device 100B. Therefore, it can be imagined that when the bottom of the groove H is located inside the electroplating layer 23, at the interface between the electroplating layer 23 and the seed layer 22, inside the seed layer 22, at the interface between the seed layer 22 and the adhesion layer 21, and inside the adhesion layer 21, the patterned metal layer 2 and the substrate 1 can be divided along the groove H to obtain the semiconductor device 100A and the semiconductor device 100B.

[0145] like Fig.12 and Fig.13 In the semiconductor device 100A or the semiconductor device 100B shown, the patterned metal layer 2 may have a plurality of grooves, and the width of the grooves is 5 um to 100 um, which is not limited in the present embodiment.

[0146] Exemplarily, the semiconductor device 100A and the semiconductor device 100B can both be high electron mobility transistors (HEMT), metal-oxide-semiconductor field-effect transistors (MOSFET), metal-semiconductor field effect transistors (MESFET), etc. Of course, the semiconductor device 100A and the semiconductor device 100B can also be other devices, which are not limited in the embodiments of the present application.

[0147] The present application also provides a method for preparing the wafer 10. Figure 1 , Figures 5 to 10 The wafer 10 shown in the figure is used as an example to introduce the preparation method. Fig.14 As shown, the preparation process 20 may include the following steps:

[0148] Step S201: forming a first electrode 31 and a first electrode 32 on the lower surface (ie, the first surface) of the substrate 1, such as Fig.15 shown.

[0149] Step S202: Photolithography and etching are performed on the upper surface (i.e., the second surface) of the substrate 1 to form through holes F1 and through holes F2. Fig.16 and Fig.17 (Top view) as shown.

[0150] Optionally, a dry etching process or a wet etching process may be used to etch the upper surface of the substrate 1. Of course, a combination of a dry etching process and a wet etching process or other processes may also be used to etch the upper surface of the substrate 1, which is not limited in the present embodiment.

[0151] The dry etching process may include a deep reactive ion etching (DRIE) process (hereinafter referred to as DRIE process), an inductively coupled plasma (ICP) etching process (hereinafter referred to as ICP etching process), etc. The wet etching process may use a solution such as potassium hydroxide (KOH) to etch the upper surface of the substrate 1.

[0152] It is conceivable that the substrate 1 may be made of silicon or other materials, so it can be considered that the embodiment of the present application forms the through-hole F1 and the through-hole F2 by adopting through silicon via (TSV) technology. Therefore, the through-hole F1 and the through-hole F2 can both be called TSV holes.

[0153] Step S203: metallizing the substrate 1, the through hole F1 and the through hole F2 to form a metal layer, such as Fig.18 The metal layer includes Fig.18 The adhesion layer 21, the seed layer 22 and the electroplating layer 23 are formed.

[0154] Step S204: Segment the metal layer to form a patterned metal layer 2, such as Figure 1 As shown. The edge of the portion of the patterned metal layer 2 located on the upper surface of the substrate 1 may be flush with the edge of the substrate 1. It is conceivable that in the process of segmenting the metal layer, the through hole F1 and the through hole F2 may be avoided to avoid damaging the metal layer at the bottom of the through hole F1 and the through hole F2.

[0155] In the preparation process 20 of the wafer 10 provided in the embodiment of the present application, a patterned metal layer 2 is formed by dividing the metal layer. Due to the division, the stress of the patterned metal layer 2 is released. Therefore, the patterned metal layer 2 can not only meet the grounding requirements of the semiconductor device obtained by dividing the wafer 10, improve the heat dissipation characteristics of the semiconductor device, but also greatly reduce the warping of the wafer 10.

[0156] In one possible implementation, Fig.19 As shown, in the above step S203, the substrate 1, the through hole F1 and the through hole F2 are metallized to form a metal layer, which may include the following steps:

[0157] Step S203a: forming an adhesive layer 21 on the upper surface of the substrate 1 and the sidewalls and bottom of each of the through holes F1 and F2. That is, the adhesive layer 21 may cover the upper surface of the substrate 1 and the sidewalls and bottom of each of the through holes F1 and F2.

[0158] Step S203b: forming a seed layer 22 and an electroplating layer 23 on the surface of the adhesion layer 21 in sequence, such as Fig.18 That is, the seed layer 22 may cover the adhesion layer 21, and the electroplating layer 23 may cover the seed layer 22. It can be seen that the adhesion layer 21 is closer to the lower surface than the seed layer 22 and the electroplating layer 23.

[0159] Optionally, the thickness of the patterned metal layer 2 may be in the micrometer range. More specifically, the thickness of the patterned metal layer 2 may be 2um to 16um. That is, the thickness of the portion of the patterned metal layer 2 located on the upper surface of the substrate, the portion located on the sidewall and bottom of the through hole F1, and the portion located on the sidewall and bottom of the through hole F2 may all be 2um to 16um. In the present application, the thickness of the portion located on the sidewall and bottom of the through hole F1 and the portion located on the sidewall and bottom of the through hole F2 may be less than or equal to the thickness of the portion located on the upper surface of the substrate 1.

[0160] In one example, the adhesion layer 21 may be made of metal materials or alloy materials such as titanium Ti, titanium nitride TiN, tantalum Ta, and tantalum nitride TaN. Of course, the adhesion layer 21 may also be made of other metal materials or alloy materials, which are not limited in the present embodiment.

[0161] In another example, the seed layer 22 can be made of metal materials such as copper Cu (Cuprum), gold Au (Aurum), tungsten W (Tungsten), nickel Ni (Nickel), tin Sn (Stannum), etc., and can also be alloy materials such as titanium tungsten TiW (Titanium Tungsten) and titanium gold TiAu (Titanium Aurum). Of course, the seed layer 22 can also be made of other metal materials or alloy materials, which is not limited in the embodiment of the present application. The thickness of the seed layer 22 can be 10nm~1um. Of course, the seed layer 22 can also be of other thicknesses, which is not limited in the present application.

[0162] In another example, the electroplating layer 23 may be made of metal materials such as copper Cu, gold Au, tin Sn, silver Ag (Argentum), etc. Of course, the electroplating layer 23 may also be made of other metal materials, which is not limited in the embodiment of the present application. The thickness of the electroplating layer 23 may be 2um to 16um. Of course, the electroplating layer 23 may also be of other thicknesses, which is not limited in the embodiment of the present application.

[0163] Optionally, the aspect ratio of the through hole F1 and the through hole F2 can be 1:5 to 10:1. Of course, the larger the aspect ratio, the deeper the through hole F1 and the through hole F2. The thickness of the electroplating layer 23 can be determined according to the aspect ratio of the through hole F1 and the through hole F2.

[0164] In another possible implementation, in the above step S204, the metal layer is segmented to form a patterned metal layer 2. Specifically, a pulsed laser may be used to segment the metal layer to form a patterned metal layer 2. Figure 1 Of course, the metal layer may also be segmented by other methods such as mechanical methods, which is not limited in the present embodiment of the application.

[0165] Furthermore, the wavelength of the pulsed laser may be 200 nm to 400 nm, the frequency of the pulsed laser may be greater than or equal to 500 Hz, and the power of the pulsed laser may be 2 W to 6 W. Of course, the wavelength, frequency and power of the pulsed laser may also be in other ranges, which are not limited in the embodiments of the present application.

[0166] refer to Figure 2The patterned metal layer 2 may have a plurality of segmentation units. Two adjacent segmentation units among the plurality of segmentation units may be segmented by a groove H. It is conceivable that when two adjacent segmentation units are segmented by a groove, it can be understood that a plurality of grooves are continuously arranged to form a groove.

[0167] Of course, two adjacent segmentation units in the plurality of segmentation units may also be segmented by a plurality of grooves H, such as Figure 3 It is conceivable that when two adjacent segmentation units are segmented by a plurality of grooves, it can be understood that the plurality of grooves are arranged at intervals and are non-continuous.

[0168] For example, each of the plurality of segmentation units may be a polygon such as a square or a rectangle. The size of each segmentation unit may be less than or equal to 15 mm.

[0169] The present application embodiment is described by taking the segmentation unit as a rectangle as an example. Figure 4 As shown, the segmentation unit is rectangular, and the width W of the segmentation unit may be less than or equal to 15 mm. It is conceivable that the length L of the segmentation unit is also less than or equal to 15 mm.

[0170] Optionally, continue to refer to Figure 4 , the width HW of the groove H may be 5um to 100um. Of course, the groove H may also be of other widths, which is not limited in the embodiment of the present application.

[0171] The position of the bottom of the groove H that divides the segmentation unit may satisfy any of the following conditions: the bottom of the groove H may be located inside the electroplating layer 23, the bottom of the groove H may be located at the interface between the electroplating 23 layer and the seed layer 22, the bottom of the groove H may be located inside the seed layer 22, the bottom of the groove H may be located at the interface between the seed layer 22 and the adhesion layer 21, the bottom of the groove H may be located inside the adhesion layer 21, the bottom of the groove H may be located at the interface between the adhesion layer 21 and the substrate 1, and the bottom of the groove H may be located inside the substrate 1. The embodiment of the present application takes the bottom of the groove H located at the interface between the adhesion layer 21 and the substrate 1 as an example.

[0172] Exemplarily, the depth of the groove H may be greater than or equal to 60% of the thickness of the patterned metal layer 2 and less than or equal to 30% of the thickness of the substrate 1. Since the thickness of the electroplating layer 23 may be greater than the thickness of the seed layer 22 and the thickness of the adhesion layer 21, when the depth of the groove H is equal to 60% of the thickness of the patterned metal layer 2, it can be considered that the bottom of the groove H may be located inside the electroplating layer 23. When the depth of the groove H is equal to 30% of the thickness of the substrate 1, it can be considered that the bottom of the groove H may be located inside the substrate 1.

[0173] In some embodiments, the preparation process 20 may further include: forming an epitaxial layer 6 on the lower surface of the substrate 1, and forming a second electrode 41, a second electrode 42, a third electrode 51 and a third electrode 52 on the surface of the epitaxial layer 6, such as Fig.15 As shown. It is conceivable that the epitaxial layer 6 may include a channel layer ( Fig.15 (not shown), the first electrode 31, the first electrode 32, the second electrode 41, the second electrode 42, the third electrode 51 and the third electrode 52 may all be in contact with the channel layer.

[0174] Optionally, the first electrode 31 and the first electrode 32 can both serve as the source of the semiconductor device divided from the wafer 10 , the second electrode 41 and the second electrode 42 can both serve as the gate of the semiconductor device, and the third electrode 51 and the third electrode 52 can both serve as the drain of the semiconductor device.

[0175] The present application also provides a method for preparing the wafer 10. Fig. 20 The preparation process 30 may include the following steps:

[0176] Step S301: forming a first electrode 31, a first electrode 32, a second electrode 41, a second electrode 42, a third electrode 51 and a third electrode 52 on the surface of the epitaxial layer 6, such as Fig.15 Since the substrate 1 and the epitaxial layer 6 are stacked, it can be said that the first electrode 31 , the first electrode 32 , the second electrode 41 , the second electrode 42 , the third electrode 51 and the third electrode 52 are formed on the surface of the substrate 1 .

[0177] Step S302: Apply bonding glue, high temperature paraffin or other bonding material 40 to the surface of the epitaxial layer 6, and bond the front side to the carrier 50, such as Fig.21 shown.

[0178] Step S303: Photolithography and etching are performed on the upper surface of the substrate 1 to form through holes F1 and through holes F2. Fig. 22 shown.

[0179] Step S304: forming an adhesion layer 21, a seed layer 22 and an electroplating layer 23 on the upper surface of the substrate 1 and the sidewalls and bottoms of the through holes F1 and F2, as shown in FIG. Fig.23 The electroplating layer 23 can be formed by electroplating process.

[0180] Step S305: segmenting the adhesion layer 21, the seed layer 22 and the electroplating layer 23 to form a patterned metal layer 2, such as Fig.24 shown.

[0181] Step S306: Use an organic cleaning solution to remove the bonding material 40, and debond the substrate 1 and the carrier 50 to obtain Figure 1 Wafer 10 is shown.

[0182] It should be understood that in the preparation process 20 and the preparation process 30 provided in the embodiments of the present application, the size of the serial number of each step does not mean the order of execution, and the order of execution of each step will not constitute any limitation on the implementation process of the embodiments of the present application.

[0183] Fig.25 A schematic diagram of the wafer 10 after the wafer 10 and the carrier 50 are debonded is shown before the adhesion layer 21 , the seed layer 22 and the electroplating layer 23 are separated (ie after the adhesion layer 21 , the seed layer 22 and the electroplating layer 23 are formed). Fig.26 FIG. 2 shows a schematic diagram of the wafer 10 after the patterned metal layer 2 is formed and the wafer 10 and the carrier 50 are debonded. Fig.25 and Fig.26 It can be found that Fig.25 The warpage of wafer 10 is obvious. Fig.26 The wafer 10 in the embodiment has basically no warpage and is relatively flat. It can be seen that the preparation method provided in the embodiment of the present application forms a patterned metal layer 2 by segmenting the adhesion layer 21, the seed layer 22 and the electroplating layer 23, releases the stress of the metal layer, and greatly reduces the warpage of the wafer 10.

[0184] In addition, although the chemical mechanical polishing (CMP) process (which can be referred to as the CMP process) can thin the metal layer and thus reduce the warpage of the wafer 10, the CMP process requires the use of a metal polishing liquid, which is incompatible with the silicon dioxide polishing liquid used in the wafer thinning and polishing process in the related art, and will increase the preparation cost of the wafer 10. Moreover, a thinner metal layer will increase the parasitic resistance of the semiconductor device divided from the wafer 10, thereby resulting in poor electrical conductivity and thermal conductivity of the semiconductor device. Therefore, compared with the CMP process, the preparation method provided in the embodiment of the present application can reduce the preparation cost of the wafer 10 and can ensure that the semiconductor device has good electrical conductivity and thermal conductivity.

[0185] The embodiment of the present application further provides a power amplifier, comprising a passive device and a semiconductor device. The passive device can be connected to the semiconductor device.

[0186] Optionally, the passive device may be a capacitor, a resistor, etc., which is not limited in the embodiment of the present application.

[0187] The present application embodiment also provides a communication system 100, such as Fig. 27 As shown, the communication system 100 may include a radio frequency integrated circuit 101 and a power amplifier 102. The power amplifier 102 may be connected to the radio frequency integrated circuit 101.

[0188] Optionally, refer to Fig.25 , the communication system 100 may further include an antenna 103. The input end of the power amplifier 102 may be connected to the RF integrated circuit 101, and the output end of the power amplifier 102 may be connected to the antenna 103. Thus, the first RF signal RF11 output by the RF integrated circuit 101 is amplified by the power amplifier 102 to obtain an amplified first RF signal RF12. The antenna 103 transmits the amplified first RF signal RF12.

[0189] Furthermore, the communication system 100 may also include a filter 104 and a low noise amplifier 105. The input end of the filter 104 may be connected to the antenna 103, the output end of the filter 104 may be connected to the input end of the low noise amplifier 105, and the output end of the low noise amplifier 105 may be connected to the RF integrated circuit 101. Thus, the second RF signal RF21 received by the antenna 103 is filtered by the filter 104 to obtain a filtered second RF signal RF22. The low noise amplifier 105 amplifies the filtered second RF signal RF22 and transmits the amplified second RF signal RF23 to the RF integrated circuit 101.

[0190] The present application also provides an electronic device 1000, such as Fig.28 The electronic device 1000 may include a power supply 200 and a communication system 100. The power supply 200 may be connected to the communication system 100 to supply power to the communication system 100.

[0191] Optionally, the electronic device 1000 may be a mobile phone, a watch, smart glasses, a Bluetooth headset, a router, etc., which is not limited in this application.

[0192] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A wafer, characterized in that: comprising a substrate, a patterned metal layer and a plurality of first electrodes; The substrate is provided with a plurality of through holes, the plurality of first electrodes are all located on the first surface of the substrate and are located one by one at the bottom of the plurality of through holes; the patterned metal layer is arranged on the second surface of the substrate and the side wall and the bottom of each through hole in the plurality of through holes, and the edge of the portion of the patterned metal layer located on the second surface is flush with the edge of the substrate; wherein the first surface and the second surface are arranged opposite to each other.

2. The wafer according to claim 1, characterized in that The patterned metal layer includes an adhesion layer, a seed layer and an electroplating layer which are stacked; wherein the adhesion layer is closer to the second surface than the seed layer and the electroplating layer.

3. The wafer according to claim 2, characterized in that The patterned metal layer has a plurality of segmentation units, and two adjacent segmentation units in the plurality of segmentation units are segmented by a groove.

4. The wafer according to claim 3, characterized in that A size of each of the plurality of segmentation units is less than or equal to 15 mm.

5. The wafer according to claim 3 or 4, characterized in that: The width of the groove is 5um to 100um.

6. The wafer according to any one of claims 3 to 5, characterized in that The position of the bottom of the groove satisfies any of the following: The bottom of the groove is located inside the electroplating layer; The bottom of the groove is located at the interface between the electroplating layer and the seed layer; The bottom of the groove is located inside the seed layer; The bottom of the groove is located at the interface between the seed layer and the adhesion layer; The bottom of the groove is located inside the adhesive layer; The bottom of the groove is located at the interface between the adhesion layer and the substrate; The bottom of the groove is located inside the substrate.

7. The wafer according to any one of claims 3 to 6, characterized in that The depth of the groove is greater than or equal to 60% of the thickness of the patterned metal layer and less than or equal to 30% of the thickness of the substrate.

8. The wafer according to any one of claims 1 to 7, characterized in that The thickness of the patterned metal layer is in the micrometer range.

9. The wafer according to any one of claims 1 to 8, characterized in that The through hole has a depth-to-width ratio of 1:5 to 10:

1.

10. A method for preparing a wafer, characterized in that: include: forming a plurality of first electrodes on a first surface of the substrate; Performing photolithography and etching on the second surface of the substrate to form a plurality of through holes; wherein the second surface and the first surface are arranged opposite to each other; Metallizing the substrate and each of the plurality of through holes to form a metal layer; The metal layer is segmented to form a patterned metal layer; wherein an edge of a portion of the patterned metal layer located on the second surface is flush with an edge of the substrate.

11. The preparation method according to claim 10, characterized in that: The step of metallizing the substrate and each of the plurality of through holes to form a metal layer comprises: forming an adhesion layer on the second surface and the sidewalls and bottom of each through hole; A seed layer and an electroplating layer are sequentially formed on the surface of the adhesion layer.

12. The preparation method according to claim 10 or 11, characterized in that: The step of dividing the metal layer to form a patterned metal layer includes: The metal layer is segmented by using a pulse laser to form the patterned metal layer.

13. The preparation method according to claim 12, characterized in that: The wavelength of the pulse laser is 200nm-400nm, the frequency of the pulse laser is greater than or equal to 500Hz, and the power of the pulse laser is 2W-6W.

14. The preparation method according to any one of claims 10 to 13, characterized in that: The patterned metal layer has a plurality of segmentation units, and two adjacent segmentation units in the plurality of segmentation units are segmented by a groove.

15. The preparation method according to claim 14, characterized in that: A size of each of the plurality of segmentation units is less than or equal to 15 mm.

16. The preparation method according to claim 14 or 15, characterized in that: The width of the groove is 5um to 100um.

17. The preparation method according to any one of claims 14 to 16, characterized in that: The position of the bottom of the groove satisfies any of the following: The bottom of the groove is located inside the electroplating layer; The bottom of the groove is located at the interface between the electroplating layer and the seed layer; The bottom of the groove is located inside the seed layer; The bottom of the groove is located at the interface between the seed layer and the adhesion layer; The bottom of the groove is located inside the adhesive layer; The bottom of the groove is located at the interface between the adhesion layer and the substrate; The bottom of the groove is located inside the substrate.

18. The preparation method according to any one of claims 14 to 17, characterized in that: The depth of the groove is greater than or equal to 60% of the thickness of the patterned metal layer and less than or equal to 30% of the thickness of the substrate.

19. The preparation method according to any one of claims 10 to 18, characterized in that: The thickness of the patterned metal layer is in the micrometer range.

20. The preparation method according to any one of claims 10 to 19, characterized in that: The through hole has a depth-to-width ratio of 1:5 to 10:1.

Images