Semiconductor package and method for manufacturing the same

Abstract

A semiconductor package according to an embodiment may include: a redistribution layer structure; the first semiconductor stacking structure is located on the upper surface of the redistribution layer structure, and the first semiconductor stacking structure comprises a first chiplet and a second chiplet arranged on the first chiplet; and the second semiconductor stack structure is located on the upper surface of the redistribution layer structure and is parallel to the first semiconductor stack structure. The bridging pipe core is electrically connected between the first semiconductor stacking structure and the second semiconductor stacking structure, and the bridging pipe core is arranged above the first semiconductor stacking structure and the second semiconductor stacking structure; and a surface mount device (SMD) disposed on an upper surface of at least one of the first semiconductor stack structure and the second semiconductor stack structure.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0091016 filed in the Korean Intellectual Property Office on July 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor package and a method for manufacturing the semiconductor package. Background Art

[0003] The semiconductor industry seeks to increase integration density so that more passive or active devices can be integrated in a given area. The development of miniaturization technology for circuit line width of front-end semiconductor processes has gradually faced limitations, which has led to a slowdown in innovation related to circuit line width. The semiconductor industry has supplemented the limitations of front-end semiconductor processes by developing semiconductor packaging technologies capable of high integration density without corresponding progress in the miniaturization of circuit line width. In line with this trend, 3.5D packaging technology has been developed, in which the bottom surface of the high bandwidth memory (HBM) and the bottom surface of the chiplet stacking structure are connected to a bridge die, a substrate is disposed under the bridge die, and a surface mount device (SMD) is disposed on the bottom surface of the substrate.

[0004] 3.5D packaging technology brings about an increase in integration density, but the semiconductor industry seeks higher integration density. Therefore, it is of great significance to develop a new semiconductor packaging technology to solve the problems of conventional semiconductor packaging technology. Summary of the invention

[0005] In the 3.5D packaging technology in which the bridge core and substrate are arranged between the high bandwidth memory (HBM) and chiplet stacking structure located at the upper part and the surface mount device (SMD) located at the lower part, there is a long electrical path between the high bandwidth memory (HBM) and chiplet stacking structure located at the upper part and the surface mount device (SMD) located at the lower part. When the vertical thickness of the 3.5D package becomes thicker, the long electrical path makes it difficult to achieve high-performance semiconductor packaging. In addition, since the surface mount device (SMD) is arranged below the substrate, the number of connecting members arranged below the substrate is reduced, thereby increasing the horizontal size of the 3.5D package.

[0006] The present disclosure provides a semiconductor package and a method for manufacturing the semiconductor package, wherein, in a 3.5D package, an upper surface of a high bandwidth memory (HBM) and an upper surface of a chiplet stacking structure are connected to a bridge core, a surface mounted device (SMD) is arranged on at least one of the upper surface of the high bandwidth memory (HBM) and the upper surface of the chiplet stacking structure, and a redistribution layer structure is arranged on a bottom surface of the high bandwidth memory (HBM) and a bottom surface of the chiplet stacking structure.

[0007] A semiconductor package may include: a redistribution layer structure; a first semiconductor stacking structure located on an upper surface of the redistribution layer structure, wherein the first semiconductor stacking structure may include a first chiplet and a second chiplet located on the first chiplet; a second semiconductor stacking structure located on the redistribution layer structure and side by side with the first semiconductor stacking structure; a bridge core forming an electrical connection between the first semiconductor stacking structure and the second semiconductor stacking structure, the bridge core being arranged above the first semiconductor stacking structure and the second semiconductor stacking structure; and a surface mounted device (SMD) located on an upper surface of at least one of the first semiconductor stacking structure and the second semiconductor stacking structure.

[0008] A semiconductor package may include: a redistribution layer structure; a first semiconductor stacking structure located on the redistribution layer structure, wherein the first semiconductor stacking structure may include: a first chiplet; a first molding material molding the side surface of the first chiplet; a second chiplet located on the first chiplet and the first molding material, so that the first chiplet is arranged between the redistribution layer structure and the second chiplet; and a first interconnection layer between the first chiplet and the second chiplet; a second semiconductor stacking structure arranged on the redistribution layer structure and side by side with the first semiconductor stacking structure; a bridge core configured to electrically connect the first semiconductor stacking structure and the second semiconductor stacking structure, the bridge core being arranged above the first semiconductor stacking structure and the second semiconductor stacking structure; a surface mount device (SMD) arranged above at least one of the first semiconductor stacking structure and the second semiconductor stacking structure; and a second molding material covering the first semiconductor stacking structure, the second semiconductor stacking structure, the bridge core and the surface mount device on the redistribution layer structure.

[0009] A method for manufacturing a semiconductor package may include: installing a first semiconductor stacking structure on a redistribution layer structure, wherein the first semiconductor stacking structure may include a first chiplet and a second chiplet located on the first chiplet; installing the second semiconductor stacking structure side by side with the first semiconductor stacking structure on the redistribution layer structure; installing a bridge core on the first semiconductor stacking structure and the second semiconductor stacking structure, wherein the bridge core is located above the first semiconductor stacking structure and the second semiconductor stacking structure and electrically connects the first semiconductor stacking structure and the second semiconductor stacking structure; and installing a surface mount device (SMD) on at least one of the first semiconductor stacking structure and the second semiconductor stacking structure.

[0010] A surface mount device (SMD) conventionally disposed under a substrate may be disposed on an upper surface of the high bandwidth memory (HBM) and an upper surface of the chiplet stacking structure. Thus, the length of the electrical path between the high bandwidth memory (HBM), the chiplet stacking structure, and the surface mount device (SMD) may be reduced.

[0011] A bridge die conventionally disposed between the upper surface of the substrate and the bottom surface of the high bandwidth memory (HBM) and the chiplet stack structure and buried in the silicon interposer may be disposed on the upper surface of the high bandwidth memory (HBM) and the upper surface of the chiplet stack structure. Thus, the silicon interposer may not be used, and the length of the electrical path between the high bandwidth memory (HBM) and the external connection members of the semiconductor package and between the chiplet stack structure and the external connection members of the semiconductor package may be reduced.

[0012] By using a redistribution layer structure instead of a conventional substrate, the redistribution layer structure can be connected to the fine pitch I / O of the chiplet stacking structure and the high bandwidth memory (HBM).

[0013] In addition, surface mount devices (SMDs) conventionally arranged along external connection members under the substrate can be arranged on the upper surface of the high bandwidth memory (HBM) and the upper surface of the chiplet stacking structure. Therefore, the number of external connection members that must be reduced to ensure an area where surface mount devices (SMDs) are provided can be reduced, and the size of the 3.5D package can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0015] Figure 2 is a top view showing an upper surface of a semiconductor package according to an embodiment.

[0016] Figure 3 is a top view showing an upper surface of a semiconductor package according to an embodiment.

[0017] Figure 4 is a cross-sectional view showing a semiconductor package according to another embodiment.

[0018] Figures 5 to 10 is a cross-sectional view illustrating a method for manufacturing a first semiconductor stacked structure according to an embodiment.

[0019] Figures 11 to 17 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The inventive concept may be implemented in various forms and is not limited to the embodiments described herein.

[0021] The drawings and descriptions are to be considered illustrative in nature, rather than restrictive. Throughout the specification, similar reference numerals represent similar elements. The same reference numerals may be used to indicate multiple similar elements, and unless otherwise specified, the reference numerals do not identify any individual element in the multiple similar elements. As used herein, the singular forms "one", "a" and "said" are intended to also include plural forms, unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items, and may be abbreviated as " / ". Ordinals such as "first", "second", "third", etc. may simply be used as labels for certain elements, steps, etc., to distinguish these elements, steps, etc. from each other, and unless otherwise specified, do not represent order. Terms described in the specification that are not described using "first", "second", etc. may still be referred to as "first" or "second" in the claims. In addition, terms referenced by specific ordinals (e.g., "first" in a specific claim) may be described elsewhere with different ordinals (e.g., "second" in the specification or another claim).

[0022] Furthermore, in the drawings, the size and thickness of each element are arbitrarily shown for convenience of description, and the inventive concept is not necessarily limited to the size and / or thickness according to the embodiments shown in the drawings.

[0023] Throughout this specification and the claims that follow, when an element is referred to as being "coupled or connected" to another element, the elements may be "directly coupled or connected" (wherein there are no intervening elements at the contact points between the elements) or "indirectly coupled or connected" (wherein other elements may be used to couple or connect the elements so that there are no contact points between the elements). When no indication is given as to whether an element is directly or indirectly coupled or connected, both direct and indirect coupling or connection are possible. In addition, unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of the elements set forth but not the exclusion of any other elements.

[0024] It should be understood that when an element such as a layer, film, region, zone or substrate is referred to as being "on" another element, it can be directly on the other element (e.g., contacting the other element), or there can be an intermediate element. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element at the contact point between the elements. In addition, in this specification, the term "above" is broadly interpreted as a higher vertical position relative to the base of the structure, and does not necessarily mean being located on the upper side of the object part based on the direction of gravity. Additionally, when two elements overlap horizontally, an element can be described as being "directly located" "above" another element.

[0025] Furthermore, throughout this specification, the phrase “in a plan view” or “on a plane” means observing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0026] Hereinafter, a semiconductor package 100 and a method for manufacturing the semiconductor package 100 will be described with reference to the accompanying drawings.

[0027] Figure 1 is a cross-sectional view showing a semiconductor package 100 according to an embodiment.

[0028] Reference Figure 1 The bridge die 190 and the surface mount device (SMD) 195 may be disposed on the upper surface of the first semiconductor stack structure 160 and the upper surface of the second semiconductor stack structure 170. The bridge die 190 and the surface mount device may be electrically connected to the first semiconductor stack structure 160 and / or the second semiconductor stack structure 170 by hybrid bonding.

[0029] The semiconductor package 100 may include an external connection structure 110, a redistribution layer structure 120, a first semiconductor stack structure 160, a second semiconductor stack structure 170, a bridge die 190, a surface mount device (SMD) 195, and a molding material 162. Since the molding material 162 may surround the second semiconductor stack structure 170, the molding material 162 may be referred to as a second molding material 162. In an embodiment, the semiconductor package 100 may include a 3.5D semiconductor package. In an embodiment, the semiconductor package 100 may include a fan-out wafer level package (FOWLP) or a fan-out panel level package (FOPLP).

[0030] The external connection structure 110 may be disposed on the bottom surface of the redistribution layer structure 120. The external connection structure 110 may include a conductive pad 111, an insulating layer 112, and an external connection member 113. The conductive pad 111 may electrically connect the first redistribution via 122 of the redistribution layer structure 120 to the corresponding external connection member 113. The insulating layer 112 may include a plurality of openings for soldering. The insulating layer 112 may prevent the external connection member 113 from short-circuiting with other external connection members 113 (e.g., electrically insulating the external connection members from each other). The external connection member 113 may electrically connect the semiconductor package 100 to an external device.

[0031] The redistribution layer structure 120 may include a dielectric layer 121, and the first redistribution via 122, the first redistribution line 123, and the second redistribution via 124 may be included in the dielectric layer 121. In another embodiment, the redistribution layer structure 120 may include Figure 1 Different numbers of redistribution lines and redistribution vias are shown, but are included within the scope of the present inventive concept.

[0032] Each first redistribution through hole 122 may be disposed between a corresponding first redistribution line 123 and a corresponding conductive pad 111. The first redistribution through hole 122 may electrically connect the first redistribution line 123 to an external connection member 113 in a vertical direction, and the external connection member 113 is connected to the conductive pad 111. The first redistribution line 123 may be disposed between the first redistribution through hole 122 and the second redistribution through hole 124. The first redistribution line 123 may electrically connect the first redistribution through hole 122 and the second redistribution through hole 124 in a horizontal direction. Each second redistribution through hole 124 may be disposed between a corresponding bonding pad 125 and a corresponding first redistribution line 123. The second redistribution through hole 124 may electrically connect the bonding pad 125 to the first redistribution line 123 in a vertical direction.

[0033] The first bonding pad 125 may be disposed between the second redistribution via 124 and the connection member 135 of the first semiconductor stack structure 160, and the second bonding pad 125 may be disposed between the second redistribution via 124 and the connection member 172 of the second semiconductor stack structure 170. The first bonding pad 125 may electrically connect the connection member 135 of the first semiconductor stack structure 160 to the second redistribution via 124 in a vertical direction, and the second bonding pad may electrically connect the connection member 172 of the second semiconductor stack structure 170 to the second redistribution via 124.

[0034] According to the present disclosure, by using the redistribution layer structure 120 instead of a conventionally used substrate, the redistribution layer structure 120 can be connected to fine pitch I / Os of the first semiconductor stack structure 160 (e.g., chiplet stack structure) and the second semiconductor stack structure 170 (e.g., high bandwidth memory (HBM)).

[0035] The first semiconductor stacking structure 160 may be disposed on the redistribution layer structure 120. The first semiconductor stacking structure 160 may be a chiplet stacking structure formed by stacking chiplets. The first semiconductor stacking structure 160 may include a first chiplet 130, a second chiplet 140 on the first chiplet 130, a first interconnect structure 150 between the first chiplet 130 and the second chiplet 140, and a molding material 161 referred to as a first molding material 161 hereinafter. A chiplet is a functional semiconductor block manufactured by distinguishing components of a high-performance processor according to function. A chiplet that does not require the use of the latest process can be manufactured by applying an inexpensive old process, and a chiplet that requires the use of the latest process can be manufactured by applying the latest process. In this way, chiplets can be manufactured separately according to function, and a single high-performance processor can be manufactured by connecting the manufactured chiplets. Each chiplet cannot operate as a unit chip, and a high-performance processor manufactured by connecting these chiplets can overcome the performance limitations of conventional single-chip processors.

[0036] The first chiplet 130 may include a first active area 131, a first chiplet substrate 132, a lower connection pad 133, a first through silicon via (TSV) 134, and a connecting member 135. In an embodiment, the first chiplet 130 may include a central processing unit (CPU) and / or a graphics processing unit (GPU). The first chiplet 130 may be electrically connected to the second chiplet 140 at an upper portion of the first chiplet 130 through a first interconnect structure 150. The lower connection pad 133 may be electrically connected to the bonding pad 125 through a connecting member 135. The redistribution layer structure 120 may be disposed below the first chiplet 130. The side surface of the first chiplet 130 may be surrounded by a first molding material 161.

[0037] The first active region 131 may be located on a front side of the first chiplet 130, which may be an upper side of the first chiplet. The first active region 131 may be located at the uppermost layer in the first chiplet 130. The first active region 131 may be located on a surface facing the second chiplet 140. The first active region 131 may be disposed between the first through silicon via 134 and the lower bonding pad 151 of the first interconnect structure 150. The first active region 131 may be directly electrically connected to the lower bonding pad 151 of the first interconnect structure 150. In an embodiment, the first active region 131 may include a logic circuit.

[0038] As used herein, components described as being "electrically connected" are configured so that electrical signals can be transmitted from one component to another (although such electrical signals may be attenuated in strength as they are transmitted and may be selectively transmitted). In addition, components that are "directly electrically connected" share a common electrical node through electrical connection of one or more conductors (e.g., wires, pads, internal wires, vias, etc.). Thus, components that are directly electrically connected do not include components that are electrically connected through active elements (such as transistors or diodes).

[0039] The first chiplet substrate 132 may be located in a back side of the first chiplet 130 facing away from the first active region 131. A lower connection pad 133 and a first through silicon via 134 may be disposed in the first chiplet substrate 132. The first chiplet substrate 132 may include a silicon material. The lower connection pad 133 may be disposed between the first through silicon via 134 and the connecting member 135. The lower connection pad 133 may electrically connect the first through silicon via 134 to the connecting member 135.

[0040] The first through silicon via 134 may be disposed between the first active region 131 and the lower connection pad 133. The first through silicon via 134 may electrically connect the first active region 131 to the lower connection pad 133. One end of the first through silicon via 134 may contact the first active region 131, and the other end of the first through silicon via 134 may contact the lower connection pad 133. The first through silicon via 134 may extend downward (e.g., toward the redistribution layer 120) in a direction from the first active region 131 of the first chiplet 130 to the back side of the first chiplet 130. Since the first through silicon via 134 is disposed within the first chiplet 130, and the first chiplet 130 and the second chiplet 140 may be arranged so that their active regions face each other and are interconnected by the first interconnect structure 150, the speed of signals and power transmitted and responded between the first chiplet 130 and the second chiplet 140 may be increased due to the relatively short electrical path through the first interconnect structure 150.

[0041] The connection member 135 may be disposed between the lower connection pad 133 and the second redistribution via 124 of the redistribution layer structure 120. The connection member 135 may electrically connect the lower connection pad 133 to the second redistribution via 124 of the redistribution layer structure 120. In an embodiment, the connection member 135 may be a micro bump or a solder ball.

[0042] In an embodiment, the lower connection pad 133 may be formed of and / or include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof. In an embodiment, the first through silicon via 134 may be formed of and / or include at least one of tungsten, aluminum, copper, and alloys thereof. In an embodiment, the connection member 135 may be formed of and / or include at least one of tin, silver, lead, nickel, copper, or alloys thereof.

[0043] The second chiplet 140 may include a second active area 141, a second chiplet substrate 142, a second through silicon via 143, and an upper connection pad 144. In an embodiment, the second chiplet 140 may include a static random access memory (SRAM). The second chiplet 140 may be electrically connected to the first chiplet 130 in the lower portion through the first interconnect structure 150. The second interconnect structure 180A may be disposed in the upper portion of the second chiplet 140. The second chiplet 140 may be electrically connected to at least one of the bridge die 190 and the surface mount device (SMD) 195 through the second interconnect structure 180A. The side surface of the second chiplet 140 may be surrounded by the second molding material 162. The footprint of the first chiplet 130 may be included in the footprint of the second chiplet 140 (e.g., the first chiplet 130 may be directly below the second chiplet 140 and not extend laterally beyond the projected side of the second chiplet 140).

[0044] The second active region 141 may be located on the front side of the second chiplet 140. The second active region 141 may be located at the lowermost layer in the second chiplet 140. The second active region 141 may be disposed between the second through silicon via 143 and the upper bonding pad 152 of the first interconnect structure 150. The second active region 141 may electrically connect the second through silicon via 143 to the upper bonding pad 152 of the first interconnect structure 150. In an embodiment, the second active region 141 may include a logic circuit.

[0045] The second chiplet substrate 142 may be located at the back side of the second chiplet 140 opposite to the second active area 141. The upper connection pad 144 and the second through silicon via 143 may be disposed in the second chiplet substrate 142. The second chiplet substrate 142 may be formed of and / or include a silicon material. The upper connection pad 144 may be disposed between the second through silicon via 143 and the lower bonding pad 181 of the second interconnect structure 180A. The upper connection pad 144 may electrically connect the lower bonding pad 181 of the second interconnect structure 180A to the second through silicon via 143.

[0046] The second through silicon via 143 may be disposed between the second active region 141 and the upper connection pad 144. The second through silicon via 143 may extend from the second active region 141 to the back side of the second chiplet 140 in an upward direction. The second through silicon via 143 may electrically connect the upper connection pad 144 to the second active region 141. One end of the second through silicon via 143 may contact the second active region 141, and the other end of the second through silicon via 143 may contact the upper connection pad 144. In this way, since the second through silicon via 143 is disposed within the second chiplet 140, connected to the first chiplet 130 through the first interconnect structure 150, and connected to the bridge die 190 or a surface mount device (SMD) through the second interconnect structure 180A, the speed of transmitting and responding signals and power between the first chiplet 130 and the second chiplet 140 and between the second chiplet 140 and the second semiconductor stack structure 170 may be increased due to a relatively short electrical path.

[0047] In an embodiment, the second through silicon via 143 may be formed of and / or include at least one of tungsten, aluminum, copper, and alloys thereof. In an embodiment, the upper connection pad 144 may be formed of and / or include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0048] The first interconnect structure 150 may be disposed between the first chiplet 130 and the second chiplet 140 and between the first molding material 161 and the second chiplet 140. The first interconnect structure 150 may include a lower bonding pad 151, an upper bonding pad 152, a lower silicon insulating layer 153, and an upper silicon insulating layer 154. The lower bonding pad 151 and the upper bonding pad 152 may electrically connect the second chiplet 140 to the first chiplet 130.

[0049] In the semiconductor package 100 according to the present disclosure, the first chiplet 130 and the second chiplet 140 can be bonded by hybrid bonding using the first interconnect structure 150. Hybrid bonding bonds two devices by fusing the same materials of the two devices using the bonding properties of the same materials. Here, hybrid refers to performing two different types of bonding, for example, bonding two devices with a first type of metal-metal bonding and a second type of non-metal-non-metal bonding. Hybrid bonding can form I / Os with fine pitches.

[0050] The lower bonding pad 151 formed on the first chiplet 130 can be directly bonded to the upper bonding pad 152 formed under the second chiplet 140 by metal-metal hybrid bonding, and the lower silicon insulation layer 153 formed on the first chiplet 130 can be directly bonded to the upper silicon insulation layer 154 formed under the second chiplet 140 by non-metal-non-metal hybrid bonding.

[0051] The second semiconductor stacked structure 170 may be disposed on the redistribution layer structure 120. The second semiconductor stacked structure 170 may be a high bandwidth memory (HBM). High bandwidth memory (HBM) is a high performance three-dimensional (3D) stacked dynamic random access memory (DRAM). High bandwidth memory (HBM) is manufactured by performing hybrid bonding or vertically stacking memory dies using microbumps to form a single memory stack. A high bandwidth memory (HBM) having multiple memory channels by a memory stack vertically stacked by memory dies can simultaneously achieve shorter latency and higher bandwidth than conventional DRAM products, and can reduce the total area occupied by a single DRAM on a substrate, and therefore, has advantages in high bandwidth compared to area, and has the advantage of reduced power consumption.

[0052] The second semiconductor stack structure 170 may include a buffer die (not shown) and a plurality of memory dies (not shown) stacked on the buffer die. The second semiconductor stack structure 170 may include an upper connection pad 171 and a connection member 172. The upper connection pad 171 may be disposed below the lower bonding pad 181 of the second interconnect structure 180A. The connection member 172 may be disposed on the bonding pad 125 of the redistribution layer structure 120. In an embodiment, the upper connection pad 171 may be formed of and / or include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof. The connection member 172 may electrically connect the second semiconductor stack structure 170 to the bonding pad 125 of the redistribution layer structure 120. In an embodiment, the connection member 172 may include a microbump or a solder ball.

[0053] The bridge die 190 may be disposed above the first semiconductor stacked structure 160 and the second semiconductor stacked structure 170. The bridge die 190 may be disposed on a portion of an upper surface of the first semiconductor stacked structure 160 and a portion of an upper surface of the second semiconductor stacked structure 170. The bridge die 190 may be electrically connected to the first semiconductor stacked structure 160 and the second semiconductor stacked structure 170 through the second interconnect structure 180A. The first semiconductor stacked structure 160 and the second semiconductor stacked structure 170 may exchange signals and power through the bridge die 190.

[0054] The bridge die 190 may include a lower connection pad 191, a connection line 192, and a bridge die substrate 193. In an embodiment, the bridge die 190 may include a silicon bridge. The lower connection pad 191 may be disposed between the upper bonding pad 182 and the connection line 192. The lower connection pad 191 may electrically connect the connection line 192 to the upper bonding pad 182. The connection line 192 may be disposed between the lower connection pads 191 and electrically connect the corresponding lower connection pads 191 to each other. The corresponding lower connection pads 191 may be a plurality of groups of lower connection pads 191 spaced laterally from each other. The lower connection pads 191 may be formed of and / or include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof. The connection line 192 may be formed of and / or include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, and alloys thereof.

[0055] According to the present disclosure, a bridge core is arranged on the upper surface of a first semiconductor stack structure 160 (e.g., a chiplet stack structure) and the upper surface of a second semiconductor stack structure 170 (e.g., a high bandwidth memory (HBM)), without the need to use a silicon interposer; and the length of the electrical path between the first semiconductor stack structure 160 and the external connection member 113 of the semiconductor package 100 and between the external connection member 113 and the second semiconductor stack structure 170 of the semiconductor package 100 can be reduced relative to conventional semiconductor packages.

[0056] A surface mount device (SMD) 195 may be disposed on at least one of the first semiconductor stack structure 160 and the second semiconductor stack structure 170. The surface mount device (SMD) 195 may be electrically connected to the first semiconductor stack structure 160 or the second semiconductor stack structure 170 through the second interconnect structure 180A. The surface mount device (SMD) 195 may provide additional functions or programming in the entire semiconductor package 100. The surface mount device (SMD) 195 may include at least one of a resistor, an inductor, a capacitor, and a jumper. The surface mount device (SMD) 195 may be electrically connected to the first semiconductor stack structure 160 or the second semiconductor stack structure 170 through the second interconnect structure 180A.

[0057] According to the present disclosure, a surface mount device (SMD) that may be conventionally disposed below a substrate may be disposed on an upper surface of a first semiconductor stack structure 160 (e.g., a chiplet stack structure), or on an upper surface of a second semiconductor stack structure 170 (e.g., a high bandwidth memory (HBM)). In addition, a surface mount device (SMD) that may be conventionally disposed below a substrate side by side with an external connection member may be disposed on an upper surface of a first semiconductor stack structure 160 (e.g., a chiplet stack structure) and an upper surface of a second semiconductor stack structure 170 (e.g., a high bandwidth memory (HBM)). Positioning a surface mount device (SMD) on an upper surface of a first semiconductor stack structure 160 or a second semiconductor stack structure 170 may increase the available space below for external connection relative to conventional placement of the surface mount device (SMD) below a substrate, wherein the number of external connection members may be reduced to ensure an area where a surface mount device (SMD) is disposed. Therefore, the size of a 3.5D semiconductor package may be reduced relative to a conventional semiconductor package including a surface mount device (SMD) below.

[0058] The second interconnect structure 180A may be disposed between the first semiconductor stack structure 160 and the bridge die 190, between the first semiconductor stack structure 160 and the surface mount device (SMD) 195, between the second semiconductor stack structure 170 and the bridge die 190, and between the second semiconductor stack structure 170 and the surface mount device (SMD) 195. The second interconnect structure 180A may include a lower bonding pad 181, an upper bonding pad 182, a lower silicon insulating layer 183, and an upper silicon insulating layer 184. The lower bonding pad 181 and the upper bonding pad 182 may electrically connect the bridge die 190 or the surface mount device (SMD) 195 to the first semiconductor stack structure 160 or the second semiconductor stack structure 170.

[0059] In the semiconductor package 100 according to the present disclosure, the bridge die 190 or the surface mount device (SMD) 195 may be bonded on the first semiconductor stack structure 160 or the second semiconductor stack structure 170 through hybrid bonding using the first interconnect structure 180A.

[0060] The lower bonding pad 181 formed on the second semiconductor stack structure 170 or the first semiconductor stack structure 160 can be directly bonded to the upper bonding pad 182 formed under the bridge core 190 or the surface mount device (SMD) 195 through metal-metal hybrid bonding, and the lower silicon insulation layer 183 formed on the first semiconductor stack structure 160 or the second semiconductor stack structure 170 can be directly bonded to the upper silicon insulation layer 184 formed under the bridge core 190 or the surface mount device (SMD) 195 through non-metal-non-metal hybrid bonding.

[0061] The second molding material 162 may be disposed on the redistribution layer structure 120 , and may surround the first semiconductor stack structure 160 , the second semiconductor stack structure 170 , the bridge die 190 , and the surface mount device (SMD) 195 .

[0062] Figure 2 is a top view showing an upper surface of a semiconductor package 100 according to an embodiment.

[0063] Reference Figure 2 , when the semiconductor package 100 excluding the second molding material 162 is viewed in a plan view, the first semiconductor stacked structure 160 may be disposed at a center portion, and the second semiconductor stacked structure 170 may be disposed around the first semiconductor stacked structure 160. Each of the bridge dies 190 may electrically connect the first semiconductor stacked structure 160 to each of the second semiconductor stacked structures 170. A surface mount device (SMD) 195 may be disposed on each of the first semiconductor stacked structure 160 and the second semiconductor stacked structure 170.

[0064] Figure 3 is a top view showing an upper surface of a semiconductor package 100 according to an embodiment.

[0065] Reference Figure 3 , when the semiconductor package 100 excluding the second molding material 162 is viewed in a plan view, the first semiconductor stacked structure 160 may be disposed at a center portion, and the second semiconductor stacked structure 170 may be disposed around the first semiconductor stacked structure 160. Each of the bridge dies 190 may electrically connect the first semiconductor stacked structure 160 to a plurality of second semiconductor stacked structures among the second semiconductor stacked structures 170. A surface mount device (SMD) 195 may be disposed on each of the first semiconductor stacked structure 160 and the second semiconductor stacked structure 170.

[0066] Figure 4 is a cross-sectional view showing a semiconductor package 100 according to another embodiment.

[0067] exist Figure 1 In the embodiment, the first semiconductor stack structure 160 and the bridge die 190, the first semiconductor stack structure 160 and the surface mount device (SMD) 195, the second semiconductor stack structure 170 and the bridge die 190, and the second semiconductor stack structure 170 and the surface mount device (SMD) 195 are connected by hybrid bonding, but in contrast, Figure 4In the embodiment, the first semiconductor stack structure 160 and the bridge die 190, the first semiconductor stack structure 160 and the surface mount device (SMD) 195, the second semiconductor stack structure 170 and the bridge die 190, and the second semiconductor stack structure 170 and the surface mount device (SMD) 195 can be connected by flip chip bonding.

[0068] Reference Figure 4 The second interconnect structure 180B can be arranged between the first semiconductor stack structure 160 and the bridge core 190, between the first semiconductor stack structure 160 and the surface mount device (SMD) 195, between the second semiconductor stack structure 170 and the bridge core 190, and between the second semiconductor stack structure 170 and the surface mount device (SMD) 195.

[0069] The connecting member 188 and the bonding pad 189 may be disposed on the bottom surface of the bridge die 190 as a second interconnect structure 180B. The connecting member 188 may be disposed between the bonding pad 189 and the upper connecting pad 144 of the second chiplet 140, and between the bonding pad 187 and the upper connecting pad 171 of the second semiconductor stack structure 170. The connecting member 188 may electrically connect the bonding pad 189 to the upper connecting pad 144 of the second chiplet 140, and electrically connect the bonding pad 189 to the upper connecting pad 171 of the second semiconductor stack structure 170. The bonding pad 189 may be disposed between the connecting member 188 and the lower connecting pad 191 of the bridge die 190. The bonding pad 189 may electrically connect the lower connecting pad 191 of the bridge die 190 to the connecting member 188.

[0070] In an embodiment, the connection member 188 may include a microbump or a solder ball. In an embodiment, the connection member 188 may be formed of and / or include at least one of tin, silver, lead, nickel, copper, or an alloy thereof. In an embodiment, the bonding pad 189 may be formed of and / or include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and an alloy thereof.

[0071] The connection member 186 and the bonding pad 187 may be disposed on the bottom surface of the surface mount device (SMD) 195 as the second interconnect structure 180B. The connection member 186 may be disposed between the bonding pad 187 and the upper connection pad 144 of the second chiplet 140, or between the bonding pad 187 and the upper connection pad 171 of the second semiconductor stack structure 170. The connection member 186 electrically connects the bonding pad 187 to the upper connection pad 144 of the second chiplet 140, and electrically connects the bonding pad 187 to the upper connection pad 171 of the second semiconductor stack structure 170. The bonding pad 187 may be disposed on the connection member 186. The bonding pad 187 may be electrically connected to the connection member 186.

[0072] In an embodiment, the connection member 186 may include a microbump or a solder ball. In an embodiment, the connection member 186 may be formed of and / or include at least one of tin, silver, lead, nickel, copper, or an alloy thereof. In an embodiment, the bonding pad 187 may be formed of and / or include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and an alloy thereof.

[0073] exist Figure 4 In the embodiment, the configuration of the second interconnect structure 180B other than the connection member 186 and the bonding pad 187 is similar to that of Figure 1 The configuration is the same as described in . Therefore, Figure 1 The content described in can also be applied to Figure 4 Components of the second interconnect structure 180B except the connecting members 186 and the bonding pads 187.

[0074] Figures 5 to 10 is a cross-sectional view illustrating a method for manufacturing the first semiconductor stacked structure 160 according to the embodiment.

[0075] Figure 5 is a cross-sectional view showing the step of attaching the second chiplet 140 on the first carrier 200 .

[0076] Reference Figure 5, the second chiplet 140 can be attached to the first carrier 200. First, a first carrier 200 can be provided. The first carrier 200 can be formed of and / or include, for example, a silicon-based material (such as glass or silicon oxide), an organic material or another material (such as aluminum oxide), any combination of these materials, etc. Then, the second chiplet 140 can be attached to the first carrier 200. In an embodiment, the second chiplet 140 can be attached to the first carrier 200 using a laser bonding process. In the second chiplet 140, an upper silicon insulation layer 154 and an upper bonding pad 152 for performing hybrid bonding can be formed on the second active area 141.

[0077] Figure 6 is a cross-sectional view showing the step of bonding the first chiplet 130 to the second chiplet 140 .

[0078] Reference Figure 6 , the first chiplet 130 may be bonded to the second chiplet 140 by hybrid bonding. In the first chiplet 130 , a lower silicon insulation layer 153 and a lower bonding pad 151 for performing hybrid bonding may be formed on the first active region 131 .

[0079] The lower bonding pad 151 on the first chiplet 130 and the upper bonding pad 152 on the second chiplet 140 can be directly bonded by metal-metal hybrid bonding. A metal bond is formed at the interface between the lower bonding pad 151 and the upper bonding pad 152 by metal-metal hybrid bonding. In an embodiment, the lower bonding pad 151 and the upper bonding pad 152 can be formed of and / or include copper. In another embodiment, the lower bonding pad 151 and the upper bonding pad 152 can be a metal material suitable for hybrid bonding.

[0080] The lower bonding pad 151 and the upper bonding pad 152 may be made of the same material, and the interface between the lower bonding pad 151 and the upper bonding pad 152 may disappear after hybrid bonding. The first chiplet 130 may be electrically connected to the second chiplet 140 through the lower bonding pad 151 and the upper bonding pad 152 .

[0081] The lower silicon insulating layer 153 and the upper silicon insulating layer 154 may be directly bonded by non-metal-non-metal hybrid bonding. A covalent bond is formed at the interface between the lower silicon insulating layer 153 and the upper silicon insulating layer 154 by the non-metal-non-metal hybrid bonding.

[0082] In an embodiment, the lower silicon insulating layer 153 and the upper silicon insulating layer 154 may be formed of and / or include silicon oxide or TEOS oxide. In an embodiment, the lower silicon insulating layer 153 and the upper silicon insulating layer 154 may be formed of SiO 2 Forming and / or including SiO 2In an embodiment, the lower silicon insulating layer 153 and the upper silicon insulating layer 154 may be silicon nitride, silicon oxynitride, or other suitable dielectric materials. In an embodiment, the lower silicon insulating layer 153 and the upper silicon insulating layer 154 may include SiN or SiCN.

[0083] The lower silicon insulation layer 153 and the upper silicon insulation layer 154 may be made of the same material, and after hybrid bonding, an interface between the lower silicon insulation layer 153 and the upper silicon insulation layer 154 may disappear.

[0084] Figure 7 is a cross-sectional view showing a step of molding the first chiplet 130 with a first molding material 161 on the second chiplet 140 .

[0085] Reference Figure 7 , the first chiplet 130 may be molded on the second chiplet 140 using a first molding material 161. In an embodiment, the molding process using the first molding material 161 may include a compression molding or transfer molding process. In an embodiment, the first molding material 161 may include an epoxy molding compound (EMC).

[0086] Figure 8 is a cross-sectional view showing a step of planarizing the first molding material 161 .

[0087] Reference Figure 8 , chemical mechanical polishing (CMP) may be performed to flatten the upper surface of the first molding material 161. The upper surface of the first molding material 161 may be flattened by applying a CMP process. After performing the CMP process, the bottom surface of the first chiplet 130 and the lower connection pads 133 may be exposed from the first molding material 161.

[0088] Fig. 9 is a cross-sectional view showing a step of forming a connection member 135 on the lower connection pad 133 of the first chiplet 130 .

[0089] Reference Fig. 9 , a connection member 135 may be formed on the lower connection pad 133 of the first chiplet 130. In an embodiment, the connection member 135 may be formed of and / or include at least one of tin, silver, lead, nickel, copper, or an alloy thereof.

[0090] Fig.10 is a cross-sectional view showing a step of separating the first carrier 200 from the second chiplet 140 .

[0091] Reference Fig.10 , the first carrier 200 can be separated from the second chiplet 140 .

[0092] Figures 11 to 17is a cross-sectional view illustrating a method for manufacturing the semiconductor package 100 according to the embodiment. Fig.11 is a cross-sectional view showing a step of forming a redistribution layer structure 120 on the second carrier 210 .

[0093] Reference Fig.11 , the redistribution layer structure 120 may be formed on the second carrier 210. First, a second carrier 210 may be provided. In an embodiment, the carrier 210 may include, for example, a silicon-based material (such as glass or silicon oxide), an organic material or another material (such as aluminum oxide), any combination of these materials, and the like. Next, a dielectric layer 121 is formed on the second carrier 210. In an embodiment, the dielectric layer 121 may include a photo-imaging dielectric (PID) used in a redistribution process. The photo-imaging dielectric is a material capable of forming a fine pattern by applying a photolithography process. As an embodiment, the photo-imaging dielectric (PID) may include a polyimide-based photoactive polymer, a novolac-based photoactive polymer, a polybenzoxazole, a silicone-based polymer, an acrylate-based polymer, or an epoxy-based polymer. In another embodiment, the dielectric layer 121 is formed of an inorganic dielectric material such as silicon nitride, silicon oxide, and the like. In an embodiment, the dielectric layer 121 may be formed by a CVD, ALD, or PECVD process.

[0094] After forming the dielectric layer 121 , a via hole may be formed by selectively etching the dielectric layer 121 , and the first redistribution via 122 may be formed by filling the via hole with a conductive material.

[0095] Then, a dielectric layer 121 may be additionally deposited on the first redistribution via 122 and the dielectric layer 121 , an opening may be formed by selectively etching the additionally deposited dielectric layer 121 , and a first redistribution line 123 may be formed by filling the opening with a conductive material.

[0096] Then, a dielectric layer 121 may be additionally deposited on the first redistribution line 123 and the dielectric layer 121 , a via hole may be formed by selectively etching the additionally deposited dielectric layer 121 , and a second redistribution via hole 124 may be formed by filling the via hole with a conductive material.

[0097] Then, a photoresist (not shown) may be additionally deposited on the second redistribution via 124 and the dielectric layer 121 , a photoresist pattern including vias may be formed by selectively exposing and developing the photoresist, and a bonding pad 125 may be formed by filling the vias with a conductive material.

[0098] In an embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, and the bonding pad 125 may be formed of and / or include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In an embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, and the bonding pad 125 may be formed by performing a sputtering process. In another embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, and the bonding pad 125 may be formed by performing an electrolytic plating process after forming a seed metal layer.

[0099] Fig.12 is a cross-sectional view illustrating a step of mounting the first semiconductor stack structure 160 on the redistribution layer structure 120 .

[0100] Reference Fig.12 The first semiconductor stack structure 160 may be mounted on the redistribution layer structure 120 by flip chip bonding. The connection members 135 of the first semiconductor stack structure 160 may be bonded to the bonding pads 125 of the redistribution layer structure 120, and thus the first semiconductor stack structure 160 and the redistribution layer structure 120 may be electrically connected.

[0101] Fig.13 is a cross-sectional view illustrating a step of mounting the second semiconductor stack structure 170 on the redistribution layer structure 120 .

[0102] Reference Fig.13 , the second semiconductor stack structure 170 may be mounted on the redistribution layer structure 120 by flip chip bonding. The first semiconductor stack structure 160 and the second semiconductor stack structure 170 may be arranged side by side and horizontally at the same height. The connection member 172 of the second semiconductor stack structure 170 may be bonded to the bonding pad 125 of the redistribution layer structure 120, and thus the first semiconductor stack structure 160 and the redistribution layer structure 120 may be electrically connected.

[0103] Fig.14 It is a cross-sectional view showing the steps of hybrid bonding a bridge core 190 on the upper surface of a first semiconductor stack structure 160 and an upper surface of a second semiconductor stack structure 170, and hybrid bonding a surface mount device (SMD) 195 on at least one of the upper surfaces of the first semiconductor stack structure 160 and the second semiconductor stack structure 170.

[0104] Reference Fig.14, the bridge die 190 may be hybrid-bonded on a portion of the upper surface of the first semiconductor stack structure 160 and a portion of the upper surface of the second semiconductor stack structure 170, and the surface mount device (SMD) 195 may be hybrid-bonded on at least one of the upper surface of the first semiconductor stack structure 160 and the upper surface of the second semiconductor stack structure 170. A lower silicon insulating layer 183 and a lower bonding pad 181 for performing hybrid bonding may be formed on the upper surface of the first semiconductor stack structure 160 and the upper surface of the second semiconductor stack structure 170, and an upper silicon insulating layer 184 and an upper bonding pad 182 for performing hybrid bonding may be formed on the bottom surface of the bridge die 190 and the bottom surface of the surface mount device (SMD) 195.

[0105] The lower bonding pad 181 and the upper bonding pad 182 may be directly bonded by metal-metal hybrid bonding. Through metal-metal hybrid bonding, a metal bond is formed at the interface between the lower bonding pad 181 and the upper bonding pad 182. In an embodiment, the lower bonding pad 181 and the upper bonding pad 182 may be formed of and / or include copper. In another embodiment, the lower bonding pad 181 and the upper bonding pad 182 may be a metal material suitable for hybrid bonding.

[0106] The lower bonding pad 181 and the upper bonding pad 182 may be made of the same material, and after hybrid bonding, the interface between the lower bonding pad 181 and the upper bonding pad 182 may disappear. Through the lower bonding pad 181 and the upper bonding pad 182, the first semiconductor stack structure 160 or the second semiconductor stack structure 170 may be electrically connected to the bridge die 190 or the surface mount device (SMD) 195.

[0107] The lower silicon insulating layer 183 and the upper silicon insulating layer 184 may be directly bonded by non-metal-non-metal hybrid bonding. A covalent bond is formed at the interface between the lower silicon insulating layer 183 and the upper silicon insulating layer 184 by the non-metal-non-metal hybrid bonding.

[0108] In an embodiment, the lower silicon insulating layer 183 and the upper silicon insulating layer 184 may be formed of and / or include silicon oxide or TEOS oxide. In an embodiment, the lower silicon insulating layer 183 and the upper silicon insulating layer 184 may include SiO 2 In an embodiment, the lower silicon insulating layer 183 and the upper silicon insulating layer 184 may be silicon nitride, silicon oxynitride, or other suitable dielectric materials. In an embodiment, the lower silicon insulating layer 183 and the upper silicon insulating layer 184 may include SiN or SiCN.

[0109] The lower silicon insulation layer 183 and the upper silicon insulation layer 184 may be made of the same material, and after hybrid bonding, an interface between the lower silicon insulation layer 183 and the upper silicon insulation layer 184 may disappear.

[0110] Fig.15 It is the successor Fig.13 A cross-sectional view is then shown of the steps of flip-chip bonding the bridge core 190 on the upper surface of the first semiconductor stack structure 160 and the upper surface of the second semiconductor stack structure 170, and flip-chip bonding the surface mount device (SMD) 195 on at least one of the upper surfaces of the first semiconductor stack structure 160 and the second semiconductor stack structure 170. Fig.15 is shown for manufacturing Figure 4 A cross-sectional view of a method for semiconductor packaging 100 according to another embodiment. Fig.16 and Fig.17 As shown, used to manufacture Figure 1 The method of the semiconductor package 100 according to the embodiment may be applied to a device for manufacturing Figure 4 A method of semiconductor packaging 100 according to another embodiment.

[0111] exist Fig.14 In the embodiment, the first semiconductor stack structure 160 and the bridge die 190, the first semiconductor stack structure 160 and the surface mount device (SMD) 195, the second semiconductor stack structure 170 and the bridge die 190, and the second semiconductor stack structure 170 and the surface mount device (SMD) 195 are connected by hybrid bonding, but in contrast, Fig.15 In the embodiment, the first semiconductor stack structure 160 and the bridge die 190, the first semiconductor stack structure 160 and the surface mount device (SMD) 195, the second semiconductor stack structure 170 and the bridge die 190, and the second semiconductor stack structure 170 and the surface mount device (SMD) 195 can be connected by flip chip bonding. The flip chip bonding can be performed by performing a reflow process.

[0112] Fig.16 is a cross-sectional view illustrating a step of molding the first semiconductor stack structure 160 , the second semiconductor stack structure 170 , the bridge die 190 , and the surface mount device (SMD) 195 on the redistribution layer structure 120 using a second molding material 162 .

[0113] Reference Fig.16 On the redistribution layer structure 120, the first semiconductor stack structure 160, the second semiconductor stack structure 170, the bridge die 190, and the surface mount device (SMD) 195 may be molded by the second molding material 162. In an embodiment, the molding process using the second molding material 162 may include a compression mode or a transfer molding process. In an embodiment, the second molding material 162 may include an epoxy molding compound (EMC).

[0114] Fig.17 is a cross-sectional view illustrating a step of separating the second carrier 210 from the redistribution layer structure 120 .

[0115] Reference Fig.17 , the second carrier 210 may be separated from the redistribution layer structure 120 .

[0116] Afterwards, if Figure 1 As shown, an external connection structure 110 may be formed on the bottom surface of the redistribution layer structure 120. An insulating layer 112 may be formed on the bottom surface of the dielectric layer 121 of the redistribution layer structure 120, and a conductive pad 111 may be formed under the first redistribution via 122. In an embodiment, the conductive pad 111 may be formed of and / or include at least one of copper, nickel, zinc, gold, silver, platinum, palladium, chromium, titanium, and alloys thereof. In an embodiment, the insulating layer 112 may be formed of and / or include a solder resist. In an embodiment, the external connection member 113 may be formed of and / or include at least one of tin, silver, lead, nickel, copper, or alloys thereof. In an embodiment, the conductive pad 111 may be formed by performing a sputtering process or an electrolytic plating process after forming a seed metal layer. In an embodiment, the insulating layer 112 may be formed by a CVD, ALD, or PECVD process.

[0117] While the invention has been described in connection with what are presently considered to be practical embodiments, it should be understood that the invention is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Redistribution layer structure; A first semiconductor stack structure located on an upper surface of the redistribution layer structure, wherein the first semiconductor stack structure includes a first chiplet and a second chiplet disposed on the first chiplet; The second semiconductor stacked structure is located on the upper surface of the redistribution layer structure and is arranged side by side with the first semiconductor stacked structure. a bridge die that forms an electrical connection between the first semiconductor stack structure and the second semiconductor stack structure, the bridge die being disposed above the first semiconductor stack structure and the second semiconductor stack structure; and A surface mount device (SMD) is located on an upper surface of at least one of the first semiconductor stack structure and the second semiconductor stack structure.

2. The semiconductor package according to claim 1, wherein The first semiconductor stack structure and the second semiconductor stack structure exchange signals through the bridge die.

3. The semiconductor package according to claim 1, wherein: The first chiplet includes a first active area at a surface facing the second chiplet.

4. The semiconductor package according to claim 3, wherein: The first chiplet includes a plurality of first through silicon vias extending in a downward direction from the first active area to a backside of the first chiplet.

5. The semiconductor package according to claim 1, wherein The second chiplet includes a second active area at a surface facing the first chiplet.

6. The semiconductor package according to claim 5, wherein: The second chiplet includes a plurality of second through silicon vias extending in an upward direction from the second active area to a back side of the second chiplet.

7. The semiconductor package according to claim 6, wherein: Each of the plurality of second through silicon vias is electrically connected to one of the bridge die or the surface mount device.

8. The semiconductor package according to claim 1, wherein The first chiplet has a first footprint and the second chiplet has a second footprint, and the first footprint is within the second footprint.

9. A semiconductor package, comprising: Redistribution layer structure; A first semiconductor stacking structure is located on the redistribution layer structure, wherein the first semiconductor stacking structure comprises: The first small chip, a first molding material, molding a side surface of the first chiplet, a second chiplet located on the first chiplet and the first molding material such that the first chiplet is disposed between the redistribution layer structure and the second chiplet, and a first interconnect structure between the first chiplet and the second chiplet; a second semiconductor stacking structure, disposed on the redistribution layer structure and arranged side by side with the first semiconductor stacking structure; A bridge die configured to electrically connect the first semiconductor stack structure and the second semiconductor stack structure, the bridge die being disposed above the first semiconductor stack structure and the second semiconductor stack structure; a surface mount device SMD disposed above at least one of the first semiconductor stack structure and the second semiconductor stack structure; and A second molding material covers the first semiconductor stack structure, the second semiconductor stack structure, the bridge die, and the surface mount device on the redistribution layer structure.

10. The semiconductor package according to claim 9, wherein The first chiplet includes a central processing unit CPU or a graphics processing unit GPU.

11. The semiconductor package according to claim 9, wherein: The second chiplet includes SRAM.

12. The semiconductor package according to claim 9, wherein: The second semiconductor stacked structure includes a high bandwidth memory HBM.

13. The semiconductor package according to claim 9, wherein: The surface mount device includes a capacitor structure. 14 . The semiconductor package of claim 9 , further comprising a second interconnect structure between the first semiconductor stack structure, the second semiconductor stack structure, and the bridge die.

15. The semiconductor package according to claim 14, wherein: The second interconnect structure includes microbumps.

16. The semiconductor package according to claim 14, wherein: The second interconnect structure comprises: a first silicon-in-sulator layer and a plurality of first bonding pads located on an upper surface of the second chiplet and an upper surface of the second semiconductor stack structure; and A second silicon-in-sulator layer and a plurality of second bonding pads are located on the bottom surface of the bridge die.

17. The semiconductor package according to claim 16, wherein: Each first bonding pad of the plurality of first bonding pads is directly bonded to each second bonding pad of the plurality of second bonding pads.

18. The semiconductor package according to claim 16, wherein: The first silicon insulating layer is directly bonded to the second silicon insulating layer.

19. A method for manufacturing a semiconductor package, the method comprising: Mounting a first semiconductor stack structure on the redistribution layer structure, wherein the first semiconductor stack structure includes a first chiplet and a second chiplet located on the first chiplet; Mounting a second semiconductor stack structure on the redistribution layer structure side by side with the first semiconductor stack structure; Mounting a bridge die on the first semiconductor stack structure and the second semiconductor stack structure, wherein the bridge die is located above the first semiconductor stack structure and the second semiconductor stack structure and electrically connects the first semiconductor stack structure and the second semiconductor stack structure; and A surface mount device (SMD) is mounted on at least one of the first semiconductor stack structure and the second semiconductor stack structure.

20. The method of claim 19, wherein: The bridge die is mounted on the first semiconductor stack structure and the second semiconductor stack structure by hybrid bonding.

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