Power semiconductor packaging structure

Abstract

The present invention provides a power semiconductor packaging structure, comprising: a substrate having a first conductive layer and a second conductive layer arranged at intervals; a power module located on the first conductive layer, and the drain of the power module is electrically connected to the first conductive layer; an interconnection structure located on a side of the power module away from the substrate, and the power module and the substrate are electrically connected through the interconnection structure; a source connector located on the second conductive layer and electrically connected to the Kelvin source of the power module. Through the present application, the problem of large switching loss caused by inductance mismatch of power devices in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor packaging structure. Background Art

[0002] The power semiconductor module packages several power devices into a whole, providing electrical connections, heat conduction, mechanical support, protection of sensitive equipment from moisture, vibration, pollution, and electrical insulation for the power devices. The power package of silicon devices is usually designed to accommodate a large device for each switch position. Most of the existing SiC power module packages are converted from Si device packages, so the power package of silicon devices provides the same idea for the packaging of SiC power modules. However, due to wafer quality and yield issues, large monolithic components are not available for commercial wide bandgap devices. Therefore, although SiC chips of the same size have higher power density than Si chips, in order to achieve high currents of hundreds of amperes, many SiC devices must be placed in parallel. There is a fundamental problem with the parallel connection of multiple devices in traditional Si device packages, that is, the design of these devices does not effectively solve problems such as current sharing.

[0003] On this basis, due to the extremely high switching speed of wide bandgap devices, which is usually hundreds of times faster than silicon devices, the inductance mismatch between devices may cause uneven stress and current overshoot problems in each switching cycle of the power device, resulting in severe switching oscillation and large switching losses. Summary of the invention

[0004] The main purpose of the present invention is to provide a power semiconductor packaging structure to solve the problem of large switching loss caused by inductance mismatch of power devices in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, there is provided a power semiconductor packaging structure, comprising: a substrate having a first conductive layer and a second conductive layer spaced apart; a power module located on the first conductive layer, and a drain of the power module is electrically connected to the first conductive layer; an interconnection structure located on a side of the power module away from the substrate, and the power module and the substrate are electrically connected via the interconnection structure; and a source connector located on the second conductive layer and electrically connected to the Kelvin source of the power module.

[0006] Optionally, the power semiconductor packaging structure also includes: a gate bus bar, located on the substrate and spaced apart from the first conductive layer and the second conductive layer; a gate resistor, one end of the gate resistor is electrically connected to the gate bus bar, and the other end of the gate resistor is electrically connected to the gate of the power module.

[0007] Optionally, the power semiconductor packaging structure further includes: a third conductive layer located on the substrate and spaced apart from the first conductive layer, the second conductive layer and the gate bus bar; a gate connector located on the third conductive layer and electrically connected to the gate bus bar.

[0008] Optionally, the power semiconductor packaging structure further includes: a fourth conductive layer located on the substrate and spaced apart from the first conductive layer and the second conductive layer; an auxiliary electrode located on the fourth conductive layer and electrically connected to the first conductive layer through the fourth conductive layer.

[0009] Optionally, the power semiconductor packaging structure further includes: a fifth conductive layer, located on the substrate and spaced apart from the first conductive layer and the second conductive layer; and a signal component, located on the fifth conductive layer.

[0010] Optionally, the power semiconductor packaging structure further includes: a bottom plate, which is located on a side of the substrate away from the power module, and the side of the bottom plate away from the substrate has pin-shaped fins.

[0011] Optionally, the power semiconductor package structure further includes: a Kelvin source bus bar located on the substrate, and the source connector is electrically connected to the Kelvin source through the Kelvin source bus bar.

[0012] Optionally, the first conductive layer includes a first sub-conductive layer and a second sub-conductive layer arranged at intervals, the power module includes a plurality of first power devices and a plurality of second power devices, and the source connector includes a first source connector and a second source connector; the plurality of first power devices are connected in parallel, and the drain of each first power device is electrically connected to the first sub-conductive layer, and the Kelvin source of each first power device is electrically connected to the first source connector; the plurality of second power devices are connected in parallel, and the drain of each second power device is electrically connected to the second sub-conductive layer, and the Kelvin source of each second power device is electrically connected to the second source connector.

[0013] Optionally, the interconnection structure includes a plurality of first copper bridge structures and a plurality of second copper bridge structures; the substrate also includes a sixth conductive layer, any two of the first conductive layer, the second conductive layer and the sixth conductive layer are arranged at intervals, and the sixth conductive layer is located on a side of the first sub-conductive layer away from the second sub-conductive layer; the sixth conductive layer is electrically connected to the plurality of first power devices through the plurality of first copper bridge structures, and the plurality of first power devices correspond one-to-one to the plurality of first copper bridge structures; the first sub-conductive layer is electrically connected to the plurality of second power devices through the plurality of second copper bridge structures, and the plurality of second power devices correspond one-to-one to the plurality of second copper bridge structures.

[0014] Optionally, the substrate includes a first metal layer, an insulating medium layer, and a second metal layer which are stacked, and the first conductive layer and the second conductive layer are located on a side of the first metal layer away from the second metal layer.

[0015] Applying the technical solution of the present invention, the power semiconductor packaging structure includes a substrate, a power module, an interconnection structure and a source connector. Specifically, the substrate has a first conductive layer and a second conductive layer that are spaced apart, the power module is located on the first conductive layer, the interconnection structure is located on the side of the power module away from the substrate, and the source connector is located on the second conductive layer. In the present application, while the power module and the substrate are electrically connected through the interconnection structure and the drain of the power module is electrically connected to the first conductive layer, the Kelvin source of the power module is also electrically connected to the source connector through the second conductive layer, so that the drive network that controls the switching state of the power device can be separated from the power path, eliminating the interference of stray inductance and the slope of the switching current on the drive network, and obtaining a drive signal that is not interfered by the large and rapidly changing current on the power path, thereby solving the problem of large switching loss caused by the inductance mismatch of the power device in the prior art, and achieving the effect of reducing the switching loss of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0017] Figure 1 A cross-sectional schematic diagram of a power semiconductor packaging structure according to an embodiment of the present invention is shown;

[0018] Figure 2 Shows Figure 1 A top view of the power semiconductor package structure shown;

[0019] Figure 3 Shows Figure 1 A side view of the power semiconductor package structure shown;

[0020] Figure 4 Shown in Figure 1 A schematic diagram of pin-shaped fins of a base plate of a power semiconductor package structure shown;

[0021] Figure 5 A cross-sectional schematic diagram of another power semiconductor packaging structure according to an embodiment of the present invention is shown;

[0022] Figure 6 Shows Figure 5 Insulating cover of the structure shown.

[0023] The above drawings include the following reference numerals:

[0024] 10. Substrate; 20. Power module; 30. Interconnection structure; 40. First conductive layer; 401. First sub-conductive layer; 402. Second sub-conductive layer; 50. Second conductive layer; 60. Third conductive layer; 100. First metal layer; 200. Insulating dielectric layer; 300. Second metal layer; 400. Fourth conductive layer; 500. Fifth conductive layer; 600. Sixth conductive layer; 70. Pin-shaped fins; 80. Bottom plate; 90. Terminals. DETAILED DESCRIPTION

[0025] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] As described in the background technology, the existing SiC power module packaging is mostly transformed from Si device packaging. Therefore, the power packaging of silicon devices provides the same idea for the packaging of SiC power modules: that is, when the power packaging of silicon devices is usually designed to accommodate a large device at each switch position, it can also be imagined that the packaging of SiC power modules is designed to accommodate a large device at each switch position. However, due to wafer quality and yield issues, commercial wide bandgap devices cannot obtain large monolithic components, that is, the idea of ​​SiC power module packaging is currently difficult to achieve. On this basis, in order to achieve high currents of hundreds of amperes, many SiC devices must be placed in parallel. There is a fundamental problem in the parallel connection of multiple devices in traditional Si device packaging, that is, the design of these devices does not effectively solve problems such as current sharing. On this basis, because wide bandgap devices have extremely high switching speeds, they are usually hundreds of times faster than silicon devices. Inductance mismatch between devices may cause problems such as uneven stress and current overshoot in each switching cycle of the power device, resulting in severe switching oscillation and large switching losses.

[0029] In addition, it is mentioned here that for traditional packages without Kelvin source leads, in each switching cycle (turn on or off), the stray inductance of the source wiring plus the switching current slope will generate a voltage signal opposite to the driving voltage signal. This voltage signal slows down the switching speed and increases the switching loss of each cycle.

[0030] In order to at least solve the problem of large switching loss of power devices caused by inductance mismatch of power devices in the prior art, an embodiment of the present application provides a power semiconductor packaging structure.

[0031] In some optional embodiments, a power semiconductor packaging structure is provided, combining Figure 1 , Figure 2 and Figure 3 As shown, the power semiconductor packaging structure includes: a substrate 10 having a first conductive layer 40 and a second conductive layer 50 arranged at intervals; a power module 20 located on the first conductive layer 40, and the drain of the power module 20 is electrically connected to the first conductive layer 40; an interconnection structure 30 located on a side of the power module 20 away from the substrate 10, and the power module 20 and the substrate 10 are electrically connected through the interconnection structure 30; a source connector (source Kelvin connector) located on the second conductive layer 50 and electrically connected to the Kelvin source of the power module 20.

[0032] Optionally, in order to make the substrate 10 lighter and have better thermal matching with other components, the substrate 10 may be aluminum silicon carbide (AlSiC).

[0033] Optionally, in order to take into account the functions of conducting on one side of the substrate 10, insulating in the middle layer, and dissipating heat on the other side, the substrate 10 may be a stacked structure. Optionally, the substrate 10 may include a first metal layer 100, an insulating dielectric layer 200, and a second metal layer 300 stacked in sequence, so that the first metal layer 100 can realize the conducting function, the insulating dielectric layer 200 can realize the middle layer insulating function, and the second metal layer 300 can be used to realize the heat dissipation function of the substrate 10.

[0034] It can be understood that, when the substrate 10 is composed of the first metal layer 100 , the insulating dielectric layer 200 and the second metal layer 300 , the first metal layer 100 may include the first conductive layer 40 and the second conductive layer 50 .

[0035] Exemplarily, the material of the first metal layer 100 and the second metal layer 300 may be copper, gold, nickel, silver, aluminum, tin, palladium, alloys, and other conductor materials. It is understandable that the material of the first conductive layer 40 and the second conductive layer 50 may be copper, gold, nickel, silver, aluminum, tin, palladium, alloys, and other conductor materials.

[0036] For example, the insulating dielectric layer 200 may include, but is not limited to, various ceramic materials such as aluminum nitride (AlN), silicon nitride (Si3N4), aluminum oxide (Al2O3), etc. Among them, compared with the substrate 10 whose insulating material layer is silicon nitride (Si3N4) or the substrate 10 whose insulating dielectric layer 200 is aluminum oxide (Al2O3), the substrate 10 whose insulating material layer is aluminum nitride (AlN) can withstand higher current and achieve higher power density.

[0037] Specifically, the power module 20 may be composed of a plurality of power devices located on the first conductive layer 40. The plurality of power devices have a plurality of drain electrodes corresponding to each other, and the plurality of drain electrodes are electrically connected to the first conductive layer 40 respectively.

[0038] Optionally, the connection method between any one of the power devices in the power module 20 and the first conductive layer 40 and the second conductive layer 50 of the substrate 10 may include but is not limited to interconnection processes such as welding and sintering. Exemplarily, the power device in the power module 20 and the first conductive layer 40 and the second conductive layer 50 of the substrate 10 may be connected instantaneously by a method of double-layer printing of variable temperature preheating solder paste, and by continuous pulse current-assisted pressureless sintering of nano-silver solder paste.

[0039] Specifically, combined Figure 2 and Figure 3As shown, the interconnection structure 30 may be a plurality of interconnection structures 30 corresponding to the plurality of power devices in the power module 20, so that the plurality of interconnection structures 30 are correspondingly located on a side of the plurality of power devices away from the substrate 10, so that each power device in the power module 20 is electrically connected to the substrate 10 through a corresponding interconnection structure 30. Exemplarily, the interconnection structure 30 may be a copper bridge structure.

[0040] Specifically, when the multiple power devices of the power module 20 have multiple Kelvin sources corresponding to each other and the multiple Kelvin sources are connected to each other, the multiple Kelvin sources of the multiple power devices can be electrically connected to the same source connector (source Kelvin connector).

[0041] By applying the technical solution of the present invention, the power semiconductor packaging structure includes a substrate 10, a power module 20, an interconnection structure 30 and a source connector (source Kelvin connector). Specifically, the substrate 10 has a first conductive layer 40 and a second conductive layer 50 arranged at intervals, the power module 20 is located on the first conductive layer 40, the interconnection structure 30 is located on a side of the power module 20 away from the substrate 10, and the source connector (source Kelvin connector) is located on the second conductive layer 50. In the present application, while the power module 20 and the substrate 10 are electrically connected through the interconnect structure 30 and the drain of the power module 20 is electrically connected to the first conductive layer 40, the Kelvin source of the power module 20 is also electrically connected to the source connector (source Kelvin connector) through the second conductive layer 50, so that the drive network that controls the switching state of the power device can be separated from the power path, eliminating the interference of stray inductance and the switching current slope on the drive network, and a drive signal that is not interfered by the large and rapidly changing current on the power path can be obtained, thereby solving the problem of large switching loss caused by inductance mismatch of the power device in the prior art and achieving the effect of reducing the switching loss of the power device.

[0042] In some optional embodiments, such as Figure 2 As shown, the power semiconductor package structure may further include a gate bus bar and a gate resistor. Figure 2 and Figure 3 As shown, the above-mentioned gate bus bar and the above-mentioned gate resistor can be respectively located on the substrate 10, and the gate bus bar is spaced apart from the first conductive layer 40 and the second conductive layer 50; one end of the gate resistor can be electrically connected to the gate bus bar, and the other end of the gate resistor can be electrically connected to the gate of the power module 20.

[0043] In the above embodiment, by configuring the gate resistor for the power module 20 , the power module 20 can have a low resistance and help buffer the gate current of the power module 20 , thereby preventing turn-on current oscillation and transferring the power loss of the driver.

[0044] Specifically, combined Figure 1 and Figure 2 As shown, the number of gate resistors can correspond one-to-one to the number of power devices in the power module 20. More specifically, multiple power devices have multiple gates corresponding one-to-one, and multiple gates correspond one-to-one to multiple gate resistors. Moreover, when multiple power devices are connected in parallel, one of the two ends of the multiple gate resistors is electrically connected to the multiple power devices one-to-one, and the other end of the two ends of the multiple gate resistors can be electrically connected to the same gate bus bar. Accordingly, it can be concluded from the above that this specific embodiment configures a separate gate resistor for each power device of the power module 20, thereby buffering the gate current of each individual power device, thereby achieving the effect of suppressing gate oscillation.

[0045] Optionally, the power semiconductor package structure may include a plurality of gate bus bars, so that each gate bus bar may be electrically connected to a plurality of power devices.

[0046] It is mentioned here that: on the one hand, the power device can be an insulated gate device. Since the gate-emitter (or gate-source) of the insulated gate device is a capacitive structure, the parasitic inductance of the gate loop is inevitable. If there is no gate resistor, the gate loop will produce strong oscillations under the excitation of the driver pulse. The series gate resistor can attenuate the oscillating current. Optionally, the above-mentioned insulated gate device can be an IGBT or a MOSFET; on the other hand, capacitors and inductors are both reactive components. If there is no gate resistor, most of the driving power will be consumed in the output tube inside the driver, causing its temperature to rise a lot. The series gate resistor can alleviate the problem of rising temperature of the output tube inside the driver.

[0047] In some optional embodiments, combined with Figure 2 and Figure 3 As shown, the power semiconductor package structure may further include a third conductive layer 60 and a gate connector. The third conductive layer 60 is located on the substrate 10, and the third conductive layer 60 is spaced apart from any two of the first conductive layer 40, the second conductive layer 50, and the gate bus bar; the gate connector may be located on the third conductive layer 60, and the gate connector may also be electrically connected to the gate bus bar.

[0048] In combination with the above, it can be known that when the gate bus bar is electrically connected to the gates of multiple power devices connected in parallel in the power module 20, the above-mentioned gate connector can be electrically connected to the multiple power devices connected in parallel in the power module 20 through the above-mentioned third conductive layer 60 and the above-mentioned gate bus bar, so that the multiple power devices connected in parallel can be operated synchronously through the above-mentioned gate connector, thereby improving the reliability and current balance of the power devices.

[0049] Alternatively, if Figure 2 As shown, the number of gate connectors may correspond to the number of gate bus bars one by one, so that the number of sub-conductive layers included in the third conductive layer 60 may correspond to the number of gate connectors one by one. Exemplarily, in the case where the gate bus bars include the first gate bus bars and the second gate bus bars, the gate connectors may include the first gate connector and the second gate connector, the third conductive layer 60 may include the third sub-conductive layer and the fourth sub-conductive layer, and the first gate connector is located on the third sub-conductive layer, and the second gate connector is located on the fourth sub-conductive layer, so that the first gate connector is electrically connected to the first gate bus bar through the third sub-conductive layer, and the second gate connector is electrically connected to the second gate bus bar through the fourth sub-conductive layer.

[0050] Optionally, combined Figure 1 , Figure 2 and Figure 3 As shown, the substrate 10 of the power semiconductor device may further include a gate conductive layer spaced apart from the first conductive layer 40, the second conductive layer 50, the third conductive layer 60, and the gate bus bar. In this case, one end of the gate resistor may be electrically connected to the gate of the power device through the gate conductive layer, and the other end of the gate resistor may be electrically connected to the gate connector through the gate bus bar and the third conductive layer 60.

[0051] In some optional embodiments, combined with Figure 1 , Figure 2 and Figure 3 As shown, in order to test the electrical performance of the module, the power semiconductor package structure may further include a fourth conductive layer 400 and an auxiliary electrode. The fourth conductive layer 400 may be located on the substrate 10, and the fourth conductive layer 400 is spaced apart from the first conductive layer 40 and the second conductive layer 50; the auxiliary electrode may be located on the fourth conductive layer 400, and the auxiliary electrode is electrically connected to the first conductive layer 40 through the fourth conductive layer 400.

[0052] Optionally, combined Figure 2 and Figure 3 As shown, the fourth conductive layer 400 is also spaced apart from the third conductive layer 60 , the gate bus bar and the gate conductive layer.

[0053] In some optional embodiments, combined with Figure 1 , Figure 2 and Figure 3 As shown, the power semiconductor package structure further includes a fifth conductive layer 500 and a signal component (signal sensor). The fifth conductive layer 500 may be located on the substrate 10, and the fifth conductive layer 500 is spaced apart from the first conductive layer 40 and the second conductive layer 50; the signal component (signal sensor) may be located on the fifth conductive layer 500.

[0054] Optionally, the fifth conductive layer 500 is also spaced apart from the third conductive layer 60 , the fourth conductive layer 400 , the gate bus bar and the gate conductive layer, respectively.

[0055] Specifically, the above-mentioned signal components (signal sensors) may include but are not limited to vibration sensors, temperature and humidity sensors, overcurrent sensors, etc. Thus, according to the above-mentioned signal components (signal sensors), it can be used for temperature measurement or other forms of internal sensing, and sense the diagnostic signal generated from the signal sensor.

[0056] In some optional embodiments, combined with Figure 1 and Figure 2 As shown, the power semiconductor package structure may further include a Kelvin source bus bar (source Kelvin bus bar). The Kelvin source bus bar (source Kelvin bus bar) is located on the substrate 10, and the source connector (source Kelvin connector) is electrically connected to the Kelvin source through the Kelvin source bus bar (source Kelvin bus bar).

[0057] Specifically, when the power module 20 includes a plurality of power devices, a plurality of Kelvin sources corresponding to the plurality of power devices are electrically connected to Kelvin source bus bars (source Kelvin bus bars) respectively.

[0058] Optionally, the Kelvin source bus bar (source Kelvin bus bar) is spaced apart from the first conductive layer 40 , the second conductive layer 50 , the third conductive layer 60 , the fourth conductive layer 400 , the fifth conductive layer 500 , the gate bus bar and the gate conductive layer, respectively.

[0059] Specifically, the number of the above-mentioned Kelvin source bus bars (source Kelvin bus bars) may correspond one-to-one to the number of source connectors (source Kelvin connectors).

[0060] In the above embodiment, by electrically connecting the Kelvin source of each power device individually to the Kelvin source bus bar (source Kelvin bus bar), the switching frequency can be provided, and the total power loss of the transistor can be reduced, the operating temperature can be lowered, and the device can be made more reliable.

[0061] In some optional embodiments, combined with Figure 2 and Figure 3As shown, the first conductive layer 40 includes a first sub-conductive layer 401 and a second sub-conductive layer 402 that are spaced apart, the power module 20 includes a plurality of first power devices (Q1, Q2, Q3, Q4, Q5, and Q6) and a plurality of second power devices (Q7, Q8, Q9, Q10, Q11, and Q12), and the source connector (source Kelvin connector) includes a first source connector and a second source connector; the plurality of first power devices (Q1, Q2, Q3, Q4, Q5, and Q6) are connected in parallel, and the drain of each first power device (Q1, Q2, Q3, Q4, Q5, and Q6) is connected to the first sub-conductive layer. The conductive layer 401 is electrically connected, and the Kelvin source of each first power device (Q1, Q2, Q3, Q4, Q5 or Q6) is electrically connected to the first source connector (source Kelvin connector); multiple second power devices (Q7, Q8, Q9, Q10, Q11 and Q12) are connected in parallel, and the drain of each second power device (Q7, Q8, Q9, Q10, Q11 or Q12) is electrically connected to the second sub-conductive layer 402, and the Kelvin source of each second power device (Q7, Q8, Q9, Q10, Q11 or Q12) is electrically connected to the second source connector (source Kelvin connector).

[0062] In the above embodiment, by connecting a plurality of first power devices (Q1, Q2, Q3, Q4, Q5 and Q6) in parallel, the plurality of first power devices (Q1, Q2, Q3, Q4, Q5 and Q6) can form a switch module, which is recorded as a first switch module; by connecting a plurality of second power devices (Q7, Q8, Q9, Q10, Q11 and Q12) in parallel, the plurality of second power devices (Q7, Q8, Q9, Q10, Q11 or Q12) can form another switch module, which is recorded as a second switch module. Furthermore, since multiple first power devices (Q1, Q2, Q3, Q4, Q5 and Q6) are located on the first sub-conductive layer 401, multiple second power devices (Q7, Q8, Q9, Q10, Q11 and Q12) are located on the second sub-conductive layer 402, and the first sub-conductive layer 401 and the second sub-conductive layer 402 both belong to the first conductive layer 40 of the substrate 10 in the power semiconductor packaging structure, the above-mentioned first switch module and the above-mentioned second switch module can constitute a half-bridge control circuit in the above-mentioned power semiconductor packaging structure.

[0063] Correspondingly, the number of the gate bus bars and the Kelvin source bus bars (source Kelvin bus bars) may correspond one-to-one to the number of the switch modules, respectively.

[0064] Of course, if Figure 2As shown, in some other optional embodiments, the power module 20 of the power semiconductor package structure may include a first power device (Q1, Q2, Q3, Q4, Q5 or Q6) and a second power device (Q7, Q8, Q9, Q10, Q11 or Q12), so that the first switch module may be composed of a first power device (Q1, Q2, Q3, Q4, Q5 or Q6), and the second switch module may be composed of a second power device (Q7, Q8, Q9, Q10, Q11 or Q12); or, the power module 20 of the power semiconductor package structure may include a plurality of first power devices (Q1, Q2, Q3, Q4, Q5 and Q6) and a second power device (Q7, Q8, Q9, Q10, Q11 1 or Q12), so that the first switch module can be composed of multiple first power devices (Q1, Q2, Q3, Q4, Q5 and Q6), and the second switch module can be composed of one second power device (Q7, Q8, Q9, Q10, Q11 or Q12); alternatively, the power module 20 of the above-mentioned power semiconductor packaging structure may include one first power device (Q1, Q2, Q3, Q4, Q5 or Q6) and multiple second power devices (Q7, Q8, Q9, Q10, Q11 and Q12), so that the first switch module can be composed of one first power device (Q1, Q2, Q3, Q4, Q5 or Q6), and the second switch module can be composed of multiple second power devices (Q7, Q8, Q9, Q10, Q11 and Q12).

[0065] In some optional embodiments, combined with Figure 1 , Figure 2 and Figure 3 As shown, the interconnection structure 30 includes a plurality of first copper bridge structures and a plurality of second copper bridge structures; the substrate 10 further includes a sixth conductive layer 600, any two of the first conductive layer 40, the second conductive layer 50 and the sixth conductive layer 600 are arranged at intervals, and the sixth conductive layer 600 is located on a side of the first sub-conductive layer 401 away from the second sub-conductive layer 402; the sixth conductive layer 600 is electrically connected to a plurality of first power devices (Q1, Q2, Q3, Q4, Q5 and Q6) through a plurality of first copper bridge structures, and the plurality of first power devices (Q1, Q2, Q3, Q4, Q5 and Q6) correspond one-to-one to the plurality of first copper bridge structures; the first sub-conductive layer 401 is electrically connected to a plurality of second power devices (Q7, Q8, Q9, Q10, Q11 and Q12) through a plurality of second copper bridge structures, and the plurality of second power devices (Q7, Q8, Q9, Q10, Q11 and Q12) correspond one-to-one to the plurality of second copper bridge structures.

[0066] Optionally, combined Figure 2 and Figure 3As shown, the sixth conductive layer 600 is also spaced apart from the third conductive layer 60 , the fourth conductive layer 400 , the gate bus bar, the gate conductive layer and the fifth conductive layer 500 , respectively.

[0067] Specifically, the above-mentioned multiple first copper bridge structures can correspond one-to-one to multiple first power devices (Q1, Q2, Q3, Q4, Q5 and Q6), and the above-mentioned multiple second copper bridge structures can correspond one-to-one to multiple second power devices (Q7, Q8, Q9, Q10, Q11 and Q12).

[0068] In the above embodiment, since the cross-sectional area of ​​the copper bridge structure (the first copper bridge structure and the second copper bridge structure) is greatly increased compared to the bonding wire, when one end of the copper bridge structure is connected to the power device and the other end is connected to the substrate 10, the reliability of the connection can be improved, and the heat dissipation capacity and current carrying capacity of the power semiconductor packaging structure can also be improved, thereby improving the power density of the power semiconductor packaging structure.

[0069] In some optional embodiments, combined with Figure 1 and Figure 4 As shown, the power semiconductor package structure further includes a bottom plate 80. The bottom plate 80 may be located on a side of the substrate 10 away from the power module 20, and the side of the bottom plate 80 away from the substrate 10 has pin-shaped fins 70.

[0070] Specifically, Figure 1 As shown, the base plate 80 can provide mechanical support for the power semiconductor packaging structure and transfer the heat generated by the power device.

[0071] Alternatively, if Figure 1 As shown, the material of the bottom plate 80 may include but is not limited to copper and aluminum silicon carbide, etc. Moreover, in some other optional embodiments, the surface of the bottom plate 80 may further include a metal coating, such as a nickel layer.

[0072] In the above implementation mode, Figure 1 and Figure 4 As shown, since the base plate 80 of the present application also has pin-shaped fins 70 (pin fin structure), it can be used for direct water cooling, thereby improving the cooling efficiency.

[0073] It is understandable that, combined with Figure 1 , Figure 2 and Figure 3 As shown, the first conductive layer 40 , the second conductive layer 50 , the third conductive layer 60 , the fourth conductive layer 400 , the fifth conductive layer 500 , the sixth conductive layer 600 , the gate bus bar, the gate conductive layer and the Kelvin source bus bar (source Kelvin bus bar) can all be considered as different conductive blocks in the first metal layer 100 .

[0074] It is further explained that, in addition to the copper bridge structure connection, the electrical connection in the embodiment of the present application can also be a wire bonding connection.

[0075] It is further explained that the interconnection methods between the substrate 10 and the bottom plate 80, the copper bridge structure (interconnection structure 30) and the power device, and the different conductive blocks in the first metal layer 100 in the embodiment of the present application may include but are not limited to interconnection processes such as welding and sintering. Exemplarily, the copper bridge structure (interconnection structure 30) and the substrate 10 can be connected by nanosilver sintering, and the sintering connection time is not more than 15 seconds. In one embodiment, the copper bridge structure (interconnection structure 30) and the power device can be directly connected by nanosilver sintering, and the connection steps are as follows: 1) Nanosilver sintering pretreatment of the power surface; 2) Nanosilver sintering pretreatment of the substrate 10 surface; 3) Sintering in the order of the copper bridge structure (interconnection structure 30), the power device and the substrate 10.

[0076] In addition, in some optional embodiments, combined with Figure 1 and Figure 3 As shown, the power semiconductor package structure may further include a terminal 90, which may be an interface between the power module 20 and an external circuit, thereby providing an electric energy path and a test port for the power module 20. Optionally, the terminal 90 may be connected to the first metal layer 100 by welding and power bonding.

[0077] In some other optional embodiments, combined with Figure 1 , Figure 2 and Figure 5 As shown, the embodiment of the present application also provides another power semiconductor packaging structure, including the three substrates 10 mentioned above, namely the first substrate, the second substrate and the third substrate, each substrate forming a half-bridge control circuit, and connected to the metal base plate 80 through connection processes such as welding and sintering, and placed in an insulating shell to form a three-phase full-bridge power module 20; each half-bridge has a separate input / output electrode and a power supply electrode. The insulating shell of this power semiconductor packaging structure is connected by bonding or the like, and the inside of the insulating shell is at least partially filled with insulating potting material; each half-bridge has a separate input / output electrode to provide input or output power; each half-bridge also has a separate power supply electrode (V+, V- electrode) to provide voltage supply. As shown Figure 6 As shown, different electrodes are connected to the substrate 10 through connection processes such as welding and bonding and extend from the insulating upper cover.

[0078] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0079] Applying the technical solution of the present invention, the power semiconductor packaging structure includes a substrate, a power module, an interconnection structure and a source connector. Specifically, the substrate has a first conductive layer and a second conductive layer that are spaced apart, the power module is located on the first conductive layer, the interconnection structure is located on the side of the power module away from the substrate, and the source connector is located on the second conductive layer. In the present application, while the power module and the substrate are electrically connected through the interconnection structure and the drain of the power module is electrically connected to the first conductive layer, the Kelvin source of the power module is also electrically connected to the source connector through the second conductive layer, so that the drive network that controls the switching state of the power device can be separated from the power path, eliminating the interference of stray inductance and the slope of the switching current on the drive network, and obtaining a drive signal that is not interfered by the large and rapidly changing current on the power path, thereby solving the problem of large switching loss caused by the inductance mismatch of the power device in the prior art, and achieving the effect of reducing the switching loss of the power device.

[0080] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A power semiconductor packaging structure, characterized in that: include: A substrate having a first conductive layer and a second conductive layer arranged at intervals, wherein the first conductive layer comprises a first sub-conductive layer and a second sub-conductive layer arranged at intervals; A power module is located on the first conductive layer, and a drain of the power module is electrically connected to the first conductive layer, and the power module includes a plurality of first power devices and a plurality of second power devices; An interconnection structure, located at a side of the power module away from the substrate, the power module and the substrate being electrically connected via the interconnection structure; A source connector, located on the second conductive layer and electrically connected to the Kelvin source of the power module, the source connector comprising a first source connector and a second source connector; A plurality of the first power devices are connected in parallel, and a drain of each of the first power devices is electrically connected to the first sub-conductive layer, and a Kelvin source of each of the first power devices is electrically connected to the first source connector; A plurality of the second power devices are connected in parallel, and a drain of each of the second power devices is electrically connected to the second sub-conductive layer, and a Kelvin source of each of the second power devices is electrically connected to the second source connector.

2. The power semiconductor packaging structure according to claim 1, characterized in that: Also includes: A gate bus bar, located on the substrate and spaced apart from the first conductive layer and the second conductive layer; A gate resistor, one end of which is electrically connected to the gate bus bar, and the other end of which is electrically connected to the gate of the power module.

3. The power semiconductor packaging structure according to claim 2, characterized in that: Also includes: a third conductive layer, located on the substrate and spaced apart from the first conductive layer, the second conductive layer and the gate bus bar; The gate connector is located on the third conductive layer and is electrically connected to the gate bus bar.

4. The power semiconductor packaging structure according to claim 1, characterized in that: Also includes: a fourth conductive layer, located on the substrate and spaced apart from the first conductive layer and the second conductive layer; The auxiliary electrode is located on the fourth conductive layer, and the auxiliary electrode is electrically connected to the first conductive layer through the fourth conductive layer.

5. The power semiconductor packaging structure according to claim 1, characterized in that: Also includes: a fifth conductive layer, located on the substrate and spaced apart from the first conductive layer and the second conductive layer; The signal component is located on the fifth conductive layer.

6. The power semiconductor packaging structure according to claim 1, characterized in that: Also includes: The bottom plate is located at a side of the base plate away from the power module, and the side of the bottom plate away from the base plate has pin-shaped fins.

7. The power semiconductor packaging structure according to any one of claims 1 to 6, characterized in that: Also includes: A Kelvin source bus bar is located on the substrate, and the source connector is electrically connected to the Kelvin source through the Kelvin source bus bar.

8. The power semiconductor packaging structure according to claim 1, characterized in that: The interconnect structure includes a plurality of first copper bridge structures and a plurality of second copper bridge structures; The substrate further includes a sixth conductive layer, any two of the first conductive layer, the second conductive layer and the sixth conductive layer are arranged at intervals, and the sixth conductive layer is located on a side of the first sub-conductive layer away from the second sub-conductive layer; The sixth conductive layer is electrically connected to the plurality of the first power devices through the plurality of the first copper bridge structures, and the plurality of the first power devices correspond to the plurality of the first copper bridge structures one by one; The first sub-conductive layer is electrically connected to the plurality of the second power devices through the plurality of the second copper bridge structures, and the plurality of the second power devices correspond to the plurality of the second copper bridge structures in a one-to-one manner.

9. The power semiconductor packaging structure according to any one of claims 1 to 6, characterized in that: The substrate comprises a first metal layer, an insulating medium layer and a second metal layer which are stacked, and the first conductive layer and the second conductive layer are located on a side of the first metal layer away from the second metal layer.

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