A MIM capacitor test structure and its preparation and testing method

Abstract

The present invention discloses a MIM capacitor test structure and its preparation and testing methods. The MIM capacitor test structure includes a semiconductor substrate, a first dielectric layer, a MIM structure lower metal layer, a second dielectric layer, a first isolation protection layer, a third dielectric layer, a second isolation protection layer, and a passivation layer. A first conductive trench is formed within the first dielectric layer, the MIM structure lower metal layer, and the second dielectric layer. The first conductive trench is provided with a trench sidewall dielectric layer, a first conductive trench barrier layer, and a MIM structure upper metal layer. The passivation layer of the present invention covers the MIM capacitor structure, protecting it from corrosion by environmental factors such as water vapor, and provides an electrode detection position away from the core research area to ensure that mechanical damage to the trench sidewalls is not caused.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing and relates to a MIM capacitor test structure and a preparation and testing method thereof. Background Art

[0002] With the continuous advancement of the integrated circuit industry, the critical dimensions (CDs) of back-end metal interconnects are shrinking. When CDs shrink below tens of nanometers, electric field strength increases while the supply voltage fails to decrease accordingly, placing increasing stress on materials and processes. Simultaneously, with the increasing complexity and integration of IC designs, the length and number of interconnects within the chip continue to increase, further increasing the risk of breakdown and posing increasingly severe challenges to interconnect reliability. Furthermore, the widespread use of three-dimensional structures such as 3D NAND and CFETs in current advanced processes places even higher demands on manufacturing processes. In particular, thin films located on the sidewalls, whether dielectric materials or metal barriers, require precise characterization and optimization. The quality of these films directly impacts device performance and reliability. Therefore, meticulous analysis and optimization are critical steps to ensure the successful implementation of high performance and high density in three-dimensional structures.

[0003] Capacitors, as a key passive component, are increasingly used in integrated circuit design. Traditionally, these capacitors typically employed either a polysilicon-insulator-polysilicon structure or a metal-oxide-silicon substrate structure. However, both structures present challenges, such as parasitic capacitance and the high dissipative resistance caused by non-metallic electrodes. To address these issues, metal-insulator-metal (MIM) capacitors have emerged. By using metal as both electrodes, the MIM structure effectively reduces parasitic capacitance and contact resistance between the electrodes, thereby providing higher conductivity and lossless high capacitance density. Consequently, MIM capacitors are gaining increasing attention and application as a new alternative to traditional integrated circuit capacitors. Research has demonstrated that MIM capacitor structures can be subjected to a range of reliability tests, including those measuring leakage current, dielectric loss, and time-dependent dielectric breakdown (TDDB). These tests help evaluate the performance and stability of MIM capacitors, ensuring their reliable use in integrated circuits.

[0004] Traditional MIM capacitor test structures typically use a flat plate capacitor format, where a layer of dielectric material is sandwiched between upper and lower metal electrodes. The main factors affecting capacitor quality and reliability include pinholes in the dielectric layer, metal spikes on the metal plate, and defects generated during the deposition of the dielectric layer. These problems can lead to capacitance decay caused by electron adsorption during use, or even capacitor breakdown failure. A significant advantage of trench-type metal-insulator-metal (MIM) capacitors over traditional flat plate capacitors is that they significantly increase capacitance density, providing a larger effective electrode surface area within the same chip area, thereby significantly increasing capacitance without increasing the footprint. This is an important technical means to improve the density and performance of integrated circuit components. In addition, when studying the sidewall performance of capacitors, the presence of sharp corners on the sidewalls can lead to electric field concentration, which in turn causes a low breakdown electric field and rapid TDDB degradation, hindering our study of the inherent properties of the dielectric layer.

[0005] When depositing the dielectric layer and metal barrier layer on the sidewall of the trench, the dielectric layer may be damaged due to factors such as process parameters, thereby affecting the reliability of the structural test results. For thin films that need to be grown on the sidewalls of three-dimensional structures such as vertical structures, traditional structures cannot qualitatively and quantitatively characterize their characteristics when deposited on the sidewalls of such three-dimensional structures. In addition, there is another potential problem with traditional capacitor structures: the probes usually directly contact the critical area, and the dielectric layer is not properly encapsulated. For thin films with weak mechanical strength, the pressure applied by the probes may induce mechanical stress, leading to problems such as a decrease in TDDB performance. Therefore, it is urgent to design a specialized MIM capacitor structure to conduct in-depth research on the reliability of the dielectric layer material on the trench sidewalls. Summary of the Invention

[0006] The purpose of the present invention is to address the deficiencies in the prior art and propose a MIM capacitor test structure and its preparation and testing method, which is specifically used to make up for the deficiencies in the sidewall reliability of the existing MIM capacitor structure, and is crucial for a deep understanding of the long-term stability of the device. A film grown on a plane may have different quality and characteristics from a film grown on a sidewall. For a film that needs to be grown on the sidewall of a three-dimensional structure such as a vertical structure, the structure of the present invention can qualitatively and quantitatively characterize the characteristics of the film when deposited on the sidewall of such a three-dimensional structure. In addition, the structure can also study the potential damage caused by the deposition of the barrier layer to the trench sidewall dielectric layer, helping us to control the process more accurately. At the same time, the trench sidewall dielectric layer will not be directly affected by mechanical stress, and effectively avoids the intrusion of water vapor, thereby ensuring the accuracy and repeatability of the test results.

[0007] To solve the above technical problems, in a first aspect, the present invention provides a MIM capacitor test structure, which comprises, from bottom to top, a semiconductor substrate, a first dielectric layer, a metal layer under the MIM structure, a second dielectric layer, a first isolation protection layer, a third dielectric layer, a second isolation protection layer, and a passivation layer;

[0008] A first conductive trench is formed in the first dielectric layer, the lower metal layer of the MIM structure, and the second dielectric layer. The first conductive trench is provided with a trench sidewall dielectric layer, a first conductive trench barrier layer, and an upper metal layer of the MIM structure from the outside to the inside. The first conductive trench barrier layer wraps the upper metal layer of the MIM structure, and the trench sidewall dielectric layer wraps the first conductive trench barrier layer. The bottoms of the trench sidewall dielectric layer, the first conductive trench barrier layer, and the upper metal layer of the MIM structure are all located in the first dielectric layer, and the tops are flush with the top of the second dielectric layer. The middle section of the trench sidewall dielectric layer is located in the lower metal layer of the MIM structure.

[0009] The lower metal layer and the second dielectric layer of the MIM structure are provided with conductive through holes, and the conductive through holes are provided with a first barrier layer and a first metal layer from the outside to the inside; the first barrier layer wraps the first metal layer;

[0010] Two second conductive trenches are formed in the first isolation protection layer and the third dielectric layer, and each second conductive trench is provided with a second conductive trench barrier layer and a conductive metal layer from the outside to the inside; the second conductive trench barrier layer wraps the conductive metal layer;

[0011] Preferably, two pad grooves are formed in the second isolation protection layer and the passivation layer, and each pad groove is provided with a second barrier layer and a second metal layer from the outside to the inside; the second barrier layer wraps the second metal layer; there is a distance between the two pad grooves; and the two pad grooves are respectively located above the two second conductive trenches;

[0012] Preferably, the top of the first conductive trench is flush with the upper portion of the second dielectric layer, and a distance exists between the bottom of the first conductive trench and the bottom of the first dielectric layer;

[0013] Preferably, the top of the conductive through hole is flush with the upper side of the second dielectric layer, and the bottom of the conductive through hole is spaced apart from the bottom of the metal layer below the MIM structure.

[0014] Preferably, there is a distance between the first conductive trench and the conductive through hole; there is a distance between the two second conductive trenches;

[0015] Preferably, the two second conductive trenches are respectively located above the first conductive trench and the conductive through-hole, the bottom length of the second conductive trench located above the first conductive trench is shorter than the top length of the first conductive trench, and the bottom length of the second conductive trench located above the conductive through-hole is longer than the top length of the conductive through-hole;

[0016] Preferably, the material of the upper metal layer and the conductive metal layer of the MIM structure is copper; the material of the second metal layer is aluminum; and the material of the first metal layer is tungsten.

[0017] In a second aspect, the present invention provides a process for preparing a MIM capacitor test structure, specifically:

[0018] Providing a semiconductor substrate, and sequentially depositing a first dielectric layer, a lower metal layer of the MIM structure, and a second dielectric layer on the semiconductor substrate;

[0019] A first conductive trench is etched by an etching process, followed by deposition of a trench sidewall dielectric layer and a first conductive trench barrier layer, filling the upper metal layer of the MIM structure and performing CMP planarization;

[0020] Etching a conductive through hole through an etching process, depositing a first barrier layer and a first metal layer in the conductive through hole and performing CMP planarization;

[0021] Depositing a first isolation protection layer and a third dielectric layer on the structure, forming two second conductive trenches by etching and depositing second conductive trench barrier layers respectively, filling the trenches with conductive metal layers and connecting them to the first conductive trenches and conductive vias under the second conductive trench barrier layers respectively;

[0022] depositing a second isolation protection layer and a top passivation layer above the two second conductive trenches;

[0023] Preferably, pad grooves are etched in the second isolation protection layer and the top passivation layer, and a second barrier layer and a second metal layer are deposited as two test pads, and the two test pads are located away from the test structure;

[0024] In a third aspect, the present invention provides a reliability testing method for a MIM capacitor test structure, specifically:

[0025] Step S1: applying multiple sets of different test voltages to a set of MIM capacitor test structures at a fixed test temperature to obtain the failure time of the trench sidewall dielectric layer in the current MIM capacitor test structure;

[0026] At the same time, applying multiple sets of different test temperatures to the MIM capacitor test structure at a fixed test voltage to obtain the failure time of the trench sidewall dielectric layer in the current MIM capacitor test structure;

[0027] Step S2: Use the reliability evaluation model to predict the failure time of the trench sidewall dielectric layer of the above-mentioned MIM capacitor test structure. According to formula (2), the linear fitting With E x The electric field acceleration factor can be extracted from the slope , through linear fitting The relationship between it and 1 / T is the activation energy Ea; according to the electric field acceleration factor , activation energy Ea is reversed to obtain the proportional constant τ;

[0028] Step S3: Substitute the electric field acceleration factor calculated in step S2 into formula (1): , activation energy Ea, proportional constant τ, and the failure time of the trench sidewall dielectric layer of the MIM capacitor test structure during normal operation can be obtained based on the actual test voltage and test temperature;

[0029] The reliability evaluation model is the E model, and the specific formula is:

[0030] (1)

[0031] After taking the logarithm of formula (1), it is specifically:

[0032] (2)

[0033] Among them, t bd is the failure time of the trench sidewall dielectric layer, τ is the proportional constant, γ is the electric field acceleration factor, E x is the test voltage electric field, Ea is the activation energy, T is the test temperature, and k is the Boltzmann constant.

[0034] Preferably, the method comprises:

[0035] Step S4: To further determine the failure behavior of the MIM capacitor test structure group and thus predict the TDDB lifetime of the entire MIM capacitor test structure group, a Weibull distribution fitting may be performed based on the failure time of the trench sidewall dielectric layer of the MIM capacitor test structure at different test voltages and test temperatures, and the shape parameter and scale parameter in the Weibull distribution fitting formula may be extracted. The shape parameter and scale parameter may be used to further predict the failure probability of the MIM capacitor test structure group, or the lifetime under a given failure probability.

[0036] The beneficial effects are:

[0037] The present invention does not require chemical mechanical grinding of the dielectric layer on the capacitor sidewall, thus avoiding errors caused by the processing technology. In addition, the passivation layer covers the MIM capacitor structure, protecting it from erosion by environmental factors such as water vapor, and provides an electrode detection position away from the core research area to ensure that no mechanical damage is caused to the groove sidewall. When studying the performance of the capacitor sidewall, since the middle section of the dielectric layer on the groove sidewall is the part to be tested, it is located in the lower metal layer of the MIM structure, avoiding the electric field concentration caused by the sharp corners of the groove, thereby causing low breakdown electric field and rapid TDDB degradation problems. This design optimization helps us study the inherent TDDB performance of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic cross-sectional view of the MIM capacitor test structure of the present invention;

[0039] Figure 2 This is the process flow of the MIM capacitor test structure of the present invention.

[0040] Reference numerals:

[0041] 101. Semiconductor substrate; 102. First dielectric layer of silicon dioxide; 103. Lower metal layer of MIM structure; 104. Second dielectric layer; 105. Dielectric layer of trench sidewall; 106. First conductive trench barrier layer; 107. Upper metal layer of MIM structure; 108. First metal layer; 109. First barrier layer; 110. First isolation protection layer; 111. Third dielectric layer; 112. Second conductive trench barrier layer; 113. Conductive metal layer; 114. Second isolation protection layer; 115. Passivation layer; 116. Second metal layer; 117. Second barrier layer. DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] See also Figures 1 to 2 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation, the form, quantity, and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may also be more complex.

[0044] like Figure 1 As shown, this embodiment provides a test structure based on a MIM capacitor, which includes, from bottom to top: a semiconductor substrate 101, a first dielectric layer 102, a MIM structure lower metal layer 103, a second dielectric layer 104, a first isolation protection layer 110, a third dielectric layer 111, a second isolation protection layer 114, and a passivation layer 115;

[0045] A first conductive trench is formed in the first dielectric layer 102, the MIM structure lower metal layer 103, and the second dielectric layer 104. The first conductive trench is provided with a trench sidewall dielectric layer 105, a first conductive trench barrier layer 106, and a MIM structure upper metal layer 107 from the outside to the inside. The first conductive trench barrier layer 106 wraps the MIM structure upper metal layer 107, and the trench sidewall dielectric layer 105 wraps the first conductive trench barrier layer 106. The bottoms of the trench sidewall dielectric layer 105, the first conductive trench barrier layer 106, and the MIM structure upper metal layer 107 are all located in the first dielectric layer 102, and the tops are flush with the top of the second dielectric layer 104. The middle section of the trench sidewall dielectric layer 105 is located in the MIM structure lower metal layer 103.

[0046] Conductive vias are opened in the lower metal layer 103 and the second dielectric layer 104 of the MIM structure. The conductive vias are provided with a first barrier layer 109 and a first metal layer 108 from the outside to the inside. The first barrier layer 109 wraps the first metal layer 108.

[0047] Two second conductive trenches are formed in the first isolation protection layer 110 and the third dielectric layer 111. Each second conductive trench is provided with a second conductive trench barrier layer 112 and a conductive metal layer 113 from the outside to the inside. The second conductive trench barrier layer 112 wraps the conductive metal layer 113.

[0048] Two pad grooves are formed in the second isolation protection layer 114 and the passivation layer 115. Each pad groove is provided with a second barrier layer 117 and a second metal layer 116 from the outside to the inside. The second barrier layer 117 wraps the second metal layer 116.

[0049] The above structure is prepared by the following process: Figure 2 As shown:

[0050] A silicon substrate is provided as semiconductor substrate 101. A silicon dioxide thin film is deposited on semiconductor substrate 101 as first dielectric layer 102 by thermal oxidation, physical vapor deposition, or a PECVD process using TEOS as a precursor gas, which reacts with oxygen or an oxidizing gas (such as N2O) through plasma excitation. More specifically, first dielectric layer 102 has a thickness of 300 to 600 nm.

[0051] By physical vapor deposition, a metal layer of TiN is deposited as the lower metal layer 103 of the MIM structure, followed by a layer of silicon dioxide as the second dielectric layer 104. Since the lower metal layer 103 of the MIM structure is TiN, it mechanically clamps the HfO2 film, resulting in good interface contact between the two.

[0052] A first conductive trench or a conductive through hole needs to be etched, in no particular order.

[0053] Here, the first conductive trench (larger in area) is etched first, and the bottom of the trench is located in the first dielectric layer 102. The trench sidewall dielectric layer 105 is first deposited, and then metal TaN / Ta is deposited in sequence by physical vapor deposition as the first conductive trench barrier layer 106. A copper seed layer is first deposited by physical vapor deposition and then electroplated to generate a large area of ​​copper to fill the upper metal layer 107 of the MIM structure. Finally, the structure is flattened by CMP (chemical mechanical polishing). It should be noted that the copper seed layer is not in the Figure 2 Therefore, the MIM structure upper metal layer 107 filled in the first conductive trench, the trench sidewall dielectric layer 105, and the MIM structure lower metal layer 103 constitute an MIM structure, which is convenient for studying the trench sidewall performance.

[0054] Specifically, when etching the first conductive trench, to ensure accurate etching endpoints, the bottom of the first conductive trench must be located within the first dielectric layer 102, ensuring that the trench reaches the designated layer without damaging underlying structures. Therefore, it is possible to study only the sidewall properties without including the bottom. Prior to this, photoresist is coated on the wafer surface through a photolithography process, and a trench-patterned photoresist mask is formed through exposure and development steps.

[0055] Specifically, the trench sidewall dielectric layer 105 is made of HfO 2 .

[0056] More specifically, before the first conductive trench is filled with metal copper, a first conductive trench barrier layer 106 is formed on the bottom and sidewalls of the trench.

[0057] Then, the conductive via is etched again. The bottom of the conductive via is located in the lower metal layer 103 of the MIM structure, so that the electrical signal applied later can flow in the MIM structure and ensure the reliability of studying only the sidewalls of the conductive trench. Then, Ti / TiN is deposited in the conductive via by physical vapor deposition as the first barrier layer 109, and then metal tungsten is filled in the via by chemical vapor deposition as the first metal layer 108, and finally CMP flattening is performed again. When etching the conductive via, in order to ensure the accuracy of the etching end point, it is necessary to control the etching process so that the bottom of the conductive via is located in the lower metal layer 103 of the MIM structure made of TiN. In this way, the conductive via can form good contact with the lower metal layer 103 of the MIM structure.

[0058] A layer of Si3N4 is deposited on the above structure as a first isolation protection layer 110 and a layer of BD (B x SiO 2 serves as the third dielectric layer 111 .

[0059] Two identical second conductive trenches are etched in the third dielectric layer 111 to connect the first conductive trench and the conductive via in the lower layer respectively. TaN / Ta is deposited in sequence as the second conductive trench barrier layer 112 and filled with metal copper as the conductive metal layer 113 .

[0060] A second isolation protection layer 114 and a TEOS (SiOC2H) layer are deposited on the third dielectric layer 111. 54 as a top passivation layer 115;

[0061] Two pad trenches are etched in the second isolation protection layer 114 and the top passivation layer 115. A TaN / Ta layer is deposited in the pad trenches as a second barrier layer 117 and filled with aluminum as a second metal layer 116. Test pads are connected to the second conductive trenches. The aluminum pads connecting to the test probes must be kept away from the structure to prevent mechanical stress from the probes, which could damage the structure and affect test reliability.

[0062] This embodiment proposes a test structure based on MIM capacitors, specifically designed to address the sidewall reliability deficiencies of existing capacitor structures. This is crucial for gaining a deeper understanding of the long-term stability of devices. Furthermore, this structure enables the study of potential damage to the dielectric layer caused by barrier layer deposition, facilitating more precise process control. Furthermore, the trench sidewall dielectric layer 105 is not directly affected by mechanical stress and effectively prevents the intrusion of water vapor, thereby ensuring the accuracy and repeatability of test results.

[0063] This embodiment also provides a reliability testing method for the above-mentioned MIM capacitor test structure, specifically:

[0064] Step S1: applying multiple sets of different test voltages to a group of MIM capacitor test structures at a fixed test temperature to obtain the failure time of the trench sidewall dielectric layer 105 in the current MIM capacitor test structure;

[0065] At the same time, multiple groups of different test temperatures are applied to the MIM capacitor test structure at a fixed test voltage to obtain the failure time of the trench sidewall dielectric layer 105 in the current MIM capacitor test structure.

[0066] Step S2: Use the reliability evaluation model to predict the failure time of the trench sidewall dielectric layer 105 of the MIM capacitor test structure. According to formula (2), the linear fitting With E x The electric field acceleration factor can be extracted from the slope , through linear fitting The relationship between it and 1 / T is the activation energy Ea; according to the electric field acceleration factor , the activation energy Ea is reversed to obtain the proportional constant τ.

[0067] Step S3: Substitute the electric field acceleration factor calculated in step S2 into formula (1): , activation energy Ea, proportionality constant τ, and according to the actual test voltage and test temperature, the failure time of the trench sidewall dielectric layer 105 of the MIM capacitor test structure during normal operation can be obtained.

[0068] The reliability evaluation model is the E model, and the specific formula is:

[0069] (1)

[0070] After taking the logarithm of formula (1), it is specifically:

[0071] (2)

[0072] Among them, t bd is the failure time of the trench sidewall dielectric layer 105, τ is the proportional constant, γ is the electric field acceleration factor, E x is the test voltage electric field, Ea is the activation energy, T is the test temperature, and k is the Boltzmann constant.

[0073] Step S4: To further determine the failure behavior of the MIM capacitor test structure group and thus predict the TDDB lifetime of the entire MIM capacitor test structure group, a Weibull distribution fitting may be performed based on the failure time of the trench sidewall dielectric layer 105 of the aforementioned MIM capacitor test structure at different test voltages and test temperatures, and the shape parameter and scale parameter in the Weibull distribution fitting formula may be extracted. The shape parameter and scale parameter may be used to further predict the failure probability of the MIM capacitor test structure group, or the lifetime under a given failure probability.

[0074] In addition to directly studying the TDDB performance of the MIM capacitor, the MIM capacitor test structure of the present invention can also be used to study factors that may cause damage to the trench sidewall dielectric layer. For example, the re-sputtering process is widely used in PVD deposition of the Ta-based first conductive trench barrier layer 106 to improve the sidewall coverage, but due to high-energy ion bombardment, damage to the trench sidewall dielectric layer 105 may be introduced. Therefore, for the application of high-porosity and low-k-value materials, special attention should be paid to the damage of the first conductive trench barrier layer 106 to the trench sidewall dielectric layer 105. The MIM capacitor of the present invention can minimize the damage to the trench sidewall dielectric layer 105 and reduce TDDB degradation by optimizing the re-sputtering process. In addition, when testing the inherent reliability of the trench sidewall dielectric layer 105, the probe does not need to directly contact the non-critical area, and the test trench sidewall dielectric layer 105 will not be damaged, so it will not affect the reliability of the structural test results.

[0075] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A MIM capacitor test structure, characterized in that The structure comprises, from bottom to top, a semiconductor substrate (101), a first dielectric layer (102), a metal layer below the MIM structure (103), a second dielectric layer (104), a first isolation protection layer (110), a third dielectric layer (111), a second isolation protection layer (114), and a passivation layer (115); A first conductive trench is formed in the first dielectric layer (102), the MIM structure lower metal layer (103), and the second dielectric layer (104); the first conductive trench is provided with a trench sidewall dielectric layer (105), a first conductive trench barrier layer (106), and a MIM structure upper metal layer (107) from the outside to the inside; the first conductive trench barrier layer (106) wraps the MIM structure upper metal layer (107), and the trench sidewall dielectric layer (105) wraps the first conductive trench barrier layer (106); the bottoms of the trench sidewall dielectric layer (105), the first conductive trench barrier layer (106), and the MIM structure upper metal layer (107) are all located in the first dielectric layer (102), and the tops are flush with the top of the second dielectric layer (104); the middle section of the trench sidewall dielectric layer 105 is located in the MIM structure lower metal layer 103; Conductive through holes are provided in the lower metal layer (103) and the second dielectric layer (104) of the MIM structure, and the conductive through holes are provided with a first barrier layer (109) and a first metal layer (108) from the outside to the inside; the first barrier layer (109) wraps the first metal layer (108); Two second conductive trenches are formed in the first isolation protection layer (110) and the third dielectric layer (111); each second conductive trench is provided with a second conductive trench barrier layer (112) and a conductive metal layer (113) from the outside to the inside; and the second conductive trench barrier layer (112) wraps the conductive metal layer (113).

2. A MIM capacitor test structure according to claim 1, characterized in that: Two pad grooves are formed in the second isolation protection layer (114) and the passivation layer (115), and each pad groove is provided with a second barrier layer (117) and a second metal layer (116) from the outside to the inside; the second barrier layer (117) wraps the second metal layer (116).

3. A MIM capacitor test structure according to claim 1, characterized in that: The top of the first conductive trench is flush with the upper portion of the second dielectric layer (104), and the bottom of the first conductive trench is spaced apart from the bottom of the first dielectric layer (102).

4. A MIM capacitor test structure according to claim 1, characterized in that: The top of the conductive through hole is flush with the upper portion of the second dielectric layer (104), and the bottom of the conductive through hole is spaced apart from the bottom of the lower metal layer (103) of the MIM structure.

5. The MIM capacitor test structure according to claim 1, wherein: There is a distance between the first conductive trench and the conductive through hole; there is a distance between the two second conductive trenches.

6. A MIM capacitor test structure according to claim 1, characterized in that: The two second conductive trenches are respectively located above the first conductive trench and the conductive through-hole. The bottom length of the second conductive trench located above the first conductive trench is shorter than the top length of the first conductive trench. The bottom length of the second conductive trench located above the conductive through-hole is longer than the top length of the conductive through-hole.

7. The MIM capacitor test structure according to claim 1, wherein: The material of the upper metal layer (107) and the conductive metal layer (113) of the MIM structure is copper; the material of the second metal layer (116) is aluminum; and the material of the first metal layer (108) is tungsten.

8. The process for preparing a MIM capacitor test structure according to any one of claims 1 to 7, characterized in that Specifically: Providing a semiconductor substrate (101), and sequentially depositing a first dielectric layer (102), a lower metal layer of an MIM structure (103), and a second dielectric layer (104) on the semiconductor substrate (101); Etching a first conductive trench through an etching process, then depositing a trench sidewall dielectric layer (105) and a first conductive trench barrier layer (106), filling the upper metal layer (107) of the MIM structure and performing CMP flattening; Etching a conductive through hole through an etching process, depositing a first barrier layer (109) and a first metal layer (108) in the conductive through hole and performing CMP flattening; Depositing a first isolation protection layer (110) and a third dielectric layer (111) above the structure, forming a second conductive trench by etching, and depositing a second conductive trench barrier layer (112), respectively, filling a conductive metal layer (113) and respectively connecting the first conductive trench and the conductive through hole under the second conductive trench barrier layer (112); A second isolation protection layer (114) and a top passivation layer (115) are deposited above the two second conductive trenches.

9. A reliability testing method for a MIM capacitor test structure according to any one of claims 1 to 7, characterized in that Specifically: Step S1, applying multiple groups of different test voltages to a group of MIM capacitor test structures at a fixed test temperature to obtain the failure time of the trench sidewall dielectric layer (105) in the current MIM capacitor test structure; At the same time, applying multiple groups of different test temperatures to the MIM capacitor test structure under a fixed test voltage to obtain the failure time of the trench sidewall dielectric layer (105) in the current MIM capacitor test structure; Step S2: Use the reliability evaluation model to predict the failure time of the trench sidewall dielectric layer (105) of the MIM capacitor test structure. According to formula (2), the linear fitting With E x The electric field acceleration factor γ can be extracted from the slope by linear fitting The activation energy Ea is obtained from the relationship with 1 / T; the proportional constant τ is obtained by inverse calculation based on the electric field acceleration factor γ and the activation energy Ea; Step S3: Substitute the electric field acceleration factor calculated in step S2 into formula (1): , activation energy Ea, proportional constant τ, and according to the actual test voltage and test temperature, the failure time of the trench sidewall dielectric layer (105) of the MIM capacitor test structure during normal operation can be obtained; The reliability evaluation model is the E model, and the specific formula is: （1） After taking the logarithm of formula (1), it is specifically: （2） Among them, t bd is the failure time of the trench sidewall dielectric layer (105), τ is the proportionality constant, γ is the electric field acceleration factor, E x is the test voltage electric field, Ea is the activation energy, T is the test temperature, and k is the Boltzmann constant.

10. The method according to claim 9, characterized in that: The method comprises: Step S4: In order to further provide the failure behavior of the MIM capacitor test structure group and thus predict the TDDB life of the entire MIM capacitor test structure group, a Weibull distribution fitting can be performed based on the failure time of the trench sidewall dielectric layer (105) of the above-mentioned MIM capacitor test structure at different test voltages and test temperatures, and the shape parameter and scale parameter in the Weibull distribution fitting formula are extracted; and the shape parameter and scale parameter are used to further predict the failure probability of the MIM capacitor test structure group, or the life under a given failure probability.

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