Nine-level inverter topological structure and modulation method thereof

Abstract

The invention provides a nine-level inverter topological structure and a modulation method thereof, the topological structure comprises a load end, and a first direct-current voltage source, a second direct-current voltage source and a third direct-current voltage source which are respectively connected with the load end, and the output voltage ratio among the first direct-current voltage source, the second direct-current voltage source and the third direct-current voltage source is 2: 1: 1. By configuring an insulated gate bipolar transistor and a power diode, the number of switching tubes is reduced, and the inverter is ensured not to have the problems of power backward flowing and instantaneous peak voltage, so that the power backward flowing phenomenon caused by the fact that the current of a high-voltage power unit reversely flows into a low-voltage power unit and the instantaneous peak voltage during inductive loading are avoided; the stability of circuit output power is ensured, the design is simplified, and a step wave and carrier wave laminated hybrid modulation method is used, so that the low switching loss of a high-voltage power unit and the excellent harmonic characteristic of the output voltage of the inverter are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-level inverter modulation, and in particular to a nine-level inverter topology structure and a modulation method thereof. Background Art

[0002] The inverter topology and its modulation strategy are key factors affecting the quality and performance of the inverter output voltage waveform. In the field of multi-level inverters, NPC (Neutral Point Clamped) inverters, FC (Flying Capacitor) inverters, and CHB (Cascaded H-Bridge) inverters have their own applications, but they all have significant limitations. The NPC inverter topology is complex and difficult to expand, and the DC bus capacitor voltage division imbalance problem is prominent; the FC inverter requires a large number of DC capacitors, the voltage division imbalance problem is prominent, and an additional pre-charging circuit needs to be designed, which increases the system complexity and cost.

[0003] In the prior art, the traditional asymmetric CHB inverter requires a large number of switching tubes to obtain a multi-level output voltage. For example, the traditional nine-level CHB inverter topology is composed of four H-bridges in cascade, which consists of four independent DC voltage sources and 16 switching tubes (IGBT). Moreover, there are problems such as power imbalance, power backflow, and uneven heating, which seriously affect the stability and reliability of the inverter. In addition, the existing modulation strategy is complex and difficult to implement. In addition, the existing modulation strategy has shortcomings such as a long period required for power balancing, which makes it difficult to meet the needs of actual applications. Summary of the invention

[0004] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a nine-level inverter topology structure and a modulation method thereof, aiming to solve the technical problems in the prior art that the traditional nine-level inverter topology structure has power imbalance, power backflow, uneven heating, etc., which seriously affect the stability and reliability of the inverter.

[0005] In order to achieve the above object, the present invention is implemented by the following technical solution: a nine-level inverter topology structure, including a load end, and a first DC voltage source, a second DC voltage source and a third DC voltage source respectively connected to the load end, wherein the output voltage ratio between the first DC voltage source, the second DC voltage source and the third DC voltage source is: 2:1:1; The nine-level inverter topology structure further includes a first switch tube and a second switch tube arranged between the second DC voltage source and the positive and negative electrodes of the load end, a third switch tube and a fourth switch tube arranged between the first DC voltage source and the second DC voltage source, a fifth switch tube and a sixth switch tube arranged between the first DC voltage source and the third DC voltage source, and a seventh switch tube and an eighth switch tube arranged between the third DC voltage source and the positive and negative electrodes of the load end; The nine-level inverter topology structure further includes a ninth switch tube disposed between the fifth switch tube and the sixth switch tube, and a tenth switch tube disposed between the second DC voltage source and the third DC voltage source; The third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube are all connected to the load end; the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube all include a switch tube body, a first power diode and a second power diode arranged on the emitter side of the switch tube body, and a third power diode and a fourth power diode arranged on the collector side of the switch tube body; the switch tube body, the first power diode, the second power diode, the third power diode and the fourth power diode constitute a bidirectional current switch.

[0006] According to one aspect of the above technical solution, the first switch tube, the second switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube, and the tenth switch tube are all insulated gate bipolar transistors.

[0007] According to one aspect of the above technical solution, the output level u1 of the first DC voltage source is: 0, -2E and +2E; the output level u2 of the second DC voltage source is: 0, -E and +E; the output level u3 of the third DC voltage source is: 0, -E and +E; The output voltage u at the load end AN Satisfy:u AN =(u1+u2+u3)= .

[0008] On the other hand, the present invention further provides a modulation method of a nine-level inverter topology structure, which is used to modulate the output voltage of the nine-level inverter topology structure in the above technical solution, and the method comprises: The output of the first DC voltage source is modulated by a step wave, and the output of the second DC voltage source and the third DC voltage source are modulated by a carrier stacking wave; The expression of the first modulation wave output by the first DC voltage source is: ; In the formula, is the first modulation wave output by the first DC voltage source, To adjust the system, is the fundamental angular frequency, is the time variable; The expression of the second modulation wave output by the second DC voltage source and the third DC voltage source is: ; In the formula, It is the second modulation wave output by the second DC voltage source or the third DC voltage source.

[0009] According to one aspect of the above technical solution, the modulation method further includes: On the basis of adopting carrier stacking modulation for the second DC voltage source and the third DC voltage source, the number of carrier signals of the second DC voltage source and the third DC voltage source is reduced, and a target modulated wave signal is output to reduce the difficulty of implementing the modulation strategy; Among them, the expression of the target modulation wave signal is: ; In the formula, is the target modulation wave signal.

[0010] According to one aspect of the above technical solution, the modulation method further includes: Reconstructing the second modulation wave and controlling the conduction angle of the first DC voltage source output to achieve power balance among the first DC voltage source, the second DC voltage source, and the third DC voltage source within a quarter of the fundamental wave cycle; The second modulated wave includes a first waveform and a second waveform, and the step of reconstructing the second modulated wave specifically includes: The positions of the first waveform and the second waveform are interchanged every single triangular wave signal cycle, so that the working cycle of the second modulation wave after reconstruction is twice that before reconstruction; Among them, the relationship between the working period and frequency of the second modulation wave before and after reconstruction is expressed as: ; In the formula, and are the single triangle wave signal period and frequency of the carrier respectively, and is the duty cycle of the carrier signal before reconstruction, and is the frequency of the carrier signal before reconstruction, and is the duty cycle of the reconstructed carrier signal, and is the frequency of the reconstructed carrier signal.

[0011] According to one aspect of the above technical solution, the expression of the control signal of the conduction angle output by the first DC voltage source is as follows: ; In the formula, and is the control signal, To adjust the system, is the conduction angle.

[0012] According to one aspect of the above technical solution, the expression of the control signal of the output voltage component of the first DC voltage source is: ; In the formula, represents the control signal of the voltage component output by the first DC voltage source when the time variable is t, and n is the harmonic order; The expression of the fundamental wave of the output voltage component of the first DC voltage source is:

[0013] In the formula, It represents the fundamental wave of the voltage component output by the first DC voltage source when the time variable is t, and E is the unit output level.

[0014] According to one aspect of the above technical solution, the expression of the control signal of the output voltage after the second DC voltage source and the third DC voltage source are superimposed is: ; In the formula, represents a control signal of a voltage component outputted by the second DC voltage source and the third DC voltage source after superposition when the time variable is t; The expression of the fundamental wave of the output voltage component after the second DC voltage source and the third DC voltage source are superimposed is: ; In the formula, It represents the fundamental wave of the output voltage component after the second DC voltage source and the third DC voltage source are superimposed when the time variable is t.

[0015] According to one aspect of the above technical solution, in the power balance state, the relationship between the conduction angle and the modulation degree is: .

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: by configuring IGBT (Insulated Gate Bipolar Transistor) and power diodes, the number of switch tubes is reduced and the inverter is guaranteed to have no power backflow and instantaneous spike voltage problems, so as to avoid the power backflow phenomenon caused by the reverse flow of the high-voltage power unit current into the low-voltage power unit and the instantaneous spike voltage under the inductive load, thereby ensuring the stability of the circuit output power and simplifying the design. In terms of modulation strategy, firstly, a hybrid modulation method of step wave + carrier stacking is used to ensure low switching loss of the high-voltage power unit and excellent harmonic characteristics of the inverter output voltage; secondly, on the basis of the hybrid carrier stacking modulation method, the modulation wave signal of the low-voltage power unit is improved, and the improved The improved hybrid carrier stacking modulation strategy reduces the number of low-voltage power unit carriers by half, optimizes the distribution of switching device frequencies, reduces the difficulty of modulation implementation and reduces the loss differences of each switching tube; finally, by reconstructing the low-voltage power unit carrier signal, power balance between low-voltage power units is achieved, and then by controlling the conduction angle of the high-voltage power unit, power balance between high and low voltage power units is achieved. The improved hybrid carrier stacking modulation strategy with power balance is used to achieve coordinated control of all power units, realizing power balance within a quarter of the fundamental wave cycle, and effectively improving the safety and reliability of the inverter operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the circuit structure of a nine-level inverter topology structure in the first embodiment of the present invention; Figure 2 is a circular diagram of the relationship between the inverter output level and the switch state in the first embodiment of the present invention; Figure 3 It is the principle diagram of the traditional HLS-PWM (Hybrid Level Shifted Pulse Width Modulation HLS-PWM) hybrid carrier stacked modulation strategy; Figure 4 It is a schematic diagram of an improved hybrid level shifted pulse width modulation (IHLS-PWM) modulation strategy in the second embodiment of the present invention; Figure 5 The waveform diagram of the low-voltage power unit carrier signal in the second embodiment of the present invention, in which (a) is the traditional carrier signal waveform and (b) is the reconstructed carrier signal waveform; Figure 6 A modulation principle diagram of a low-voltage power unit after reconstruction of a carrier signal in a second embodiment of the present invention; Figure 7A schematic diagram of the modulation principle between high-voltage and low-voltage power units for controlling the conduction angle in the second embodiment of the present invention; Figure 8 is a curve diagram showing the relationship between the conduction angle and the modulation degree in the case of power balance in the second embodiment of the present invention; Fig. 9 FIG. 1 is a pulse signal diagram of each level output by the inverter in the second embodiment of the present invention; Fig.10 1 is a pulse signal diagram of the combination of switch conduction states when the inverter outputs various levels in a complete fundamental wave cycle in the second embodiment of the present invention, in which (a) is a pulse signal diagram of a positive half cycle, and (b) is a pulse signal diagram of a negative half cycle; Fig.11 It is a waveform diagram of the output voltage components of each power unit when the inverter adopts the traditional HLS-PWM modulation strategy under different modulation degrees in the second embodiment of the present invention; Fig.12 It is a waveform diagram of the output voltage components of each power unit when the inverter adopts the power balancing IHLS-PWM modulation strategy under different modulation degrees in the second embodiment of the present invention; Fig.13 It is a waveform diagram of the output power of each power unit when the inverter adopts the traditional HLS-PWM modulation strategy under different modulation degrees in the second embodiment of the present invention; Fig.14 This is a waveform diagram of the output power of each power unit when the inverter adopts the power balancing IHLS-PWM modulation strategy under different modulation in the second embodiment of the present invention; Fig.15 Graph showing the relationship between the output power and modulation degree of each power unit in the second embodiment of the present invention, wherein (a) is a graph showing the average output power curve of each power unit under the traditional HLS-PWM modulation strategy, and (b) is a graph showing the average output power curve of each power unit under the power-balanced IHLS-PWM modulation strategy; Fig.16 1 is an output voltage spectrum diagram of the inverter in the second embodiment of the present invention, in which (a) is an output voltage spectrum diagram of the inverter under the condition of the traditional HLS-PWM modulation strategy, and (b) is an output voltage spectrum diagram of the inverter under the condition of the power balanced IHLS-PWM modulation strategy; Fig.17 It is a comparison diagram of the relationship between the output voltage THD and the modulation degree of the inverter under the traditional HLS-PWM modulation strategy and the power balanced IHLS-PWM modulation strategy in the second embodiment of the present invention; Fig.181 is an output voltage waveform, current waveform and output voltage harmonic spectrum diagram of the load end in the second embodiment of the present invention, in which (a) is an output voltage waveform, current waveform and output voltage harmonic spectrum diagram of the load end when the modulation index is 0.9, and (b) is an output voltage waveform, current waveform and output voltage harmonic spectrum diagram of the load end when the modulation index is 0.6; Fig.19 1 is a waveform diagram of the output voltage components of each power unit in the second embodiment of the present invention, in which (a) is a waveform diagram of the output voltage components of each power unit when the modulation index is 0.9, and (b) is a waveform diagram of the output voltage components of each power unit when the modulation index is 0.6; Fig. 20 1 is an output power waveform diagram of each power unit in the second embodiment of the present invention, in which (a) is an output power waveform diagram of each power unit when the modulation index is 0.9, and (b) is an output power waveform diagram of each power unit when the modulation index is 0.6; The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0018] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0019] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0021] See also Figure 1 , which is a schematic diagram of a nine-level inverter topology structure in a first embodiment of the present invention. As shown in the figure, the topology structure includes: A load terminal 10, and a first DC voltage source 11, a second DC voltage source 12 and a third DC voltage source 13 respectively connected to the load terminal 10, wherein the output voltage ratio among the first DC voltage source 11, the second DC voltage source 12 and the third DC voltage source 13 is 2:1:1; The nine-level inverter topology structure further includes a first switch tube 21 and a second switch tube 22 arranged between the second DC voltage source 12 and the positive and negative electrodes of the load end 10, a third switch tube 23 and a fourth switch tube 24 arranged between the first DC voltage source 11 and the second DC voltage source 12, a fifth switch tube 25 and a sixth switch tube 26 arranged between the first DC voltage source 11 and the third DC voltage source 13, and a seventh switch tube 27 and an eighth switch tube 28 arranged between the third DC voltage source 13 and the positive and negative electrodes of the load end 10; The nine-level inverter topology structure further includes a ninth switch tube 29 disposed between the fifth switch tube 25 and the sixth switch tube 26, and a tenth switch tube 210 disposed between the second DC voltage source 12 and the third DC voltage source 13; The third switch tube 23, the fourth switch tube 24, the fifth switch tube 25 and the sixth switch tube 26 are all connected to the load end 10; the third switch tube 23, the fourth switch tube 24, the fifth switch tube 25 and the sixth switch tube 26 each include a switch tube body, a first power diode 31 and a second power diode 32 arranged on the emitter side of the switch tube body, and a third power diode 33 and a fourth power diode 34 arranged on the collector side of the switch tube body; the switch tube body, the first power diode 31, the second power diode 32, the third power diode 33 and the fourth power diode 34 constitute a bidirectional current switch.

[0022] For ease of understanding, the traditional nine-level CHB inverter topology consists of four cascaded H-bridges, which are composed of four independent DC voltage sources and 16 switches (IGBTs). The nine-level inverter topology in this solution reduces the number of switches by six compared to the traditional nine-level CHB inverter topology.

[0023] Preferably, in this embodiment, the first switch tube 21 , the second switch tube 22 , the seventh switch tube 27 , the eighth switch tube 28 , the ninth switch tube 29 , and the tenth switch tube 210 are all insulated gate bipolar transistors.

[0024] Furthermore, in this embodiment, the output level u1 of the first DC voltage source 11 is: 0, -2E and +2E; the output level u2 of the second DC voltage source 12 is: 0, -E and +E; the output level u3 of the third DC voltage source 13 is: 0, -E and +E; The output voltage u of the load end 10 AN Satisfy:u AN =(u1+u2+u3)= .

[0025] According to the conduction state of each switch tube, the high-voltage power unit H1 (including the first DC voltage source 11 and the corresponding switch tube in the conduction state) can output three levels of 0, +2E and -2E, and the low-voltage power unit L2 (including the second DC voltage source 12 and the corresponding switch tube in the conduction state) and the low-voltage power unit L3 (including the third DC voltage source 13 and the corresponding switch tube in the conduction state) can output three levels of 0, +E and -E. There are a total of seven power supply combinations of E1 (first DC voltage source 11), E2 (second DC voltage source 12), E3 (third DC voltage source 13), E2+E3, E1+E2, E1+E3, and E1+E2+E3, which can output 0, ±E, ±2E, ±3E, and ±4E. For ease of understanding, the power units in the text are the above-mentioned first DC voltage source 11, second DC voltage source 12, and third DC voltage source 13.

[0026] like Figure 2 As shown, it is a ring diagram of the relationship between the inverter output level and the switch state, indicating that the inverter has a total of 18 switch state combinations in one power cycle. Figure 2 “1, 2, …, 10” indicates the corresponding switch tubes in the on state at the current electrical level (0, ±E, ±2E, ±3E, ±4E), 1 indicates that the first switch tube 21 is on, 2 indicates that the second switch tube 22 is on, and so on, 10 indicates that the tenth switch tube 210 is on, and the switch tube state that has not appeared is off.

[0027] According to the switching devices and output characteristics of the inverter topology, the inverter does not have the reverse flow of the current output by the high-voltage power unit into the low-voltage power unit in the level level of all redundant switch state combinations, so the inverter mentioned in this article does not have the problem of power backflow between various electric powers. In the case of a resistive inductive load, the lagging inductive current can flow back to the power supply of the corresponding voltage level, so there is no problem of instantaneous spike voltage at the resistive inductive load terminal 10.

[0028] In summary, the nine-level inverter topology structure in the above-mentioned embodiment of the present invention reduces the number of switching tubes and ensures that the inverter does not have power backflow and instantaneous spike voltage problems by configuring IGBT (Insulated Gate Bipolar Transistor) and power diodes, so as to avoid the power backflow phenomenon caused by the reverse flow of high-voltage power unit current into the low-voltage power unit and the instantaneous spike voltage under inductive load, thereby ensuring the stability of circuit output power and simplifying the design.

[0029] Based on the nine-level inverter topology structure in the first embodiment, a second embodiment of the present invention provides a modulation method of a nine-level inverter topology structure, the method comprising: The output of the first DC voltage source is modulated by a step wave, and the outputs of the second DC voltage source and the third DC voltage source are modulated by a carrier stacking wave.

[0030] For the inverter with a power supply voltage level of 2:1:1, the high-voltage power unit H1 adopts step wave modulation, and the low-voltage power units L2 and L3 adopt carrier stacking modulation. The principle of the traditional HLS-PWM (Hybrid Level Shifted Pulse Width Modulation HLS-PWM) hybrid carrier stacking modulation strategy is as follows: Figure 3 shown. v H is the modulation wave signal of the high voltage power unit H1, v C1+ =+2, v C1- =-2 is the carrier signal of the high voltage power unit; v L is the modulation wave signal of the low voltage power units L2 and L3, v C2+ , v C2- , v C3+ , v C3- (Frequency is f CR , an isosceles triangle carrier with a peak-to-peak value of 1, and a vertical offset of 1 between two adjacent carriers) is the carrier signal of the low-voltage power unit.

[0031] The expression of the first modulation wave output by the first DC voltage source is: (1); In the formula, is the first modulation wave output by the first DC voltage source, To adjust the system, is the fundamental angular frequency, is the time variable; The expression of the second modulation wave output by the second DC voltage source and the third DC voltage source is: (2); In the formula, It is the second modulation wave output by the second DC voltage source or the third DC voltage source.

[0032] The output voltage component u1 of the high voltage power unit H1 is: when v H ≥ v C1+ When u1=+2E; when v C1 -< v H < v C1+ When u1=0; when v H ≤ v C1- When u1= -2E. The output voltage component u2 of the low voltage power unit L2 is: v L ≥ v C2+ When u2=+E; when v C2- < v L < v C2+ When u2=0; when v L ≤ v C2- When u2=-E. The output voltage component u3 of the low voltage power unit L3 is: v L ≥ v C3+ When u3= +E; when v C3- < v L < v C3+ When u3=0; when v L ≤ v C3- , u3= -E.

[0033] In a complete power cycle, the high-voltage power unit H1 works in a low-frequency state and the output levels are -2E, 0, +2E, and the output waveform is a square wave; the low-voltage power units L2 and L3 work in a high-frequency state and the output levels are -E, 0, +E, and the output waveforms are high-frequency PWM waves. The output voltage components of the high-voltage power unit and the low-voltage power unit are superimposed to obtain a nine-level inverter output voltage u ANThe inverter adopts the traditional HLS-PWM modulation strategy. The polarity of the output voltage components of each unit is constant within a complete working cycle, that is, there is no power backflow problem in the inverter power unit; this modulation method can also reduce the switching frequency of the high-voltage power unit switch tube to reduce switching losses, and the inverter output voltage maintains good harmonic characteristics.

[0034] Preferably, in this embodiment, the modulation method further includes: On the basis of adopting carrier stacking modulation for the second DC voltage source and the third DC voltage source, the number of carrier signals of the second DC voltage source and the third DC voltage source is reduced, and the target modulated wave signal is output to reduce the difficulty of implementing the modulation strategy.

[0035] For ease of understanding, this solution proposes an improved hybrid level shifted pulse width modulation (IHLS-PWM) modulation strategy for the traditional HLS-PWM modulation strategy. The principle of the IHLS-PWM modulation strategy is as follows: Figure 4 shown. It is the improved modulation wave signal of low voltage power unit L2 and L3. v C2+ , v C3+ is the carrier signal of the low voltage power unit. v L After the negative half-cycle part is shifted upward by "+2" units, the improved modulation wave signal is obtained. The improved low-voltage power unit reduces the number of carrier signals in one complete power cycle of the inverter by half.

[0036] The carrier signal, modulation wave signal and output voltage component u1 of the high-voltage power unit H1 remain unchanged.

[0037] Carrier signal of low voltage power units L2 and L3 v C2+ , v C3+ Keeping the same, the expression of the modulated wave signal in a complete power cycle is: (3); In the formula, is the target modulation wave signal.

[0038] Specifically, the output voltage component u2 of the low-voltage power unit L2 is: In the half cycle, when ≥ v C2+When u2=+E, < v C2+ When u2=0; In the half cycle, when ≥ v C2+ When u2=0, < v C2+ When u2=-E. The output voltage component u3 of the low voltage power unit L3 is: In the half cycle, when ≥ v C3+ When u3=+E, < v C3+ When u3=0; In the half cycle, when ≥ v C3+ When u3=0, < v C3+ , u3=-E.

[0039] The IHLS-PWM modulation strategy is used to control the conduction state of the switch tube, and the modulation wave and carrier signal are optimized for the low-voltage power unit, reducing the difficulty of implementing the control signal. Within a complete power cycle of the inverter, the control signals of some of the improved switch tubes have changed, narrowing the gap in the pulse signal frequency between the low-voltage power units, that is, reducing the difference in switching losses of some switch tubes. However, there is still a large gap in the working operation time of each power unit, that is, there is a power imbalance problem between the low-voltage power units and between the high and low-voltage power units.

[0040] Furthermore, in this embodiment, the modulation method further includes: Reconstructing the second modulation wave and controlling the conduction angle of the first DC voltage source output to achieve power balance among the first DC voltage source, the second DC voltage source, and the third DC voltage source within a quarter of the fundamental wave cycle; The second modulated wave includes a first waveform and a second waveform, and the step of reconstructing the second modulated wave specifically includes: Every single triangle wave signal cycle, the positions of the first waveform and the second waveform are swapped, and the working cycle of the second modulation wave after reconstruction is twice that before reconstruction.

[0041] Aiming at the problem that the IHLS-PWM modulation strategy cannot achieve power balance among various power units, the carrier signals of the low-voltage power units are reconstructed based on the modulation strategy. The principle of low-voltage power unit carrier reconstruction is as follows: Figure 5 As shown, Figure 5 (a) is the traditional carrier signal waveform. Figure 5 (b) in the figure is the reconstructed carrier signal waveform.

[0042] Assume that the single triangle wave signal period of the carrier is T CR , the frequency is f CR , the peak-to-peak value is 1; the working period of the carrier signal before reconstruction is T C2+ , T C3+ , the frequency is f C2+ , f C3+ , the working period of the reconstructed carrier signal is , , the frequency is , , the improved modulation wave signal period of the low voltage power unit is T , the frequency is f .

[0043] Starting from time 0, every T CR Time will v C2+ and v C3+ The waveforms are swapped to obtain the waveform of the reconstructed carrier signal , The working period of the reconstructed carrier signal is twice that of the carrier signal before reconstruction. The relationship between the period and frequency can be expressed as: (4); In the formula, and are the single triangle wave signal period and frequency of the carrier respectively, and is the duty cycle of the carrier signal before reconstruction, and is the frequency of the carrier signal before reconstruction, and is the duty cycle of the reconstructed carrier signal, and is the frequency of the reconstructed carrier signal.

[0044] definition t on2+ , t on3+ They are the time during which the low voltage power units L2 and L3 output +E level voltage in one positive half cycle respectively;t on2- , t on3- are the time during which the low voltage power units L2 and L3 output -E level voltage in a negative half cycle respectively; P 2+ , P 3+ are the average output powers of the low voltage power units L2 and L3 in a positive half cycle respectively; P 2- , P 3- are the average output power of low voltage power units L2 and L3 in a negative half cycle. The modulation principle diagram of the low voltage power unit after carrier reconstruction is shown in Figure 6 shown.

[0045] Since the reconstructed carrier wave is completely symmetrical in rotation in the positive half cycle or the negative half cycle, that is, the waveforms of the voltage components u2 and u3 are also completely symmetrical about the midpoint in the positive half cycle or the negative half cycle, the time expression for the low-voltage power units L2 and L3 to output a +E level voltage in a positive half cycle and a -E level voltage in a negative half cycle is: (5); Since the amplitudes of the voltage components u2 and u3 are both E, combined with equation (5), we can get that the low-voltage power units L2 and L3 are in a positive half cycle and a negative half cycle. The average voltage of the internal output is: (6); In the formula, , are the average voltages output by the low-voltage power unit L2 in the positive half cycle and the negative half cycle respectively, , They are the average voltages output by the low-voltage power unit L3 in the positive half cycle and the negative half cycle respectively.

[0046] The inverter low-voltage power units L2 and L3 are in series structure. When the power sources E2 and E3 output the same level, they work alternately. The output current magnitude and direction are consistent. Therefore, the average output active power of the low-voltage power units L2 and L3 in a positive half cycle and a negative half cycle is equal. The expression is: (7); Compared with the IHLS-PWM modulation strategy, by reconstructing the carrier of the low-voltage power unit, the output voltage component u after the low-voltage power units L2 and L3 are superimposed in series 2+3The output waveform remains unchanged after carrier reconstruction, and the switching signals of some switching devices are further optimized, further narrowing the switching frequency gap of some switching tubes when the low-voltage power unit is working. Through carrier reconstruction, each low-voltage power unit achieves power balance within 1 / 4 fundamental wave period.

[0047] Based on the carrier reconstruction of the low-voltage power units L2 and L3 to achieve power balance between the low-voltage power units, the conduction angle of the switch tube of the high-voltage power unit H1 is controlled. To achieve power balance between high and low voltage power units, the modulation principle between high and low voltage power units controlling the conduction angle is as follows Figure 7 shown.

[0048] according to Figure 7 It can be known that the conduction angle of the switch tube Modulation m a Related, by Figure 7 The control signal of the conduction angle output by the first DC voltage source can be derived. and They are: (8); In the formula, and is the control signal, To adjust the system, is the conduction angle.

[0049] The control signal of the output voltage component of the high-voltage power unit H1 is defined as v 1, v 1 is a square wave. When the first DC voltage source outputs a voltage component of the control signal v The Fourier decomposition expression of 1 is: (9); The control signal of the output voltage after the low-voltage power units L2 and L3 are superimposed is defined as v 2+3 , v 2+3 It is a segmented mixed waveform. When the second DC voltage source and the third DC voltage source are superimposed, the control signal of the output voltage is The Fourier decomposition expression of is: (10).

[0050] According to formula (1), the output voltage can be obtained u AN Fundamental uAN(1) The expression is: (11); According to formula (9), the output voltage component of high-voltage power unit H1 can be obtained: u Fundamental wave of 1 u 1(1) The expression is: (12); According to formula (10), the output voltage u after the low-voltage power units L2 and L3 are superimposed can be obtained: 2+3 The fundamental wave u 2+3(1) The expression is: (13); In the adjustment system When the modulation index is 100, the carrier reconstruction technology is used between the low-voltage power units to achieve power balance between the low-voltage power units; When the output voltage fundamental wave of the high-voltage power unit and the low-voltage power unit is superimposed, the magnitude is equal, that is, u 1(1) =u 2+3(1) =0.5u AN(1) , power balance between high and low voltage power units can be achieved.

[0051] Combining formula (11), formula (12) and formula (13), we can get the conduction angle Modulation The relationship is: (14); In the case of power balance, the switch conduction angle Modulation The relationship curve is as follows Figure 8 shown.

[0052] This scheme proposes an improved IHLS-PWM modulation strategy for power balance based on the IHLS-PWM modulation strategy. This modulation strategy uses carrier reconstruction between low-voltage power units and controls the conduction angle of the H1 switch tube of the high-voltage power unit. This method can achieve power balance among all power units of the inverter under full modulation. Figure 6 and Figure 7 It can be seen that power balance is achieved between the low-voltage power units and between the high- and low-voltage power units within 1 / 4 fundamental wave cycle, which further reduces the switching loss gap of some switching tubes and effectively improves the safety and reliability of the inverter operation.

[0053] according to Figure 7 Output voltage waveform of the inverter AN as well as Figure 2The relationship diagram between the inverter output level and the switch state combination is shown in Figure 2. Under the condition of the power balanced IHLS-PWM modulation strategy, the pulse signals A1~A1 that control the inverter output at all levels can be obtained. 12 ,like Fig. 9 As shown. A1~A3 are pulse signals of output E1, E2, E3 levels respectively; A4 is the pulse signal corresponding to the output zero level; A5~A8 are pulse signals corresponding to the output -E~ -4E levels respectively; A9~A 12 They are pulse signals corresponding to the output +E~ +4E levels respectively.

[0054] The inverter has two output modes, E2 and E3, when outputting "±E" level; two output modes, "E1, E2+E3" when outputting "±2E" level; two output modes, "E1+E2, E1+E3" when outputting "±3E"; and one output mode, "E1+E2+E3" when outputting "±4E".

[0055] The pulse signal of the switch tube conduction state combination in a complete fundamental wave cycle is as follows Fig.10 As shown, where "S x1，x2，… (x1 is 1 or 2, ..., or 10; x2 is 1 or 2, ..., or 10; ...)" means that when the corresponding level is output, the switch tubes in the on state are the x1th switch tube and the x2th switch tube. When the level is non-zero, all redundant switch state combinations are used. When the level is zero, the switch state combination of S1, 2 is selected, that is, the combination of the first switch tube and the second switch tube. Fig.10 The switch tube S1~S 10 The pulse signal logic expression in the on state is as follows (15): (15); For easy understanding, Refers to the negation of the pulse signal A1 at a high level. When the pulse signal A1 is at a high level, is low level; when the pulse signal A1 is low level, is high level.

[0056] In order to further verify the feasibility of the new nine-level inverter topology and its power balanced IHLS-PWM modulation strategy, Matlab2018b / Simulink is used to simulate and analyze the inverter. The simulation parameter settings are shown in Table 1.

[0057] Table 1

[0058] Fig.11The simulation waveforms of the output voltage components of each power unit when the inverter adopts the traditional HLS-PWM modulation strategy under different modulation indices. When the modulation index is 0.3, the waveform of the output voltage component u1 of the high-voltage power unit H1 fluctuates around the zero point, that is, it does not participate in the work of the inverter output. The waveforms of the output voltage components u2 and u3 of the low-voltage power units L2 and L3 are both three-level PWM waves, but the pulse width and frequency of the waveforms are quite different; when the modulation index is 0.6 and 0.9, the waveform of u1 is a symmetrical square wave, and the waveforms of u2 and u3 are always three-level PWM waves with large frequency differences. When the modulation index changes from "0.3→0.6→0.9", the number of output voltage levels of the inverter is a PWM wave of "5→7→9". The voltage peak value of the nine-level waveform is about 311V and the effective value is about 220V. The time it takes to output a complete waveform is 0.02s.

[0059] Fig.12 The following are the simulated waveforms of the output voltage components of each power unit when the inverter adopts the power-balanced IHLS-PWM modulation strategy under different modulation indices. When the modulation indices are 0.3, 0.6, and 0.9, the waveform of the output voltage component u1 of the high-voltage power unit H1 is a symmetrical square wave, and both participate in the work of the inverter output; the waveforms of the output voltage components u2 and u3 of the low-voltage power units L2 and L3 are three-level PWM waves, and the pulse width and frequency of the waveforms are basically the same. When the modulation indices change from "0.3→0.6→0.9", the number of output voltage levels of the inverter is a PWM wave that changes from "5→7→9".

[0060] Fig.13 The following is the simulated waveform of the output power of each power unit when the inverter adopts the traditional HLS-PWM modulation strategy under different modulation degrees. As shown in the figure, the output power ratio of each power unit and the corresponding power supply voltage ratio under the same modulation degree are far apart, and power balance cannot be achieved between power units under different modulation degrees.

[0061] Fig.14 The simulation waveforms of the output power of each power unit when the inverter adopts the power balancing IHLS-PWM modulation strategy under different modulation degrees. The instantaneous output power waveforms of low-voltage power units L2 and L3 remain consistent under the same modulation degree, and the output power ratio between each power unit under different modulation degrees remains basically consistent with the corresponding power supply voltage ratio, achieving power balancing.

[0062] Depend on Fig.15 As shown in (a), the average output power of each power unit of the inverter under the traditional HLS-PWM modulation strategy always has a large difference under different modulation indices. <0.5, high voltage power unit H1 has no power output; Fig.15From (b), it can be seen that under the power balancing IHLS-PWM modulation strategy, the average output power curves of the low-voltage power units L2 and L3 of the inverter are basically consistent, and the average output power curves of each power unit satisfy the power balancing condition of P1:P2:P3=2:1:1, that is, power balancing between each power unit is achieved under the full modulation system.

[0063] Fig.16 (a) and Fig.16 (b) in the figure shows the output voltage spectrum when the inverter adopts two modulation strategies. Under the two modulation strategies, the output voltage fundamental amplitude of the inverter is positively correlated with the modulation index, and the total harmonic distortion THD value of the output voltage is negatively correlated with the modulation index. The main harmonic frequencies of the output voltage of the inverter under the two modulation strategies are concentrated at 5kHz and its vicinity, and low THD can be maintained under the full modulation index, indicating that the output voltage of the inverter has good harmonic characteristics under the two modulation strategies.

[0064] Fig.17 The relationship curves of the inverter output voltage THD and modulation degree under two modulation strategies are shown in Figure 2. Fig.16 and Fig.17 It can be seen that within the full modulation range, the output voltage THD of the inverter under the two modulation strategies is basically the same; and the inverter adopts the power balancing IHLS-PWM modulation strategy to achieve power balancing of each power unit under the full modulation range.

[0065] In order to further verify the feasibility of the new nine-level inverter topology and its power balanced IHLS-PWM modulation strategy, an experimental prototype of the inverter was built and the experimental prototype parameters are shown in Table 2. The inverter was tested under the conditions of modulation ma of 0.9 and 0.6 respectively.

[0066] Table 2

[0067] Modulation Under the conditions of 0.9 and 0.6, the output voltage u at the load end AN Waveform, current i AN The waveform and output voltage harmonic spectrum are as follows: Fig.18 As shown in the figure, the output voltage is a step wave and the output current is approximately a sine wave. =0.9, the number of output levels is 9, the output voltage peak is 48V, and the output current peak is 0.9A; =0.6, the number of output levels is 7, the output voltage peak is 36V, and the output current peak is 0.6A. The main harmonic frequencies of the output voltage are concentrated at 5kHz and its vicinity, and the harmonic distribution law is around the carrier frequency f CR Near an integer multiple of .

[0068] Fig.19 The modulation index of each power unit The waveform of the output voltage component under the conditions of 0.9 and 0.6. Under different modulation indices, the high-voltage power unit H1 operates at the fundamental frequency and the output voltage component waveform is a symmetrical square wave; the output voltage component waveforms of the low-voltage power units L2 and L3 are both three-level PWM waves, and their frequencies are basically the same.

[0069] Fig. 20 (a) and Fig. 20 (b) in the figure shows the modulation degree of each power unit. The output power waveform at 0.9 and 0.6. =0.9, the average power output of H1, L2, and L3 power units in one cycle are 9.419W, 4.684W, and 4.723W respectively; =0.6, the average power is 4.094W, 2.051W, and 2.002W respectively. Under the two modulation indexes, the output power ratio of each power unit basically meets 2:1:1, that is, the power balance between each power unit is achieved.

[0070] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A nine-level inverter topology structure, characterized in that: It includes a load end, and a first DC voltage source, a second DC voltage source and a third DC voltage source respectively connected to the load end, wherein the output voltage ratio between the first DC voltage source, the second DC voltage source and the third DC voltage source is 2:1:1; The nine-level inverter topology structure further includes a first switch tube and a second switch tube arranged between the second DC voltage source and the positive and negative electrodes of the load end, a third switch tube and a fourth switch tube arranged between the first DC voltage source and the second DC voltage source, a fifth switch tube and a sixth switch tube arranged between the first DC voltage source and the third DC voltage source, and a seventh switch tube and an eighth switch tube arranged between the third DC voltage source and the positive and negative electrodes of the load end; The nine-level inverter topology structure further includes a ninth switch tube disposed between the fifth switch tube and the sixth switch tube, and a tenth switch tube disposed between the second DC voltage source and the third DC voltage source; The third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube are all connected to the load end; the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube all include a switch tube body, a first power diode and a second power diode arranged on the emitter side of the switch tube body, and a third power diode and a fourth power diode arranged on the collector side of the switch tube body; the switch tube body, the first power diode, the second power diode, the third power diode and the fourth power diode constitute a bidirectional current switch.

2. The nine-level inverter topology structure according to claim 1, characterized in that: The first switch tube, the second switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube, and the tenth switch tube are all insulated gate bipolar transistors.

3. The nine-level inverter topology structure according to claim 1, characterized in that: The output level u1 of the first DC voltage source is: 0, -2E and +2E; the output level u2 of the second DC voltage source is: 0, -E and +E; the output level u3 of the third DC voltage source is: 0, -E and +E; The output voltage u at the load end AN Satisfy:u AN =(u1+u2+u3)= .

4. A modulation method for a nine-level inverter topology structure, characterized in that: For modulating the output voltage of the nine-level inverter topology structure according to any one of claims 1 to 3, the method comprising: The output of the first DC voltage source is modulated by a step wave, and the output of the second DC voltage source and the third DC voltage source are modulated by a carrier stacking wave; The expression of the first modulation wave output by the first DC voltage source is: ； In the formula, is the first modulation wave output by the first DC voltage source, To adjust the system, is the fundamental angular frequency, is the time variable; The expression of the second modulation wave output by the second DC voltage source and the third DC voltage source is: ； In the formula, It is the second modulation wave output by the second DC voltage source or the third DC voltage source.

5. The modulation method of the nine-level inverter topology structure according to claim 4, characterized in that: The modulation method further comprises: On the basis of adopting carrier stacking modulation for the second DC voltage source and the third DC voltage source, reducing the number of carrier signals of the second DC voltage source and the third DC voltage source, and outputting a target modulated wave signal; Among them, the expression of the target modulation wave signal is: ； In the formula, is the target modulation wave signal.

6. The modulation method of the nine-level inverter topology structure according to claim 5, characterized in that: The modulation method further comprises: Reconstructing the second modulation wave and controlling the conduction angle of the first DC voltage source output to achieve power balance among the first DC voltage source, the second DC voltage source, and the third DC voltage source within a quarter of the fundamental wave cycle; The second modulated wave includes a first waveform and a second waveform, and the step of reconstructing the second modulated wave specifically includes: The positions of the first waveform and the second waveform are interchanged every single triangular wave signal cycle, so that the working cycle of the second modulation wave after reconstruction is twice that before reconstruction; Among them, the relationship between the working period and frequency of the second modulation wave before and after reconstruction is expressed as: ； In the formula, and are the single triangle wave signal period and frequency of the carrier respectively, and is the duty cycle of the carrier signal before reconstruction, and is the frequency of the carrier signal before reconstruction, and is the duty cycle of the reconstructed carrier signal, and is the frequency of the reconstructed carrier signal.

7. The modulation method of the nine-level inverter topology structure according to claim 6, characterized in that: The expression of the control signal of the conduction angle output by the first DC voltage source is as follows: ； In the formula, and is the control signal, To adjust the system, is the conduction angle.

8. The modulation method of the nine-level inverter topology structure according to claim 7, characterized in that: The expression of the control signal of the output voltage component of the first DC voltage source is: ； In the formula, represents the control signal of the voltage component output by the first DC voltage source when the time variable is t, and n is the harmonic order; The expression of the fundamental wave of the output voltage component of the first DC voltage source is: ； In the formula, It represents the fundamental wave of the voltage component output by the first DC voltage source when the time variable is t, and E is the unit output level.

9. The modulation method of the nine-level inverter topology structure according to claim 8, characterized in that: The expression of the control signal of the output voltage after the second DC voltage source and the third DC voltage source are superimposed is: ； In the formula, represents a control signal of a voltage component outputted by the second DC voltage source and the third DC voltage source after superposition when the time variable is t; The expression of the fundamental wave of the output voltage component after the second DC voltage source and the third DC voltage source are superimposed is: ； In the formula, It represents the fundamental wave of the output voltage component after the second DC voltage source and the third DC voltage source are superimposed when the time variable is t.

10. The modulation method of the nine-level inverter topology structure according to claim 9, characterized in that: In the power balance state, the relationship between the conduction angle and the modulation degree is: 。

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