Semiconductor device

Abstract

The present invention addresses the problem of providing a semiconductor device capable of appropriately changing the voltage amplitude of a differential signal without using a resistor. The semiconductor device includes: a first upper and lower arm including a first switching element on a first potential side and a second switching element on a second potential side connected in series with the first switching element, the first upper and lower arm outputting a first signal by the first switching element and the second switching element operating complementarily; and a second up-down arm which is arranged in parallel with the first up-down arm and includes a third switching element on the first potential side and a fourth switching element on the second potential side connected in series with the third switching element. A third switching element and a fourth switching element complementarily operate to generate and output a second signal whose potential changes complementarily with respect to the first signal; and a voltage control circuit connected to the first and second upper and lower arms and limiting the voltage amplitudes of the first and second signals on the basis of the bias voltage.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Patent document 1 discloses a driver circuit using a low voltage differential signal (LVDS) interface to achieve high-speed data transmission (see Patent document 1). Figure 1 ). A pair of transmission paths for transmitting a differential signal to a receiving circuit is connected to the driver circuit. A terminal resistor, i.e., a resistor, is provided in the pair of transmission paths for setting the voltage amplitude of the differential signal. A current from a current source flows to the resistor, thereby generating a potential difference between the pair of transmission paths. In the prior art, the voltage amplitude of the differential signal is set by changing the value of the resistor or the value of the current source.

[0003] [Prior art literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2000-031810 Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] However, in the prior art, in order to use the resistor provided outside the driver circuit to set the voltage amplitude of the differential signal, the resistor provided on the receiving circuit side is used, so the structure of the system including the receiving circuit becomes complicated, and the yield may be reduced. In addition, the resistor may become an obstacle to the need to further shorten the manufacturing time of the system including the receiving circuit. In addition, if the value of the current source on the driver circuit side is changed without replacing the resistor, it may not be possible to obtain the appropriate voltage amplitude of the differential signal. As such, in the prior art, there is room for improvement in appropriately changing the voltage amplitude of the differential signal.

[0008] The present disclosure is based on the above circumstances, and an object of the present disclosure is to provide a semiconductor device that can appropriately change the voltage amplitude of a differential signal without using a resistor.

[0009] [Technical means to solve the problem]

[0010] In order to solve the above-mentioned problem, the semiconductor device disclosed in the present invention is a semiconductor device that outputs a differential signal, and the semiconductor device includes: a first upper and lower arm, including a first switching element on one side of a first potential and a second switching element on one side of a second potential lower than the first potential connected in series with the first switching element, and a first signal is output by the first switching element and the second switching element acting complementarily; a second upper and lower arm, which is arranged in parallel with the first upper and lower arms and includes a third switching element on one side of the first potential and a fourth switching element on one side of the second potential connected in series with the third switching element, and a second signal whose potential changes complementarily with respect to the first signal is generated and output by the third switching element and the fourth switching element acting complementarily; and a voltage control circuit, which is connected to the first upper and lower arms and the second upper and lower arms, and limits the voltage amplitudes of the first signal and the second signal based on a bias voltage.

[0011] [Effects of the Invention]

[0012] According to the present disclosure, it is possible to provide a semiconductor device capable of appropriately changing the voltage amplitude of a differential signal without using a resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a diagram showing the structure of a display device according to an embodiment of the present disclosure.

[0014] Figure 2 It is a diagram showing the structure of a communication system according to an embodiment of the present disclosure.

[0015] Figure 3 It is a diagram showing the configuration of a transmission circuit according to an embodiment of the present disclosure.

[0016] Figure 4 This is a timing chart for explaining the operation of the transmission circuit.

[0017] Figure 5 It is a diagram showing the configuration of a transmission circuit according to a first modification.

[0018] Figure 6 It is a diagram showing the configuration of a transmission circuit according to a second variation.

[0019] Figure 7 It is a timing chart for explaining the operation of the transmission circuit of the second modification example.

[0020] Figure 8 It is a diagram showing the configuration of a transmission circuit according to a third modified example.

[0021] [Explanation of Symbols]

[0022] 1: First switching element

[0023] 2: Second switch element

[0024] 3: The third switching element

[0025] 4: Fourth switch element

[0026] 5: Current source

[0027] 5a: Current Source

[0028] 6: Voltage control circuit

[0029] 6A: Voltage control circuit

[0030] 6A1: First voltage control circuit

[0031] 6A2: Second voltage control circuit

[0032] 6B: Voltage Control Circuit

[0033] 6B1: First voltage control circuit

[0034] 6B2: Second voltage control circuit

[0035] 6C: Voltage Control Circuit

[0036] 6C1: First voltage control circuit

[0037] 6C2: Second voltage control circuit

[0038] 6C3: Third voltage control circuit

[0039] 6C4: Fourth voltage control circuit

[0040] 10: Display Panel

[0041] 11: Timing controller

[0042] 12: Signal output circuit

[0043] 13: Gate Driver

[0044] 20: Transmission Path

[0045] 21: First capacitor element

[0046] 22: Second capacitor element

[0047] 23: Differential signal

[0048] 24: First Signal

[0049] 25: Second signal

[0050] 26: First logic signal

[0051] 27: Second logic signal

[0052] 31: First upper and lower arms

[0053] 32: Second upper and lower arms

[0054] 61: First transistor pair

[0055] 62: Second transistor pair

[0056] 100: Display device

[0057] 111: Transmitting circuit

[0058] 111A: Transmitting circuit

[0059] 111B: Transmitting circuit

[0060] 111C: Transmitting circuit

[0061] 121: Receiving circuit

[0062] 200: Communication Systems DETAILED DESCRIPTION

[0063] Hereinafter, the embodiments will be described based on the drawings. In addition, the same or similar symbols are attached to the same functions or structures, and the description thereof will be omitted as appropriate.

[0064] [Example]

[0065] (Display device)

[0066] Figure 1 1 is a diagram showing the structure of a display device according to an embodiment of the present disclosure. The display device 100 can be interpreted as a vehicle display device mounted on a car or the like. The display device 100 includes a display panel 10, a timing controller 11, a driver integrated circuit (IC) 12 (also referred to as a signal output circuit), and a gate driver 13.

[0067] The display panel 10 may be interpreted as an image display device such as a liquid crystal display panel or an organic electroluminescence (EL) panel.

[0068] The timing controller 11 can control the display timing of the image in the display panel 10 by controlling the plurality of driver ICs 12 and the gate driver 13. The timing controller 11 can generate a clock signal and supply it to the driver IC 12. The timing controller 11 can supply a scanning control signal synchronized with the image data to the gate driver 13. The timing controller 11 can be interpreted as a semiconductor device including a transmission circuit described later. The transmission circuit can be interpreted as a driver circuit.

[0069] The driver IC 12 may control the lighting state of a plurality of light emitting elements provided in the display panel 10. The gate driver 13 may generate a gate signal based on a signal supplied from the timing controller 11 and supply the gate signal to the display panel 10.

[0070] The timing controller 11 and the driver IC 12 may constitute a communication system 200. The communication system 200 may be interpreted as a system using mini-LVDS.

[0071] Next, refer to Figure 2 The configuration of the communication system 200 will be described. Figure 2 2 is a diagram showing a configuration of a communication system according to an embodiment of the present disclosure. The communication system 200 includes a timing controller 11 and a signal output circuit 12. The timing controller 11 and the signal output circuit 12 are connected to each other via a transmission path 20 so as to be communicable.

[0072] The timing controller 11 includes a transmission circuit 111. The transmission circuit 111 can be interpreted as a semiconductor device that outputs the differential signal 23. The transmission circuit 111 can also be interpreted as a circuit that transmits data using the differential signal 23. In addition, the transmission circuit 111 can also be applied to devices other than the timing controller 11.

[0073] The differential signal 23 includes two signals that change in a complementary manner. Specifically, the differential signal 23 includes a first signal 24 transmitted via a first capacitor 21 configured in the transmission path 20, and a second signal 25 transmitted via a second capacitor 22 configured in the transmission path 20. The second signal 25 can be interpreted as a signal whose potential changes in a complementary manner relative to the first signal 24.

[0074] The signal output circuit 12 includes a receiving circuit 121. The receiving circuit 121 can be interpreted as a data receiving circuit of an AC coupling method that supplies a differential signal 23 transmitted via a capacitor element. The AC coupling method can be interpreted as a method of removing the DC component of the input signal and transmitting only the AC component to the receiving circuit 121. The receiving circuit 121 has a first input terminal IN1 to which a first signal 24 is input, and a second input terminal IN2 to which a second signal 25 is input. The first input terminal IN1 can be interpreted as a positive terminal (+ terminal), and the second input terminal IN2 can be interpreted as a negative terminal (- terminal).

[0075] The receiving circuit 121 outputs a first logic signal 26 corresponding to the potential of the first signal 24 and a second logic signal 27 corresponding to the potential of the second signal 25. Specifically, the first signal 24 and the second signal 25 can be amplified to output the first logic signal 26 and the second logic signal 27 with a voltage level greater than the first signal 24 and the second signal 25. The first logic signal 26 is sent to the first output terminal OUT1 via the first output terminal OUT2. Figure 1The display panel 10 shown in FIG. 1 is a display panel 10 in which the second logic signal 27 is sent to the display panel 10 via the second output terminal OUT2. Figure 1 The display panel 10 is shown.

[0076] Next, refer to Figure 3 The specific structure of the transmission circuit 111 will be described. Figure 3 1 is a diagram showing a configuration of a transmission circuit according to an embodiment of the present disclosure. The transmission circuit 111 includes a first upper and lower arm 31 , a second upper and lower arm 32 , and a voltage control circuit 6 .

[0077] (First upper and lower arm)

[0078] The first upper and lower arms 31 can be interpreted as a circuit including a first switching element 1 and a second switching element 2 connected in series. Specifically, the first upper and lower arms 31 can be interpreted as a circuit including a first switching element 1 on a first potential side and a second switching element 2 on a second potential side lower than the first potential connected in series with the first switching element 1. The first upper and lower arms 31 can output the first signal 24 by the first switching element 1 and the second switching element 2 operating complementarily.

[0079] The first potential can be interpreted as the potential of the power supply VDD, and the second potential can be interpreted as the potential of the ground GND. The first switch element 1 and the second switch element 2 can be interpreted as transistors, respectively.

[0080] (Second upper and lower arm)

[0081] The second upper and lower arms 32 can be interpreted as a circuit configured in parallel with the first upper and lower arms 31, and can be interpreted as a circuit including the third switch element 3 and the fourth switch element 4 connected in series. Specifically, the second upper and lower arms 32 can be interpreted as a circuit including the third switch element 3 on the first potential side, and the fourth switch element 4 on the second potential side lower than the first potential connected in series with the third switch element 3. The second upper and lower arms 32 can output the second signal 25 by the third switch element 3 and the fourth switch element 4 complementarily operating. The third switch element 3 and the fourth switch element 4 can be interpreted as transistors, respectively.

[0082] The on / off operation of each of the switching elements from the first switching element 1 to the fourth switching element 4 is controlled by a control circuit (not shown).

[0083] exist Figure 3 , the first switch element 1 and the fourth switch element 4 are in the on state, and the second switch element 2 and the third switch element 3 are in the off state. In this case, the current from the current source 5 flows in the order of the first switch element 1, the first input terminal IN1, the second input terminal IN2, the fourth switch element 4, and the ground GND.

[0084] In contrast, when the first switch element 1 and the fourth switch element 4 are in the off state and the second switch element 2 and the third switch element 3 are in the on state, the current from the current source 5 flows in the order of the fourth switch element 4, the second input terminal IN2, the first input terminal IN1, the second switch element 2, and the ground GND.

[0085] (Voltage Control Circuit)

[0086] The voltage control circuit 6 can be interpreted as a control circuit that controls the voltage amplitude of the differential signal 23. The voltage control circuit 6 can be interpreted as a circuit that is connected to the first upper and lower arms 31 and the second upper and lower arms 32 and limits the voltage amplitude of the first signal 24 and the second signal 25 based on the bias voltage Vbias.

[0087] Specifically, the voltage control circuit 6 can be interpreted as a transistor connected between the current source 5 set at the first potential (power supply VDD) and the first switch element 1 , and further connected between the current source 5 and the third switch element 3 .

[0088] More specifically, the voltage control circuit 6 can be interpreted as an enhancement type P-channel transistor, wherein a bias voltage Vbias is applied to the gate G, the drain D is grounded, and the source S is connected to the current source 5, one end of the first switch element 1, and one end of the third switch element 3.

[0089] The bias voltage Vbias can be interpreted as a voltage generated by a voltage generating circuit (not shown). The bias voltage Vbias can be interpreted as a voltage that specifies the voltage amplitude of each of the first signal 24 and the second signal 25. The bias voltage Vbias can be interpreted as a voltage that limits the voltage applied to the first upper and lower arms 31 and the second upper and lower arms 32 to a specific potential.

[0090] (Operation of the transmission circuit)

[0091] Next, refer to Figure 4 The operation of the transmission circuit 111 will be described. Figure 4 is a timing diagram for explaining the operation of the transmission circuit. Figure 4 , a clock signal (φ) input to the first arm or the second arm from a control circuit not shown, a clock signal ( / φ) input to the first arm or the second arm from a control circuit not shown, a first signal 24 input to the first input terminal IN1, and a second signal 25 input to the second input terminal IN2 are shown. The clock signal ( / φ) can be interpreted as a signal whose potential changes complementarily with respect to the clock signal (φ).

[0092] When the first switching element 1 and the fourth switching element 4 are turned on by the clock signal φ and the second switching element 2 and the third switching element 3 are turned off by the clock signal / φ at time t1, the voltage of the first signal 24 increases and the voltage of the second signal 25 decreases.

[0093] When the voltage of the first signal 24 reaches a specific voltage at time t2 after a certain time has passed from time t1, a current flows to the voltage control circuit 6, thereby suppressing the increase in the voltage amplitude of the first signal 24. The specific voltage can be interpreted as a voltage obtained by adding the gate-source voltage Vgs of the transistor of the voltage control circuit 6 to the bias voltage Vbias. The specific voltage can also be interpreted as a voltage for causing the current from the current source 5 to flow to the voltage control circuit 6, that is, for causing the current to bypass the voltage control circuit 6. By changing the bias voltage, the voltage amplitude of the first signal 24 can be changed.

[0094] At time t3 after a certain time from time t2, when the first switch element 1 and the fourth switch element 4 are turned off by the clock signal φ and the second switch element 2 and the third switch element 3 are turned on by the clock signal / φ, the voltage of the second signal 25 increases and the voltage of the first signal 24 decreases.

[0095] When the voltage of the second signal 25 reaches a specific voltage at time t4 after a certain time has passed from time t3, current flows to the voltage control circuit 6, thereby suppressing the increase in the voltage amplitude of the second signal 25. As described above, the specific voltage can be interpreted as a voltage obtained by adding the gate-source voltage Vgs to the bias voltage Vbias, and can also be interpreted as a voltage that causes the current from the current source 5 to flow to the voltage control circuit 6. By changing the bias voltage, the voltage amplitude of the second signal 25 can be changed.

[0096] In this way, the transmitting circuit 111 of the present disclosure can change the voltage amplitude of the differential signal by setting the bias voltage Vbias. In contrast, in the prior art, a resistor is provided outside the driver circuit corresponding to the transmitting circuit 111, and the voltage amplitude of the differential signal is set using the resistor. Therefore, the structure of the system including the receiving circuit becomes complicated and the yield may decrease. In addition, the resistor may become an obstacle to the need to further shorten the manufacturing time of the system including the receiving circuit. In addition, if the value of the current source on the driver circuit side is changed without replacing the resistor, it may not be possible to obtain the appropriate voltage amplitude of the differential signal.

[0097] (Function, Effect)

[0098] The transmission circuit 111 of the present disclosure includes a voltage control circuit 6 that limits the voltage amplitude of the differential signal based on the bias voltage. With the above structure, the voltage amplitude of the differential signal can be changed without providing a resistor outside the driver circuit. Therefore, it is possible to simplify the system structure including the receiving circuit and perform high-speed communication with the voltage amplitude of the differential signal limited.

[0099] In addition, since the structure of the system including the receiving circuit is simplified, the yield can be improved. In addition, the manufacturing time of the system including the receiving circuit can be further shortened. In addition, the voltage amplitude of the differential signal can be easily changed without replacing the resistor. In addition, the voltage amplitude of the differential signal can be easily changed without changing the current of the current source 5.

[0100] (First Modification)

[0101] Figure 5 FIG. 1 is a diagram showing a configuration of a transmission circuit according to a first variation. Figure 3 The transmission circuit 111 shown is different in that the voltage control circuit 6A of the transmission circuit 111A of the first modification includes a first voltage control circuit 6A1 and a second voltage control circuit 6A2 .

[0102] The first voltage control circuit 6A1 can be interpreted as a transistor connected between the third switch element 3 and the fourth switch element 4. Specifically, the first voltage control circuit 6A1 can be interpreted as an enhancement type P-channel transistor, wherein a bias voltage Vbias is applied to the gate G, the drain D is grounded, and the source S is connected to the other end of the third switch element 3 and one end of the fourth switch element 4.

[0103] The second voltage control circuit 6A2 can be interpreted as a transistor connected between the first switch element 1 and the second switch element 2. Specifically, the second voltage control circuit 6A2 can be interpreted as an enhancement type P-channel transistor, wherein a bias voltage Vbias is applied to the gate G, the drain D is grounded, and the source S is connected to the other end of the first switch element 1 and one end of the second switch element 2.

[0104] The transmission circuit 111A of the first variation can be used with Figure 3 The transmitting circuit 111 shown in FIG. 1 operates in the same manner. Figure 4At the time t2 shown, when the voltage of the first signal 24 reaches a specific voltage, current flows to the second voltage control circuit 6A2, thereby suppressing the increase in the voltage amplitude of the first signal 24. The specific voltage can be interpreted as a voltage obtained by adding the gate-source voltage Vgs of the transistor constituting the second voltage control circuit 6A2 to the bias voltage Vbias. The specific voltage can also be interpreted as a voltage for causing the current from the current source 5 to flow to the second voltage control circuit 6A2, that is, for causing the current to bypass the second voltage control circuit 6A2. By changing the bias voltage, the voltage amplitude of the first signal 24 can be changed.

[0105] In addition, when Figure 4 At the time t4 shown, when the voltage of the second signal 25 reaches a specific voltage, a current flows to the first voltage control circuit 6A1, thereby suppressing the increase in the voltage amplitude of the second signal 25. As described above, the specific voltage can be interpreted as a voltage obtained by adding the gate-source voltage Vgs of the transistor constituting the first voltage control circuit 6A1 to the bias voltage Vbias, or as a voltage that causes the current from the current source 5 to flow to the first voltage control circuit 6A1. By changing the bias voltage, the voltage amplitude of the second signal 25 can be changed.

[0106] So far, a configuration example of a transmission circuit for defining an upper limit of a voltage amplitude of a differential signal has been described. Next, a configuration example (a second modification example and a third modification example) of a transmission circuit for defining a lower limit of a voltage amplitude will be described.

[0107] (Second Modification)

[0108] Figure 6 FIG. 2 is a diagram showing a configuration of a transmission circuit according to a second variation. Figure 3 The difference of the transmission circuit 111 shown is that the voltage control circuit 6B of the transmission circuit 111B of the second modification includes a first voltage control circuit 6B1 and a second voltage control circuit 6B2. In the transmission circuit 111B, the other end of the second switch element 2 and the other end of the fourth switch element 4 are connected to the current source 5a on the second potential side.

[0109] The first voltage control circuit 6B1 includes a first conductive type transistor. The first conductive type transistor can be interpreted as a transistor connected between the first current source set at the first potential and the first switch element 1, and connected between the first current source and the third switch element 3. The first current source can be interpreted as a current source 5. Specifically, the first voltage control circuit 6B1 can be interpreted as a transistor connected between the current source 5 set at the first potential and the first switch element 1, and connected between the current source 5 and the third switch element 3. More specifically, the first voltage control circuit 6B1 can be interpreted as an enhancement type P-channel transistor, wherein a bias voltage Vbiasp is applied to the gate G, the drain D is grounded, and the source S is connected to the current source 5, one end of the first switch element 1, and one end of the third switch element 3.

[0110] The second voltage control circuit 6B2 includes a second conductive type transistor. The second conductive type transistor can be interpreted as a transistor connected between the second current source set at the second potential and the second switch element 2, and connected between the second current source and the fourth switch element 4. The second current source can be interpreted as a current source 5a. Specifically, the second voltage control circuit 6B2 can be interpreted as a transistor connected between the current source 5a set at the second potential and the second switch element 2, and connected between the current source 5a and the fourth switch element 4. More specifically, the second voltage control circuit 6B2 can be interpreted as an enhanced N-channel transistor, wherein a bias voltage Vbiasn is applied to the gate G, the drain D is connected to the power supply VDD, and the source S is connected to the current source 5a, the other end of the second switch element 2, and the other end of the fourth switch element 4.

[0111] (Operation of Transmitting Circuit of Second Modification)

[0112] Next, refer to Figure 7 The operation of the transmission circuit 111B will be described. Figure 7 2 is a timing chart for explaining the operation of the transmission circuit of the second modification example. Figure 7 , a clock signal (φ) input to the first arm or the second arm from a control circuit not shown in the figure, a clock signal ( / φ) input to the first arm or the second arm from a control circuit not shown in the figure, a first signal 24 input to the first input terminal IN1, and a second signal 25 input to the second input terminal IN2 are shown.

[0113] When the first switching element 1 and the fourth switching element 4 are turned on by the clock signal φ and the second switching element 2 and the third switching element 3 are turned off by the clock signal / φ at time t1, the voltage of the first signal 24 increases and the voltage of the second signal 25 decreases.

[0114] When the voltage of the first signal 24 reaches a specific voltage at time t2 after a certain time has passed from time t1, current flows to the first voltage control circuit 6B1, thereby suppressing the increase in the voltage amplitude of the first signal 24. The specific voltage can be interpreted as a voltage obtained by adding the gate-source voltage Vgsp of the transistor of the first voltage control circuit 6B1 to the bias voltage Vbiasp in the first voltage control circuit 6B1. The specific voltage can also be interpreted as a voltage for causing the current from the current source 5 to flow to the first voltage control circuit 6B1, that is, for causing the current to bypass the first voltage control circuit 6B1. By changing the bias voltage Vbiasp, the voltage amplitude of the first signal 24 can be changed.

[0115] At time t3 after a certain time from time t2, when the first switch element 1 and the fourth switch element 4 are turned off by the clock signal φ and the second switch element 2 and the third switch element 3 are turned on by the clock signal / φ, the voltage of the second signal 25 increases and the voltage of the first signal 24 decreases.

[0116] When the voltage of the second signal 25 reaches a specific voltage at time t4 after a certain time has passed from time t3, current flows to the second voltage control circuit 6B2, thereby suppressing the decrease in the voltage amplitude of the second signal 25. As described above, the specific voltage can be interpreted as a voltage obtained by adding the gate-source voltage Vgsn to the bias voltage Vbiasn in the second voltage control circuit 6B2, or as a voltage that causes the current from the current source 5 to flow to the second voltage control circuit 6B2. By changing the bias voltage Vbiasn, the voltage amplitude of the second signal 25 can be changed.

[0117] The transmission circuit 111B can change the upper limit and lower limit of the voltage amplitude of the differential signal by changing the bias voltage Vbiasp and the bias voltage Vbiasn. According to the transmission circuit 111B, the voltage amplitude of the differential signal can be set more finely, thereby achieving higher-speed data transmission.

[0118] (Third Modification)

[0119] Figure 8 FIG. 2 is a diagram showing a configuration of a transmission circuit according to a third variation. Figure 6 The difference of the transmission circuit 111B shown is that the voltage control circuit 6C of the transmission circuit 111C of the third modification includes a first transistor pair 61 and a second transistor pair 62. Specifically, the voltage control circuit 6C includes a first voltage control circuit 6C1, a second voltage control circuit 6C2, a third voltage control circuit 6C3, and a fourth voltage control circuit 6C4.

[0120] The first transistor pair 61 can be interpreted as a transistor pair including a first conductive type transistor and a second conductive type transistor connected in series between the first potential and the second potential, and connected between the third switch element 3 and the fourth switch element 4. The second transistor pair 62 can be interpreted as a transistor pair including a first conductive type transistor and a second conductive type transistor connected in series between the first potential and the second potential, and connected between the first switch element 1 and the second switch element 2.

[0121] The first voltage control circuit 6C1 can be interpreted as a transistor connected between the third switch element 3 and the fourth switch element 4. Specifically, the first voltage control circuit 6C1 can be interpreted as an enhanced N-channel transistor, wherein a bias voltage Vbiasp is applied to the gate G, the drain D is connected to the power supply VDD, the source S is connected to the other end of the third switch element 3 and one end of the fourth switch element 4, and the source S is connected to the source S of the second voltage control circuit 6C2.

[0122] The second voltage control circuit 6C2 can be interpreted as a transistor connected between the third switch element 3 and the fourth switch element 4. Specifically, the second voltage control circuit 6C2 can be interpreted as an enhancement type P-channel transistor, wherein a bias voltage Vbiasn is applied to the gate G, the drain D is grounded, the source S is connected to the other end of the third switch element 3 and one end of the fourth switch element 4, and the source S is connected to the source S of the first voltage control circuit 6C1.

[0123] The third voltage control circuit 6C3 can be interpreted as a transistor connected between the first switch element 1 and the second switch element 2. Specifically, the third voltage control circuit 6C3 can be interpreted as an enhanced N-channel transistor, wherein a bias voltage Vbiasp is applied to the gate G, the drain D is connected to the power supply VDD, the source S is connected to the other end of the first switch element 1 and one end of the second switch element 2, and the source S is connected to the source S of the fourth voltage control circuit 6C4.

[0124] The fourth voltage control circuit 6C4 can be interpreted as a transistor connected between the first switch element 1 and the second switch element 2. Specifically, the fourth voltage control circuit 6C4 can be interpreted as an enhancement type P-channel transistor, wherein a bias voltage Vbiasn is applied to the gate G, the drain D is grounded, the source S is connected to the other end of the first switch element 1 and one end of the second switch element 2, and the source S is connected to the source S of the third voltage control circuit 6C3.

[0125] The transmission circuit 111C of the third variation can be used with Figure 6 The transmission circuit 111B shown in FIG. 1 operates in the same manner. Figure 7At the time t2 shown, when the voltage of the first signal 24 reaches a specific voltage, current flows to the fourth voltage control circuit 6C4, thereby suppressing the increase in the voltage amplitude of the first signal 24. The specific voltage can be interpreted as a voltage obtained by adding the gate-source voltage Vgsn of the transistor constituting the fourth voltage control circuit 6C4 to the bias voltage Vbiasn. The specific voltage can also be interpreted as a voltage for causing the current from the current source 5 to flow to the fourth voltage control circuit 6C4, that is, to bypass the fourth voltage control circuit 6C4. By changing the bias voltage, the upper limit of the voltage amplitude of the first signal 24 can be changed.

[0126] When Figure 7 At the time t2 shown, when the voltage of the second signal 25 reaches a specific voltage, current flows to the first voltage control circuit 6C1, thereby suppressing the decrease in the voltage amplitude of the second signal 25. The specific voltage can be interpreted as a voltage obtained by adding the gate-source voltage Vgsp of the transistor constituting the first voltage control circuit 6C1 to the bias voltage Vbiasp. The specific voltage can also be interpreted as a voltage for causing the current from the current source 5a to flow to the first voltage control circuit 6C1, that is, to bypass the first voltage control circuit 6C1. By changing the bias voltage, the lower limit of the voltage amplitude of the second signal 25 can be changed.

[0127] When Figure 7 At the time t4 shown, when the voltage of the first signal 24 reaches a specific voltage, current flows to the third voltage control circuit 6C3, thereby suppressing the decrease in the voltage amplitude of the first signal 24. The specific voltage can be interpreted as a voltage obtained by adding the gate-source voltage Vgsp of the transistor constituting the third voltage control circuit 6C3 to the bias voltage Vbiasp. The specific voltage can also be interpreted as a voltage for causing the current from the current source 5a to flow to the third voltage control circuit 6C3, that is, to bypass the third voltage control circuit 6C3. By changing the bias voltage, the lower limit of the voltage amplitude of the first signal 24 can be changed.

[0128] When Figure 7 At the time t4 shown, when the voltage of the second signal 25 reaches a specific voltage, current flows to the second voltage control circuit 6C2, thereby suppressing the increase in the voltage amplitude of the second signal 25. The specific voltage can be interpreted as a voltage obtained by adding the gate-source voltage Vgsn of the transistor constituting the second voltage control circuit 6C2 to the bias voltage Vbiasn. The specific voltage can also be interpreted as a voltage for causing the current from the current source 5 to flow to the second voltage control circuit 6C2, that is, to bypass the second voltage control circuit 6C2. By changing the bias voltage, the upper limit of the voltage amplitude of the second signal 25 can be changed.

[0129] In addition, regarding the above description, the following supplementary notes are further disclosed.

[0130] (Note 1)

[0131] A semiconductor device is a semiconductor device that outputs a differential signal, and the semiconductor device comprises:

[0132] A first upper and lower arm includes a first switch element at a first potential side and a second switch element at a second potential side lower than the first potential connected in series with the first switch element, and the first switch element and the second switch element complementarily operate to output a first signal;

[0133] a second upper and lower arm, arranged in parallel with the first upper and lower arms and including a third switch element on the first potential side and a fourth switch element on the second potential side connected in series with the third switch element, wherein the third switch element and the fourth switch element complementarily operate to generate and output a second signal whose potential changes complementarily with respect to the first signal; and

[0134] The voltage control circuit is connected to the first upper and lower arms and the second upper and lower arms, and limits the voltage amplitudes of the first signal and the second signal based on a bias voltage.

[0135] (Note 2)

[0136] The semiconductor device according to Supplement 1, wherein

[0137] The voltage control circuit is connected between a current source set at the first potential and the first switching element, and is connected between the current source and the third switching element.

[0138] (Note 3)

[0139] The semiconductor device according to Supplement 1 or 2, wherein

[0140] The voltage control circuit includes a first voltage control circuit connected between the third switching element and the fourth switching element, and a second voltage control circuit connected between the first switching element and the second switching element.

[0141] (Note 4)

[0142] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the voltage control circuit comprises:

[0143] A first voltage control circuit includes a first conductivity type transistor connected between a first current source set at the first potential and the first switch element and connected between the first current source and the third switch element; and

[0144] The second voltage control circuit includes a second conductivity type transistor connected between a second current source set at the second potential and the second switch element and connected between the second current source and the fourth switch element.

[0145] (Note 5)

[0146] The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the voltage control circuit comprises:

[0147] A first transistor pair includes a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and connected between the third switch element and the fourth switch element; and

[0148] The second transistor pair includes a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and is connected between the first switch element and the second switch element.

Claims

1. A semiconductor device, which is a semiconductor device that outputs a differential signal, comprising: A first upper and lower arm includes a first switch element at a first potential side and a second switch element at a second potential side lower than the first potential connected in series with the first switch element, and the first switch element and the second switch element complementarily operate to output a first signal; a second upper and lower arm, arranged in parallel with the first upper and lower arm and including a third switch element on the first potential side and a fourth switch element on the second potential side connected in series with the third switch element, wherein the third switch element and the fourth switch element complementarily operate to generate and output a second signal whose potential changes complementarily with respect to the first signal; as well as The voltage control circuit is connected to the first upper and lower arms and the second upper and lower arms, and limits the voltage amplitudes of the first signal and the second signal based on a bias voltage.

2. The semiconductor device according to claim 1, wherein The voltage control circuit is connected between a current source set at the first potential and the first switching element, and is connected between the current source and the third switching element.

3. The semiconductor device according to claim 1, wherein The voltage control circuit includes a first voltage control circuit connected between the third switching element and the fourth switching element, and a second voltage control circuit connected between the first switching element and the second switching element.

4. The semiconductor device according to claim 1, wherein the voltage control circuit comprises: A first voltage control circuit includes a first conductivity type transistor connected between a first current source set at the first potential and the first switch element and connected between the first current source and the third switch element; and The second voltage control circuit includes a second conductivity type transistor connected between a second current source set at the second potential and the second switch element and connected between the second current source and the fourth switch element.

5. The semiconductor device according to claim 1, wherein the voltage control circuit comprises: A first transistor pair includes a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and connected between the third switch element and the fourth switch element; and The second transistor pair includes a first conductivity type transistor and a second conductivity type transistor connected in series between the first potential and the second potential, and is connected between the first switch element and the second switch element.

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