Automatic detection circuit for frequency divider ratio change

Abstract

The present invention discloses an automatic detection circuit for changes in the frequency divider's frequency division ratio, which is used to connect to the frequency divider and detect changes in the frequency divider's frequency division ratio in real time. The detection circuit includes a frequency division circuit, an inverter, a DFF trigger, an XOR gate operation circuit, and a NOR operation circuit. The inverter is connected to each frequency division ratio bit port of the frequency divider and outputs a corresponding node signal, which is input into the DFF trigger. The frequency division circuit is connected to the output port of the frequency divider, divides the divided clock by the frequency divider again, and inputs the obtained clock signal into each DFF trigger as a sampling clock. The output signal of the DFF trigger, each bit signal, and the node signal are input into the corresponding XOR gate operation circuit and then pass through the NOR operation circuit to obtain an output signal, which serves as a reset signal or other identification signal or logic control signal for a counter to control the frequency divider, ensuring that the frequency divider outputs the correct clock frequency in a timely manner after the frequency division ratio is changed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a circuit for automatically detecting changes in a frequency divider's frequency division ratio. Background Art

[0002] In digital circuits and communication systems, clock dividers are key components used to convert input high-frequency clock signals into lower-frequency output signals to obtain the required frequency, eliminating the need for additional low-frequency clock generation circuits to meet the clock requirements of different systems.

[0003] In existing clock divider circuits, the divider typically uses a counter to implement the frequency division function and adjust the division ratio. The counter counts the input clock signal according to a preset division ratio. When the count reaches the preset value, it outputs a clock pulse and resets the counter to begin the next counting cycle. In practical applications, when the division ratio needs to be suddenly changed to adapt to different operating conditions or system requirements, traditional clock divider circuits remain stuck in the counting state of the previous division ratio when the division ratio is changed. Therefore, the counter cannot immediately adapt to the new division ratio and must restart counting from the initial state. This can lead to counting errors, resulting in inaccurate output clock signal frequencies, which in turn affects system performance and stability.

[0004] To address this issue, several methods have been proposed, such as manually resetting counters and using synchronization mechanisms. However, these methods all have limitations. Manually resetting counters requires additional operations, which not only increases system complexity but can also lead to system crashes due to operational errors in practical applications. While using synchronization mechanisms can address the issue of count errors to a certain extent, they require additional clock signals and control logic, increasing circuit complexity and power consumption.

[0005] Therefore, there is an urgent need for a circuit that can automatically detect changes in the division ratio and reset the counter in time to ensure that the clock divider can accurately and stably output the clock signal frequency required after the division ratio is changed when the division ratio is changed. Summary of the Invention

[0006] The problem to be solved by the present invention is to provide a circuit for automatically detecting changes in the frequency divider division ratio, and use the detected signal to control the counting circuit in the clock division ratio circuit, thereby ensuring that the clock divider outputs the correct clock frequency after the division ratio is changed.

[0007] The present invention adopts the following technical solution: a frequency divider frequency ratio change automatic detection circuit, which is used to connect the frequency divider and detect the change value of the frequency divider frequency ratio in real time, including: a frequency dividing circuit, an inverter, a DFF trigger, an XOR gate operation circuit, and a NOR operation circuit.

[0008] The frequency divider's division ratio port is Bit<n:0> , the inverter, DFF flip-flop and XOR gate operation circuit are correspondingly set to n+1, and a bit signal of each frequency division ratio port is input into an inverter, and the corresponding Bitb node signal is output through the inverter and input into the data node signal port of the corresponding DFF flip-flop;

[0009] The frequency division circuit is connected to the output port CLKOUT of the frequency divider, divides the clock divided by the frequency divider again, and inputs the obtained clock signal into the time node signal port of each DFF trigger, outputs the Q signal and Qn signal through the DFF trigger, and then inputs the Q signal, Qn signal and each Bit signal and Bitb node signal into the corresponding XOR gate operation circuit. After XOR logic calculation, they are input into the NOR operation circuit to obtain the output signal Dt for frequency divider control.

[0010] The input ports of the frequency divider include: the divided high-frequency clock CLK, the frequency division ratio Bit<n:0> , reset signal RST, Bit<n:0> It is represented as an n+1-bit binary; the output port of the frequency divider is CLKOUT, which is used to output the clock after the frequency divider is divided.

[0011] The frequency divider divides the frequency through a counter and uses the high-frequency clock CLK for counting. The frequency division ratio is N, which is calculated as follows:

[0012] N=Bit <n>*2^n+Bit <n-1>*2^(n-1)+……+Bit <0> *2^0

[0013] The divider adjusts the frequency division ratio by Bit<n:0> , so that the output port CLKOUT outputs the corresponding clock division value; when the counter reaches the set division ratio value N, it generates a cycle of CLKOUT clock. After division, the clock frequency output by CLKOUT is the CLK high-frequency clock frequency value divided by N.

[0014] Furthermore, the frequency division circuit includes at least two divide-by-two circuits for dividing the clock CLKOUT output by the frequency divider by two at least twice in a row, so that the divided clock can sample the change in the division ratio to obtain the clock CLK1.

[0015] Furthermore, the clock CLK1 is input to the time node signal port of each DFF trigger as the sampling clock of the DFF trigger. The DFF trigger uses the divided clock CLK1 to sample the value of the frequency division ratio setting of the divider.

[0016] In particular, the sampling delay of the DFF trigger itself is greater than the sampling delay of the high and low level changes of the Bit signal.

[0017] Furthermore, the XOR gate operation circuit performs XOR calculations on the input Q signal and Qn signal, the Bit signal and the Bitb node signal, respectively, and performs XOR calculations again on the obtained results before outputting them.

[0018] When the values ​​of the frequency dividing ratios before and after the frequency divider change, the value obtained by the XOR gate operation circuit is high.

[0019] Furthermore, the NOR operation circuit includes multiple inputs, and the output of each XOR gate operation circuit is connected to the input of one NOR operation circuit, and the multiple inputs are subjected to NOR operation to obtain the output signal Dt of the NOR operation circuit.

[0020] When the detection circuit detects that the frequency division ratio of the frequency divider has changed, the output signal Dt of the NOR operation circuit is used as the reset signal RST of the frequency divider, and the counter is reset to the initial state and counted again to ensure that the count reaches the changed frequency division ratio.

[0021] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0022] 1. The automatic detection circuit for frequency divider frequency division ratio changes of the present invention has a wide operating frequency range and can be applied to frequency dividers with various frequency division ratios. The circuit design is simple, flexible and simple. It is designed by utilizing the time difference before and after the frequency division ratio changes, the acquisition and storage function of the D flip-flop and the logical function characteristics of the exclusive OR gate. It has low power consumption and strong scalability.

[0023] 2. The output signal obtained by the automatic detection circuit of the frequency divider division ratio change of the present invention can be used as a reset signal of the counter, or as other identification signal or logic control signal to perform various related controls of the frequency converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the input and output ports of the frequency divider of the present invention;

[0025] Figure 2 This is a connection block diagram of the frequency divider detection circuit of the present invention;

[0026] Figure 3 This is a schematic diagram of a circuit for automatically detecting changes in frequency division ratios according to the present invention;

[0027] Figure 4 This is the principle diagram of the DFF trigger of the present invention;

[0028] Figure 5 This is a schematic diagram of the XOR gate operation circuit of the present invention;

[0029] Figure 6 This is a schematic diagram of the bit level change principle of the detection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the application are further elaborated in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments of other researchers in this field on this embodiment fall within the scope of protection of the present invention. At the same time, the step numbers in the embodiments of the present invention are only set for the convenience of explanation and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0031] The frequency divider circuit is a widely used circuit, especially in high-frequency clock generator circuits. If the clock is too high and a low-frequency clock is needed later, the frequency divider can be used to achieve this without the need for an additional low-frequency clock generation circuit.

[0032] The schematic diagram of the frequency divider is as follows Figure 1 As shown, there are three input ports, namely CLK, Bit <n:0>, RST, where the CLK port is the divided clock, which is a high-frequency clock, Bit <n:0>The frequency divider output port is CLKOUT, which outputs the divided clock. The frequency divider adjusts the frequency divider ratio Bit through the interface controller.<n:0> , so that the CLKOUT terminal outputs the corresponding clock division value.

[0033] In current frequency divider circuits, the frequency division function is generally implemented using a counter, that is, using the CLK high-frequency clock for counting. When the count reaches the set frequency division ratio, a cycle of the CLKOUT clock is generated.

[0034] The frequency division ratio is N, and the binary form of N is Bit <n:0>The divided clock frequency is the CLK high-frequency clock frequency value divided by N.

[0035] N=Bit <n>*2^n+Bit <n-1>*2^(n-1)+……+Bit <0> *2^0

[0036] Since the frequency division value is obtained by counting the counter when the frequency division ratio N is changed, the counter is still counting based on the previous frequency division ratio when the frequency division ratio is changed. As a result, after the new frequency division ratio is set, it cannot respond in time and finally outputs the wrong clock frequency division value. At this time, a frequency division ratio change detection circuit is required, such as Figure 2 As shown in the figure, the change in the division ratio is detected in real time by a detection circuit. When there is a change, the detection circuit resets the counter in the clock divider with the detected value, causing the counter to restart counting until it reaches the changed division ratio value, completing a full counting cycle. At this point, the frequency output by the divider is guaranteed to be the correct divided clock.

[0037] In one embodiment of the present invention, a frequency divider division ratio change automatic detection circuit is proposed, which is connected to a 4-bit frequency divider and detects the change of the frequency divider division ratio in real time, such as Figure 3 As shown, it includes: a divide-by-two frequency circuit, an inverter, a DFF trigger, an XOR gate operation circuit, and a NOR operation circuit.

[0038] Specifically, in Figure 3 In the circuit, Bit<3:0> represents 4 bits, which are written as Bit <3> ,Bit <2> ,Bit <1> ,Bit <0> , CLKOUT is the clock signal after the divider, so the CLKOUT signal is a clock that always exists. X1 and X2 are two-way frequency divider circuits. The clock CLKOUT after the divider is divided by two twice, that is, the clock signal CLK1 is obtained by four-way frequency divider. CLK1 is connected to the clock node signal terminal CK of X7, X8, X9, and X10 respectively, as the sampling clock of the DFF trigger, and the frequency division ratio Bit is respectively<n:0> Take samples.

[0039] The 4 bits of Bit<3:0> are input to inverters X3, X4, X5, and X6 for signal inversion. <3> The node signal after passing through inverter X3 is Bitb <3> , similarly Bit <2> The corresponding node signal is Bitb <2> 、Bit <1> The corresponding node signal is Bitb <1> 、Bit <0> The corresponding node signal is Bitb <0> The corresponding node signal Bitb is output through the inverter and input to the data node signal terminal D of the corresponding DFF trigger.

[0040] The DFF trigger structure is as follows Figure 4 As shown, the input is the clock node signal terminal CK and the data node signal terminal D. In the sampling phase, when the rising edge or falling edge of the clock signal CK arrives, the DFF trigger samples the data at the data input terminal D. In the holding phase, the DFF trigger stores the sampled data inside it until the next clock signal arrives, and finally outputs the Q signal and Qn signal.

[0041] Furthermore, the Q signal and Qn signal as well as each Bit signal and Bitb node signal are input to the corresponding XOR gate operation circuits X11, X12, X13, and X14. The XOR gate circuit structure is as follows: Figure 5 As shown, in the XOR gate circuit, the input Q signal and Qn signal, Bit signal and Bitb node signal are XORed respectively, and the results are further XORed to obtain the output signal D corresponding to each bit. <n> ，D <n-1>...D <0> .

[0042] Furthermore, the output signal D of the XOR gate operation circuit is <n> ，D <n-1>...D <0> , input to the four-input NOR operation circuit to obtain the output signal Dt, and the divider is controlled based on Dt.

[0043] Since the CLK1 clock is very low, for the DFF trigger corresponding to the xth bit, the value Q sampled at a certain moment will always be <x>With Bit <x>The value of is different (x is any value from 0 to n). <x>、Qn <x>、Bit <x>、Bitb <x>Perform XOR, as long as the frequency division ratio changes, the XOR value D <x>(x is any value from 0 to n) is high level 1, and the signal D is processed by the NOR operation circuit. <n> ，D <n-1>...D <0> After performing OR NOT, the obtained logic level Dt changes to low level 0, and the signal Dt is transmitted to the RST reset terminal of the counter in the divider for reset, so that the counter returns to the initial state and counts again to ensure the accuracy of the count. The clock frequency is divided into the clock frequency after the division ratio changes.

[0044] Specifically, the principle of automatic detection of the change of the frequency division ratio is as follows: Assume that there is a Bit in the 4 bits Bit<3:0> of this embodiment. <3> A level change occurs, such as Figure 6 As shown, the circuit changes from a low level 0 to a high level 1. Since the circuit in this embodiment is not an ideal circuit, there is a time delay Δt.

[0045] At this time Figure 3 In the X7 DFF trigger, Bit <3> Continuously sampling, due to the delay ratio of DFF itself Figure 6 The delay is large, Δt is generally a maximum of about 100 ps, ​​but the delay of the DFF trigger itself is several nS or even larger, so there is a time t1 when the CLK1 clock can sample the Bit <3> It is low level 0, and the output Q <3> is 0, after Δt, Bit <3> Changes to high level 1. At this moment (as long as the time change does not exceed the delay time of the DFF trigger itself), Bit <3> is 1, Bitb <3> is 0, Q <3> Still 0, Qn <3> If the four input signals are 1, then the logic operation of X11 XOR gate makes D <3> It is high level 1, X15 is a four-input NOR circuit. As long as one of the signals in the four-input NOR circuit is high level, the output Dt will change from high level to low level. The low level signal can be used as the Rst reset signal of the counter circuit in the divider, resetting the counter to its initial state, or giving it to other logic circuits for operation, etc.

[0046] Similarly, if one bit in Bit<2:0> changes, the same circuit principle applies, and Dt eventually changes from a high level to a low level.

[0047] It should be noted that the present invention is not limited to the number of bits described in the embodiment but can be extended to other or even larger numbers of bits, thus demonstrating its strong scalability. Furthermore, the output signal Dt obtained by the detection circuit of the present invention can be used as a reset signal for a counter, as an identification signal, or as a logic control signal for other control functions of the frequency divider.

[0048] Other controls include: 1. Used for identification signals to show that the division ratio has indeed changed; 2. Used for logic control signals. If the division ratio changes due to external interference, which is an abnormal situation, the Dt signal can be used to reset the divider circuit or other control circuit for abnormal detection or control.

[0049] In summary, the automatic detection circuit for changes in the frequency divider division ratio of the present invention detects changes in the frequency divider division ratio in real time and uses the detected signal to control the counting circuit in the clock division ratio circuit, thereby ensuring that after the division ratio is changed, the frequency of the clock after division is the correct clock frequency.

[0050] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention. < / n> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / n> < / n> < / n> < / n>

Claims

1. A frequency divider division ratio change automatic detection circuit, used for connecting to a frequency divider and detecting the change value of the frequency divider division ratio in real time, characterized in that: include: Frequency division circuit, inverter, DFF trigger, XOR gate operation circuit, NOR operation circuit; The frequency divider's division ratio port is Bit<n:0> , the inverter, DFF flip-flop and XOR gate operation circuit are correspondingly set to n+1, and a bit signal of each frequency division ratio port is input into an inverter, and the corresponding Bitb node signal is output through the inverter and input into the data node signal port of the corresponding DFF flip-flop; The frequency division circuit is connected to the output port CLKOUT of the frequency divider, divides the clock divided by the frequency divider again, and inputs the obtained clock signal to the time node signal port of each DFF trigger, outputs the Q signal and Qn signal through the DFF trigger, and then inputs the Q signal, Qn signal and each Bit signal and Bitb node signal into the corresponding XOR gate operation circuit, and after XOR logic calculation, inputs the NOR operation circuit to obtain the output signal Dt for controlling the frequency divider; The frequency division circuit includes at least two divide-by-two circuits for dividing the clock CLKOUT output by the frequency divider by two at least twice in a row to obtain the clock CLK1, so that the divided clock CLK1 can sample the change value of the division ratio.

2. The automatic detection circuit for frequency divider frequency division ratio change according to claim 1, characterized in that: The frequency divider, the input port includes: the divided high-frequency clock CLK, the frequency division ratio Bit<n:0> , reset signal RST, Bit<n:0> It is represented as an n+1-bit binary; the output port is CLKOUT, which is used to output the clock divided by the frequency divider; the frequency divider divides the frequency through a counter and uses the high-frequency clock CLK for counting.

3. The automatic detection circuit for frequency divider frequency division ratio change according to claim 1, characterized in that: The clock CLK1 is input to the time node signal port of each DFF trigger as the sampling clock of the DFF trigger. The DFF trigger uses the divided clock CLK1 to sample the value set by the front and back frequency division ratios of the frequency divider.

4. The automatic detection circuit for frequency divider frequency division ratio change according to claim 3, characterized in that: The sampling delay of the DFF trigger itself is greater than the sampling delay of the high and low level changes of the Bit signal.

5. The automatic detection circuit for frequency divider frequency division ratio change according to claim 1, characterized in that: The XOR gate operation circuit performs XOR calculations on the input Q signal and Qn signal, the Bit signal and the Bitb node signal respectively, and performs XOR calculations on the obtained results again before outputting them.

6. The automatic detection circuit for frequency divider frequency division ratio change according to claim 5, characterized in that: When the values ​​of the frequency dividing ratios before and after the frequency divider change, the value output by the XOR gate operation circuit is high.

7. The automatic detection circuit for frequency divider frequency division ratio change according to claim 1, characterized in that: The NOR operation circuit includes multiple inputs, and the output of each XOR gate operation circuit is connected to the input of one NOR operation circuit. The multiple inputs are subjected to NOR operation to obtain the output signal Dt of the NOR operation circuit.

8. The automatic detection circuit for frequency divider frequency division ratio change according to claim 7, characterized in that: When the detection circuit detects that the frequency division ratio of the frequency divider has changed, the output signal Dt of the NOR operation circuit is used as the reset signal RST of the frequency divider, and the counter is reset to the initial state and counted again to ensure that the count reaches the changed frequency division ratio.

9. The automatic detection circuit for frequency divider frequency division ratio change according to claim 1, wherein: The output signal Dt of the NOR operation circuit is also used as an identification signal or a logic control signal to control the frequency divider.

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