Signal processing circuit and signal processing method

Abstract

The invention discloses a signal processing circuit and a signal processing method. The circuit comprises an input module, an interpolation filter and a processing module, and the interpolation filter comprises a first filter and a second filter which are parallel to each other; wherein the input module is used for inputting a sequence to be processed; the first filter stores the odd number coefficient of the interpolation filter and is used for performing interpolation filtering processing on the sequence to be processed based on the odd number coefficient of the interpolation filter to obtain a processed odd number sequence; the second filter stores the even coefficient of the interpolation filter and is used for performing interpolation filtering processing on the sequence to be processed based on the even coefficient of the interpolation filter to obtain a processed even sequence; and the processing module is used for obtaining a first digital pre-distortion signal based on the processed odd sequence and the processed even sequence.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a signal processing circuit and a signal processing method. Background Art

[0002] At present, due to the nonlinear characteristics of the power amplifier (PA), the spectrum of the transmitted signal will be regenerated. When a lower sampling rate is used for digital pre-distortion (DPD) model training, aliasing distortion will be generated, resulting in reduced linearity of the PA. Therefore, in order to eliminate the influence of distortion, in related technologies, the bandwidth of DPD training is generally 5 times that of the effective signal. When facing the large bandwidth and high-speed scenarios of 5G and future 6G, the sampling rate requirements will be higher, and the requirements for the clock frequency of the digital circuit and the digital-to-analog conversion and analog-to-digital conversion are also relatively high. Therefore, it is urgent to provide a new digital pre-distortion processing solution. Summary of the invention

[0003] In view of this, embodiments of the present application hope to provide a signal processing circuit and a signal processing method.

[0004] The technical solution of the embodiment of the present application is implemented as follows:

[0005] The embodiment of the present application provides a signal processing circuit, the circuit comprising: an input module, an interpolation filter, and a processing module, the interpolation filter comprising two parallel first filters and a second filter; wherein,

[0006] The input module is used to input the sequence to be processed;

[0007] The first filter stores the odd coefficients of the interpolation filter, and is used to perform interpolation filtering processing on the sequence to be processed based on the odd coefficients of the interpolation filter to obtain a processed odd sequence;

[0008] The second filter stores the even coefficients of the interpolation filter, and is used to perform interpolation filtering processing on the sequence to be processed based on the even coefficients of the interpolation filter to obtain a processed even sequence;

[0009] The processing module is used to obtain a first digital predistortion signal based on the processed odd sequence and the processed even sequence.

[0010] In addition, according to at least one embodiment of the present application, the processing module includes:

[0011] A first digital pre-distortion processing module, configured to perform digital pre-distortion processing on the processed odd-numbered sequence using a plurality of first lookup tables to obtain a first digital pre-distortion result;

[0012] A second digital pre-distortion processing module, configured to perform digital pre-distortion processing on the processed even-numbered sequence using a plurality of second lookup tables to obtain a second digital pre-distortion result;

[0013] A third digital pre-distortion processing module, configured to perform digital pre-distortion processing on the processed odd-numbered sequence and the processed even-numbered sequence using a plurality of third lookup tables to obtain a third digital pre-distortion result;

[0014] a fourth digital predistortion processing module, configured to perform digital predistortion processing on the processed odd-numbered sequence and the processed even-numbered sequence using a plurality of fourth lookup tables to obtain a fourth digital predistortion result;

[0015] The summing module is used to sum the first digital pre-distortion result, the second digital pre-distortion result, the third digital pre-distortion result and the fourth digital pre-distortion result to obtain the first digital pre-distortion signal.

[0016] In addition, according to at least one embodiment of the present application, the expression of the first lookup table is:

[0017] LUT(|x(nq)|);

[0018] in,

[0019] |x(nq)| represents the absolute value of the sequence input at time nq; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple first lookup tables increases in odd numbers starting from 1;

[0020] The expression of the second lookup table is:

[0021] LUT(|x(nq)|);

[0022] in,

[0023] |x(nq)| represents the absolute value of the sequence input at time nq; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the plurality of second lookup tables increases in even numbers starting from 0;

[0024] The expression of the third lookup table is:

[0025] LUT(|x(nq±m)|);

[0026] Wherein, |x(nq±m)| represents the absolute value of the sequence input at time nq±m; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple third lookup tables is incremented by an integer starting from 0, and for each q, the corresponding q+m combination or qm combination is searched through a preset combination list, and m is an integer increasing from 1; when q is an odd number, the q+m combination or qm combination corresponding to the third lookup table is an odd number, and when q is an even number, the q+m combination or qm combination corresponding to the third lookup table is an even number;

[0027] The expression of the fourth lookup table is:

[0028] LUT(|x(nq±m)|);

[0029] Among them, |x(nq±m)| represents the absolute value of the sequence input at time nq±m; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple fourth lookup tables is incremented by integers starting from 0, and for each q, the corresponding q+m combination or qm combination is searched through the preset combination list, and m is an integer increasing from 1; when q is an odd number, the q+m combination or qm combination corresponding to the fourth lookup table is an even number, and when q is an even number, the q+m combination or qm combination corresponding to the fourth lookup table is an odd number.

[0030] In addition, according to at least one embodiment of the present application, the first digital predistortion processing module is specifically used to:

[0031] Determine a plurality of first search results using the plurality of first search tables;

[0032] Multiplying the plurality of first search results by corresponding elements in the processed odd-numbered sequence to obtain a plurality of first multiplication results;

[0033] The multiple first multiplication results are added to obtain the first digital pre-distortion result.

[0034] In addition, according to at least one embodiment of the present application, the second digital predistortion processing module is specifically used to:

[0035] Determine a plurality of second search results using the plurality of second search tables;

[0036] Multiplying the plurality of second search results by corresponding elements in the processed even-numbered sequence to obtain a plurality of second multiplication results;

[0037] The multiple second multiplication results are added to obtain the second digital predistortion result.

[0038] In addition, according to at least one embodiment of the present application, the third digital predistortion processing module is specifically used to:

[0039] Determine a plurality of third search results using the plurality of third search tables;

[0040] multiplying the plurality of third search results with corresponding elements in the processed odd number sequence and the processed even number sequence to obtain a plurality of third multiplication results;

[0041] The multiple third multiplication results are added to obtain the third digital pre-distortion result.

[0042] In addition, according to at least one embodiment of the present application, the fourth digital predistortion processing module is specifically configured to:

[0043] Determine a plurality of fourth search results using the plurality of fourth search tables;

[0044] multiplying the plurality of fourth search results with corresponding elements in the processed odd number sequence and the processed even number sequence to obtain a plurality of fourth multiplication results;

[0045] The multiple fourth multiplication results are added to obtain the fourth digital pre-distortion result.

[0046] In addition, according to at least one embodiment of the present application, the circuit further includes a first switch;

[0047] The first switch is used to disconnect the input module and the second filter to input the sequence to be processed into the processing module.

[0048] In addition, according to at least one embodiment of the present application, the second digital predistortion processing module is further configured to perform digital predistortion processing on the sequence to be processed using the multiple second lookup tables to obtain a fifth digital predistortion result;

[0049] The third digital pre-distortion processing module is further used to perform digital pre-distortion processing on the sequence to be processed by using the multiple third lookup tables to obtain a sixth digital pre-distortion result;

[0050] The fourth digital pre-distortion processing module is further used to perform digital pre-distortion processing on the sequence to be processed by using the multiple fourth lookup tables to obtain a seventh digital pre-distortion result;

[0051] The summing module is further configured to sum the fifth digital pre-distortion result, the sixth digital pre-distortion result, and the seventh digital pre-distortion result to obtain a second digital pre-distortion signal.

[0052] The embodiment of the present application further provides a signal processing method, which is applied to a signal processing circuit, wherein the circuit includes an input module, an interpolation filter, and a processing module, wherein the interpolation filter includes two parallel first filters and a second filter, wherein the first filter stores odd coefficients of the interpolation filter, and the second filter stores even coefficients of the interpolation filter, and the method includes:

[0053] Get the input sequence to be processed;

[0054] Based on the odd coefficients of the interpolation filter, the sequence to be processed is subjected to interpolation filtering processing to obtain a processed odd sequence;

[0055] Based on the even coefficients of the interpolation filter, the sequence to be processed is subjected to interpolation filtering processing to obtain a processed even sequence;

[0056] A first digital predistortion signal is obtained based on the processed odd sequence and the processed even sequence.

[0057] The signal processing circuit and signal processing method provided by the embodiments of the present application include: an input module, an interpolation filter, and a processing module, wherein the interpolation filter includes two parallel first filters and a second filter; wherein the input module is used to input a sequence to be processed; the first filter stores the odd coefficients of the interpolation filter, and is used to perform interpolation filtering processing on the sequence to be processed based on the odd coefficients of the interpolation filter to obtain a processed odd sequence; the second filter stores the even coefficients of the interpolation filter, and is used to perform interpolation filtering processing on the sequence to be processed based on the even coefficients of the interpolation filter to obtain a processed even sequence; the processing module is used to obtain a first digital predistortion signal based on the processed odd sequence and the processed even sequence.

[0058] By adopting the technical solution provided in the embodiment of the present application, a flexible and configurable digital pre-distortion hardware is proposed based on a multi-phase architecture to implement digital pre-distortion processing, complete the low-speed clock to achieve high-speed signal parallel processing, and the sampling rate is relatively low, so the clock frequency of the digital circuit and the digital-to-analog conversion and analog-to-digital conversion requirements are low, and the additional hardware design difficulty of the clock network and the digital-to-analog conversion or analog-to-digital conversion will not be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 This is a schematic diagram of the circuit structure of DPD in the related art Figure 1 ;

[0060] Figure 2 It is a schematic diagram of the circuit structure for implementing DPD based on a lookup table in the related art;

[0061] Figure 3 This is a schematic diagram of the circuit structure of DPD in the related art Figure 2 ;

[0062] Figure 4 It is a schematic diagram of the structure of the signal processing circuit of the embodiment of the present application;

[0063] Figure 5 The specific structure of the signal processing circuit in the embodiment of the present application is shown in FIG. Figure 1 ;

[0064] Figure 6 The specific structure of the signal processing circuit in the embodiment of the present application is shown in FIG. Figure 2 ;

[0065] Figure 7 is a schematic diagram of a first lookup table in an embodiment of the present application;

[0066] Figure 8 is a schematic diagram of a second lookup table in an embodiment of the present application;

[0067] Fig. 9 is a schematic diagram of the third lookup table and the fourth lookup table of the embodiment of the present application;

[0068] Fig.10 is a schematic diagram of obtaining a first digital predistortion signal according to an embodiment of the present application;

[0069] Fig.11 It is a schematic diagram of the implementation flow of the signal processing method of the embodiment of the present application. DETAILED DESCRIPTION

[0070] Before introducing the technical solutions of the embodiments of the present application, the related technologies are first introduced.

[0071] See also Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of DPD in related technologies. Since the nonlinear characteristics of the power amplifier (PA) will cause the spectrum regeneration of the transmitted signal, when a lower sampling rate is used for DPD model training, aliasing distortion will be generated, resulting in reduced linearity of the PA. Therefore, in order to eliminate the influence of distortion, in related technologies, the bandwidth of DPD training is generally 5 times that of the effective signal.

[0072] See also Figure 2 , Figure 2 Schematic diagram of the circuit structure for implementing DPD based on a lookup table in the related art. Figure 2 As shown, after the extraction of the DPD parameter model is completed, a lookup table solution is generally used in hardware implementation. The DPD model uses M parallel lookup tables (LUTs) to simulate the nonlinearity of the PA. The DPD model is expressed as formula (1), as follows:

[0073]

[0074] Wherein, x(n) represents the output signal of the predistortion (PD) at time n; u(n-m+1) represents the input signal of the predistortion (PD) at time n-m+1; |u(n-m+1)| represents the absolute value of the input signal of the predistortion (PD) at time n-m+1; w ij Represents the memory polynomial coefficient; m represents the memory depth, ranging from 1 to M, where M is an integer greater than 1; i represents the nonlinear order, ranging from 0 to N-1, where N is an integer greater than 1.

[0075] See also Figure 3 , Figure 3 It is a schematic diagram of the circuit composition structure of DPD in the related technology, such as Figure 3 As shown, it includes an upsampling module and a DPD module. The upsampling module is used to perform upsampling processing on the input sequence to be processed Tx to obtain a processed sequence, wherein the sampling frequency after the upsampling processing (expressed by Fs) is different from the sampling frequency before the upsampling processing (expressed by Fs / 2); the DPD module is used to perform digital predistortion processing on the processed sequence to obtain a digital predistortion signal.

[0076] In summary, the bandwidth of DPD training in traditional technical solutions is generally 5 times that of the effective signal. However, when facing the large-bandwidth and high-speed scenarios of 5G and future 6G, the sampling rate requirements will be higher, which will place higher requirements on the clock frequency of the digital circuit and the digital-to-analog conversion (DA) / analog-to-digital conversion (AD), and increase the design difficulty of the transmitter and observation path.

[0077] Based on this, in order to solve the requirement of traditional DPD solutions for large bandwidth rates for model training, in an embodiment of the present application, a flexible and configurable digital pre-distortion hardware is proposed based on a multi-phase architecture to realize digital pre-distortion processing, so as to complete the low-speed clock to realize high-speed signal parallel processing, and can flexibly configure the use of the lookup table (LUT) according to the changes in the existing network usage scenarios. At the same time, in order to simplify the design of the clock network in the link, the upsampling process of the interpolation filter also uses a multi-phase architecture to further optimize the design of the digital circuit.

[0078] See also Figure 4 , Figure 4 is a schematic diagram of the structure of the signal processing circuit of the embodiment of the present application, such as Figure 4As shown, the signal processing circuit includes: an input module 41, an interpolation filter 42, and a processing module 43, wherein the interpolation filter includes two parallel first filters 421 and second filters 422; wherein,

[0079] The input module 41 is used to input a sequence to be processed;

[0080] The first filter 421 stores the odd coefficients of the interpolation filter, and is used to perform interpolation filtering processing on the sequence to be processed based on the odd coefficients of the interpolation filter to obtain a processed odd sequence;

[0081] The second filter 422 stores the even coefficients of the interpolation filter, and is used to perform interpolation filtering processing on the sequence to be processed based on the even coefficients of the interpolation filter to obtain a processed even sequence;

[0082] The processing module 43 is configured to obtain a first digital predistortion signal based on the processed odd sequence and the processed even sequence.

[0083] Here, in order to meet the signal processing rate requirements of broadband scenarios and not increase the complexity of the clock network design in the link, the design of the interpolation filter twice resampling can adopt a multi-phase architecture design to ensure that the rate of the odd and even phases after interpolation is still the sampling frequency before interpolation.

[0084] In one embodiment, the processing module 43 includes:

[0085] A first digital pre-distortion processing module, configured to perform digital pre-distortion processing on the processed odd-numbered sequence using a plurality of first lookup tables to obtain a first digital pre-distortion result;

[0086] A second digital pre-distortion processing module, configured to perform digital pre-distortion processing on the processed even-numbered sequence using a plurality of second lookup tables to obtain a second digital pre-distortion result;

[0087] A third digital pre-distortion processing module, configured to perform digital pre-distortion processing on the processed odd-numbered sequence and the processed even-numbered sequence using a plurality of third lookup tables to obtain a third digital pre-distortion result;

[0088] a fourth digital predistortion processing module, configured to perform digital predistortion processing on the processed odd-numbered sequence and the processed even-numbered sequence using a plurality of fourth lookup tables to obtain a fourth digital predistortion result;

[0089] The summing module is used to sum the first digital pre-distortion result, the second digital pre-distortion result, the third digital pre-distortion result and the fourth digital pre-distortion result to obtain the first digital pre-distortion signal.

[0090] In one embodiment, the expression of the first lookup table is:

[0091] LUT(|x(nq)|);

[0092] in,

[0093] |x(nq)| represents the absolute value of the sequence input at time nq; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple first lookup tables increases in odd numbers starting from 1;

[0094] The expression of the second lookup table is:

[0095] LUT(|x(nq)|);

[0096] in,

[0097] |x(nq)| represents the absolute value of the sequence input at time nq; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the plurality of second lookup tables increases in even numbers starting from 0;

[0098] The expression of the third lookup table is:

[0099] LUT(|x(nq±m)|);

[0100] in,

[0101] |x(nq±m)| represents the absolute value of the sequence input at time nq±m; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple third lookup tables is incremented by integers starting from 0, and for each q, the corresponding q+m combination or qm combination is searched through a preset combination list, where m is an integer incremented starting from 1; when q is an odd number, the q+m combination or qm combination corresponding to the third lookup table is an odd number, and when q is an even number, the q+m combination or qm combination corresponding to the third lookup table is an even number;

[0102] The expression of the fourth lookup table is:

[0103] LUT(|x(nq±m)|);

[0104] in,

[0105] |x(nq±m)| represents the absolute value of the sequence input at time nq±m; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple fourth lookup tables is incremented by integers starting from 0, and for each q, the corresponding q+m combination or qm combination is searched through the preset combination list, m is an integer increasing from 1; when q is an odd number, the q+m combination or qm combination corresponding to the fourth lookup table is an even number, and when q is an even number, the q+m combination or qm combination corresponding to the fourth lookup table is an odd number.

[0106] In one embodiment, the first digital predistortion processing module is specifically configured to:

[0107] Determine a plurality of first search results using the plurality of first search tables;

[0108] Multiplying the plurality of first search results by corresponding elements in the processed odd-numbered sequence to obtain a plurality of first multiplication results;

[0109] The multiple first multiplication results are added to obtain the first digital pre-distortion result.

[0110] Specifically, absolute value processing is performed on each data element in the processed odd sequence to obtain the absolute value of the sequence; multiple first lookup tables are searched using the absolute value of the processed odd sequence to obtain corresponding multiple first search results; the multiple first search results are multiplied by corresponding elements in the processed odd sequence to obtain multiple first multiplication results, and the multiple first multiplication results are added to obtain the first digital pre-distortion result.

[0111] In one embodiment, the second digital predistortion processing module is specifically used to:

[0112] Determine a plurality of second search results using the plurality of second search tables;

[0113] Multiplying the plurality of second search results by corresponding elements in the processed even-numbered sequence to obtain a plurality of second multiplication results;

[0114] The multiple second multiplication results are added to obtain the second digital predistortion result.

[0115] Specifically, absolute value processing is performed on each data element in the processed even sequence to obtain the absolute value of the sequence; multiple second lookup tables are searched using the absolute value of the processed even sequence to obtain multiple corresponding second lookup results; the multiple second lookup results are multiplied by corresponding elements in the processed even sequence to obtain multiple second multiplication results, and the multiple second multiplication results are added to obtain the second digital pre-distortion result.

[0116] In one embodiment, the third digital predistortion processing module is specifically used to:

[0117] Determine a plurality of third search results using the plurality of third search tables;

[0118] multiplying the plurality of third search results with corresponding elements in the processed odd number sequence and the processed even number sequence to obtain a plurality of third multiplication results;

[0119] The multiple third multiplication results are added to obtain the third digital pre-distortion result.

[0120] Specifically, absolute value processing is performed on each data element in the processed even sequence to obtain the absolute value of the sequence; absolute value processing is performed on each data element in the processed odd sequence to obtain the absolute value of the sequence; the absolute value of the processed odd sequence and the absolute value of the processed even sequence are used to search multiple third lookup tables to obtain corresponding multiple third search results, the multiple third search results are multiplied with corresponding elements in the processed odd sequence and the processed even sequence to obtain multiple third multiplication results, and the multiple third multiplication results are added to obtain the third digital pre-distortion result.

[0121] In one embodiment, the fourth digital predistortion processing module is specifically used to:

[0122] Determine a plurality of fourth search results using the plurality of fourth search tables;

[0123] multiplying the plurality of fourth search results with corresponding elements in the processed odd number sequence and the processed even number sequence to obtain a plurality of fourth multiplication results;

[0124] The multiple fourth multiplication results are added to obtain the fourth digital pre-distortion result.

[0125] Specifically, absolute value processing is performed on each data element in the processed even sequence to obtain the absolute value of the sequence; absolute value processing is performed on each data element in the processed odd sequence to obtain the absolute value of the sequence; the absolute value of the processed odd sequence and the absolute value of the processed even sequence are used to search multiple fourth lookup tables to obtain corresponding multiple fourth lookup results; the multiple fourth lookup results are multiplied with corresponding elements in the processed odd sequence and the processed even sequence to obtain multiple fourth multiplication results, and the multiple fourth multiplication results are added to obtain the fourth digital pre-distortion result.

[0126] In actual applications, in narrowband scenarios, digital predistortion (DPD) does not have high requirements for signal processing bandwidth, and single-channel hardware resource processing can fully match the pre-calibrated performance. Therefore, in actual applications, it is no longer necessary to upsample in the DPD hardware module. Therefore, a first switch can be added to bypass one of the interpolation filters, such as the second filter.

[0127] Based on this, in one embodiment, the circuit further includes a first switch;

[0128] The first switch is used to disconnect the input module and the second filter to input the sequence to be processed into the processing module.

[0129] That is, one of the interpolation filters, for example, the second filter, may be bypassed by adding a first switch.

[0130] In one embodiment, the second digital predistortion processing module is further used to perform digital predistortion processing on the sequence to be processed using the multiple second lookup tables to obtain a fifth digital predistortion result;

[0131] The third digital pre-distortion processing module is further used to perform digital pre-distortion processing on the sequence to be processed by using the multiple third lookup tables to obtain a sixth digital pre-distortion result;

[0132] The fourth digital pre-distortion processing module is further used to perform digital pre-distortion processing on the sequence to be processed by using the multiple fourth lookup tables to obtain a seventh digital pre-distortion result;

[0133] The summing module is further configured to sum the fifth digital pre-distortion result, the sixth digital pre-distortion result, and the seventh digital pre-distortion result to obtain a second digital pre-distortion signal.

[0134] In the embodiment of the present application, the following advantages are possessed:

[0135] (1) Based on the multi-phase architecture, a flexible and configurable digital pre-distortion hardware is proposed to implement digital pre-distortion processing, which completes the parallel processing of high-speed signals with a low-speed clock. The sampling rate is relatively low, which does not increase the difficulty of additional hardware design of the clock network or AD / DA.

[0136] At the same time, in order to simplify the design of the clock network in the link, the upsampling process of the interpolation filter also uses a multi-phase architecture, further optimizing the design of the digital circuit.

[0137] (2) The use of the lookup table (LUT) can be flexibly configured according to the changes in the existing network usage scenarios, such as broadband scenarios and narrowband scenarios, to complete the pre-distortion correction of single-phase or multi-phase DPD.

[0138] See also Figure 5 , Figure 5 is a schematic diagram of the specific structure of the signal processing circuit of the embodiment of the present application, such as Figure 5 As shown, the signal processing circuit includes: an input module, a filter FIR_1, a filter FIR_2, an absolute value module 1, an absolute value module 2, a multiplication module 1, a multiplication module 2, a multiplication module 3, a multiplication module 4, an addition module 1, an addition module 2, an addition module 3, a predistortion module 1 (PD1), a predistortion module 2 (PD2), and a predistortion module 3 (PD3);

[0139] in,

[0140] The input module corresponds to the above-mentioned input module 41;

[0141] The filter FIR_1 and the filter FIR_2 constitute the above interpolation filter 42, and the interpolation filter 42 includes two parallel first filters 421 and second filters 422; the filter FIR_2 corresponds to the first filter 421; the filter FIR_1 corresponds to the second filter 422;

[0142] Absolute value module 1, absolute value module 2, multiplication module 1, multiplication module 2, multiplication module 3, multiplication module 4, addition module 1, addition module 2, addition module 3, pre-distortion module 1 (PD1), pre-distortion module 2 (PD2), and pre-distortion module 3 (PD3) constitute the above-mentioned processing module 43.

[0143] The working principle of the signal processing circuit is described below.

[0144] The input module is used to input a sequence to be processed, where the sequence to be processed is represented by Tx.

[0145] The filter FIR_2 stores the odd coefficients of the interpolation filter and is used to perform interpolation filtering processing on the sequence to be processed based on the odd coefficients of the interpolation filter to obtain a processed odd sequence.

[0146] The filter FIR_1 stores the even coefficients of the interpolation filter and is used to perform interpolation filtering processing on the sequence to be processed based on the even coefficients of the interpolation filter to obtain a processed even sequence.

[0147] It should be noted that in order to meet the signal processing rate requirements of broadband scenarios and not increase the complexity of the clock network design in the link, the design of the double resampling of the interpolation filter can adopt a multi-phase architecture design to ensure that the rate of the odd and even phases after interpolation is still the sampling frequency before interpolation (expressed as Fs / 2), wherein the filter FIR_1 stores the even coefficients in the interpolation filter (which can also be described as the even tap coefficients), and the filter FIR_2 stores the odd coefficients in the interpolation filter (which can also be described as the odd tap coefficients), and the filter FIR_1 performs interpolation filtering on the processing sequence Tx based on the even coefficients of the interpolation filter to obtain the processed even sequence, expressed as s1(n); the filter FIR_2 performs interpolation filtering on the processing sequence Tx based on the odd coefficients of the interpolation filter to obtain the processed odd sequence, expressed as s2(n), wherein s1(n) and s2(n) constitute the signal to be digitally predistorted at a high rate.

[0148] It should be noted that the pre-distortion module 1 (PD1), the pre-distortion module 2 (PD2), and the pre-distortion module 3 (PD3) are memory resource blocks opened up in hardware and are used to store N lookup tables (LUTs), where N is an integer greater than 1.

[0149] Here, the digital pre-distortion (DPD) model is expressed as formula (2) using the general memory polynomial (GMP) model, as follows:

[0150]

[0151] Wherein, z(n) represents the output signal of the predistortion (PD) at time n; x(nq) represents the input signal of the predistortion (PD) at time nq; |x(nq)| represents the absolute value of the input signal of the predistortion (PD) at time nq; |x(nqm)| represents the absolute value of the input signal of the predistortion (PD) at time nqm; a kq Represents the memory polynomial coefficient; b kqm represents the cross-term coefficient; k represents the nonlinear order, where for the memory polynomial part, the value range of k is 0 to K-1, K is an integer greater than 2, and for the cross-term part, the value range of k is 1 to K b , K bis an integer greater than 1; q represents the memory depth, where the value range of q is 0 to Q-1 for the memory depth in the memory polynomial, and Q is an integer greater than 2, where the value range of q is 0 to q for the memory depth in the cross term. b -1,q b is an integer greater than 1; m represents the degree of crossover in the cross term, and the value range of m is 1 to M b , M b is an integer greater than 1.

[0152] Here, the digital pre-distortion (DPD) is expressed in the form of a lookup table as formula (3), formula (4), formula (5), and formula (6), which are as follows:

[0153] z(n)=z1+z2+z3 (3)

[0154]

[0155] Wherein, z(n) represents the output signal of the predistortion (PD) at time n; x(nq) represents the input signal of the predistortion (PD) at time nq; |x(nq)| represents the absolute value of the input signal of the predistortion (PD) at time nq; |x(nqm)| represents the absolute value of the input signal of the predistortion (PD) at time nqm; |x(n-q+m)| represents the absolute value of the input signal of the predistortion (PD) at time n-q+m; q represents the memory depth, wherein the memory depth in formula (4) ranges from 0 to Q-1, Q is an integer greater than 2, and the memory depth in formula (5) and formula (6) ranges from 0 to q b -1,q b is an integer greater than 1; m represents the crossover degree, where the crossover degree in formula (5) and formula (6) ranges from 1 to M b , M b is an integer greater than 1.

[0156] From formula (3), formula (4), formula (5), and formula (6), we can see that the number of lookup tables N = Q + 2 × q b ×Mb, where Q is an integer greater than 2, q b 、M b are all integers greater than 1.

[0157] Here, since the input of the lookup table is strongly related to the delay term of the absolute value of the signal, for example, LUT0 is used to calculate LUT(|x(n)|), LUT1 is used to calculate LUT(|x(n-1)|), and so on, the delay of the absolute value of the signal stored in the predistortion module 1 (PD1) is the same even number as the input signal delay, that is, the second lookup table; the delay of the absolute value of the signal stored in the predistortion module 2 (PD2) is the same odd number as the input signal delay, that is, the first lookup table; the delay of the absolute value of the signal stored in the predistortion module (PD3) is the same odd number as the input signal delay, that is, the first lookup table; The lookup tables are intersecting with the input signal delay (including two different even numbers, two different odd numbers, one of the two is odd and the other is even), namely, the third lookup table and the fourth lookup table, and the second lookup table in the predistortion module 1 (PD1) only allows data access in the even sequence s1 (n), the first lookup table in the predistortion module 2 (PD2) only allows data access in the odd sequence s2 (n), and the third lookup table and the fourth lookup table in the predistortion module 3 (PD3) allow data access in both the odd sequence s2 (n) and the even sequence s1 (n).

[0158] Here, the absolute value module 2, the predistortion module 2 (PD2), and the multiplication module 2 constitute a first digital predistortion processing module in the processing module 43, which is used to perform digital predistortion processing on the processed odd sequence using multiple first lookup tables to obtain a first digital predistortion result.

[0159] Here, the first digital predistortion processing module is specifically used for:

[0160] Determine a plurality of first search results using the plurality of first search tables;

[0161] The multiple first search results are multiplied by corresponding elements in the processed odd-numbered sequence to obtain multiple first multiplication results; and the multiple first multiplication results are added to obtain the first digital pre-distortion result.

[0162] That is, the absolute value module 2 performs absolute value processing on each data element in the input odd sequence s2(n) to obtain the absolute value of the sequence; the pre-distortion module 2 (PD2) is used to use the absolute value of the input odd sequence s2(n) to search multiple first lookup tables to obtain corresponding multiple first lookup results; the multiplication module 2 is used to multiply the multiple first lookup results with the corresponding elements in the processed odd sequence s2(n) to obtain multiple first multiplication results, and add the multiple first multiplication results to obtain the first digital pre-distortion result.

[0163] Here, the absolute value module 1, the predistortion module 1 (PD1), and the multiplication module 1 constitute a second digital predistortion processing module in the processing module 43, which is used to obtain a second digital predistortion result for the processed even sequence using multiple second lookup tables.

[0164] Here, the second digital pre-distortion processing module is specifically used for:

[0165] Determine a plurality of second search results using the plurality of second search tables;

[0166] Multiplying the plurality of second search results by corresponding elements in the processed even-numbered sequence to obtain a plurality of second multiplication results;

[0167] The multiple second multiplication results are added to obtain the second digital predistortion result.

[0168] That is, the absolute value module 1 is used to perform absolute value processing on each data element in the input even sequence s1(n) to obtain the absolute value of the sequence; the predistortion module 1 (PD1) is used to use the absolute value of the input even sequence s1(n) to search multiple second lookup tables to obtain corresponding multiple second lookup results; the multiplication module 1 is used to multiply the multiple second lookup results with the corresponding elements in the processed even sequence s1(n) to obtain multiple second multiplication results, and add the multiple second multiplication results to obtain the second digital predistortion result.

[0169] Here, the absolute value module 1, the absolute value module 2, the predistortion module 3 (PD3), the multiplication module 3, and the multiplication module 4 constitute a third digital predistortion processing module and a fourth digital predistortion processing module in the processing module 43, wherein the third digital predistortion processing module is used to use multiple third lookup tables to perform digital predistortion processing on the processed odd sequence and the processed even sequence to obtain a third digital predistortion result, and the fourth digital predistortion processing module is used to use multiple fourth lookup tables to perform digital predistortion processing on the processed odd sequence and the processed even sequence to obtain a fourth digital predistortion result.

[0170] Here, the third digital predistortion processing module is specifically used for:

[0171] Determine a plurality of third search results using the plurality of third search tables;

[0172] The plurality of third search results are multiplied with corresponding elements in the processed odd sequence and the processed even sequence to obtain a plurality of third multiplication results; and the plurality of third multiplication results are added to obtain the third digital predistortion result.

[0173] Here, the fourth digital predistortion processing module is specifically used for:

[0174] Determine a plurality of fourth search results using the plurality of fourth search tables;

[0175] The plurality of fourth search results are multiplied with corresponding elements in the processed odd sequence and the processed even sequence to obtain a plurality of fourth multiplication results; and the plurality of fourth multiplication results are added to obtain the fourth digital predistortion result.

[0176] That is, the absolute value module 1 is used to perform absolute value processing on each data element in the input even sequence s1(n) to obtain the absolute value of the sequence; the absolute value module 2 is used to perform absolute value processing on each data element in the input odd sequence s2(n) to obtain the absolute value of the sequence; the predistortion module 3 (PD3) is used to use the absolute value of the input odd sequence s2(n) and the absolute value of the input even sequence s1(n) to search multiple third lookup tables to obtain corresponding multiple third lookup results, and to search multiple fourth lookup tables to obtain corresponding multiple fourth lookup results; the multiplication module Block 3 is used to multiply the multiple third search results with the corresponding elements in the processed odd sequence s2(n) and the processed even sequence s1(n) to obtain multiple third multiplication results, and add the multiple third multiplication results to obtain the third digital pre-distortion result; the multiplication module 4 is used to multiply the multiple fourth search results with the corresponding elements in the processed odd sequence s2(n) and the processed even sequence s1(n) to obtain multiple fourth multiplication results, and add the multiple fourth multiplication results to obtain the fourth digital pre-distortion result.

[0177] Here, the adding module 1, the adding module 2, and the adding module 3 constitute a summing module in the processing module 43, which is used to sum the first digital pre-distortion result, the second digital pre-distortion result, the third digital pre-distortion result, and the fourth digital pre-distortion result to obtain the first digital pre-distortion signal.

[0178] Specifically, the adding module 1 is used to sum the second digital pre-distortion result and the third digital pre-distortion result, the adding module 2 is used to sum the first digital pre-distortion result and the fourth digital pre-distortion result, and the adding module 3 is used to sum the summed results of the adding module 1 and the adding module 2 to obtain the first digital pre-distortion signal.

[0179] Here, after confirming the storage order of the lookup table, various pre-distortion results are added in actual operation to finally obtain the result after digital pre-distortion processing, thereby completing the parallel processing of high-speed signals at a low speed.

[0180] It should be noted that in a narrowband scenario, digital predistortion (DPD) does not have high requirements for the signal processing bandwidth, and single-channel hardware resource processing can fully match the pre-calibrated performance. Therefore, in actual application, it is no longer necessary to upsample in the DPD hardware module. Therefore, a first switch can be added to bypass one of the filters in the interpolation filter, such as the second filter (filter FIR_2), and at this time, only the LUT resources in the predistortion module 1 (PD1) and the predistortion module 3 (PD3) need to be updated. Alternatively, a first switch can be added to bypass one of the filters in the interpolation filter, such as the first filter (filter FIR_1), and at this time, only the LUT resources in the predistortion module 2 (PD2) and the predistortion module 3 (PD3) need to be updated. This can reduce the use of a large number of hardware computing resources and reduce the dynamic power consumption of the hardware.

[0181] In this way, in a narrowband scenario, the signal processing circuit may also include: a first switch; wherein the first switch is used to disconnect the connection between the input module and the second filter to input the sequence to be processed into the processing module, or the first switch is used to disconnect the connection between the input module and the first filter to input the sequence to be processed into the processing module.

[0182] See also Figure 6 , Figure 6 is a schematic diagram of the specific structure of the signal processing circuit of the embodiment of the present application, such as Figure 6 As shown, in a narrowband scenario, the signal processing circuit may include: an input module, a switch 1, an absolute value module 1, a multiplication module 1, a multiplication module 3, an addition module 1, a predistortion module 1 (PD1), and a predistortion module 3 (PD3);

[0183] in,

[0184] The input module corresponds to the above-mentioned input module 41;

[0185] Switch 1 corresponds to the first switch, and is used to disconnect the input module from the second filter (filter FIR_1);

[0186] The absolute value module 1 , the predistortion module 1 ( PD1 ), and the multiplication module 1 constitute a second digital predistortion processing module in the processing module 43 .

[0187] The absolute value module 1 , the predistortion module 3 ( PD3 ), and the multiplication module 3 constitute a third digital predistortion processing module and a fourth digital predistortion processing module in the processing module 43 .

[0188] Here, the second digital pre-distortion processing module is further used to obtain a fifth digital pre-distortion result for the sequence to be processed by using a plurality of second lookup tables.

[0189] Here, the second digital pre-distortion processing module is specifically used for:

[0190] Determine a plurality of fifth search results using the plurality of second search tables;

[0191] multiplying the plurality of fifth search results by corresponding elements in the sequence to be processed to obtain a plurality of fifth multiplication results;

[0192] The multiple fifth multiplication results are added to obtain the fifth digital pre-distortion result.

[0193] That is, the absolute value module 1 is used to perform absolute value processing on each data element in the input sequence to be processed to obtain the absolute value of the sequence; the pre-distortion module 1 (PD1) is used to use the absolute value of the input sequence to be processed to search multiple second lookup tables to obtain corresponding multiple fifth lookup results; the multiplication module 1 is used to multiply the multiple fifth lookup results with the corresponding elements in the sequence to be processed to obtain multiple fifth multiplication results, and add the multiple fifth multiplication results to obtain the fifth digital pre-distortion result.

[0194] Here, the third digital pre-distortion processing module is further used to perform digital pre-distortion processing on the sequence to be processed using the multiple third lookup tables to obtain a sixth digital pre-distortion result; the fourth digital pre-distortion processing module is further used to perform digital pre-distortion processing on the sequence to be processed using the multiple fourth lookup tables to obtain a seventh digital pre-distortion result.

[0195] Here, the third digital predistortion processing module is specifically used for:

[0196] Determine a plurality of sixth search results using the plurality of third search tables;

[0197] multiplying the plurality of sixth search results by corresponding elements in the sequence to be processed to obtain a plurality of sixth multiplication results;

[0198] The multiple sixth multiplication results are added to obtain the sixth digital pre-distortion result.

[0199] Here, the fourth digital predistortion processing module is specifically used for:

[0200] Determine a plurality of seventh search results using the plurality of fourth search tables;

[0201] multiplying the plurality of seventh search results by corresponding elements in the sequence to be processed to obtain a plurality of seventh multiplication results;

[0202] The plurality of seventh multiplication results are added to obtain the seventh digital predistortion result.

[0203] That is, the absolute value module 1 is used to perform absolute value processing on each data element of the input sequence to be processed to obtain the absolute value of the sequence; the pre-distortion module 3 (PD3) is used to use the absolute value of the input sequence to be processed to search multiple third lookup tables to obtain corresponding multiple sixth lookup results, and search multiple fourth lookup tables to obtain corresponding multiple seventh lookup results; the multiplication module 3 is used to multiply the multiple sixth lookup results with the corresponding elements in the sequence to be processed respectively to obtain multiple sixth multiplication results, add the multiple sixth multiplication results to obtain the sixth digital pre-distortion result, and multiply the multiple seventh lookup results with the corresponding elements in the sequence to be processed to obtain multiple seventh multiplication results; add the multiple seventh multiplication results to obtain the seventh digital pre-distortion result.

[0204] Here, the adding module 1 constitutes a summing module in the processing module 43, and is also used to sum the fifth digital pre-distortion result, the sixth digital pre-distortion result, and the seventh digital pre-distortion result to obtain a second digital pre-distortion signal.

[0205] The following is an explanation with reference to specific examples.

[0206] For example, assuming that DPD uses the GMP model, the maximum supported lookup tables (LUTs) are 32, of which 8 LUTs are stored in predistortion module 1 (PD1) and predistortion module 2 (PD2), and 16 LUTs are stored in predistortion module 3 (PD3). In the broadband scenario, an interpolation filter is used to complete double resampling and simultaneously divide the high-rate signal x(n) into an even sequence s1(n) and an odd sequence s2(n).

[0207] Table 1 is a schematic diagram of the lookup tables stored in the predistortion module 1 (PD1), the predistortion module 2 (PD2), and the predistortion module 3 (PD3). As shown in Table 1, the delay of the absolute value of the signal stored in the predistortion module 1 (PD1) is the same even number as the input signal delay, that is, 8 second lookup tables, namely, LUT0, LUT2, LUT4, LUT6, LUT8, LUT10, LUT12, and LUT14. The delay of the absolute value of the signal stored in the predistortion module 2 (PD2) is the same odd number as the input signal delay, that is, 8 first lookup tables, namely, LUT1, LUT3, LUT5, LUT7, LUT9, LUT11, LUT13, and LUT15. The delay of the absolute value of the signal stored in the predistortion module 3 (PD3) is crossed with the input signal delay (including the two being different even numbers, the two being different even numbers, and the two being different odd numbers). The eight third lookup tables are LUT16, LUT17, LUT18, LUT19, LUT20, LUT21, LUT22, and LUT23, and the eight fourth lookup tables are LUT24, LUT25, LUT26, LUT27, LUT28, LUT29, LUT30, and LUT31, respectively. The lookup table in the predistortion module 1 (PD1) only allows data elements in the even sequence s1(n) to be accessed, and the lookup table in the predistortion module 2 (PD2) only allows data elements in the odd sequence s2(n) to be accessed. Since the input of the lookup table is strongly correlated with the delay term of the absolute value of the signal, it is very convenient to perform a lookup operation when confirming the output based on the delay of the absolute value of the input signal.

[0208] Table 1

[0209] LUT15 …… LUT4 LUT19 LUT27 LUT3 LUT31 LUT23 LUT18 LUT26 LUT2 LUT30 LUT22 LUT17 LUT25 LUT1 LUT29 LUT21 LUT16 LUT24 LUT0 LUT28 LUT20

[0210] Here, the eight first lookup tables stored in the pre-distortion module 2 (PD2) include LUT1, LUT3, LUT5, LUT7, LUT9, LUT11, LUT13, and LUT15.

[0211] Here, the expression of the first lookup table is:

[0212] LUT(|x(nq)|);

[0213] in,

[0214] |x(nq)| represents the absolute value of the sequence input at time nq; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple first lookup tables increases according to odd numbers starting from 1.

[0215] See also Figure 7 , Figure 7 is a schematic diagram of the first lookup table of the embodiment of the present application, such as Figure 7 As shown, eight first lookup tables are stored in the pre-distortion module 2 (PD2), including LUT1, LUT3, LUT5, LUT7, LUT9, LUT11, LUT13, and LUT15. The expression of LUT1 is LUT(|x(n-1)|), the expression of LUT3 is LUT(|x(n-3)|), the expression of LUT5 is LUT(|x(n-5)|), the expression of LUT7 is LUT(|x(n-7)|), the expression of LUT9 is LUT(|x(n-9)|), the expression of LUT11 is LUT(|x(n-11)|), the expression of LUT13 is LUT(|x(n-13)|), and the expression of LUT15 is LUT(|x(n-15)|).

[0216] First, the sequence to be processed Tx is subjected to interpolation filtering to obtain an even sequence s1(n) and an odd sequence s2(n).

[0217] Here, the elements in the even sequence s1(n) include: x(n), x(n-2), x(n-4), x(n-6), x(n-8), x(n-10), x(n-12), and x(n-14), which are represented by s1(n), s1(n-1), s1(n-2), s1(n-3), s1(n-4), s1(n-5), s1(n-6), and s1(n-7), respectively.

[0218] Here, the elements in the odd sequence s2(n) include: x(n-1), x(n-3), x(n-5), x(n-7), x(n-9), x(n-11), x(n-13), and x(n-15), which are represented by s2(n-1), s2(n-2), s2(n-3), s2(n-4), s2(n-5), s2(n-6), s2(n-7), and s2(n-8), respectively.

[0219] Then, the processed odd sequence is subjected to digital predistortion processing using eight first lookup tables to obtain a first digital predistortion result. The eight first lookup tables include LUT1, LUT3, LUT5, LUT7, LUT9, LUT11, LUT13, and LUT15.

[0220] Here, taking LUT1 as an example, according to the expression of LUT1, the input is determined to be the absolute value of the element x(n-1) in the odd sequence s2(n), that is, |x(n-1)|. By searching LUT1, the corresponding first search result is obtained, and the first search result is multiplied by the element x(n-1) in the odd sequence s2(n) to obtain the first multiplication result.

[0221] Here, the eight second lookup tables stored in the pre-distortion module 1 (PD1) include LUT0, LUT2, LUT4, LUT6, LUT8, LUT10, LUT12, and LUT14.

[0222] Here, the expression of the second lookup table is:

[0223] LUT(|x(nq)|);

[0224] in,

[0225] |x(nq)| represents the absolute value of the sequence input at time nq; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple second lookup tables increases in even numbers starting from 0.

[0226] See also Figure 8 , Figure 8 is a schematic diagram of the second lookup table of the embodiment of the present application, such as Figure 8 As shown, eight second lookup tables are stored in the predistortion module 1 (PD1), including LUT0, LUT2, LUT4, LUT6, LUT8, LUT10, LUT12, and LUT14. The expression of LUT0 is LUT(|x(n)|), the expression of LUT2 is LUT(|x(n-2)|), the expression of LUT4 is LUT(|x(n-4)|), the expression of LUT6 is LUT(|x(n-6)|), the expression of LUT8 is LUT(|x(n-8)|), the expression of LUT10 is LUT(|x(n-10)|), the expression of LUT12 is LUT(|x(n-12)|), and the expression of LUT14 is LUT(|x(n-14)|).

[0227] First, the sequence to be processed Tx is subjected to interpolation filtering to obtain an even sequence s1(n) and an odd sequence s2(n).

[0228] Here, the elements in the even sequence s1(n) include: x(n), x(n-2), x(n-4), x(n-6), x(n-8), x(n-10), x(n-12), and x(n-14), which are represented by s1(n), s1(n-1), s1(n-2), s1(n-3), s1(n-4), s1(n-5), s1(n-6), and s1(n-7), respectively.

[0229] Here, the elements in the odd sequence s2(n) include: x(n-1), x(n-3), x(n-5), x(n-7), x(n-9), x(n-11), x(n-13), and x(n-15), which are represented by s2(n-1), s2(n-2), s2(n-3), s2(n-4), s2(n-5), s2(n-6), s2(n-7), and s2(n-8), respectively.

[0230] Then, the processed even sequence is subjected to digital predistortion processing using eight second lookup tables to obtain a second digital predistortion result. The eight second lookup tables include LUT0, LUT2, LUT4, LUT6, LUT8, LUT10, LUT12, and LUT14.

[0231] Here, taking LUT2 as an example, according to the expression of LUT2, the input is determined to be the absolute value of the element x(n-2) in the even sequence s1(n), that is, |x(n-2)|. By searching LUT2, the corresponding second search result is obtained, and the second search result is multiplied by the element x(n-2) in the even sequence s1(n) to obtain the second multiplication result.

[0232] Here, 8 third lookup tables and 8 fourth lookup tables are stored in the pre-distortion module 3 (PD3), wherein the 8 third lookup tables are LUT16, LUT17, LUT18, LUT19, LUT20, LUT21, LUT22, and LUT23, and the 8 fourth lookup tables are LUT24, LUT25, LUT26, LUT27, LUT28, LUT29, LUT30, and LUT31.

[0233] Here, the expression of the third lookup table is:

[0234] LUT(|x(nq±m)|);

[0235] Among them, |x(nq±m)| represents the absolute value of the sequence input at time nq±m; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple third lookup tables is incremented by integers starting from 0, and for each q, the corresponding q+m combination or qm combination is searched through a preset combination list, and m is an integer increasing from 1; when q is an odd number, the q+m combination or qm combination corresponding to the third lookup table is an odd number, and when q is an even number, the q+m combination or qm combination corresponding to the third lookup table is an even number.

[0236] Here, the expression of the fourth lookup table is:

[0237] LUT(|x(nq±m)|);

[0238] Among them, |x(nq±m)| represents the absolute value of the sequence input at time nq±m; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple fourth lookup tables is incremented by integers starting from 0, and for each q, the corresponding q+m combination or qm combination is searched through the preset combination list, and m is an integer increasing from 1; when q is an odd number, the q+m combination or qm combination corresponding to the fourth lookup table is an even number, and when q is an even number, the q+m combination or qm combination corresponding to the fourth lookup table is an odd number.

[0239] Table 2 is a schematic diagram of a preset combination list. As shown in Table 2, assuming that the upper limit of the value of q is 3 and the upper limit of the value of m is 2, when q=0, the q+m combination corresponding to the third lookup table is 0+2, and the qm combination is 0-2; when q=1, the q+m combination corresponding to the third lookup table is 1+2, and the qm combination is 1-2; when q=2, the q+m combination corresponding to the third lookup table is 2+2, and the qm combination is 2-2; when q=3, the q+m combination corresponding to the third lookup table is 0+2, and the qm combination is 0-2. The q+m combination is 3+2, and the qm combination is 3-2; similarly, when q=0, the q+m combination corresponding to the fourth lookup table is 0+1, and the qm combination is 0-1; when q=1, the q+m combination corresponding to the fourth lookup table is 1+1, and the qm combination is 1-1; when q=2, the q+m combination corresponding to the fourth lookup table is 2+1, and the qm combination is 2-1; when q=3, the q+m combination corresponding to the fourth lookup table is 3+1, and the qm combination is 3-1.

[0240] Table 2

[0241]

[0242] See also Fig. 9 , Fig. 9 Schematic diagram of the third lookup table and the fourth lookup table of the embodiment of the present application. Fig. 9 As shown, 8 third lookup tables and 8 fourth lookup tables are stored in the predistortion module 3 (PD3), the 8 third lookup tables are LUT16, LUT17, LUT18, LUT19, LUT20, LUT21, LUT22, and LUT23, and the 8 fourth lookup tables are LUT24, LUT25, LUT26, LUT27, LUT28, LUT29, LUT30, and LUT31, wherein the expression of LUT16 is LUT(|x(n+2)|), the expression of LUT17 is LUT(|x(n+1)|), the expression of LUT18 is LUT(|x(n)|), the expression of LUT19 is LUT(|x(n-1)|), and the expression of LUT20 is LUT(|x(n-2 )|), the expression of LUT21 is LUT(|x(n-3)|), the expression of LUT22 is LUT(|x(n-4)|), the expression of LUT23 is LUT(|x(n-5)|), the expression of LUT24 is LUT(|x(n+1)|), the expression of LUT25 is LUT(|x(n)|), the expression of LUT26 is LUT(|x(n-1)|), the expression of LUT27 is LUT(|x(n-2)|), the expression of LUT28 is LUT(|x(n-1)|), the expression of LUT29 is LUT(|x(n-2)|), the expression of LUT30 is LUT(|x(n-3)|), and the expression of LUT31 is LUT(|x(n-4)|).

[0243] First, the sequence to be processed Tx is subjected to interpolation filtering to obtain an even sequence s1(n) and an odd sequence s2(n).

[0244] Here, the elements in the even sequence s1(n) include: x(n), x(n-2), x(n-4), x(n-6), x(n-8), x(n-10), x(n-12), and x(n-14), which are represented by s1(n), s1(n-1), s1(n-2), s1(n-3), s1(n-4), s1(n-5), s1(n-6), and s1(n-7), respectively.

[0245] Here, the elements in the odd sequence s2(n) include: x(n-1), x(n-3), x(n-5), x(n-7), x(n-9), x(n-11), x(n-13), and x(n-15), which are represented by s2(n-1), s2(n-2), s2(n-3), s2(n-4), s2(n-5), s2(n-6), s2(n-7), and s2(n-8), respectively.

[0246] Then, eight third lookup tables are used to perform digital predistortion processing on the processed odd sequence and the processed even sequence to obtain a third digital predistortion result, and eight fourth lookup tables are used to perform digital predistortion processing on the processed odd sequence and the processed even sequence to obtain a fourth digital predistortion result.

[0247] Here, the eight third lookup tables are LUT16, LUT17, LUT18, LUT19, LUT20, LUT21, LUT22, and LUT23 respectively.

[0248] Here, taking LUT16 as an example, according to the expression of LUT16, the absolute value of the element x(n+2) in the input even sequence s1(n), namely |x(n+2)|, is determined, and by searching LUT16, the corresponding third search result is obtained, and the third search result is multiplied by the element x(n) in the even sequence s1(n) to obtain the third multiplication result.

[0249] Here, the eight fourth lookup tables are LUT24, LUT25, LUT26, LUT27, LUT28, LUT29, LUT30, and LUT31 respectively.

[0250] Here, taking LUT24 as an example, according to the expression of LUT24, the absolute value of the element x(n+1) in the input odd sequence s2(n), namely |x(n+1)|, is determined, and by searching LUT24, the corresponding fourth search result is obtained, and the fourth search result is multiplied by the element x(n) in the even sequence s1(n) to obtain a fourth multiplication result.

[0251] See also Fig.10 , Fig.10 is a schematic diagram of obtaining a first digital predistortion signal according to an embodiment of the present application, such as Fig.10 As shown, the process of obtaining the first digital predistortion signal may include:

[0252] First, the sequence to be processed Tx is subjected to interpolation filtering to obtain an even sequence s1(n) and an odd sequence s2(n).

[0253] Here, the elements in the even sequence s1(n) include: x(n), x(n-2), x(n-4), x(n-6), x(n-8), x(n-10), x(n-12), and x(n-14), which are represented by s1(n), s1(n-1), s1(n-2), s1(n-3), s1(n-4), s1(n-5), s1(n-6), and s1(n-7), respectively.

[0254] Here, the elements in the odd sequence s2(n) include: x(n-1), x(n-3), x(n-5), x(n-7), x(n-9), x(n-11), x(n-13), and x(n-15), which are represented by s2(n-1), s2(n-2), s2(n-3), s2(n-4), s2(n-5), s2(n-6), s2(n-7), and s2(n-8), respectively.

[0255] Then, the digital predistortion result is determined using a lookup table.

[0256] Specifically, it may include:

[0257] 8 first lookup results are obtained by using 8 first lookup tables, namely LUT1, LUT3, LUT5, LUT7, LUT9, LUT11, LUT13, and LUT15. The 8 first lookup results are multiplied by the corresponding elements in the processed odd sequence s2(n) to obtain a first digital predistortion result; wherein the corresponding elements in the odd sequence s2(n) include: x(n-1), x(n-3), x(n-5), x(n-7), x(n-9), x(n-11), x(n-13), and x(n-15), which are represented by s2(n-1), s2(n-2), s2(n-3), s2(n-4), s2(n-5), s2(n-6), s2(n-7), and s2(n-8), respectively.

[0258] Specifically, the first search result of LUT1 is multiplied by x(n-1) to obtain a first multiplication result; the first search result of LUT3 is multiplied by x(n-3) to obtain a first multiplication result; the first search result of LUT5 is multiplied by x(n-5) to obtain a first multiplication result; the first search result of LUT7 is multiplied by x(n-7) to obtain a first multiplication result; the first search result of LUT9 is multiplied by x(n-9) to obtain a first multiplication result; the first search result of LUT11 is multiplied by x(n-11) to obtain a first multiplication result; the first search result of LUT13 is multiplied by x(n-13) to obtain a first multiplication result; the first search result of LUT15 is multiplied by x(n-15) to obtain a first multiplication result; these 8 first multiplication results are added to obtain a first digital pre-distortion result.

[0259] 8 second lookup results are obtained by using 8 second lookup tables, namely LUT0, LUT2, LUT4, LUT6, LUT8, LUT10, LUT12, and LUT14. The 8 second lookup results are multiplied by the corresponding elements in the processed even sequence s1(n) to obtain a second digital predistortion result; wherein the corresponding elements in the even sequence s1(n) include: x(n), x(n-2), x(n-4), x(n-6), x(n-8), x(n-10), x(n-12), and x(n-14), which are represented by s1(n), s1(n-1), s1(n-2), s1(n-3), s1(n-4), s1(n-5), s1(n-6), and s1(n-7), respectively.

[0260] Specifically, the second search result of LUT0 is multiplied by x(n) to obtain a second multiplication result; the second search result of LUT2 is multiplied by x(n-2) to obtain a second multiplication result; the second search result of LUT4 is multiplied by x(n-4) to obtain a second multiplication result; the second search result of LUT6 is multiplied by x(n-6) to obtain a second multiplication result; the second search result of LUT8 is multiplied by x(n-8) to obtain a second multiplication result; the second search result of LUT10 is multiplied by x(n-10) to obtain a second multiplication result; the second search result of LUT12 is multiplied by x(n-12) to obtain a second multiplication result; the second search result of LUT14 is multiplied by x(n-14) to obtain a second multiplication result; these 8 second multiplication results are added to obtain a second digital pre-distortion result.

[0261] 8 third lookup results are obtained by using 8 third lookup tables, namely LUT16, LUT17, LUT18, LUT19, LUT20, LUT21, LUT22 and LUT23, and the 8 third lookup results are multiplied with the corresponding elements in the processed odd sequence s2(n) and the processed even sequence s1(n) to obtain the third digital predistortion result; wherein the corresponding elements in the odd sequence s2(n) include: x(n-1) and x(n-3), which are represented by s2(n-1) and s2(n-2) respectively; the corresponding elements in the even sequence s1(n) include: x(n) and x(n-2), which are represented by s1(n) and s1(n-1) respectively.

[0262] Specifically, the third search result of LUT16 is multiplied by x(n) to obtain a third multiplication result; the third search result of LUT17 is multiplied by x(n-1) to obtain a third multiplication result; the third search result of LUT18 is multiplied by x(n-2) to obtain a third multiplication result; the third search result of LUT19 is multiplied by x(n-3) to obtain a third multiplication result; the third search result of LUT20 is multiplied by x(n) to obtain a third multiplication result; the third search result of LUT21 is multiplied by x(n-1) to obtain a third multiplication result; the third search result of LUT22 is multiplied by x(n-2) to obtain a third multiplication result; the third search result of LUT23 is multiplied by x(n-3) to obtain a third multiplication result; these 8 third multiplication results are added to obtain a third digital pre-distortion result.

[0263] Eight fourth lookup tables, namely LUT24, LUT25, LUT26, LUT27, LUT28, LUT29, LUT30 and LUT31, are used to obtain eight fourth lookup results, and the eight fourth lookup results are multiplied with corresponding elements in the processed odd sequence s2(n) and the processed even sequence s1(n) to obtain the fourth digital predistortion result; wherein the corresponding elements in the odd sequence s2(n) include: x(n-1) and x(n-3), which are represented by s2(n-1) and s2(n-2) respectively; and the corresponding elements in the even sequence s1(n) include: x(n) and x(n-2), which are represented by s1(n) and s1(n-1) respectively.

[0264] Specifically, the fourth search result of LUT24 is multiplied by x(n) to obtain a fourth multiplication result; the fourth search result of LUT25 is multiplied by x(n-1) to obtain a fourth multiplication result; the fourth search result of LUT26 is multiplied by x(n-2) to obtain a fourth multiplication result; the fourth search result of LUT27 is multiplied by x(n-3) to obtain a fourth multiplication result; the fourth search result of LUT28 is multiplied by x(n) to obtain a fourth multiplication result; the fourth search result of LUT29 is multiplied by x(n-1) to obtain a fourth multiplication result; the fourth search result of LUT30 is multiplied by x(n-2) to obtain a fourth multiplication result; the fourth search result of LUT31 is multiplied by x(n-3) to obtain a fourth multiplication result; these 8 fourth multiplication results are added to obtain a fourth digital pre-distortion result.

[0265] The first digital predistortion result, the second digital predistortion result, the third digital predistortion result and the fourth digital predistortion result are summed to obtain the first digital predistortion signal.

[0266] See also Fig.11 , Fig.11 is a schematic diagram of the implementation flow of the signal processing method of the embodiment of the present application, such as Fig.11 As shown, the method is applied to a signal processing circuit, the circuit includes an input module, an interpolation filter, and a processing module, the interpolation filter includes two parallel first filters and second filters, the first filter stores odd coefficients of the interpolation filter, and the second filter stores even coefficients of the interpolation filter, the method includes:

[0267] Step 1101: Obtain an input sequence to be processed;

[0268] Step 1102: Based on the odd coefficients of the interpolation filter, the sequence to be processed is subjected to interpolation filtering processing to obtain a processed odd sequence; based on the even coefficients of the interpolation filter, the sequence to be processed is subjected to interpolation filtering processing to obtain a processed even sequence;

[0269] Step 1103: Obtain a first digital predistortion signal based on the processed odd sequence and the processed even sequence.

[0270] In one embodiment, obtaining a first digital predistortion signal based on the processed odd sequence and the processed even sequence includes:

[0271] Using a plurality of first lookup tables, performing digital predistortion processing on the processed odd-numbered sequence to obtain a first digital predistortion result;

[0272] Using a plurality of second lookup tables, performing digital predistortion processing on the processed even-numbered sequence to obtain a second digital predistortion result;

[0273] Using a plurality of third lookup tables, performing digital predistortion processing on the processed odd-numbered sequence and the processed even-numbered sequence to obtain a third digital predistortion result;

[0274] Using a plurality of fourth lookup tables, performing digital predistortion processing on the processed odd-numbered sequence and the processed even-numbered sequence to obtain a fourth digital predistortion result;

[0275] The first digital predistortion result, the second digital predistortion result, the third digital predistortion result and the fourth digital predistortion result are summed to obtain the first digital predistortion signal.

[0276] In one embodiment, the expression of the first lookup table is:

[0277] LUT(|x(nq)|);

[0278] in,

[0279] |x(nq)| represents the absolute value of the sequence input at time nq; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple first lookup tables increases in odd numbers starting from 1;

[0280] The expression of the second lookup table is:

[0281] LUT(|x(nq)|);

[0282] in,

[0283] |x(nq)| represents the absolute value of the sequence input at time nq; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the plurality of second lookup tables increases in even numbers starting from 0;

[0284] The expression of the third lookup table is:

[0285] LUT(|x(nq±m)|);

[0286] Wherein, |x(nq±m)| represents the absolute value of the sequence input at time nq±m; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple third lookup tables is incremented by an integer starting from 0, and for each q, the corresponding q+m combination or qm combination is searched through a preset combination list, and m is an integer increasing from 1; when q is an odd number, the q+m combination or qm combination corresponding to the third lookup table is an odd number, and when q is an even number, the q+m combination or qm combination corresponding to the third lookup table is an even number;

[0287] The expression of the fourth lookup table is:

[0288] LUT(|x(nq±m)|);

[0289] Among them, |x(nq±m)| represents the absolute value of the sequence input at time nq±m; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple fourth lookup tables is incremented by integers starting from 0, and for each q, the corresponding q+m combination or qm combination is searched through the preset combination list, and m is an integer increasing from 1; when q is an odd number, the q+m combination or qm combination corresponding to the fourth lookup table is an even number, and when q is an even number, the q+m combination or qm combination corresponding to the fourth lookup table is an odd number.

[0290] In one embodiment, the using of a plurality of first lookup tables to perform digital predistortion processing on the processed odd-numbered sequence to obtain a first digital predistortion result includes:

[0291] Determine a plurality of first search results using the plurality of first search tables;

[0292] Multiplying the plurality of first search results by corresponding elements in the processed odd-numbered sequence to obtain a plurality of first multiplication results;

[0293] The multiple first multiplication results are added to obtain the first digital pre-distortion result.

[0294] In one embodiment, the using of a plurality of second lookup tables to obtain a second digital predistortion result for the processed even sequence includes:

[0295] Determine a plurality of second search results using the plurality of second search tables;

[0296] Multiplying the plurality of second search results by corresponding elements in the processed even-numbered sequence to obtain a plurality of second multiplication results;

[0297] The multiple second multiplication results are added to obtain the second digital predistortion result.

[0298] In one embodiment, the using of a plurality of third lookup tables to perform digital predistortion processing on the processed odd sequence and the processed even sequence to obtain a third digital predistortion result includes:

[0299] Determine a plurality of third search results using the plurality of third search tables;

[0300] multiplying the plurality of third search results with corresponding elements in the processed odd number sequence and the processed even number sequence to obtain a plurality of third multiplication results;

[0301] The multiple third multiplication results are added to obtain the third digital pre-distortion result.

[0302] In one embodiment, the using of a plurality of fourth lookup tables to perform digital predistortion processing on the processed odd-numbered sequence and the processed even-numbered sequence to obtain a fourth digital predistortion result includes:

[0303] Determine a plurality of fourth search results using the plurality of fourth search tables;

[0304] multiplying the plurality of fourth search results with corresponding elements in the processed odd number sequence and the processed even number sequence to obtain a plurality of fourth multiplication results;

[0305] The multiple fourth multiplication results are added to obtain the fourth digital pre-distortion result.

[0306] In one embodiment, the circuit further comprises a first switch; the first switch is used to disconnect the input module and the second filter so as to input the sequence to be processed into the processing module.

[0307] In one embodiment, the method further comprises:

[0308] Using the plurality of second lookup tables, performing digital predistortion processing on the sequence to be processed to obtain a fifth digital predistortion result;

[0309] Using the plurality of third lookup tables, performing digital predistortion processing on the sequence to be processed to obtain a sixth digital predistortion result;

[0310] Using the plurality of fourth lookup tables, performing digital predistortion processing on the sequence to be processed to obtain a seventh digital predistortion result;

[0311] The fifth digital pre-distortion result, the sixth digital pre-distortion result, and the seventh digital pre-distortion result are summed to obtain a second digital pre-distortion signal.

Claims

1. A signal processing circuit, characterized in that: include: An input module, an interpolation filter, and a processing module, wherein the interpolation filter includes two parallel first filters and a second filter; wherein, The input module is used to input the sequence to be processed; The first filter stores the odd coefficients of the interpolation filter, and is used to perform interpolation filtering processing on the sequence to be processed based on the odd coefficients of the interpolation filter to obtain a processed odd sequence; The second filter stores the even coefficients of the interpolation filter, and is used to perform interpolation filtering processing on the sequence to be processed based on the even coefficients of the interpolation filter to obtain a processed even sequence; The processing module is used to obtain a first digital predistortion signal based on the processed odd sequence and the processed even sequence.

2. The circuit according to claim 1, characterized in that The processing module comprises: A first digital pre-distortion processing module, configured to perform digital pre-distortion processing on the processed odd-numbered sequence using a plurality of first lookup tables to obtain a first digital pre-distortion result; A second digital pre-distortion processing module, configured to perform digital pre-distortion processing on the processed even-numbered sequence using a plurality of second lookup tables to obtain a second digital pre-distortion result; A third digital pre-distortion processing module, configured to perform digital pre-distortion processing on the processed odd-numbered sequence and the processed even-numbered sequence using a plurality of third lookup tables to obtain a third digital pre-distortion result; a fourth digital predistortion processing module, configured to perform digital predistortion processing on the processed odd-numbered sequence and the processed even-numbered sequence using a plurality of fourth lookup tables to obtain a fourth digital predistortion result; The summing module is used to sum the first digital pre-distortion result, the second digital pre-distortion result, the third digital pre-distortion result and the fourth digital pre-distortion result to obtain the first digital pre-distortion signal.

3. The circuit according to claim 2, characterized in that The expression of the first lookup table is: LUT(|x(nq)|); in, |x(nq)| represents the absolute value of the sequence input at time nq; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple first lookup tables increases in odd numbers starting from 1; The expression of the second lookup table is: LUT(|x(nq)|); in, |x(nq)| represents the absolute value of the sequence input at time nq; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the plurality of second lookup tables increases in even numbers starting from 0; The expression of the third lookup table is: LUT(|x(nq±m)|); Wherein, |x(nq±m)| represents the absolute value of the sequence input at time nq±m; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple third lookup tables is incremented by an integer starting from 0, and for each q, the corresponding q+m combination or qm combination is searched through a preset combination list, and m is an integer increasing from 1; when q is an odd number, the q+m combination or qm combination corresponding to the third lookup table is an odd number, and when q is an even number, the q+m combination or qm combination corresponding to the third lookup table is an even number; The expression of the fourth lookup table is: LUT(|x(nq±m)|); Among them, |x(nq±m)| represents the absolute value of the sequence input at time nq±m; the x(n) sequence input at time n is obtained by alternately selecting elements from the odd sequence and the even sequence; q represents the memory depth, and the q corresponding to the multiple fourth lookup tables is incremented by integers starting from 0, and for each q, the corresponding q+m combination or qm combination is searched through the preset combination list, and m is an integer increasing from 1; when q is an odd number, the q+m combination or qm combination corresponding to the fourth lookup table is an even number, and when q is an even number, the q+m combination or qm combination corresponding to the fourth lookup table is an odd number.

4. The circuit according to claim 3, characterized in that The first digital predistortion processing module is specifically used to: Determine a plurality of first search results using the plurality of first search tables; Multiplying the plurality of first search results by corresponding elements in the processed odd-numbered sequence to obtain a plurality of first multiplication results; The multiple first multiplication results are added to obtain the first digital pre-distortion result.

5. The circuit according to claim 3, characterized in that The second digital predistortion processing module is specifically used for: Determine a plurality of second search results using the plurality of second search tables; Multiplying the plurality of second search results by corresponding elements in the processed even-numbered sequence to obtain a plurality of second multiplication results; The multiple second multiplication results are added to obtain the second digital predistortion result.

6. The circuit according to claim 3, characterized in that The third digital predistortion processing module is specifically used for: Determine a plurality of third search results using the plurality of third search tables; multiplying the plurality of third search results with corresponding elements in the processed odd number sequence and the processed even number sequence to obtain a plurality of third multiplication results; The multiple third multiplication results are added to obtain the third digital pre-distortion result.

7. The circuit according to claim 3, characterized in that The fourth digital predistortion processing module is specifically used for: Determine a plurality of fourth search results using the plurality of fourth search tables; multiplying the plurality of fourth search results with corresponding elements in the processed odd number sequence and the processed even number sequence to obtain a plurality of fourth multiplication results; The multiple fourth multiplication results are added to obtain the fourth digital pre-distortion result.

8. The circuit according to claim 3, characterized in that The circuit also includes a first switch; The first switch is used to disconnect the input module and the second filter to input the sequence to be processed into the processing module.

9. The circuit according to claim 8, characterized in that The second digital pre-distortion processing module is further used to perform digital pre-distortion processing on the sequence to be processed by using the multiple second lookup tables to obtain a fifth digital pre-distortion result; The third digital pre-distortion processing module is further used to perform digital pre-distortion processing on the sequence to be processed by using the multiple third lookup tables to obtain a sixth digital pre-distortion result; The fourth digital pre-distortion processing module is further used to perform digital pre-distortion processing on the sequence to be processed by using the multiple fourth lookup tables to obtain a seventh digital pre-distortion result; The summing module is further configured to sum the fifth digital pre-distortion result, the sixth digital pre-distortion result, and the seventh digital pre-distortion result to obtain a second digital pre-distortion signal.

10. A signal processing method, characterized in that: Applied to a signal processing circuit, the circuit includes an input module, an interpolation filter, and a processing module, the interpolation filter includes two parallel first filters and second filters, the first filter stores odd coefficients of the interpolation filter, and the second filter stores even coefficients of the interpolation filter, the method includes: Get the input sequence to be processed; Based on the odd coefficients of the interpolation filter, the sequence to be processed is subjected to interpolation filtering processing to obtain a processed odd sequence; Based on the even coefficients of the interpolation filter, the sequence to be processed is subjected to interpolation filtering processing to obtain a processed even sequence; A first digital predistortion signal is obtained based on the processed odd sequence and the processed even sequence.

Images