Space-time interference cancellation algorithm parallelization FPGA implementation device and method

Abstract

The invention belongs to the technical field of digital signal processing, and particularly discloses a space-time interference cancellation algorithm parallelization FPGA implementation device and method, and the device comprises an input vector generation module which delays and arranges reference signals of multiple channels, and obtains space-time input vectors of the reference signals; the correlation matrix calculation module is used for acquiring an autocorrelation matrix and a cross-correlation vector; the matrix decomposition module is used for performing matrix decomposition on the autocorrelation matrix to obtain an upper triangular matrix; the weight determination module is used for carrying out weight solving by utilizing the upper triangular matrix and the cross-correlation vector to obtain an optimal weight; the delay matching module is used for delaying the reference signal and carrying out time sequence alignment on the reference signal and the optimal weight to obtain a delay matching result; and the weighting and combining module is used for weighting the reference signals subjected to the time sequence alignment according to the optimal weight to obtain weighted signals and combining the weighted signals with the received signals so as to realize interference elimination of the received signals. According to the invention, the real-time tracking capability can be improved and the processing delay can be reduced.

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