Three-dimensional memory device and forming method thereof

Abstract

Disclosed is a three-dimensional (3D) memory device including: a memory array chip including: a stack including alternating conductive layers and dielectric layers; a storage structure extending vertically through the stack; wherein the memory structure comprises a memory layer located on the side wall of the memory structure and a conductive material filled in the memory structure, and the memory structure comprises a first side and a second side opposite to the first side; wherein the memory layer comprises: a first portion corresponding to a capacitor structure, the first portion comprising a first material; and a second portion corresponding to the transistor structure, the second portion comprising a second material different from the first material.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly, to a three-dimensional (3D) memory device and a method of forming the same. Background Art

[0002] Dynamic random access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell having a capacitor and an array transistor, both of which are typically based on metal oxide semiconductor (MOS) technology. The capacitor can be set to a charged state or a discharged state. These two states are taken to represent the two values ​​of the bit, which are conventionally referred to as 0 and 1. DRAM also includes peripheral transistors to form peripheral circuits. The peripheral circuits and array transistors manipulate data input / output (I / O) and memory cell operations (e.g., write or read).

[0003] As DRAM technology moves toward higher density and higher capacity, for example, toward the 10nm node, the number of capacitors increases dramatically, and the size of capacitors decreases dramatically, making the density and size of capacitors gradually approaching the limit. At small size nodes, the capacitor manufacturing process becomes more complex, and leakage becomes more significant, resulting in a decrease in DRAM performance. Summary of the invention

[0004] Embodiments of a three-dimensional memory device and a method of forming the same are described in the present disclosure.

[0005] One aspect of the present disclosure provides a three-dimensional (3D) memory device, which includes: a memory array chip, including: a stack including alternating conductive layers and dielectric layers; a memory structure vertically extending through the stack; wherein the memory structure includes a memory layer located at a sidewall of the memory structure, and a conductive material filled in the memory structure, and the memory structure includes a first side and a second side opposite to the first side; wherein the memory layer includes: a first portion corresponding to a capacitor structure, the first portion including a first material; and a second portion corresponding to a transistor structure, the second portion including a second material different from the first material.

[0006] In some examples, the first material includes a ferroelectric material and the second material includes an oxide dielectric material.

[0007] In some examples, the first material includes a crystalline ferroelectric material and the second material includes an amorphous ferroelectric material.

[0008] In some examples, the second portion penetrates through one of the conductive layers.

[0009] In some examples, the 3D memory device further includes: a first contact structure in contact with one side of the memory structure; and a second contact structure in contact with the conductive layer of the stack.

[0010] In some examples, the first contact structure contacts the first side of the memory structure, and the second portion of the memory layer is closer to the first side relative to the first portion, wherein the first material is also located on the second side of the memory structure.

[0011] In some examples, the first contact structure contacts the second side of the memory structure, and the second portion of the memory layer is closer to the second side than the first portion.

[0012] In some examples, the memory array chip is provided with a first bonding layer, and the 3D memory device further includes: a peripheral circuit chip including a second bonding layer; wherein the first bonding layer of the memory array chip is bonded to the second bonding layer of the peripheral circuit chip, and wherein, when the first contact structure contacts the first side of the memory structure, the first contact structure is located on a side of the memory array chip close to the peripheral circuit chip, and when the first contact structure contacts the second side of the memory structure, the first contact structure is located on a side of the memory array chip away from the peripheral circuit chip.

[0013] In some examples, the 3D memory device further includes a peripheral circuit chip, the peripheral circuit chip including a substrate and a peripheral circuit layer, wherein the memory array chip is directly formed on the peripheral circuit layer, and wherein the first contact structure is located on a side of the memory array chip away from the peripheral circuit chip.

[0014] Another aspect of the present disclosure provides a method for forming a 3D memory device, comprising: forming a memory array chip, comprising the following steps: forming a substrate; forming a stack including alternating conductive layers and dielectric layers on the substrate; etching a groove through the stack, wherein the etching stops on the surface of the substrate; forming a memory layer along the sidewalls and bottom of the groove; and filling the groove with a conductive material; wherein the memory layer comprises: a first portion corresponding to a capacitor structure to be formed, the first portion comprising a first material; and a second portion corresponding to a transistor structure to be formed, the second portion comprising a second material different from the first material.

[0015] In some examples, forming the memory layer includes: depositing the first material; performing planarization to remove the first material on the surface of the stack; etching back the layer of the first material; and depositing the second material in a recess left after etching back the layer of the first material.

[0016] In some examples, the etch-back of the layer of the first material has a depth that spans across one of the conductive layers.

[0017] In some examples, the first material includes a ferroelectric material and the second material includes an oxide dielectric material.

[0018] In some examples, the first material includes a crystalline ferroelectric material and the second material includes an amorphous ferroelectric material.

[0019] In some examples, after filling the conductive material, the method further includes: performing a planarization operation to remove excess conductive material and the second material on the surface of the stack.

[0020] In some examples, the method further includes: forming a first contact hole and a second contact hole, the first contact hole exposing the conductive material and the second contact hole exposing the conductive layer in the stack; forming a spacer layer on the sidewalls of the second contact hole; and depositing a barrier layer on the sidewalls and bottoms of the first contact hole and the second contact hole and filling the contact material.

[0021] In some examples, the method further includes: forming a first bonding layer on the memory array chip; forming a peripheral circuit chip, the peripheral circuit chip including a second bonding layer; bonding the memory array chip to the peripheral circuit chip by bonding the first bonding layer to the second bonding layer, wherein the first contact structure in contact with the transistor structure is located on a side of the memory array chip close to the peripheral circuit chip or on a side of the memory array chip away from the peripheral circuit chip.

[0022] In some examples, the method further includes: forming a peripheral circuit chip before forming the memory array chip, the peripheral circuit chip comprising a second substrate and a peripheral circuit layer; and forming the memory array chip on the peripheral circuit layer, wherein a first contact structure in contact with the transistor structure is located on a side of the memory array chip away from the peripheral circuit chip.

[0023] Another aspect of the present disclosure provides a storage system, comprising: a storage device, which is configured to store data, and the storage device includes: a storage array chip, including: a stack including alternating conductive layers and dielectric layers; a storage structure extending vertically through the stack; wherein the storage structure includes a memory layer located at a sidewall of the storage structure, and a conductive material filled in the storage structure, and the storage structure includes a first side and a second side opposite to the first side; wherein the memory layer includes: a first portion corresponding to a capacitor structure, the first portion including a first material; and a second portion corresponding to a transistor structure, the second portion including a second material different from the first material; and a memory controller, the memory controller is coupled to the storage device and is configured to control the storage device.

[0024] Other aspects of the present disclosure may be understood by those skilled in the art based on the specification, claims, and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0026] Figure 1 shows a schematic diagram of a 3D memory device;

[0027] Figure 2 A schematic cross-sectional view of a memory array chip according to an embodiment of the present disclosure is shown;

[0028] Figure 3 A schematic cross-sectional view of a memory array chip according to another embodiment of the present disclosure is shown;

[0029] Figure 4 A flow chart showing a method for forming a memory array chip according to an embodiment of the present disclosure is shown;

[0030] Figure 5 A flow chart showing a method for forming a memory layer in a memory array chip according to an embodiment of the present disclosure is shown;

[0031] Figures 6A-6L A cross-sectional view showing a device structure at each process in a method for forming a memory array chip according to an embodiment of the present disclosure;

[0032] Fig. 7A and Figure 7B shows a cross-sectional view of a 3D memory device according to an embodiment of the present disclosure;

[0033] Figure 8shows a cross-sectional view of a 3D memory device according to another embodiment of the present disclosure;

[0034] Fig. 9 A block diagram of an exemplary system having a memory device according to an embodiment of the present disclosure is shown.

[0035] The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, in which like reference numerals identify corresponding elements throughout. In the accompanying drawings, like reference numerals generally indicate equivalent, functionally similar, and / or structurally similar elements. The figure in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference numeral.

[0036] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0037] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

[0038] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of a person skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments (whether or not explicitly described).

[0039] Generally, terms can be understood at least in part based on the context of use. For example, at least in part based on the context, the term "one or more" used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, at least in part based on the context, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage. In addition, again at least in part based on the context, the term "based on" can be understood to not necessarily be intended to convey a set of exclusive factors, and can instead allow for the presence of additional factors that are not necessarily explicitly described.

[0040] It should be easily understood that the terms “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only being directly on something, but also includes being on something with intervening features or layers therebetween, and such that “on” or “over” includes not only the meaning of being on or over something, but also includes the meaning of being on or over something with no intervening features or layers therebetween (i.e., directly on something).

[0041] In addition, spatially relative terms, such as "below," "below," "beneath," "above," "above," etc., may be used herein for ease of description to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0042] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned, or it can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, for example, silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0043] Figure 1 A schematic diagram of a 3D memory device 100 is shown. The 3D memory device 100 may represent an example of a bonded chip, or an example of a monolithic integrated memory device. In the former, components of the 3D memory device 100 (e.g., a memory array layer 104 and a peripheral circuit layer 102) may be formed on different substrates, respectively, and then combined to form a bonded chip. In the latter, the memory array layer 104 and the peripheral circuit layer 102 of the 3D memory device 100 may be integrated together, for example, after the peripheral circuit layer 102 is manufactured, the memory array layer 104 may be manufactured on a dielectric layer of the peripheral circuit layer 102. The 3D memory device 100 may include a substrate 101, a peripheral circuit layer 102 including a peripheral circuit, and a memory array layer 104 protecting a storage structure.

[0044] The peripheral circuits (or "control and sensing circuits") may include any suitable digital, analog and / or mixed signal circuits for facilitating the operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the above functional circuits, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor or a capacitor). According to some embodiments, the peripheral circuits in the peripheral circuit layer 102 may be implemented using complementary metal oxide semiconductor (CMOS) technology, for example, a logic process (e.g., a technology node of 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0045] like Figure 1 As shown, the 3D memory device 100 may include a memory array layer 104, which includes an array of memory cells (memory cell array) that can use transistors as switches and selection devices. In some embodiments, the memory cell array may include an array of DRAM cells. For ease of description, the present disclosure uses a DRAM cell array as an example to describe the memory cell array. However, it will be understood that the memory cell array is not limited to a DRAM cell array, and may include any other suitable type of memory cell array that can use transistors as switches and selection devices, such as a phase change memory (PCM) cell array, a static random access memory (SRAM) cell array, a ferroelectric random access memory (FRAM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array (to name a few), or any combination thereof.

[0046] The storage array layer 104 can be a DRAM device in which the storage cells are provided in the form of a DRAM cell array. In some embodiments, each DRAM cell includes a capacitor for storing a data bit as a positive charge or a negative charge, and one or more transistors (also referred to as pass transistors) that control (e.g., switch and select) access to the DRAM cell. In some embodiments, each DRAM cell is a one transistor, one capacitor (1T1C) cell. Since transistors always leak a small amount of charge, the capacitors discharge slowly, causing the information stored therein to be depleted. Therefore, according to some embodiments, for example, the DRAM cells must be refreshed by peripheral circuits in the peripheral circuit layer 102 to maintain the data.

[0047] At present, the storage density and size of the storage unit of the 1T1C structure are close to the process limit, and the leakage is significant and the retention time is short. Therefore, a new memory structure is needed to replace the 1T1C structure to increase storage density, reduce leakage, improve storage performance, and simplify the manufacturing process.

[0048] Note that the x, y, and z axes are included in Figure 1 1 to further illustrate the spatial relationship of the components in the 3D memory device 100. The substrate of the 3D memory device may include two lateral surfaces extending laterally in the xy plane: a top surface on the front side of the wafer on which semiconductor devices may be formed, and a bottom surface on the back side of the wafer opposite to the front side. The z-axis is perpendicular to the x-axis and the y-axis.

[0049] As used herein, when the substrate is located in the lowest plane of the 3D memory device in the z direction (a vertical direction perpendicular to the xy plane, for example, the thickness direction of the substrate), whether one component (for example, a layer or a device) of the 3D memory device is "before", "above" or "below" another component (for example, a layer or a device) in the z direction is determined relative to the substrate of the 3D memory device. The same concepts used to describe spatial relationships are applied throughout the present disclosure. In addition, in the description of the present disclosure, the term "depth" may be used to indicate a distance or length from a top surface or a bottom surface of a reference object (for example, a substrate) along the z direction.

[0050] Figure 2 FIG. 2 shows a schematic cross-sectional view of a memory array chip 200 according to an embodiment of the present disclosure. Figure 2 In an embodiment of the present invention, the memory array chip 200 includes a semiconductor substrate 201, a stack 210 including alternating conductive layers 202 and dielectric layers 204 located above the substrate 201, and a memory structure 220 extending vertically through the stack and extending to the substrate. In an embodiment, the semiconductor substrate 201 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI) or any other suitable semiconductor material. In some embodiments, the semiconductor substrate 201 may be a doped polysilicon substrate, for example, a P-type doped polysilicon substrate or an N-type doped polysilicon substrate. In an embodiment, the material of the dielectric layer 204 may include an insulating material, which may include at least one of silicon oxide, silicon nitride, doped silicon oxide, organic silicate glass and organic insulating material, but is not limited thereto. In an embodiment, the conductive material of the conductive layer 202 may include at least one of tungsten, cobalt, copper, aluminum, doped silicon and silicide, for example, but is not limited thereto.

[0051] In an embodiment, the storage structure 220 extends vertically through the stack 210 along the z direction and reaches the surface of the substrate 201. Figure 2 As shown, the memory structure 220 includes a memory layer located at the sidewall and bottom of the memory structure, and a conductive material 208 filled in the memory structure. For example, the conductive material 208 filled in the memory structure 220 may be polysilicon, but is not limited thereto. In this article, polysilicon is used as an example for explanation. In an embodiment, the memory layer located at the sidewall and bottom of the memory structure includes two parts, namely, a first part 212 corresponding to the final capacitor structure 242 and a second part 214 corresponding to the final transistor structure 241. Figure 2 In the illustrated embodiment, the second portion 214 includes a sidewall portion of the memory layer closer to the top of the memory structure 220, i.e., the second portion 214 is farther from the substrate 201 relative to the first portion 212, and the first portion 212 includes a sidewall portion and a bottom portion of the memory layer closer to the bottom of the memory structure 220, i.e., the first portion 212 is closer to the substrate 201 relative to the second portion 214. In an embodiment, the first portion includes a first material, and the second portion includes a second material, the second material being different from the first material.

[0052] In some embodiments, the first material used to form the capacitor structure may include a ferroelectric material, and the second material used to form the transistor structure may include an oxide dielectric material, such as a high-k dielectric material, such as aluminum oxide or hafnium oxide. In other embodiments, the first material used to form the capacitor structure may include a crystalline ferroelectric material, and the second material used to form the transistor structure may include an amorphous ferroelectric material.

[0053] exist Figure 2 In the illustrated embodiment, the second part of the memory layer used to form the transistor structure runs through a conductive layer 202, and the first part of the memory layer used to form the capacitor structure can run through a stack of several conductive layers 202 and dielectric layers 204, so that a structure in which a transistor and multiple capacitors are connected in series can be formed in the vertical direction, that is, a 3D1TnC storage structure, thereby improving the storage density. In addition, since ferroelectric materials are used as capacitor dielectrics in the capacitor structure to realize data storage and reading, the read and write speed is faster, the data retention is good, the power consumption is low, and the reliability is high, thereby improving the performance of the storage device. In addition, since the gate dielectric of the transistor can also be formed using ferroelectric materials, the switching speed of the transistor is improved, the power consumption is reduced, and the performance of the overall storage device is further greatly improved.

[0054] exist Figure 2In the illustrated embodiment, the memory array chip 200 further includes a plurality of contact structures. The contact structures include a first contact structure 226 in contact with one side of the memory structure 220, and a second contact structure 222 in contact with the conductive layer 202 of the stack 210. In an embodiment, the first contact structure 226 is in direct contact with the polysilicon on one side of the transistor structure 241 to form a drain contact of the transistor and one electrode plate of each capacitor connected in series below, and the second contact structure 222 is in contact with each conductive layer 202 of the stack 210 to form a gate contact of the transistor and another electrode plate of each capacitor.

[0055] Figure 3 FIG. 3 is a schematic cross-sectional view of a memory array chip 300 according to another embodiment of the present disclosure. The structure of the memory array chip 300 is substantially similar to that of the memory array chip 200, except that the position of the first portion 212 for forming the capacitor structure 242 is reversed from the position of the second portion 214 for forming the transistor structure 241. Figure 3 In an embodiment, the memory layer is located only on the sidewalls of the memory structure 220, but not on the bottom. In an embodiment, the first portion includes a first material, and the second portion includes a second material, the second material being different from the first material.

[0056] In some embodiments, the first material used to form the capacitor structure may include a ferroelectric material, and the second material used to form the transistor structure may include an oxide dielectric material, such as a high-k dielectric material, such as aluminum oxide or hafnium oxide. In other embodiments, the first material used to form the capacitor structure may include a crystalline ferroelectric material, and the second material used to form the transistor structure may include an amorphous ferroelectric material.

[0057] exist Figure 3 In the illustrated embodiment, the second portion of the memory layer for forming a transistor structure passes through a conductive layer 202, and the first portion of the memory layer for forming a capacitor structure can pass through a stack of several conductive layers 202 and dielectric layers 204, thereby forming a structure in which a transistor and multiple capacitors are connected in series in the vertical direction, that is, a 3D1TnC storage structure.

[0058] exist Figure 3In the illustrated embodiment, the memory array chip 300 further includes a plurality of contact structures. The contact structures include a first contact structure 226 in contact with one side of the memory structure 220, and a second contact structure 222 in contact with the conductive layer 202 of the stack 210. In an embodiment, the first contact structure 226 is in direct contact with the polysilicon on one side of the transistor structure 241 to form a drain contact of the transistor and one electrode plate of each capacitor connected in series therewith, and the second contact structure 222 is in contact with each conductive layer 202 of the stack 210 to form a gate contact of the transistor and another electrode plate of each capacitor.

[0059] It should be understood that in Figure 3 In the illustrated embodiment, the layer below the stack 210 is not a semiconductor substrate, but should be removed and replaced with another dielectric layer in a subsequent memory device formation process, and then the above-mentioned first contact structure 226 is formed in the dielectric layer.

[0060] Figure 4 The method for forming the Figure 2 A flow chart of a method 400 of the memory array chip 200 is shown. Figure 5 A flow chart of a method 500 for forming a memory layer in a memory array chip 200 according to an embodiment of the present disclosure is shown. Figures 6A-6L The cross-sectional view of the device at each process in the method of forming a memory array chip according to an embodiment of the present disclosure is shown. Figures 6A-6L The cross-sectional view of the device structure shown in Figure 4 and Figure 5 The method flow shown is explained.

[0061] Figure 4 The method 400 begins at operation 402, where a semiconductor substrate 201 is first provided. As described herein, the semiconductor substrate 201 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable semiconductor material. In some embodiments, the semiconductor substrate 101 may be a doped polysilicon substrate, for example, a P-type doped polysilicon substrate or an N-type doped polysilicon substrate.

[0062] The method 400 proceeds to operation 404, wherein a stack 210 of a conductive layer and a dielectric layer is formed on the semiconductor substrate 201, such as Fig. 6AAs shown. The stack 210 may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. The stack 210 includes a plurality of alternating conductive layers 202 and dielectric layers 204, that is, in addition to the top layer and the bottom layer of the stack 210, each conductive layer 202 may be sandwiched by two adjacent dielectric layers 204, and each dielectric layer 204 may be sandwiched by two adjacent conductive layers 202. As described herein, the material of the dielectric layer 204 may include an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, doped silicon oxide, organic silicate glass, and an organic insulating material.

[0063] Next, the method 400 proceeds to operation 406, where a trench 502 extending to the semiconductor substrate is formed through the stack 210, such as Figure 6B In some embodiments, the process of forming the trench 502 may include: forming the trench 502 penetrating the stack 210 and extending to the semiconductor substrate 201 by a dry / wet etching process, thereby exposing the surface of the substrate.

[0064] Next, the method 400 proceeds to operation 408, wherein a memory layer is formed along the sidewalls and bottom of the trench 502. As described herein, the memory layer includes two portions, namely a first portion 212 corresponding to the final capacitor structure 242 and a second portion 214 corresponding to the final transistor structure 241. In an embodiment, the first portion 212 includes a first material and the second portion 214 includes a second material, the second material being different from the first material. In some embodiments, the first material for forming the capacitor structure may include a ferroelectric material, and the second material for forming the transistor structure may include an oxide dielectric material, for example, a high-k dielectric material, such as aluminum oxide or hafnium oxide. In other embodiments, the first material for forming the capacitor structure may include a crystalline ferroelectric material, and the second material for forming the transistor structure may include an amorphous ferroelectric material.

[0065] Method 500 provides a method for forming a memory layer. Method 500 begins with operation 502, wherein a first material 512 for forming a capacitor structure is first deposited on the bottom and sidewalls of the trench 502 formed by operation 406, such as Figure 6C In an embodiment, the first material 512 may be formed in the trench 502 by one or more thin film deposition processes such as CVD, PVD, ALD or any combination thereof. Figure 6CAs shown, the first material 512 covers not only the bottom and sidewalls of the trench 502, but also the top surface of the stack 210. As described herein, the first material 512 used to form the capacitor structure may include a ferroelectric material. In other embodiments, the first material 512 used to form the capacitor structure may include a crystallized ferroelectric material.

[0066] Next, the method 500 proceeds to operation 504, where a planarization operation is performed to remove the first material on the surface of the stack. Fig.6D As shown, excess first material on the surface of the stack 210 may be removed after the first material 512 is deposited by performing a planarization process such as CMP.

[0067] Next, the method 500 proceeds to operation 506, wherein the first material on the sidewalls of the trench is etched back to a height lower than the top surface of the stack. Fig. 6E As shown, the first material 512 can be etched back by using a wet etching and / or dry etching process, so that the height of the first material 512 on the sidewall of the trench 502 is lower than the top surface of the stack 210, so that a portion of the stack 210 located at the sidewall of the trench 502 is exposed. In some embodiments, the depth of the etch back of the first material 512 is a depth corresponding to one conductive layer 202.

[0068] Next, the method 500 proceeds to operation 508, where a second material is deposited in the recess on the sidewall of the trench left by etching back the first material layer. Fig. 6F As shown, a second material 514 may be deposited along the sidewalls of the trench 502, i.e., on the exposed portion of the stack 210, by one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. As described herein, the second material 514 is different from the first material 512. In some embodiments, the second material used to form the transistor structure may include an oxide dielectric material, for example, a high-k dielectric material, such as aluminum oxide or hafnium oxide. In other embodiments, the second material used to form the transistor structure may include an amorphous ferroelectric material.

[0069] Back to Figure 4 , method 400 proceeds to operation 410, wherein the trench is filled with a conductive material. Figure 6G As shown, a conductive material 508, such as polysilicon, may be deposited in the trench by one or more thin film deposition processes including but not limited to CVD, PVD, ALD or any combination thereof. In an embodiment, at this time, the bottom and sidewalls of the trench are already lined with a memory layer including a first material 512 and a second material 514, and the polysilicon material is formed inside the memory layer.

[0070] Next, method 400 proceeds to operation 412 where a planarization operation is performed to remove excess material on top of the stack. Figure 6H As shown, the excess polysilicon 508 located above the top surface of the stack 210 may be removed by performing a planarization process such as CMP. Fig.6I As shown, excess second material 514 on the top surface of stack 210 can be further removed by performing a planarization process such as CMP, so that the top surface of the storage structure formed by first material 512, second material 514 and polysilicon material 508 is flush with the top surface of stack 210.

[0071] Finally, the formation Figure 2 The method of the memory array chip 200 further includes forming a contact structure. Figure 6J As shown, first Figure 6H A dielectric layer is deposited on the top surface of the structure shown, and then a wet etching and / or dry etching process can be used to etch openings 528 in the dielectric layer, and the positions of these openings 528 correspond to the positions where the first contact structure and the second contact structure are to be formed. In an embodiment, the first contact structure is in direct contact with the polysilicon on the side close to the second material 514 to form a drain contact of the transistor and one electrode plate of each capacitor connected in series below, and the second contact structure is in contact with each conductive layer 202 of the stack 210 to form a gate contact of the transistor and another electrode plate of each capacitor.

[0072] like Figure 6K As shown, a spacer layer 530 may be deposited on the sidewalls of the opening 528 by one or more thin film deposition processes including but not limited to CVD, PVD, ALD or any combination thereof. In an embodiment, the spacer layer may include an insulating material including silicon oxide, silicon nitride, doped silicon oxide, etc.

[0073] like Figure 6L As shown, a dielectric layer 552 can be deposited on the sidewalls and bottom of the opening 528 lined with the spacer layer 530 by one or more thin film deposition processes including but not limited to CVD, PVD, ALD or any combination thereof, and then a conductive layer 522 is deposited to fill the opening, so that the first contact structure and the second contact structure can be formed simultaneously in the same process flow.

[0074] Through the above process flow, it is achieved that the transistor and capacitor elements of the 1TnC structure of the 3D DRAM memory device are formed in one go by using the same process flow, thereby greatly simplifying the overall architecture of the 3D DRAM memory device and its formation process, and reducing the process cost.

[0075] Fig. 7A and Figure 7B 1 shows a cross-sectional view of a 3D memory device according to an embodiment of the present disclosure. Fig. 7A As shown, a 3D memory device 700 is shown, which includes a memory array chip 602 and a peripheral circuit chip 604. As mentioned above, the memory device 700 is formed by bonding, wherein the memory array chip 602 and the peripheral circuit chip 604 can be formed on different substrates respectively, and then bonded together in a face-to-face manner by flip chip bonding or the like to form a bonded chip. Fig. 7A As shown, there is a bonding interface 644 between the memory array chip 602 and the peripheral circuit chip 604, and a large number of interconnections (e.g., bonding contacts) can be formed through the bonding interface 644 to make direct, short-distance (e.g., micrometer-level) electrical connections between the memory array chip 602 and the peripheral circuit chip 604. According to some embodiments, the bonding interface 644 is vertically formed between the memory array chip 602 and the peripheral circuit chip 604 in the 3D memory device 700, and the memory array chip 602 and the peripheral circuit chip 604 are vertically joined by bonding (e.g., hybrid bonding). Hybrid bonding, also known as "metal / dielectric hybrid bonding", is a direct bonding technology (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) and can simultaneously obtain metal-metal (e.g., copper to copper) bonding and dielectric-dielectric (e.g., silicon oxide to silicon oxide) bonding. Data transmission between the memory cell array in the memory array chip 602 and the peripheral circuit in the peripheral circuit chip 604 may be performed through interconnections (eg, bonding contacts) across the bonding interface 644 .

[0076] exist Fig. 7A In the embodiment shown, the structure of the storage array chip 602 is similar to Figure 2 The structure of the memory array chip 200 is shown in FIG. Note that since the memory array chip 602 is bonded to the peripheral circuit chip 604 by flip chip bonding, Figure 2 The bottom of the storage structure shown in Fig. 7A becomes the top of the storage device, Figure 2 The top of the storage structure shown in Fig. 7A The memory array chip 602 includes a stack composed of alternating conductive layers and dielectric layers, and a memory structure 220 extending vertically through the stack. The memory structure 220 includes a memory layer located on the sidewall and top of the memory structure, and a conductive material 208 filled in the memory structure. In an embodiment, the memory layer located on the sidewall and top of the memory structure 220 includes two parts, namely, a first part 212 corresponding to the final capacitor structure and a second part 214 corresponding to the final transistor structure. Fig. 7AAs shown, the memory structure 220 includes a first side and a second side opposite to the first side, wherein the first side is a side close to the peripheral circuit chip, and the second side is a side away from the peripheral circuit chip. In an embodiment, the second portion 214 includes a sidewall portion of the memory layer closer to the first side of the memory structure 220 and penetrates a conductive layer, that is, the second portion 214 is closer to the peripheral circuit chip relative to the first portion 212, and the first portion 212 includes a sidewall portion and a top portion of the memory layer closer to the second side of the memory structure 220 and penetrates one or more conductive layers, that is, the first portion 212 is farther away from the peripheral circuit chip relative to the second portion 214. . In an embodiment, the first portion includes a first material, and the second portion includes a second material, and the second material is different from the first material.

[0077] like Fig. 7A As shown, the first contact structure directly contacts the polysilicon on the second material 214 side of the storage structure 220 on the first side, thereby leading out the drain of the transistor. The second contact structures are respectively in contact with the conductive layers in the stack. Subsequently, the first contact structure and the second contact structure are respectively electrically connected to the peripheral circuit in the peripheral circuit chip 604 through interconnection, bonding contacts, etc.

[0078] Figure 7B A 3D memory device 720 is shown, which includes a memory array chip 602 and a peripheral circuit chip 604. As described above, the memory device 700 is formed by bonding, wherein the memory array chip 602 and the peripheral circuit chip 604 can be formed on different substrates, respectively, and then bonded together in a face-to-face manner by flip chip bonding or the like to form a bonded chip.

[0079] Figure 7B The 3D memory device 720 is shown with Fig. 7A The 3D memory device 700 shown in FIG. 1 is substantially similar to the 3D memory device 700 shown in FIG. 1 , except that the structure of the memory array chip 602 in the 3D memory device 720 is similar to that in FIG. Figure 3The structure of the memory array chip 300 shown in . Compared with the memory array chip 200, the position of the first portion 212 for forming the capacitor structure 242 is upside down from the position of the second portion 214 for forming the transistor structure 241, and the memory layer is only located on the sidewall of the memory structure 220. In an embodiment, the memory structure 220 includes a first side and a second side opposite to the first side, wherein the first side is a side close to the peripheral circuit chip, and the second side is a side away from the peripheral circuit chip. In an embodiment, the first portion 212 includes a sidewall portion of the memory layer closer to the first side of the memory structure 220 and penetrates one or more conductive layers, that is, the first portion 212 is closer to the peripheral circuit chip relative to the second portion 214, and the second portion 214 includes a sidewall portion of the memory layer closer to the second side of the memory structure 220 and penetrates a conductive layer, that is, the second portion 214 is farther away from the peripheral circuit chip relative to the first portion 212. . The first portion includes a first material, and the second portion includes a second material, the second material being different from the first material. As Figure 7B As shown, the first contact structure directly contacts the polysilicon on the second material 214 side of the memory structure 220 on the second side, thereby leading out the drain of the transistor. The second contact structures are respectively in contact with the conductive layers in the stack.

[0080] Figure 8 FIG. 8 shows a cross-sectional view of a 3D memory device 800 according to another embodiment of the present disclosure. Figure 8 As shown, the 3D memory device 800 includes a memory array chip 702 and a peripheral circuit chip 704. As described above, the 3D memory device 800 may be a monolithic integrated memory device, wherein the memory array chip 702 and the peripheral circuit chip 704 may be integrated together, for example, after the peripheral circuit chip 704 is manufactured, the memory array chip 702 may be directly manufactured on the dielectric layer of the peripheral circuit chip 704.

[0081] exist Figure 8 In the embodiment shown, the structure of the storage array chip 702 is similar to Figure 2 The structure of the memory array chip 200 shown in FIG. Specifically, the memory array chip 702 includes a stack composed of alternating conductive layers and dielectric layers, and a memory structure 220 extending vertically through the stack. The memory structure 220 includes a memory layer located at the sidewall and bottom of the memory structure, and a conductive material 208 filled in the memory structure. In an embodiment, the memory layer located at the sidewall and bottom of the memory structure 220 includes two parts, namely, a first part 212 corresponding to the final capacitor structure and a second part 214 corresponding to the final transistor structure. Figure 8As shown, the storage structure 220 includes a first side and a second side opposite to the first side, wherein the first side is a side close to the peripheral circuit chip, and the second side is a side away from the peripheral circuit chip. In an embodiment, the first portion 212 includes a sidewall portion and a bottom portion of the memory layer closer to the first side of the storage structure 220 and penetrates one or more conductive layers, that is, the first portion 212 is closer to the peripheral circuit chip relative to the second portion 214, and the second portion 214 includes a sidewall portion of the memory layer closer to the second side of the storage structure 220 and penetrates a conductive layer, that is, the second portion 214 is closer to the peripheral circuit chip relative to the first portion 212. In an embodiment, the first portion includes a first material, and the second portion includes a second material, and the second material is different from the first material. Figure 8 As shown, the first contact structure directly contacts the polysilicon on the second material 214 side of the memory structure 220 on the second side, thereby leading out the drain of the transistor. The second contact structures are respectively in contact with the conductive layers in the stack.

[0082] Fig. 9 1 is a block diagram of an exemplary system 900 having a storage device according to an embodiment of the present disclosure. The system 900 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Fig. 9 As shown, the system 900 may include a host 908 and a memory system 902 having one or more memory devices 904 and a memory controller 906. The host 908 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 908 may be configured to send data to the memory device 904 or receive data from the memory device 904.

[0083] The memory device 904 may be any memory device disclosed herein, such as the 3D memory devices 700, 720, and 800. In some embodiments, the memory device 904 includes a memory array chip, the memory array chip including: a stack including alternating conductive layers and dielectric layers; a memory structure extending vertically through the stack; wherein the memory structure includes a memory layer located at a sidewall of the memory structure, and a conductive material filled in the memory structure, and the memory structure includes a first side and a second side opposite to the first side; wherein the memory layer includes: a first portion corresponding to a capacitor structure, the first portion including a first material; and a second portion corresponding to a transistor structure, the second portion including a second material different from the first material.

[0084] According to some embodiments, the memory controller 906 is coupled to the memory device 904 and the host 908 and is configured to control the memory device 904. The memory controller 906 can manage data stored in the memory device 904 and communicate with the host 908. The memory controller 906 can be configured to control the operation of the memory device 904, such as read, write, and refresh operations. The memory controller 906 can also be configured to manage various functions related to the data stored or to be stored in the memory device 904, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0085] In some embodiments, the memory controller 906 may also be configured to determine the maximum storage capacity, the number of memory banks, the memory type and speed, the memory particle data depth and data width, and other important parameters that the computer system can use. The memory controller 906 may also perform any other suitable function. The memory controller 906 may communicate with an external device (e.g., the host 908) according to a specific communication protocol. For example, the memory controller 906 may communicate with an external device through at least one of various interface protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a minicomputer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0086] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0087] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional storage device, comprising: Storage array chips, including: A stack comprising alternating conductive and dielectric layers; a storage structure extending vertically through the stack; The storage structure includes a memory layer located at a sidewall of the storage structure, and a conductive material filled in the storage structure, and the storage structure includes a first side and a second side opposite to the first side; Wherein, the memory layer comprises: corresponding to a first portion of the capacitor structure, the first portion comprising a first material; and Corresponding to a second portion of the transistor structure, the second portion includes a second material different from the first material.

2. The three-dimensional memory device according to claim 1, wherein: The first material comprises a ferroelectric material and the second material comprises an oxide dielectric material.

3. The three-dimensional memory device according to claim 1, wherein: The first material comprises a crystalline ferroelectric material and the second material comprises an amorphous ferroelectric material.

4. The three-dimensional memory device according to any one of claims 1 to 3, wherein: The second portion penetrates through one of the conductive layers.

5. The three-dimensional memory device according to claim 1, further comprising: a first contact structure in contact with one side of the storage structure; as well as The second contact structure contacts the conductive layer of the stack.

6. The three-dimensional memory device according to claim 5, wherein: The first contact structure contacts the first side of the memory structure, and the second portion of the memory layer is closer to the first side than the first portion, wherein the first material is also located on the second side of the memory structure.

7. The three-dimensional memory device according to claim 5, wherein: The first contact structure contacts the second side of the memory structure, and the second portion of the memory layer is closer to the second side than the first portion.

8. The three-dimensional memory device according to claim 6 or 7, wherein: The memory array chip is provided with a first bonding layer, and the three-dimensional memory device further comprises: A peripheral circuit chip including a second bonding layer; The first bonding layer of the memory array chip is bonded to the second bonding layer of the peripheral circuit chip, and Wherein, when the first contact structure contacts the first side of the storage structure, the first contact structure is located on a side of the storage array chip close to the peripheral circuit chip, When the first contact structure contacts the second side of the memory structure, the first contact structure is located on a side of the memory array chip away from the peripheral circuit chip.

9. The three-dimensional memory device according to claim 6, further comprising a peripheral circuit chip, the peripheral circuit chip comprising a substrate and a peripheral circuit layer, wherein: The memory array chip is directly formed on the peripheral circuit layer, and Wherein, the first contact structure is located on a side of the memory array chip away from the peripheral circuit chip.

10. A method of forming a three-dimensional memory device, comprising: Forming a storage array chip includes the following steps: forming a substrate; forming a stack comprising alternating conductive and dielectric layers on the substrate; etching a trench through the stack, the etching stopping on a surface of the substrate; forming a memory layer along the sidewalls and bottom of the trench; and filling the groove with a conductive material; Wherein, the memory layer comprises: corresponding to a first portion that will form a capacitor structure, the first portion comprising a first material; and Corresponding to a second portion where a transistor structure will be formed, the second portion includes a second material different from the first material.

11. The method according to claim 10, wherein: Forming the memory layer includes: depositing the first material; performing planarization to remove the first material on the surface of the stack; etching back the layer of the first material; and The second material is deposited in the recess left after etching back the layer of the first material.

12. The method according to claim 11, wherein: The depth of the etch back performed on the layer of the first material spans across one of the conductive layers.

13. The method according to claim 10, wherein: The first material comprises a ferroelectric material and the second material comprises an oxide dielectric material.

14. The method according to claim 10, wherein: The first material comprises a crystalline ferroelectric material and the second material comprises an amorphous ferroelectric material.

15. The method according to claim 11, wherein: After filling the conductive material, the method further comprises: A planarization operation is performed to remove excess of the conductive material and the second material on the surface of the stack.

16. The method according to claim 10, further comprising: forming a first contact hole and a second contact hole, wherein the first contact hole exposes the conductive material, and the second contact hole exposes the conductive layer in the stack; forming a spacer layer on a sidewall of the second contact hole; as well as A barrier layer is deposited on the sidewalls and bottoms of the first contact hole and the second contact hole and filled with a contact material.

17. The method according to claim 10, further comprising: forming a first bonding layer on the memory array chip; forming a peripheral circuit chip, the peripheral circuit chip comprising a second bonding layer; The memory array chip is bonded to the peripheral circuit chip by bonding the first bonding layer to the second bonding layer, The first contact structure in contact with the transistor structure is located on a side of the memory array chip close to the peripheral circuit chip or on a side of the memory array chip far from the peripheral circuit chip.

18. The method according to claim 10, further comprising: Before forming the memory array chip, a peripheral circuit chip is formed, wherein the peripheral circuit chip includes a second substrate and a peripheral circuit layer; as well as forming the memory array chip on the peripheral circuit layer, Wherein, the first contact structure in contact with the transistor structure is located on a side of the memory array chip away from the peripheral circuit chip.

19. A storage system comprising: A storage device, the storage device being configured to store data, the storage device comprising: Storage array chips, including: A stack comprising alternating conductive and dielectric layers; a storage structure extending vertically through the stack; The storage structure includes a memory layer located at a sidewall of the storage structure, and a conductive material filled in the storage structure, and the storage structure includes a first side and a second side opposite to the first side; Wherein, the memory layer comprises: corresponding to a first portion of the capacitor structure, the first portion comprising a first material; and corresponding to a second portion of the transistor structure, the second portion comprising a second material different from the first material; and A memory controller is coupled to the memory device and is configured to control the memory device.

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