Method for forming memory structure

Abstract

A method for forming a memory structure includes: providing a substrate comprising a base and several active areas with isolation layers between the active areas; forming several memory gate structures, with a first spacing trench or a second spacing trench between adjacent memory gate structures, the first spacing trench having a width smaller than the second spacing trench; forming a first barrier layer, a second barrier layer, and a third barrier layer, wherein the second barrier layer completely fills the first spacing trench but does not completely fill the second spacing trench; the third barrier layer exposes the top surface of the second barrier layer within the first spacing trench; using a wet etching process to remove the second and first barrier layers within the first spacing trench and the isolation layer exposed by the first spacing trench; and forming a source doping layer within the active area and the base exposed by the first spacing trench. By varying the spacing trench sizes and combining planarization treatment to reduce process mask counts, wet etching is used to reduce etching damage to the memory gate structures, thereby improving device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a memory structure. Background Art

[0002] NOR flash memory, developed based on Intel's ETOX structure, is a non-volatile memory that retains stored data even after the chip loses power. NOR flash memory is a voltage-controlled device that uses hot electron injection to write data and tunneling to erase data. Its notable feature is its high random read speed. As a non-volatile memory, NOR flash memory offers advantages such as non-volatility, high device density, low power consumption, and electrical rewritability. It is widely used in portable electronic products such as mobile phones, digital cameras, and smart cards.

[0003] The structure of a Flash memory cell is similar to that of a MOS device, with a floating gate and dielectric layer used to store charge. The access of electrons to and from the floating gate causes the device threshold voltage to change, thereby indicating the state of the Flash memory cell. The NorFlash array is connected together by horizontal gates, called word lines. The drains are connected to vertical metal strips, called bit lines, through contact holes. The sources of two adjacent devices are connected together to form a horizontal source line.

[0004] However, existing Nor Flash devices still have many problems during their formation. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a memory structure, so as to reduce process masks and improve the performance of the device structure.

[0006] To solve the above problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate, the substrate comprising a base, and a plurality of active areas arranged in parallel along a first direction on the base, the active areas extending along a second direction, the first direction being perpendicular to the second direction, and isolation trenches being provided between adjacent active areas; forming an isolation layer in the isolation trenches; forming a plurality of memory gate structures arranged in parallel along the second direction on the substrate, the memory gate structures spanning the plurality of active areas along the first direction, the memory gate structures comprising a floating gate structure and a control gate structure located on the floating gate structure, a first spacing trench being provided between some adjacent memory gate structures, and a second spacing trench being provided between some adjacent memory gate structures, the first spacing trench and the second spacing trench respectively exposing a portion of the top surface of the active area and a portion of the top surface of the isolation layer, and along the second direction, the width dimension of the first spacing trench is smaller than the width dimension of the second spacing trench; and forming a plurality of memory gate structures on the sidewalls and bottom surfaces of the first spacing trench, the sidewalls and A first barrier layer is formed on the bottom surface and the top surfaces of several of the storage gate structures; a second barrier layer is formed on the surface of the first barrier layer, the material of the second barrier layer is different from the material of the first barrier layer, the second barrier layer fills the first spacing groove and does not fill the second spacing groove; a third barrier material layer is formed on the surface of the second barrier layer, the material of the third barrier material layer is different from the material of the second barrier layer; the third barrier material layer is planarized until the surface of the second barrier layer is exposed, thereby forming a third barrier layer, the third barrier layer exposes the top surface of the second barrier layer located in the first spacing groove; a wet etching process is used to remove the second barrier layer and the first barrier layer located in the first spacing groove, and the isolation layer exposed by the first spacing groove is removed until the substrate is exposed; after removing the isolation layer, a first ion implantation process is performed on the active area and the substrate exposed by the first spacing groove to form a source doping layer, and the source doping layer extends along the first direction.

[0007] Optionally, the floating gate structure includes: a tunneling oxide layer, and a floating gate layer located on the tunneling oxide layer.

[0008] Optionally, the control gate structure includes: a gate dielectric layer, and a control gate layer located on the gate dielectric layer.

[0009] Optionally, the method for forming the storage gate structure includes: forming a tunneling oxide material layer on the substrate and the isolation layer; forming a floating gate material layer on the tunneling oxide material layer; forming a gate dielectric material layer on the floating gate material layer; forming a control gate material layer on the gate dielectric material layer; forming a patterned layer on the control gate material layer, the patterned layer exposing a portion of the top surface of the control gate material layer; etching a portion of the control gate material layer, the gate dielectric material layer, the floating gate material layer and the tunneling oxide material layer using the patterned layer as a mask until the top surface of the substrate and the top surface of the isolation layer are exposed to form the storage gate structure; after forming the storage gate structure, removing the patterned layer.

[0010] Optionally, the gate dielectric layer includes: a single-layer structure or a multi-layer structure.

[0011] Optionally, when the gate dielectric layer is a multi-layer structure, the gate dielectric layer includes: a first oxide layer, a nitride layer located on the first oxide layer, and a second oxide layer located on the nitride layer.

[0012] Optionally, materials of the floating gate layer and the control gate layer are both semiconductor materials.

[0013] Optionally, the semiconductor material includes: polysilicon.

[0014] Optionally, the material of the first barrier layer is the same as that of the third barrier material layer; and the material of the second barrier layer is the same as that of the isolation layer.

[0015] Optionally, the material of the first barrier layer and the material of the third barrier material layer include silicon nitride; and the material of the second barrier layer includes silicon oxide.

[0016] Optionally, the wet etching process includes: a first wet etching process, the first wet etching process is used to remove the second barrier layer located in the first spacing groove; a second wet etching process, the second wet etching process is used to remove the first barrier layer located in the first spacing groove; and a third wet etching process, the third wet etching process is used to remove the isolation layer exposed by the first spacing groove.

[0017] Optionally, the etching solution of the first wet etching process includes hydrofluoric acid; the etching solution of the second wet etching process includes phosphoric acid; and the etching solution of the third wet etching process includes hydrofluoric acid.

[0018] Optionally, after removing the isolation layer, the first barrier layer located on the bottom surface and sidewall of the second spacing groove is used as a mask to perform the first ion implantation process on the first spacing groove exposing the active area and the substrate to form the source doping layer.

[0019] Optionally, the planarization process includes a chemical mechanical polishing process.

[0020] Optionally, after forming the storage gate structure and before forming the first blocking layer, it also includes: forming a lightly doped region in the active region exposed by the first spacing groove and the active region exposed by the second spacing groove, the lightly doped region having second ions, and the electrical type of the first ions is the same as the electrical type of the second ions.

[0021] Optionally, after forming the source doping layer, it also includes: removing the first barrier layer located in the second spacing groove; forming a sidewall structure on the sidewall of the storage gate structure; after forming the sidewall structure, forming a drain doping layer in the active area exposed by the second spacing groove, the drain doping layer having a third ion, and the electrical type of the third ion is the same as the electrical type of the first ion.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the method for forming a memory structure according to the technical solution of the present invention, the characteristic that the width of the first spacing trench is smaller than the width of the second spacing trench along the second direction is utilized to ensure that the second barrier layer is fully filled in the first spacing trench but not fully filled in the second spacing trench. Combined with the planarization process, the third barrier layer is formed to expose only the top surface of the second barrier layer within the first spacing trench. Subsequent wet etching, utilizing the characteristic that different materials have different etch rates, ensures that only the isolation layer exposed by the first spacing trench is removed. This process saves a photomask step, thereby reducing process costs. Furthermore, because the wet etching process does not have a bombardment effect, the removal of the second, first, and isolation layers by the wet etching process does not cause excessive etching damage to the memory gate structure, effectively improving device performance. Furthermore, the wet etching process produces less residue, effectively preventing excessive residue accumulation on the source doped region, which could increase its resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1 to 4 It is a schematic structural diagram of each step of a method for forming a memory structure;

[0025] Figures 5 to 19 1 is a schematic structural diagram of each step of a method for forming a memory structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] As described in the background art, existing Nor Flash devices still have many problems during their formation, which will be described in detail below with reference to the accompanying drawings.

[0027] Figures 1 to 4 The present invention is a schematic structural diagram of each step of a method for forming a memory structure.

[0028] Please refer to Figures 1 to 3 , Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA, Figure 3 yes Figure 1 A cross-sectional diagram along line BB in FIG. 1 provides a substrate, the substrate comprising a base 100, and a plurality of active regions 101 arranged in parallel along a first direction X on the base 100, the active regions 101 extending along a second direction Y, the first direction X being perpendicular to the second direction Y, and isolation trenches (not shown) being provided between adjacent active regions 101; an isolation layer 102 being formed in the isolation trenches; and a plurality of storage gate structures 103 arranged in parallel along the second direction Y being formed on the substrate, the storage gate structures 103 spanning the plurality of active regions 101 along the first direction X. The storage gate structure 103 includes a floating gate structure (not labeled) and a control gate structure (not labeled) located on the floating gate structure. A first spacing groove 104 is provided between some adjacent storage gate structures 103, and a second spacing groove 105 is provided between some adjacent storage gate structures 103. The first spacing groove 104 and the second spacing groove 105 respectively expose part of the top surface of the active area 101 and part of the top surface of the isolation layer 102. Along the second direction Y, the width dimension d1 of the first spacing groove 104 is smaller than the width dimension d2 of the second spacing groove 105.

[0029] Please refer to Figure 4 , Figure 4 and Figure 2A sacrificial layer (not shown) is formed on the substrate, the sacrificial layer covering a plurality of the storage gate structures 103, and the sacrificial layer exposing the first spacing groove 104; using the sacrificial layer as a mask, a dry etching process is adopted to remove the isolation layer 102 exposed by the first spacing groove 104 until the base 100 is exposed; after removing the isolation layer 102, a first ion implantation process is performed on the active area 101 and the base 100 exposed by the first spacing groove 104 to form a source doping layer 106, and the source doping layer 106 extends along the first direction X.

[0030] In this embodiment, based on the circuit design of the device structure, the source doping layers 106 of the various storage gate structures 103 need to be connected together to form a common source terminal, while the drain doping layers of the various storage gate structures 103 do not need to be connected together. Since the source doping layers 106 are formed using an ion implantation process, if the isolation layer 102 between adjacent active areas 101 is not removed, it is difficult for the ions to be implanted into the substrate 100, thereby preventing the formed source doping layers 106 from being connected to form an integral structure.

[0031] In this process, the sacrificial layer is formed by a photomask process, and the sacrificial layer only exposes the position where the source doping layer 106 needs to be formed. However, the use of a photomask process to form the sacrificial layer will increase the process cost. In addition, a dry etching process is used to remove the isolation layer 102 exposed by the first spacing groove 104. Since the dry etching process contains bombarding etching particles, the active area 101 and the storage gate structure 103 will also be etched to a certain extent during the removal of the isolation layer 102. In particular, for the storage gate structure 103, the dry etching process is likely to cause etching damage to the control gate layer in the storage gate structure 103, thereby forming an inclined surface (such as Figure 4 As shown in part A in the figure, metal silicide needs to be formed on the surface of the control gate layer subsequently. When the size of the device structure becomes smaller and smaller, the metal silicide located on the inclined surface of the control gate layer is very close to the floating gate layer and the gate dielectric layer in the storage gate structure 103, which can easily cause leakage or short circuit.

[0032] Based on this, the present invention provides a method for forming a memory structure. This method utilizes the characteristic that the width of the first spacing trench is smaller than the width of the second spacing trench along the second direction, so that the second barrier layer can be fully filled in the first spacing trench but not fully filled in the second spacing trench. Combined with the planarization process, the third barrier layer is formed to expose only the top surface of the second barrier layer within the first spacing trench. Subsequent wet etching, utilizing the characteristic that different materials have different etch rates, ensures that only the isolation layer exposed by the first spacing trench is removed. This process saves a photomask step, thereby reducing process costs. Furthermore, because the wet etching process does not have a bombardment effect, the removal of the second, first, and isolation layers by the wet etching process does not cause excessive etching damage to the memory gate structure, effectively improving device performance. Furthermore, the wet etching process produces less residue, effectively preventing excessive residue accumulation on the source doped region, which could increase the resistance of the source doped region.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figures 5 to 19 1 is a schematic structural diagram of each step of a method for forming a memory structure in an embodiment of the present invention.

[0035] Please refer to Figure 5 and Figure 6 , Figure 6 yes Figure 5 In the cross-sectional diagram along line CC, a substrate is provided, which includes a base 200 and a plurality of active areas 201 arranged in parallel along a first direction X on the base 200. The active areas 201 extend along a second direction Y, and the first direction X is perpendicular to the second direction Y. Isolation trenches 202 are provided between adjacent active areas 201.

[0036] In this embodiment, the material of the substrate is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0037] In this embodiment, the method for forming the substrate includes: providing an initial substrate (not shown); and performing patterning on the initial substrate to form the substrate.

[0038] Please refer to Figure 7 , Figure 7 and Figure 6 In the same viewing direction, an isolation layer 203 is formed in the isolation trench 202.

[0039] In this embodiment, the method for forming the isolation layer 203 includes: forming an isolation material layer (not shown) in the isolation trench 202 and on the substrate; and etching back the isolation material layer until the top surface of the substrate is exposed to form the isolation layer 203.

[0040] In this embodiment, the isolation layer 203 is made of silicon oxide.

[0041] Please refer to Figure 8 and Figure 9 , Figure 9 yes Figure 8 In the cross-sectional schematic diagram along line DD, a plurality of storage gate structures 204 arranged in parallel along the second direction Y are formed on the substrate, and the storage gate structures 204 span the plurality of active areas 201 along the first direction X. The storage gate structures 204 include a floating gate structure (not labeled) and a control gate structure (not labeled) located on the floating gate structure. A first spacing groove 205 is provided between some adjacent storage gate structures 204, and a second spacing groove 206 is provided between some adjacent storage gate structures 204. The first spacing groove 205 and the second spacing groove 206 expose a portion of the top surface of the active area 201 and a portion of the top surface of the isolation layer 203, respectively. Along the second direction Y, a width dimension d1 of the first spacing groove 205 is smaller than a width dimension d2 of the second spacing groove 206.

[0042] In this embodiment, the floating gate structure includes: a tunneling oxide layer and a floating gate layer located on the tunneling oxide layer.

[0043] In this embodiment, the control gate structure includes: a gate dielectric layer and a control gate layer located on the gate dielectric layer.

[0044] In this embodiment, the method for forming the storage gate structure 204 includes: forming a tunneling oxide material layer (not shown) on the substrate and the isolation layer 203; forming a floating gate material layer (not shown) on the tunneling oxide material layer; forming a gate dielectric material layer (not shown) on the floating gate material layer; forming a control gate material layer (not shown) on the gate dielectric material layer; forming a patterned layer (not shown) on the control gate material layer, the patterned layer exposing a portion of the top surface of the control gate material layer; etching a portion of the control gate material layer, the gate dielectric material layer, the floating gate material layer and the tunneling oxide material layer using the patterned layer as a mask until the top surface of the substrate and the top surface of the isolation layer are exposed, thereby forming the storage gate structure 204; after forming the storage gate structure, removing the patterned layer.

[0045] In this embodiment, the gate dielectric layer is a multi-layer structure. Specifically, the gate dielectric layer includes: a first oxide layer, a nitride layer located on the first oxide layer, and a second oxide layer located on the nitride layer.

[0046] When the gate dielectric layer is a multi-layer structure, the first silicon oxide layer and the second silicon oxide layer in the gate dielectric layer can be better combined with the base crystal, and the silicon nitride layer is in the middle, which can block the extension of defects (such as pinholes). Therefore, the three-layer structure design can complement the deficiencies.

[0047] In other embodiments, the gate dielectric layer may also be a single-layer structure.

[0048] In this embodiment, the floating gate layer and the control gate layer are both made of semiconductor materials, specifically polysilicon.

[0049] Please refer to Figure 10 , Figure 10 and Figure 9 In accordance with the viewing direction, a lightly doped region 207 is formed in the active region 201 exposed by the first spacing groove 205 and in the active region 201 exposed by the second spacing groove 206, and the lightly doped region 207 has second ions, and the electrical type of the first ions is the same as the electrical type of the second ions.

[0050] For Nor Flash devices, to obtain the required drive current and suppress the short channel effect, a substrate and source / drain with a higher doping concentration are usually used, thereby generating a high electric field in the depletion region of the source / drain. When the high-voltage input / output device operates at saturation current, the charges in the inversion layer are accelerated by the lateral electric field on the channel surface and collide with the lattice to ionize, generating a large number of hot carriers (electron-hole pairs). Hot electrons and hot holes can cross the interface barrier and be emitted into the gate dielectric layer, forming a hot carrier injection effect (HCI). Hot carriers entering the gate dielectric layer have the following effects: an increase in threshold voltage, a decrease in saturation drive current, and a decrease in carrier mobility. At the same time, hot electrons or hot holes can also be affected by the junction electric field and enter the substrate, forming substrate leakage current. The above effects caused by hot carriers can seriously affect the operating characteristics and reliability of the device.

[0051] Therefore, in order to improve the hot carrier injection effect problem, the lightly doped drain (LDD) 207 is formed for optimization, and the performance of the device structure is improved by reducing the dose of the second ion implantation in the lightly doped drain 207 and increasing the implantation energy of the second ion.

[0052] It should be noted that, in this embodiment, since the lightly doped region 207 needs to be formed at both the source end and the drain end, a photomask is not required during the process of implanting the second ions.

[0053] Please refer to Figure 11 A first barrier layer 208 is formed on the sidewalls and bottom surfaces of the first spacing trench 205 , the sidewalls and bottom surfaces of the second spacing trench 206 , and the top surfaces of several of the storage gate structures 204 .

[0054] In this embodiment, since the first barrier layer 208 needs to cover the surface of each of the memory gate structures 204 , a chemical vapor deposition process with good step coverage needs to be adopted.

[0055] In this embodiment, the first barrier layer 208 is made of silicon nitride.

[0056] Please refer to Figure 12 A second barrier layer 209 is formed on the surface of the first barrier layer 208 . The material of the second barrier layer 209 is different from that of the first barrier layer 208 . The second barrier layer 209 fills the first spacing groove 205 but does not fill the second spacing groove 206 .

[0057] In this embodiment, the material of the second barrier layer 209 is the same as that of the isolation layer 203 , and the material of the second barrier layer 209 is silicon oxide.

[0058] Please refer to Figure 13 A third barrier material layer 210 is formed on the surface of the second barrier layer 209 . The material of the third barrier material layer 210 is different from that of the second barrier layer 209 .

[0059] In this embodiment, since the first spacing groove 205 has been fully filled with the second barrier layer 209, and the second spacing groove 206 has not been fully filled with the second barrier layer 209, the morphology of the formed third barrier material layer 210 is also stepped, wherein the third barrier material layer 210 located above the first spacing groove 205 is at the highest position and will be removed first in the subsequent planarization process.

[0060] In this embodiment, the material of the first barrier layer 208 is the same as that of the third barrier material layer 210 , and the material of the third barrier material layer 210 is silicon nitride.

[0061] Please refer to Figure 14The third barrier material layer 210 is planarized until the surface of the second barrier layer 209 is exposed, thereby forming a third barrier layer 211 . The third barrier layer 211 exposes the top surface of the second barrier layer 206 located in the first spacing groove 205 .

[0062] In this embodiment, the planarization process adopts a chemical mechanical polishing process.

[0063] In this embodiment, by adjusting the process parameters of the chemical mechanical polishing, it is possible to ensure that silicon nitride is removed during the polishing process and stops at the silicon oxide surface.

[0064] Please refer to Figure 15 and Figure 16 , Figure 15 and Figure 14 The viewing direction is consistent with Figure 16 and Figure 7 In the same viewing direction, a wet etching process is used to remove the second barrier layer 209 and the first barrier layer 208 located in the first spacing groove 205, and remove the isolation layer 203 exposed by the first spacing groove 205 until the substrate 200 is exposed.

[0065] In this embodiment, the wet etching process includes a first wet etching process, which is used to remove the second barrier layer 209 located within the first spacing grooves 205. During the removal of the second barrier layer 209 within the first spacing grooves 205, since other areas are covered by the third barrier layer 211, by adjusting the process parameters of the first wet etching process, it is possible to ensure that only the second barrier layer 209 within the first spacing grooves 205 is removed, while minimal etching damage to the third barrier layer 211 in other areas is caused.

[0066] It should be noted that, in this embodiment, since the material of the sidewall structure formed on both sides of the storage gate structure 204 also includes silicon nitride, and the material of the first barrier layer 208 is also silicon nitride, when removing the first barrier layer 208 located in the first spacing groove 205, it is only necessary to remove the first barrier layer 208 located on the bottom surface of the first spacing groove 205, and retain the first barrier layer 208 located on the side wall of the first spacing groove 205.

[0067] In this embodiment, the wet etching process further includes a second wet etching process, which is used to remove the first barrier layer 208 located within the first spacing groove 205. Since the third barrier layer 211 covering other areas is made of the same material as the first barrier layer 208 during the removal of the first barrier layer 208 within the second spacing groove 205, the third barrier layer 211 in other areas is also removed during the etching process. By adjusting the process parameters of the second wet etching process, it is possible to ensure that only the first barrier layer 208 and the third barrier layer 211 are removed, while minimal etching damage to the second barrier layer 209 in other areas is caused.

[0068] In this embodiment, the wet etching process further includes a third wet etching process, which is used to remove the isolation layer 203 exposed by the first spacer groove 205. Since, during the removal of the isolation layer 203 exposed by the second spacer groove 206, the second barrier layer 209 covering other areas is made of the same material as the isolation layer 203, the second barrier layer 209 in other areas will also be removed during the etching process. By adjusting the process parameters of the third wet etching process, it is possible to ensure that only the isolation layer 203 and the second barrier layer 209 are removed, while minimal etching damage to the first barrier layer 208 in other areas is caused.

[0069] In this embodiment, the etching solution of the first wet etching process includes hydrofluoric acid; the etching solution of the second wet etching process includes phosphoric acid; and the etching solution of the third wet etching process includes hydrofluoric acid.

[0070] In this embodiment, by utilizing the characteristic that the width dimension d1 of the first spacing trench 205 is smaller than the width dimension d2 of the second spacing trench 206 along the second direction Y, the second barrier layer 209 is fully filled in the first spacing trench 205 while leaving the second spacing trench 206 partially filled. Combined with the planarization process, the third barrier layer 211 is formed to expose only the top surface of the second barrier layer 209 within the first spacing trench 205. Subsequent wet etching, utilizing the characteristic that different materials have different etch rates, ensures that only the isolation layer 203 exposed by the first spacing trench 205 is removed. This process saves a photomask step, thereby reducing process costs. Furthermore, because the wet etching process does not have a bombardment effect, the removal of the second barrier layer 209, the first barrier layer 208, and the isolation layer 203 by the wet etching process does not cause excessive etching damage to the memory gate structure 204, effectively improving device performance. Furthermore, the wet etching process forms less residue, thereby effectively preventing excessive residue from accumulating on the subsequently formed source doping region, thereby increasing the resistance of the source doping region.

[0071] Please refer to Figure 17 and Figure 18 , Figure 17 and Figure 15 The viewing direction is consistent with Figure 18 and Figure 16 In the same viewing direction, after removing the isolation layer 203, the active area 201 and the substrate 200 exposed by the first spacing groove 205 are subjected to a first ion implantation process to form a source doping layer 212, and the source doping layer 212 extends along the first direction X.

[0072] In this embodiment, after removing the isolation layer 203, the first barrier layer 208 located on the bottom surface and side wall of the second spacing groove 206 is used as a mask to expose the active area 201 and the substrate 200 in the first spacing groove 205 and perform the first ion implantation treatment to form the source doping layer 212.

[0073] Please refer to Figure 19 , Figure 19 and Figure 17In accordance with the viewing direction, after forming the source doping layer 212, the first barrier layer 208 located in the second spacing groove 206 is removed; a sidewall structure 213 is formed on the sidewall of the storage gate structure 204; after forming the sidewall structure 213, a drain doping layer 214 is formed in the active area 201 exposed by the second spacing groove 206, and the drain doping layer 214 has a third ion, and the electrical type of the third ion is the same as the electrical type of the first ion.

[0074] It should be noted that, in this embodiment, since the material in the sidewall structure 213 also includes silicon nitride, and the material of the first barrier layer 208 is also silicon nitride, when removing the first barrier layer 208 located in the second spacing groove 206, it is only necessary to remove the first barrier layer 208 located on the bottom surface of the second spacing groove 206, while retaining the first barrier layer 208 located on the side wall of the second spacing groove 206.

[0075] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a memory structure, characterized in that: include: Providing a substrate, the substrate comprising a base and a plurality of active regions arranged in parallel along a first direction on the base, the active regions extending along a second direction, the first direction being perpendicular to the second direction, and isolation trenches being provided between adjacent active regions; forming an isolation layer in the isolation trench; forming a plurality of memory gate structures arranged in parallel along the second direction on the substrate, the memory gate structures spanning the plurality of active regions along the first direction, the memory gate structures comprising floating gate structures and control gate structures located on the floating gate structures, first spacing trenches being provided between some adjacent memory gate structures, and second spacing trenches being provided between some adjacent memory gate structures, the first spacing trenches and the second spacing trenches respectively exposing portions of the top surface of the active region and the top surface of the isolation layer, and a width of the first spacing trench being smaller than a width of the second spacing trench along the second direction; forming a first barrier layer on the sidewalls and bottom surfaces of the first spacing trench, the sidewalls and bottom surfaces of the second spacing trench, and top surfaces of the plurality of storage gate structures; forming a second barrier layer on the surface of the first barrier layer, wherein the material of the second barrier layer is different from that of the first barrier layer, and the second barrier layer completely fills the first spacing grooves but does not completely fill the second spacing grooves; forming a third barrier material layer on the surface of the second barrier layer, wherein the material of the third barrier material layer is different from that of the second barrier layer; performing a planarization process on the third barrier material layer until the surface of the second barrier layer is exposed to form a third barrier layer, wherein the third barrier layer exposes the top surface of the second barrier layer located in the first spacing groove; Using a wet etching process, remove the second barrier layer and the first barrier layer located in the first spacing groove, and remove the isolation layer exposed by the first spacing groove, until the substrate is exposed; After removing the isolation layer, a first ion implantation process is performed on the active area and the substrate exposed by the first isolation groove to form a source doping layer, wherein the source doping layer extends along the first direction.

2. The method for forming a memory structure according to claim 1, wherein: The floating gate structure includes a tunneling oxide layer and a floating gate layer located on the tunneling oxide layer.

3. The method for forming a memory structure according to claim 2, wherein: The control gate structure includes a gate dielectric layer and a control gate layer located on the gate dielectric layer.

4. The method for forming a memory structure according to claim 3, wherein: The method for forming the storage gate structure includes: forming a tunneling oxide material layer on the substrate and the isolation layer; forming a floating gate material layer on the tunneling oxide material layer; forming a gate dielectric material layer on the floating gate material layer; forming a control gate material layer on the gate dielectric material layer; forming a patterned layer on the control gate material layer, the patterned layer exposing a portion of the top surface of the control gate material layer; etching a portion of the control gate material layer, the gate dielectric material layer, the floating gate material layer and the tunneling oxide material layer using the patterned layer as a mask until the top surface of the substrate and the top surface of the isolation layer are exposed, thereby forming the storage gate structure; and removing the patterned layer after forming the storage gate structure.

5. The method for forming a memory structure according to claim 3, wherein: The gate dielectric layer includes: a single-layer structure or a multi-layer structure.

6. The method for forming a memory structure according to claim 5, wherein: When the gate dielectric layer is a multi-layer structure, the gate dielectric layer includes: a first oxide layer, a nitride layer located on the first oxide layer, and a second oxide layer located on the nitride layer.

7. The method for forming a memory structure according to claim 3, wherein: The floating gate layer and the control gate layer are both made of semiconductor materials.

8. The method for forming a memory structure according to claim 7, wherein: The semiconductor material includes polysilicon.

9. The method for forming a memory structure according to claim 1, wherein: The material of the first barrier layer is the same as that of the third barrier material layer; the material of the second barrier layer is the same as that of the isolation layer.

10. The method for forming a memory structure according to claim 9, wherein: The material of the first barrier layer and the material of the third barrier material layer include silicon nitride; the material of the second barrier layer includes silicon oxide.

11. The method for forming a memory structure according to claim 9, wherein: The wet etching process includes: a first wet etching process, wherein the first wet etching process is used to remove the second barrier layer located in the first spacing groove; a second wet etching process, wherein the second wet etching process is used to remove the first barrier layer located in the first spacing groove; and a third wet etching process, wherein the third wet etching process is used to remove the isolation layer exposed by the first spacing groove.

12. The method for forming a memory structure according to claim 11, wherein: The etching solution of the first wet etching process includes hydrofluoric acid; the etching solution of the second wet etching process includes phosphoric acid; and the etching solution of the third wet etching process includes hydrofluoric acid.

13. The method for forming a memory structure according to claim 11, wherein: After removing the isolation layer, the first barrier layer located on the bottom surface and sidewall of the second isolation groove is used as a mask to perform the first ion implantation process on the active area and the substrate exposed in the first isolation groove to form the source doping layer.

14. The method for forming a memory structure according to claim 1, wherein: The planarization process includes a chemical mechanical polishing process.

15. The method for forming a memory structure according to claim 1, wherein: After forming the storage gate structure and before forming the first blocking layer, it also includes: forming a lightly doped area in the active area exposed by the first spacing groove and the active area exposed by the second spacing groove, the lightly doped area having second ions, and the electrical type of the first ions is the same as the electrical type of the second ions.

16. The method for forming a memory structure according to claim 11, wherein: After forming the source doping layer, it also includes: removing the first barrier layer located in the second spacing groove; forming a sidewall structure on the sidewall of the storage gate structure; after forming the sidewall structure, forming a drain doping layer in the active area exposed by the second spacing groove, the drain doping layer having third ions, and the electrical type of the third ions is the same as the electrical type of the first ions.

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