Silicon carbide transistor structure and preparation method thereof

Abstract

The present invention provides a silicon carbide transistor structure and a preparation method thereof. By forming a thin sacrificial oxide layer at the bottom of the gate contact hole, the present invention can prevent the sputtered metal filled in the gate contact hole from reacting with polysilicon when forming an ohmic contact structure in the source contact hole, thereby meeting the condition that the same mask can be used for the lithography and etching processes of the source contact hole and the gate contact hole; at the same time, the sacrificial oxide layer is thin, which is also convenient for removing the sacrificial oxide layer together with the first metal layer that has not reacted, with less impact on other film layers. By using the same mask for lithography and etching to simultaneously form the source contact hole and the gate contact hole, the number of mask layers is reduced. On the one hand, it can save lithography and etching process time, which is conducive to reducing process manufacturing costs. On the other hand, it is conducive to reducing parameter anomalies caused by external defects, improving process stability, thereby improving production efficiency and increasing production capacity.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide transistor structure and a preparation method thereof. Background Art

[0002] As semiconductor integrated circuit manufacturing technology continues to advance, the performance of semiconductor devices continues to improve. As a new type of power device, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET or MOS) devices have the characteristics of high breakdown voltage, low on-resistance, high temperature resistance, and low loss compared to traditional silicon (Si)-based power devices. Thanks to its above advantages, silicon carbide transistors are generally used in high-voltage fields of 650V and above, and can replace silicon-based super-junction MOSFET devices and high-voltage IGBT devices.

[0003] Silicon carbide transistors typically consist of a control gate made of polycrystalline silicon (poly) formed on a silicon carbide substrate and a drive gate made of polycrystalline silicon formed on a field oxide. The control gate acts as the gate, with both sides connected via a contact-to-source structure (CTS) to control transistor conduction. The drive gate, connected to the top by a gate contact structure (CTG), provides a path for connecting the gate to external circuits, ensuring that the gate voltage is correctly applied to the transistor structure, thereby controlling the flow of channel current.

[0004] In the current silicon carbide transistor manufacturing process, source and gate contact holes typically require separate photolithography and etching processes using two different masks. The bottom of the source contact hole is typically annealed with nickel metal (Ni) to form an ohmic contact. If excessive nickel is used, causing it to fill the gate contact hole, it will react violently with the polysilicon at the bottom of the gate contact hole, necessitating separate processing for the source and gate contact holes. In the silicon carbide transistor device manufacturing process, more complex processes require more mask layers, which in turn increases external defects introduced into the production line, and results in higher manufacturing time, labor, and raw material costs. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a silicon carbide transistor structure and a preparation method thereof. By improving the process, the lithography and etching processes of the source contact holes and the gate contact holes can use the same mask, which can reduce the number of mask layers, save process time, avoid parameter anomalies caused by external defects, improve process stability, and help reduce process manufacturing costs.

[0006] In order to solve the above problems, the present invention provides a method for preparing a silicon carbide transistor structure, comprising the following steps: forming a substrate, the substrate comprising a silicon carbide substrate, a first polysilicon structure and a second polysilicon structure spaced apart on the surface of the silicon carbide substrate, and a dielectric layer covering the surface of the silicon carbide substrate, the first polysilicon structure and the second polysilicon structure; performing a common etching process, etching the dielectric layer using the same mask, and simultaneously forming a first contact hole and a second contact hole, the first contact hole being located on both sides of the first polysilicon structure and exposing the silicon carbide substrate, and the second contact hole being located on the top of the second polysilicon structure and exposing the second polysilicon layer of the second polysilicon structure; growing a sacrificial oxide layer on the surface of the second polysilicon layer exposed by the second contact hole, the sacrificial oxide layer and the second polysilicon layer being exposed. The dielectric layer is made of the same material, and the film thickness of the sacrificial oxide layer is an order of magnitude smaller than the film thickness of the dielectric layer; a first metal sputtering process is performed to form a first metal layer, and at the bottom of the first contact hole, the first metal layer reacts with the silicon carbide substrate to form a metal compound as an ohmic contact structure, and at the bottom of the second contact hole, the first metal layer and the second polysilicon layer do not react due to the resistance of the sacrificial oxide layer; the sacrificial oxide layer and the unreacted first metal layer are removed; and a second metal sputtering process is performed to form a second metal layer, wherein the second metal layer that fills the first contact hole and contacts the ohmic contact structure serves as a first contact structure, and the second metal layer that fills the second contact hole and contacts the second polysilicon layer serves as a second contact structure.

[0007] In order to solve the above problems, the present invention further provides a silicon carbide transistor structure, which is prepared using the method for preparing the silicon carbide transistor structure described in the present invention.

[0008] The above technical solution, by forming a relatively thin sacrificial oxide layer at the bottom of the gate contact hole, can prevent the sputtered metal filling the gate contact hole from reacting with the polysilicon when forming the ohmic contact structure in the source contact hole, thereby satisfying the requirement that the same photomask can be used for the lithography and etching processes of the source and gate contact holes. At the same time, the thin film of the sacrificial oxide layer also facilitates the removal of the sacrificial oxide layer when removing the unreacted first metal layer, with minimal impact on other film layers. By using the same photomask for photolithography and etching to simultaneously form the source and gate contact holes, the number of mask layers is reduced. On the one hand, this can save photolithography and etching process time, which helps reduce process manufacturing costs. On the other hand, it can also help reduce parameter anomalies caused by external defects, improve process stability, and thus improve production efficiency and increase production capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for describing the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present invention. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0010] Figure 1 A flowchart of a method for fabricating a silicon carbide transistor structure according to an embodiment of the present invention;

[0011] Figure 2 A schematic diagram of the local topography of forming a substrate according to an embodiment of the present invention;

[0012] Figure 3 A schematic diagram of the local topography after performing a common etching process according to an embodiment of the present invention;

[0013] Figure 4 A schematic diagram of the local morphology of forming a sacrificial oxide layer according to an embodiment of the present invention;

[0014] Figure 5 A schematic diagram of the local topography of forming a first metal layer according to an embodiment of the present invention;

[0015] Figure 6 A schematic diagram of the local morphology after the sacrificial oxide layer is removed according to an embodiment of the present invention;

[0016] Figure 7 FIG. 1 is a schematic diagram of the local topography of forming a second metal layer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following is a clear and complete description of the technical solutions in the embodiments of the present invention, with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0018] Please also refer to Figures 1 to 7 ,in, Figure 1 A flowchart of a method for fabricating a silicon carbide transistor structure according to an embodiment of the present invention; Figure 2 A schematic diagram of the local topography of forming a substrate according to an embodiment of the present invention; Figure 3 A schematic diagram of the local topography after performing a common etching process according to an embodiment of the present invention; Figure 4 A schematic diagram of the local morphology of forming a sacrificial oxide layer according to an embodiment of the present invention; Figure 5A schematic diagram of the local topography of forming a first metal layer according to an embodiment of the present invention; Figure 6 A schematic diagram of the local morphology after the sacrificial oxide layer is removed according to an embodiment of the present invention; Figure 7 FIG. 1 is a schematic diagram of the local topography of forming a second metal layer according to an embodiment of the present invention.

[0019] like Figure 1 As shown, the preparation method of the silicon carbide transistor structure described in this embodiment includes the following steps: S1, forming a substrate, the substrate including a silicon carbide substrate, a first polysilicon structure and a second polysilicon structure spaced apart on the surface of the silicon carbide substrate, and a dielectric layer covering the surface of the silicon carbide substrate, the first polysilicon structure and the second polysilicon structure; S2, performing a common plate etching process, etching the dielectric layer using the same mask, and simultaneously forming a first contact hole and a second contact hole, the first contact hole being located on both sides of the first polysilicon structure and exposing the silicon carbide substrate, and the second contact hole being located on the top of the second polysilicon structure and exposing the second polysilicon layer of the second polysilicon structure; S3, growing a sacrificial oxide layer on the surface of the second polysilicon layer exposed by the second contact hole, the sacrificial oxide layer and the dielectric layer The materials of the first contact hole and the second contact hole are the same, and the thickness of the sacrificial oxide layer is an order of magnitude smaller than the thickness of the dielectric layer; S4, performing a first metal sputtering process to form a first metal layer, at the bottom of the first contact hole, the first metal layer reacts with the silicon carbide substrate to form a metal compound as an ohmic contact structure, and at the bottom of the second contact hole, the first metal layer and the second polysilicon layer do not react due to the resistance of the sacrificial oxide layer; S5, removing the sacrificial oxide layer and the unreacted first metal layer; and S6, performing a second metal sputtering process to form a second metal layer, wherein the second metal layer that fills the first contact hole and contacts with the ohmic contact structure serves as a first contact structure, and the second metal layer that fills the second contact hole and contacts with the second polysilicon layer serves as a second contact structure.

[0020] See also Figure 2 In step S1, a substrate is formed, wherein the substrate includes a silicon carbide substrate, a first polysilicon structure 21 and a second polysilicon structure 22 spaced apart on the surface of the silicon carbide substrate, and a dielectric layer 23 covering the surface of the silicon carbide substrate, the first polysilicon structure 21 and the second polysilicon structure 22.

[0021] In this embodiment, the silicon carbide (SiC) substrate includes a supporting substrate 201 and a silicon carbide epitaxial layer 202 formed on the supporting substrate 201. The supporting substrate 201 can be any one of a silicon (Si) substrate and a silicon carbide (SiC) substrate. The supporting substrate 201 can also be a stacked structure, such as a silicon / germanium / silicon stack. The silicon carbide epitaxial layer 202 is a layer of silicon carbide thin film epitaxially grown (EPI) on the supporting substrate 201. The silicon carbide epitaxial layer 202 can be grown by chemical vapor deposition (CVD). CVD technology mainly uses one or more gaseous compounds or single substances containing thin film elements to chemically react on the substrate surface to form a thin film. The silicon carbide epitaxial layer 202 can subsequently react with the first metal used in the first metal sputtering process to form a metal compound as an ohmic contact structure.

[0022] In this embodiment, in the step of forming a substrate, the first polysilicon structure 21 is a control gate structure, including a gate oxide layer 211 formed on the surface of the silicon carbide substrate and a first polysilicon layer 212 covering the gate oxide layer 211, and the dielectric layer 23 covers the gate oxide layer 211 and the first polysilicon layer 212. The second polysilicon structure 22 is a drive gate structure, including a field oxide layer 221 formed on the surface of the silicon carbide substrate and a second polysilicon layer 222 covering the field oxide layer 221, and the dielectric layer 23 covers the field oxide layer 221 and the second polysilicon layer 222. The thickness of the field oxide layer 221 is greater than the thickness of the gate oxide layer 211. Specifically, the thickness of the field oxide layer 221 is greater than or equal to 10,000 angstroms. The formation process of the first polysilicon structure 21 and the second polysilicon structure 22 can refer to existing related processes and will not be repeated here.

[0023] Continuing with the above embodiment, the first contact hole 231 is a source contact hole, and accordingly, the first contact structure 71 (shown in FIG. Figure 7 The second contact hole 232 is a gate contact hole, and the second contact structure 72 (shown in FIG. Figure 7 The gate contact structure (CTG) in the middle is used for the two gate structures: the control gate structure is connected to the source contact structure (CTS) on both sides of the gate to control the conduction of the transistor; the top of the drive gate structure is connected to the gate contact structure (CTG) to provide a path for connecting the gate to the external circuit, ensuring that the gate voltage is correctly applied to the transistor structure, thereby controlling the flow of channel current.

[0024] In this embodiment, the dielectric layer 23, the field oxide layer 221, and the gate oxide layer 211 are all made of silicon dioxide (SiO2). The formation process of the dielectric layer 23, the field oxide layer 221, and the gate oxide layer 211 can refer to the existing related processes and will not be repeated here.

[0025] See also Figure 3 And step S2, performing a common etching process, using the same mask to etch the dielectric layer 23, and simultaneously forming a first contact hole 231 and a second contact hole 232, wherein the first contact hole 231 is located on both sides of the first polysilicon structure 21 and exposes the silicon carbide substrate, and the second contact hole 232 is located on the top of the second polysilicon structure 22 and exposes the second polysilicon layer 222 of the second polysilicon structure 22.

[0026] By using the same photomask for photolithography and etching to simultaneously form the first contact hole 231 (which can serve as a source contact hole) and the second contact hole 232 (which can serve as a gate contact hole), this embodiment reduces the number of photomask layers compared to the prior art, where the source contact hole and the gate contact hole require separate photolithography and etching processes using two different photomasks. Reducing the number of photomask layers not only saves time during the photolithography and etching processes, but also helps reduce process manufacturing costs. It also helps reduce parameter anomalies caused by external defects, improving process stability and thus increasing production efficiency and capacity.

[0027] See also Figure 4 And step S3, growing a sacrificial oxide layer 40 on the surface of the second polysilicon layer 222 exposed by the second contact hole 232, wherein the sacrificial oxide layer 40 is made of the same material as the dielectric layer 23, and the film thickness of the sacrificial oxide layer 40 is an order of magnitude smaller than the film thickness of the dielectric layer 23.

[0028] In some embodiments, the dielectric layer 23 and the sacrificial oxide layer 40 are both made of silicon dioxide (SiO2). The sacrificial oxide layer 40 has a thickness on the order of hundreds of angstroms, and the dielectric layer 23 has a thickness on the order of tens of thousands of angstroms. For example, the sacrificial oxide layer 40 has a thickness of 100 angstroms, and the dielectric layer 23 has a thickness greater than or equal to 15,000 angstroms.

[0029] In this embodiment, the step of growing a sacrificial oxide layer 40 on the surface of the second polysilicon layer 222 exposed by the second contact hole 232 specifically includes placing the substrate in a furnace tube at a preset process temperature to perform an oxidation reaction, wherein the preset process temperature is higher than or equal to the oxidation temperature of polysilicon and lower than the oxidation temperature of silicon carbide, so that an oxide layer is grown and oxidized only on the surface of the second polysilicon layer 222 exposed by the second contact hole 232 to form the sacrificial oxide layer 40, and substantially no oxide layer is formed on the surface of the silicon carbide substrate. Specifically, the preset process temperature is 600° C. to 1200° C., for example, 600° C., 650° C., 700° C., 800° C., 900° C., 1000° C., 1100° C., 1150° C., 1200° C., etc. As a result, a 100-angstrom oxide layer is grown on the surface of the second polysilicon layer 222 to prevent the metal and polysilicon from reacting in the subsequent metal sputtering process for forming an ohmic contact; and basically no oxide layer is formed on the surface of the silicon carbide substrate, which will not affect the reaction between the metal and silicon carbide in the metal sputtering process for forming an ohmic contact.

[0030] See also Figure 5 And step S4, performing a first metal sputtering process to form a first metal layer 50, at the bottom of the first contact hole 231, the first metal layer 50 reacts with the silicon carbide substrate to form a metal compound as an ohmic contact structure 51, at the bottom of the second contact hole 232, due to the resistance of the sacrificial oxide layer 40, the first metal layer 50 and the second polysilicon layer 222 do not react.

[0031] Specifically, the first metal layer 50 covers the dielectric layer 23, the inner wall of the first contact hole 231, and the inner wall of the second contact hole 232. At the bottom of the first contact hole 231, the first metal layer 50 reacts with the silicon carbide substrate to form a metal compound serving as an ohmic contact structure 51. At the bottom of the second contact hole 232, the first metal layer 50 and the second polysilicon layer 222 do not react due to the protection provided by the sacrificial oxide layer 40. The presence of the sacrificial oxide layer 40 prevents the sputtered metal filling the gate contact hole from reacting with the polysilicon when forming the ohmic contact structure in the source contact hole. That is, the sputtered metal does not affect the polysilicon layer at the bottom of the gate contact hole, thereby satisfying the requirement that the same mask can be used for the lithography and etching processes of the source and gate contact holes.

[0032] In this embodiment, the step of performing a first metal sputtering process to form a first metal layer 50 specifically includes: performing a metal nickel (Ni) sputtering process, whereby at the bottom of the first contact hole 231, the metal nickel reacts with the silicon carbide substrate to form a nickel silicon compound (NiSi) as the ohmic contact structure 51; at the bottom of the second contact hole 232, due to the resistance of the sacrificial oxide layer 40, the metal nickel does not react with the second polysilicon layer 222, so that the sputtered metal will not affect the second polysilicon layer 222.

[0033] See also Figure 6 And step S5, removing the sacrificial oxide layer 40 and the unreacted first metal layer 50.

[0034] Because the thickness of the sacrificial oxide layer 40 is an order of magnitude smaller than that of the dielectric layer 23, even if the sacrificial oxide layer 40 and the dielectric layer are made of the same material, only the thinner sacrificial oxide layer 40 on the polysilicon surface at the bottom of the second contact hole 232 can be removed, with minimal impact on the layers in other areas. For example, the silicon dioxide layer (the sacrificial oxide layer 40) on the polysilicon surface at the bottom of the second contact hole 232 is only 100 angstroms thick, while the silicon dioxide layer in other areas is as thick as 15,000 angstroms. Therefore, removing the 100 angstroms of silicon dioxide layer on the polysilicon surface has minimal impact on the silicon dioxide layer in other areas.

[0035] See also Figure 7 And step S6, performing a second metal sputtering process to form a second metal layer 70, wherein the second metal layer 70 that fills the first contact hole 231 and contacts the ohmic contact structure 51 serves as the first contact structure 71, and the second metal layer 70 that fills the second contact hole 232 and contacts the second polysilicon layer 222 serves as the second contact structure 72.

[0036] In this embodiment, the step of performing a second metal sputtering process to form a second metal layer 70 specifically includes: performing an aluminum-copper alloy sputtering process to form an aluminum-copper metal layer that fills the first contact hole 231 and contacts the ohmic contact structure 51, fills the second contact hole 232 and contacts the second polysilicon layer 222, and covers the dielectric layer 23 and is continuously distributed as the second metal layer 70.

[0037] This embodiment forms a relatively thin sacrificial oxide layer at the bottom of the gate contact hole, thereby preventing the sputtered metal filling the gate contact hole from reacting with the polysilicon when forming the ohmic contact structure in the source contact hole, thereby satisfying the condition that the same photomask can be used for the lithography and etching processes of the source contact hole and the gate contact hole. At the same time, the thin sacrificial oxide layer is also convenient for removing the sacrificial oxide layer when removing the unreacted first metal layer, with less impact on other film layers. By using the same photomask for photolithography and etching to simultaneously form the source contact hole and the gate contact hole, the number of mask layers is reduced. On the one hand, this can save photolithography and etching process time, which is conducive to reducing process manufacturing costs. On the other hand, it can help reduce parameter anomalies caused by external defects, improve process stability, thereby improving production efficiency and increasing production capacity.

[0038] Based on the same inventive concept, an embodiment of the present invention further provides a silicon carbide transistor structure, which can be manufactured using the above-mentioned manufacturing method of the present invention.

[0039] See also Figure 7 , which is a schematic diagram of a silicon carbide transistor structure provided by an embodiment of the present invention. Figure 7 As shown, the silicon carbide transistor structure provided in this embodiment is fabricated using the above-described method of the present invention and specifically includes: a silicon carbide substrate, a first polysilicon structure 21 and a second polysilicon structure 22 spaced apart on the surface of the silicon carbide substrate, a dielectric layer 23 covering the surface of the silicon carbide substrate, the first polysilicon structure 21, and the second polysilicon structure 22, ohmic contact structures 51 located within the silicon carbide substrate on both sides of the first polysilicon structure 21, a first contact structure 71 in contact with the ohmic contact structure 51, and a second contact structure 72 located on top of the second polysilicon structure 22 and in contact with the second polysilicon layer 222 of the second polysilicon structure 22. The first contact structure 71 and the second contact structure 72 are formed using a common etching process performed using the same photomask.

[0040] In this embodiment, the silicon carbide (SiC) substrate includes a support substrate 201 and a silicon carbide epitaxial layer 202 formed on the support substrate 201 .

[0041] In this embodiment, the first polysilicon structure 21 is a control gate structure, including a gate oxide layer 211 formed on the surface of the silicon carbide substrate and a first polysilicon layer 212 covering the gate oxide layer 211, and the dielectric layer 23 covers the gate oxide layer 211 and the first polysilicon layer 212. The second polysilicon structure 22 is a drive gate structure, including a field oxide layer 221 formed on the surface of the silicon carbide substrate and a second polysilicon layer 222 covering the field oxide layer 221, and the dielectric layer 23 covers the field oxide layer 221 and partially covers the second polysilicon layer 222. The film thickness of the field oxide layer 221 is greater than the film thickness of the gate oxide layer 211. Specifically, the film thickness of the field oxide layer 221 is greater than or equal to 10,000 angstroms.

[0042] Continuing with the above embodiment, the first contact structure 71 is a source contact structure (CTS); the second contact structure 72 is a gate contact structure (CTG). The two gate structures of the first polysilicon structure 21 and the second polysilicon structure 22 are used as follows: the control gate structure serves as the gate, with both sides connected via the source contact structure (CTS) to control transistor conduction; the top of the drive gate structure is connected via the gate contact structure (CTG) to provide a path for connecting the gate to the external circuit, ensuring that the gate voltage is correctly applied to the transistor structure, thereby controlling the flow of channel current.

[0043] In this embodiment, the dielectric layer 23 , the field oxide layer 221 , and the gate oxide layer 211 are all made of silicon dioxide (SiO 2 ).

[0044] In this embodiment, the first metal is nickel (Ni), and the ohmic contact structure 51 is a nickel silicon compound (NiSi) formed by the reaction of nickel and the silicon carbide substrate.

[0045] In this embodiment, the material of the first contact structure 71 and the second contact structure 72 is an aluminum-copper alloy, which also covers the dielectric layer 23 and is a continuously distributed metal film layer.

[0046] It should be noted that references in this specification to "one embodiment," "an embodiment," "exemplary embodiments," "some embodiments," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of one skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described. Generally, terms can be understood, at least in part, from their usage in the context. For example, the term "one or more," as used herein, can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a feature, structure, or combination of features in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can also be understood to express either singular or plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can alternatively, again depending, at least in part, on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted that in this specification, “connected / coupled” refers not only to direct coupling of one component to another component, but also to indirect coupling of one component to another component via an intermediate component.

[0047] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies has been omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0048] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing a silicon carbide transistor structure, characterized in that: The steps include: forming a substrate comprising a silicon carbide substrate, a first polysilicon structure and a second polysilicon structure spaced apart on a surface of the silicon carbide substrate, and a dielectric layer covering the surface of the silicon carbide substrate, the first polysilicon structure, and the second polysilicon structure; Performing a common etching process to etch the dielectric layer using the same photomask to simultaneously form a first contact hole and a second contact hole, wherein the first contact hole is located on both sides of the first polysilicon structure and exposes the silicon carbide substrate, and the second contact hole is located on the top of the second polysilicon structure and exposes the second polysilicon layer of the second polysilicon structure; Growing a sacrificial oxide layer on the surface of the second polysilicon layer exposed by the second contact hole, wherein the sacrificial oxide layer is made of the same material as the dielectric layer and has a thickness that is an order of magnitude smaller than that of the dielectric layer; Performing a first metal sputtering process to form a first metal layer, wherein the first metal layer reacts with the silicon carbide substrate at the bottom of the first contact hole to form a metal compound as an ohmic contact structure, and the first metal layer does not react with the second polysilicon layer at the bottom of the second contact hole due to the resistance of the sacrificial oxide layer; removing the sacrificial oxide layer and the unreacted first metal layer; as well as A second metal sputtering process is performed to form a second metal layer, wherein the second metal layer that fills the first contact hole and contacts the ohmic contact structure serves as a first contact structure, and the second metal layer that fills the second contact hole and contacts the second polysilicon layer serves as a second contact structure.

2. The method according to claim 1, characterized in that The silicon carbide substrate includes a support substrate and a silicon carbide epitaxial layer formed on the support substrate, and the ohmic contact structure is formed in the silicon carbide epitaxial layer.

3. The method according to claim 1, characterized in that In the step of forming a substrate, the first polysilicon structure is a control gate structure, including a gate oxide layer formed on the surface of the silicon carbide substrate and a first polysilicon layer covering the gate oxide layer, and the dielectric layer covers the gate oxide layer and the first polysilicon layer; The second polysilicon structure is a driving gate structure, comprising a field oxide layer formed on the surface of the silicon carbide substrate and a second polysilicon layer covering the field oxide layer, and the dielectric layer covers the field oxide layer and the second polysilicon layer; Wherein, the film thickness of the field oxide layer is greater than the film thickness of the gate oxide layer.

4. The method according to claim 3, characterized in that The first contact structure is a source contact structure, and the second contact structure is a gate contact structure.

5. The method according to claim 3, characterized in that The dielectric layer, the sacrificial oxide layer, the field oxide layer and the gate oxide layer are all made of silicon dioxide.

6. The method according to claim 1, wherein The step of growing a sacrificial oxide layer on the surface of the second polysilicon layer exposed by the second contact hole specifically includes: The substrate is placed in a furnace tube at a preset process temperature to perform an oxidation reaction, wherein the preset process temperature is higher than or equal to the oxidation temperature of polysilicon and lower than the oxidation temperature of silicon carbide, so that only the surface of the second polysilicon layer exposed by the second contact hole is oxidized and grown to form an oxide layer as the sacrificial oxide layer.

7. The method according to claim 6, characterized in that The preset process temperature is 600°C to 1200°C.

8. The method according to claim 1 or 6, characterized in that The thickness of the sacrificial oxide layer is 100 angstroms, and the thickness of the dielectric layer is greater than or equal to 15,000 angstroms.

9. The method according to claim 1, characterized in that The step of performing a first metal sputtering process to form a first metal layer specifically includes: A metal nickel sputtering process is performed, whereby at the bottom of the first contact hole, the metal nickel reacts with the silicon carbide substrate to form a nickel-silicon compound as the ohmic contact structure; at the bottom of the second contact hole, the metal nickel does not react with the second polysilicon layer due to the resistance of the sacrificial oxide layer.

10. The method according to claim 1, characterized in that The step of performing a second metal sputtering process to form a second metal layer specifically includes: An aluminum-copper alloy sputtering process is performed to form an aluminum-copper metal layer as the second metal layer, which fills the first contact hole and contacts the ohmic contact structure, fills the second contact hole and contacts the second polysilicon layer, and covers the dielectric layer.

11. A silicon carbide transistor structure, characterized in that: The silicon carbide transistor structure is prepared by using the method for preparing a silicon carbide transistor structure according to any one of claims 1 to 10.

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