PSJ-GaN structure-based double-channel HEMT chip and manufacturing method thereof
By realizing dual-channel design and gate cascade in the PSJ-GaN structure, the problem of current density and frequency synchronization of GaN HEMT devices is solved, and the synchronization switching effect of high current and high frequency is achieved, achieving Si and SiC, etc. The device has considerable performance.
Patent Information
- Application Number
- CN202411310227.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2025-01-14
AI Technical Summary
GaN HEMT power devices based on PSJ structure have shortcomings in the synchronization of current density and switching frequency, and it is difficult to reach the level of devices such as SiC/Si/IGBT.
By realizing a dual-channel design in the PSJ-GaN structure, the epitaxial growth of the dual PSJ structure is adopted to increase the electron concentration and current density, and at the same time, the gate cascade is used to ensure the synchronous existence or disappearance of 2DHG, and keep the frequency consistent.
Without increasing the chip surface area, the current is doubled, the withstand voltage remains unchanged, and the switching control effect is improved. It can achieve high-frequency synchronous switches compared with devices such as Si and SiC.
Smart Images
Figure CN119317143A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor process technology, and in particular to a double-channel HEMT chip based on a PSJ-GaN structure and a manufacturing method thereof. Background Art
[0002] With the maturity of third-generation semiconductor materials and device technologies, GaN power devices with characteristics such as high frequency / high power are becoming more and more popular in the market. In addition to the increasingly higher requirements for energy consumption, industries such as power electronics or automobiles also have high requirements for current.
[0003] At present, the voltage resistance of chips based on the PSJ structure is relatively high, but compared with power devices such as SiC / Si / IGBT, its current is affected by the channel electron concentration and it is difficult to reach a very high level.
[0004] GaN HEMT power devices have a planar structure. A single channel layer makes it difficult to increase the current density, while multiple channel layers make it difficult for the gate to fully control the opening / closing of the electron channel in the channel, and it is difficult to synchronize the switching frequency of multiple channels in terms of switching timing. Summary of the invention
[0005] The embodiment of the present application provides a dual-channel HEMT chip based on a PSJ-GaN structure and a manufacturing method thereof, which can upgrade the original single channel to a dual channel without increasing the chip surface area and maintaining the same withstand voltage, and the relative electron concentration is doubled, the relative current is doubled, and the switch control effect is good, and the switch timing can be kept consistent.
[0006] According to a first aspect of an embodiment of the present application, a double-channel HEMT chip based on a PSJ-GaN structure is provided, comprising a base layer and a buffer layer, a third gallium nitride layer, and a second aluminum gallium nitride layer sequentially grown on the surface of the base layer, a second source electrode, a second gallium nitride layer, and a second drain electrode are grown on the surface of the second aluminum gallium nitride layer, wherein the second source electrode and the second drain electrode are relatively distributed on both sides of the second gallium nitride layer, a second gate electrode and a first aluminum gallium nitride layer with a gap fit are grown on the surface of the second gallium nitride layer, and a step structure for supporting the first aluminum gallium nitride layer is integrally provided on the surface of the second gallium nitride layer, a first source electrode, a first gallium nitride layer, and a first drain electrode are grown on the surface of the first aluminum gallium nitride layer, a P-GaN layer and a first gate electrode are sequentially grown on the surface of the first gallium nitride layer, wherein the first gate electrode and the second gate electrode are connected to form a gate electrode, the first source electrode and the second source electrode are connected to form a source electrode, and the first drain electrode and the second drain electrode are connected to form a drain electrode.
[0007] A second aspect of the embodiment of the present application provides a method for manufacturing the dual-channel HEMT chip based on the PSJ-GaN structure, comprising the following steps in sequence:
[0008] S10, epitaxial structure growth, sequentially growing a buffer layer, a third gallium nitride layer, a second aluminum gallium nitride layer, a second gallium nitride layer, a first aluminum gallium nitride layer, a first gallium nitride layer and a P-GaN layer on the base layer;
[0009] S20, chip etching, specifically including:
[0010] S21, photolithography and etching of the P-GaN layer, the first gallium nitride layer, the first aluminum gallium nitride layer, and the boundary between the second gallium nitride layer and the second aluminum gallium nitride layer, and de-resist and clean;
[0011] S22, photolithography and etching the P-GaN layer, the first gallium nitride layer and the first aluminum gallium nitride layer to the second gallium nitride layer, so that the top boundary portion of the second gallium nitride layer is a hollow gap, and de-resist and clean;
[0012] S23, photolithography and etching of the P-GaN layer, the first gallium nitride layer and the boundary of the first aluminum gallium nitride layer, and de-resistance and cleaning;
[0013] S24, photolithography and etching of the P-GaN layer to the boundary of the first gallium nitride layer, and de-resistance and cleaning;
[0014] S30, photolithographically manufacturing a first source electrode, a second source electrode, a first drain electrode, a second drain electrode, a first gate electrode, and a second gate electrode at corresponding positions.
[0015] In a possible implementation, the method further includes step S40, manufacturing an isolation layer, a connection layer and a protection layer, wherein the isolation layer is used to isolate the second source electrode, the second gate electrode, the first source electrode, the first gate electrode, the first drain electrode and the second drain electrode, as well as the source electrode, the gate electrode and the drain electrode, and the isolation layer is manufactured by coating polyimide through a photolithography process;
[0016] The connection layer is used to connect the first source electrode and the second source electrode to form a source electrode, connect the first gate electrode and the second gate electrode to form a gate electrode, and connect the first drain electrode and the second drain electrode to form a drain electrode. The connection layer is photolithographically processed by a negative photolithography process, and then Ni / Au is evaporated by E-beam, and finally stripped and cleaned.
[0017] The protective layer is used to cover the entire HEMT chip at the end away from the base layer. The protective layer is produced by coating polyimide and performing a photolithography process.
[0018] In a possible implementation, during the manufacturing process of the isolation layer and the protection layer, both are baked in an atmosphere at a temperature of 300-350° C. for 1 hour after the photolithography process.
[0019] In a possible implementation, step S30 specifically includes: photolithography to expose the first source electrode, the second source electrode, the first drain electrode and the second drain electrode, and then evaporate Ti / Al / Ni / Au to remove excess metal, and then anneal to perform N-ohmic;
[0020] Then, six regions including the first source, the second source, the first drain, the second drain, the first gate and the second gate are exposed by photolithography, and Ni / Au is evaporated to remove excess metal, and then annealing is performed for P-ohmic.
[0021] In a possible implementation, in step S30, RTA 800-900° C. rapid annealing is used for N-ohmic, and RTA 560° C. rapid annealing is used for P-ohmic.
[0022] Beneficial effects: Compared with the prior art, the dual-channel HEMT chip and manufacturing method based on the PSJ-GaN structure provided by the present application realizes a dual-channel design by epitaxially growing a dual PSJ structure at the epitaxial end once, which can make the chip reach twice the current of the conventional PSJ structure, achieve an ultra-large current application range, and can be directly comparable to Si and SiC devices. In addition, the gate cascade method is used to ensure that 2DHG exists or disappears at the same time, so that the frequency can be kept in the same timing.
[0023] These and other objects, features and advantages of the present invention will be fully reflected in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 The schematic diagram of the structure of the double-channel HEMT chip based on the PSJ-GaN structure of the present application is shown.
[0025] Figure 2 The schematic diagram shows the structure of the dual-channel HEMT chip in the present application when it is in the on state.
[0026] Figure 3 The schematic diagram shows the structure of the dual-channel HEMT chip in the present application when it is in the off state.
[0027] Figure 4 The schematic diagram of the epitaxial wafer structure in the dual-channel HEMT chip in the present application is shown.
[0028] Figure 5 A schematic diagram of the structure of etching each thin film layer in the dual-channel HEMT chip in the present application is shown.
[0029] Figure 6 The schematic diagram shows the structure of the isolation layer, the connection layer and the protection layer in the dual-channel HEMT chip of the present application. DETAILED DESCRIPTION
[0030] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.
[0031] Those skilled in the art should understand that, in the disclosure of the specification, the orientation or position relationship indicated by the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the orientation or position relationship shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.
[0032] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "one" should not be understood as a limitation on the quantity.
[0033] refer to Figures 1 to 3 In a first aspect, the present application provides a dual-channel HEMT chip based on a PSJ-GaN structure, combined with Figure 1 , comprising a base layer 101 and a buffer layer 102, a third gallium nitride layer 103 and a second aluminum gallium nitride layer 104 sequentially grown on the surface of the base layer 101, wherein a second source S2, a second gallium nitride layer 105 and a second drain D2 are grown on the surface of the second aluminum gallium nitride layer 104, wherein the second source S2 and the second drain D2 are relatively distributed on both sides of the second gallium nitride layer 105, and a second gate G2 and a first aluminum gallium nitride layer 106 with a gap fit are grown on the surface of the second gallium nitride layer 105, and a second gallium nitride layer 106 for supporting the first aluminum gallium nitride layer 106 is integrally provided on the surface of the second gallium nitride layer 105. 6, so that the second gate G2 and the second drain D2 can avoid the contact part of the first aluminum gallium nitride layer 106 and the second gallium nitride layer 105. In addition, the first source S1, the first gallium nitride layer 107 and the first drain D1 are grown on the surface of the first aluminum gallium nitride layer 106, and the P-GaN layer 108 and the first gate G1 are grown on the surface of the first gallium nitride layer 107 in sequence, wherein the first gate G1 and the second gate G2 are connected to form a gate G, wherein the first source S1 and the second source S2 are connected to form a source S, and the first drain D1 and the second drain D2 are connected to form a drain D.
[0034] Specifically, the drain D and source S of the chip are connected to the circuit respectively, and the gate G is connected to the driving circuit (square wave signal of a given frequency), and the chip operates.
[0035] One case is that the chip is in the on state, combined with Figure 2 When the gate G inputs a high level (about 3V or more), 2DHG_1 in the first gallium nitride layer 107 increases under the piezoelectric excitation of the first gate G1, and 2DHG_2 in the second gallium nitride layer 108 increases under the piezoelectric excitation of the second gate G2. Since the first gate G1 and the second gate G2 are cascaded on the gate G at the same time, the opening timing of 2DHG_1 and 2DHG_2 is synchronized; at the same time, under the voltage at both ends of the source S and the drain D, 2DEG_1 forms a stable current in channel 1, and 2DEG_2 forms a stable current in channel 2, so that the chip can be smoothly turned on;
[0036] One case is that the chip is in the off state, combined with Figure 3 When the gate G inputs a low level (about -5V or less), the negative voltage of the first gate G1 causes 2DHG_1 to be extracted from the first gallium nitride layer 107, and the negative voltage of the second gate G2 causes 2DHG_2 to be extracted from the second gallium nitride layer 108. At this moment, there is no 2DHG in both channels, and 2DEG_1 and 2DEG_2 in channel 1 and channel 2 are respectively extracted by the positive voltage at the drain D (the first drain D1 and the second drain D2), and the electronic channel in the chip disappears, thereby realizing the off state of the chip; at the same time, due to the stable depletion zone formed by the spontaneous polarization of AlGaN (including the first aluminum gallium nitride layer and the second aluminum gallium nitride layer), the electric field in the off state is evenly distributed (almost no spike electric field), so that the chip withstand voltage can reach a very high state.
[0037] Since the first gate G1 and the second gate G2 are cascaded to the gate G, the number of holes formed in the upper and lower parts is roughly the same, and the time of disappearance or generation is consistent, so the timing (frequency) is synchronized and the withstand voltage is stable.
[0038] The double-channel HEMT chip based on the PSJ-GaN structure provided in the present application is based on the PSJ structure principle, and a double PSJ structure is realized at the epitaxial end (such as Figure 4), forming a dual-channel structure, so that the chip can reach twice the current of the conventional PSJ structure, realizing the ultra-large current application range of ordinary GaN-HEMT devices, and can directly match Si and SiC devices in terms of current. Since the generation and disappearance of 2DHG affects the switching frequency of the device, the dual-channel PSJ structure uses a gate electrode connection method to ensure that 2DHG exists or disappears at the same time in order to keep the switching frequency in the same timing (not one channel is in the on state and the other channel is in the off state).
[0039] The second aspect of the embodiment of the present application provides a method for manufacturing the double-channel HEMT chip based on the PSJ-GaN structure, Figure 4 , including the following steps in sequence:
[0040] S10, epitaxial structure growth, sequentially growing a buffer layer 102, a third gallium nitride layer 103, a second aluminum gallium nitride layer 104, a second gallium nitride layer 105, a first aluminum gallium nitride layer 106, a first gallium nitride layer 107 and a P-GaN layer 108 on the base layer 101;
[0041] S20, chip etching, combined Figure 5 , specifically including:
[0042] S21, photolithography and etching of the P-GaN layer 108, the first gallium nitride layer 107, the first aluminum gallium nitride layer 106 and the boundary between the second gallium nitride layer 105 and the second aluminum gallium nitride layer 104, and de-resist and clean;
[0043] S22, photolithography and etching of the P-GaN layer 108, the first gallium nitride layer 107 and the first aluminum gallium nitride layer 106 to the second gallium nitride layer 105, so that the top boundary portion of the second gallium nitride layer 105 is a hollow gap, and de-resist and clean;
[0044] S23, photolithography and etching of the boundary between the P-GaN layer 108, the first gallium nitride layer 107 and the first aluminum gallium nitride layer 106, and de-resistance and cleaning;
[0045] S24, photolithography and etching of the P-GaN layer 108 to the boundary of the first gallium nitride layer 107, and de-resistance and cleaning;
[0046] S30 , photolithography is performed to form a first source S1 , a second source S2 , a first drain D1 , a second drain D2 , a first gate G1 , and a second gate G2 at corresponding positions.
[0047] Furthermore, combined with Figure 6The method further comprises step S40, manufacturing isolation layers 301, 302, connection layers 207, 208, 209 and protection layer 303, wherein the isolation layers 301, 302 are used to isolate the second source S2, the second gate G2, the first source S1, the first gate G1, the first drain D1 and the second drain D2, as well as the source S, the gate G and the drain D, and play an insulating role. The isolation layers 301, 302 are manufactured by coating polyimide and photolithography;
[0048] The connection layers 207, 208, and 209 are used to connect the first source electrode S1 and the second source electrode S2 to form the source electrode S, connect the first gate electrode G1 and the second gate electrode G2 to form the gate electrode G, and connect the first drain electrode D1 and the second drain electrode D2 to form the drain electrode D, and play the role of connecting electrodes. The connection layers 207, 208, and 209 are photolithographically processed by negative photolithography, and then Ni / Au is evaporated by E-beam, and finally stripped and cleaned;
[0049] The protective layer 303 is used to cover the entire HEMT chip at the end away from the base layer. The protective layer 303 is made by coating polyimide and performing a photolithography process.
[0050] In one embodiment, during the manufacturing process of the isolation layers 301, 302 and the protection layer 303, they are baked at a temperature of 300-350°C for 1 hour after the photolithography process, so that the structure is stable.
[0051] In one embodiment, step S30 specifically includes: photolithography to expose the first source S1, the second source S2, the first drain D1 and the second drain D2, then evaporate Ti / Al / Ni / Au to remove excess metal, and then anneal for N-ohmic;
[0052] Then, six regions, namely, the first source S1, the second source S2, the first drain D1, the second drain D2, the first gate G1 and the second gate G2, are exposed by photolithography, and Ni / Au is evaporated to remove excess metal, and then annealing is performed for P-ohmic.
[0053] In one embodiment, in step S30, RTA 800-900° C. rapid annealing is used for N-ohmic, and RTA 560° C. rapid annealing is used for P-ohmic.
[0054] It should be noted that the terms "first, second" in the present application are only used for descriptive purposes and do not indicate any order. They cannot be understood as indicating or implying relative importance. These terms can be interpreted as names.
[0055] It should be understood by those skilled in the art that the embodiments of the present invention described above and shown in the accompanying drawings are only examples and do not limit the present invention. The advantages of the present invention have been fully and effectively achieved. The functional and structural principles of the present invention have been demonstrated and explained in the embodiments, and the embodiments of the present invention may be deformed or modified in any way without departing from the principles.
Claims
1. A dual-channel HEMT chip based on PSJ-GaN structure, characterized in that: The invention comprises a base layer, and a buffer layer, a third gallium nitride layer, and a second aluminum gallium nitride layer grown on the surface of the base layer in sequence, a second source electrode, a second gallium nitride layer, and a second drain electrode are grown on the surface of the second aluminum gallium nitride layer, wherein the second source electrode and the second drain electrode are relatively distributed on both sides of the second gallium nitride layer, a second gate electrode and a first aluminum gallium nitride layer are grown on the surface of the second gallium nitride layer with a gap fit, and a step structure for supporting the first aluminum gallium nitride layer is integrally provided on the surface of the second gallium nitride layer, a first source electrode, a first gallium nitride layer, and a first drain electrode are grown on the surface of the first aluminum gallium nitride layer, a P-GaN layer and a first gate electrode are grown on the surface of the first gallium nitride layer in sequence, wherein the first gate electrode and the second gate electrode are connected to form a gate electrode, the first source electrode and the second source electrode are connected to form a source electrode, and the first drain electrode and the second drain electrode are connected to form a drain electrode.
2. A method for manufacturing a double-channel HEMT chip based on a PSJ-GaN structure as claimed in claim 1, characterized in that: The following steps are included in sequence: S10, epitaxial structure growth, sequentially growing a buffer layer, a third gallium nitride layer, a second aluminum gallium nitride layer, a second gallium nitride layer, a first aluminum gallium nitride layer, a first gallium nitride layer and a P-GaN layer on the base layer; S20, chip etching, specifically including: S21, photolithography and etching of the P-GaN layer, the first gallium nitride layer, the first aluminum gallium nitride layer, and the boundary between the second gallium nitride layer and the second aluminum gallium nitride layer, and de-resist and clean; S22, photolithography and etching the P-GaN layer, the first gallium nitride layer and the first aluminum gallium nitride layer to the second gallium nitride layer, so that the top boundary portion of the second gallium nitride layer is a hollow gap, and de-resist and clean; S23, photolithography and etching of the P-GaN layer, the first gallium nitride layer and the boundary of the first aluminum gallium nitride layer, and de-resistance and cleaning; S24, photolithography and etching of the P-GaN layer to the boundary of the first gallium nitride layer, and de-resistance and cleaning; S30, photolithographically manufacturing a first source electrode, a second source electrode, a first drain electrode, a second drain electrode, a first gate electrode, and a second gate electrode at corresponding positions.
3. The method for manufacturing a double-channel HEMT chip based on a PSJ-GaN structure according to claim 2, characterized in that: The method further includes step S40 of manufacturing an isolation layer, a connection layer and a protection layer, wherein the isolation layer is used to isolate the second source electrode, the second gate electrode, the first source electrode, the first gate electrode, the first drain electrode and the second drain electrode, as well as the source electrode, the gate electrode and the drain electrode, and the isolation layer is manufactured by coating polyimide through a photolithography process; The connection layer is used to connect the first source electrode and the second source electrode to form a source electrode, connect the first gate electrode and the second gate electrode to form a gate electrode, and connect the first drain electrode and the second drain electrode to form a drain electrode. The connection layer is photolithographically processed by a negative photolithography process, and then Ni / Au is evaporated by E-beam, and finally stripped and cleaned. The protective layer is used to cover the entire HEMT chip at the end away from the base layer. The protective layer is produced by coating polyimide and performing a photolithography process.
4. The method for manufacturing a double-channel HEMT chip based on a PSJ-GaN structure according to claim 3, characterized in that: During the manufacturing process of the isolation layer and the protective layer, they are both baked at a temperature of 300-350° C. for 1 hour after the photolithography process.
5. The method for manufacturing a double-channel HEMT chip based on a PSJ-GaN structure according to claim 2, characterized in that: Step S30 specifically includes: photolithography to expose the first source, the second source, the first drain and the second drain, then evaporate Ti / Al / Ni / Au to remove excess metal, and then anneal to perform N-ohmic; Then, six regions including the first source, the second source, the first drain, the second drain, the first gate and the second gate are exposed by photolithography, and Ni / Au is evaporated to remove excess metal, and then annealing is performed for P-ohmic.
6. The method for manufacturing a double-channel HEMT chip based on a PSJ-GaN structure according to claim 5, characterized in that: In step S30, RTA 800-900°C rapid annealing is used for N-ohmic, and RTA 560°C rapid annealing is used for P-ohmic.