Gallium nitride HEMT device and preparation method thereof

Abstract

The invention discloses a gallium nitride HEMT device and a preparation method thereof. The device comprises a substrate, a buffer layer, a channel layer and a barrier layer, wherein the buffer layer, the channel layer and the barrier layer are sequentially arranged on the substrate; a two-dimensional electron gas channel is formed between the channel layer and the barrier layer; the two ends of the barrier layer are respectively provided with two epitaxial grooves, and the two epitaxial grooves extend into the channel layer so as to cut off the two-dimensional electron gas channels at the epitaxial grooves. The two tin oxide epitaxial layers respectively grow in the two epitaxial grooves; the source electrode and the drain electrode respectively grow on the two tin oxide epitaxial layers; the dielectric layer is arranged on the barrier layer and covers the surface, except the area where the two tin oxide epitaxial layers are located, of the barrier layer; and the gate electrode is arranged on the dielectric layer and is positioned between the source electrode and the drain electrode. The device provided by the invention has relatively small ohmic contact resistance, and can meet the application requirements of high-voltage and high-power electronic devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium nitride HEMT device and a preparation method thereof. Background Art

[0002] The third generation of semiconductor materials, namely wide bandgap semiconductor (WBGS) semiconductor materials, were developed after the first generation of silicon, germanium, and the second generation of gallium arsenide, indium phosphide, etc. Among the third generation of semiconductor materials, gallium nitride (GaN) has superior properties such as wide bandgap, direct bandgap, high breakdown electric field, low dielectric constant, high electron saturation drift velocity, strong radiation resistance and good chemical stability, becoming the key semiconductor material for manufacturing a new generation of microelectronic devices and circuits after germanium, silicon and gallium arsenide. In particular, it has unique advantages in high temperature, high power, high frequency and radiation-resistant electronic devices, as well as full wavelength and short wavelength optoelectronic devices, and is currently an ideal material for realizing high temperature, high power, high frequency and radiation-resistant, full wavelength optoelectronic devices.

[0003] However, for GaN HEMT power devices, due to the problem of high ohmic contact resistance of current devices, it is difficult to meet the application requirements of high-voltage and high-power electronic devices. Summary of the invention

[0004] Therefore, the technical problem to be solved by the present invention is to provide a gallium nitride HEMT device which can achieve good ohmic contact performance without high-temperature activation, has low ohmic contact resistance, high threshold voltage, high breakdown voltage, high current density and excellent pinch-off characteristics, and is suitable for high-voltage and high-power electronic device applications; and provide a method for preparing the gallium nitride HEMT device.

[0005] To this end, according to a first aspect, the present invention provides a gallium nitride HEMT device, comprising:

[0006] A substrate and a buffer layer, a channel layer and a barrier layer sequentially arranged on the substrate; a two-dimensional electron gas channel is formed between the channel layer and the barrier layer; two epitaxial grooves are respectively arranged at both ends of the barrier layer, and the two epitaxial grooves also extend into the channel layer to cut off the two-dimensional electron gas channel at the epitaxial grooves;

[0007] Two tin oxide epitaxial layers are grown in two epitaxial trenches respectively;

[0008] The source electrode and the drain electrode are grown on two tin oxide epitaxial layers respectively;

[0009] A dielectric layer is disposed on the barrier layer and covers the surface of the barrier layer except for the areas where the two tin oxide epitaxial layers are located;

[0010] The gate electrode is disposed on the dielectric layer and located between the source electrode and the drain electrode.

[0011] In an optional implementation, the source electrode and the drain electrode both include an X element structure layer disposed on the tin oxide epitaxial layer and a metal structure layer disposed on the X element structure layer; wherein the X element is a group IV simple metal element or a group IV alloy element.

[0012] In an optional implementation, the X element structural layer is a tin structural layer, and the thickness of the tin structural layer is between 1 nm and 20 nm.

[0013] In an optional implementation, the metal structure layer is a Ti / Al / Ti / Au structure layer.

[0014] In an optional implementation, the dielectric layer is an in-situ grown silicon nitride layer.

[0015] According to a second aspect, the present invention provides a method for preparing a gallium nitride HEMT device, comprising the following steps:

[0016] A buffer layer, a channel layer and a barrier layer are sequentially grown on the substrate; a two-dimensional electron gas channel is formed between the channel layer and the barrier layer;

[0017] Etching two ends of the barrier layer to form two epitaxial grooves at the two ends of the barrier layer respectively; the two epitaxial grooves also extend into the channel layer to cut off the two-dimensional electron gas channel at the epitaxial grooves;

[0018] growing a tin oxide epitaxial layer in the epitaxial trench;

[0019] growing a source electrode and a drain electrode on the two tin oxide epitaxial layers respectively;

[0020] growing a dielectric layer on the barrier layer between the two tin oxide epitaxial layers;

[0021] A gate electrode is grown on the dielectric layer.

[0022] In an optional implementation, the tin oxide epitaxial layer is grown by atomic layer deposition.

[0023] In an optional implementation, the source electrode and the drain electrode both include an X element structure layer disposed on the tin oxide epitaxial layer and a metal structure layer disposed on the X element structure layer; wherein the X element is a group IV simple metal element or a group IV alloy element.

[0024] In an optional implementation, the X element structural layer is a tin structural layer, and the thickness of the tin structural layer is between 1 nm and 20 nm.

[0025] The technical solution provided by the present invention has the following advantages:

[0026] 1. The gallium nitride HEMT device provided by the present invention can improve the charge extraction capability of the interface by using the high electron mobility of the tin oxide epitaxial layer, by respectively arranging two epitaxial grooves extending into the channel layer and cutting off the two-dimensional electron gas channel between the barrier layer and the channel layer at both ends of the barrier layer, and arranging a tin oxide epitaxial layer in the epitaxial grooves; and by arranging the source electrode and the drain electrode on the tin oxide epitaxial layer, not only can the device achieve good ohmic contact between the two electrodes (source electrode and drain electrode) and the tin oxide epitaxial layer without high-temperature activation, but also make the ohmic contact in the device be the contact between the electrode metal (the electrode metal of the source electrode and the drain electrode) and the tin oxide, thereby greatly reducing the resistance of the contact surface, and finally reducing the ohmic contact resistance of the gallium nitride HEMT device, so that the gallium nitride HEMT device has low ohmic contact resistance, high threshold voltage, high breakdown voltage, high current density and excellent pinch-off characteristics, and can meet the application requirements of high-voltage and high-power electronic devices.

[0027] 2. The gallium nitride HEMT device provided by the present invention can form N-type heavy doping between the surface of the tin oxide epitaxial layer and the source and drain electrodes by arranging the source electrode and the drain electrode including an X element structure layer arranged on the tin oxide epitaxial layer and a metal structure layer arranged on the X element structure layer, and arranging the X element structure layer to be a group IV single metal element or a group IV alloy element, thereby further reducing the ohmic contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A schematic structural diagram of a gallium nitride HEMT device provided by an embodiment of the present invention;

[0030] Figure 2 A method flow chart of a method for preparing a gallium nitride HEMT device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In the description of the present invention, it should be noted that the terms "upper", "lower", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0033] Example 1

[0034] This embodiment provides a gallium nitride HEMT device, such as Figure 1 As shown, the gallium nitride HEMT device includes a substrate, a buffer layer, a channel layer, a barrier layer, a tin oxide epitaxial layer, a source electrode ( Figure 1 S electrode in), drain electrode ( Figure 1 D electrode in), dielectric layer and gate electrode ( Figure 1 The buffer layer, the channel layer and the barrier layer are sequentially arranged on the substrate, and a two-dimensional electron gas channel is formed between the channel layer and the barrier layer; two epitaxial grooves are respectively arranged at both ends of the barrier layer, and the two epitaxial grooves are also extended into the channel layer to cut off the two-dimensional electron gas channel at the epitaxial grooves; two tin oxide epitaxial layers are respectively grown in the two epitaxial grooves; the source electrode and the drain electrode are respectively grown on the two tin oxide epitaxial layers; the dielectric layer is arranged on the barrier layer and covers the surface of the barrier layer except the area where the two tin oxide epitaxial layers are located; the gate electrode is arranged on the dielectric layer and is located between the source electrode and the drain electrode.

[0035] In this embodiment, the channel layer and the barrier layer may be a GaN channel layer and an AlGaN barrier layer, or may be a GaN channel layer and an InAlN barrier layer, etc.

[0036] In this embodiment, the substrate may be any substrate suitable for epitaxial growth of GaN thin films, and the substrate may be insulating or semi-insulating. Specifically, the substrate may be any one of sapphire, silicon, silicon carbide, gallium nitride, and diamond, and the size of the substrate may range from 2 inches to 8 inches.

[0037] In this embodiment, the buffer layer may be a GaN buffer layer or an AlN buffer layer or the like.

[0038] In an optional specific implementation manner, in order to further improve the quality of the channel layer, such as Figure 1As shown, a nucleation layer can be set between the buffer layer and the substrate. Specifically, the nucleation layer can be set to a GaN nucleation layer; in specific implementation, the GaN nucleation layer can be grown by metal organic chemical vapor deposition (MOCVD) or other methods under low temperature conditions, and the growth temperature can be between 400°C and 700°C; in specific implementation, the film thickness of the GaN nucleation layer can be set to between 10nm and 50nm. At this time, the GaN buffer layer thereon can be set to a GaN thin film layer formed by unintentional doping growth using metal organic chemical vapor deposition (MOCVD) or other methods, and the film thickness of the GaN buffer layer can be between 100nm and 10um.

[0039] In this embodiment, the epitaxial groove is obtained by etching the barrier layer and the channel layer. Figure 1 As shown, it only extends into part of the channel layer, but may also penetrate the channel layer. In specific implementation, taking the thickness of the barrier layer as 30nm and the thickness of the channel layer as 270nm as an example, the depth of the epitaxial groove may be 50nm, 200nm or 300nm, etc.

[0040] In this embodiment, the tin oxide epitaxial layer can be grown by using an atomic layer deposition (ALD) method to achieve precise and controllable deposition growth of the tin oxide epitaxial layer at room temperature.

[0041] In this embodiment, the dielectric layer can be SiN x The dielectric layer; the source electrode and the drain electrode can be Ti / Al / Ti / Au electrodes; the gate electrode can be Ni / Au electrodes. In specific implementation, the dielectric layer can be grown by in-situ growth.

[0042] In summary, the gallium nitride HEMT device in this embodiment, by respectively arranging two epitaxial grooves extending into the channel layer and cutting off the two-dimensional electron gas channel between the barrier layer and the channel layer at both ends of the barrier layer, and arranging a tin oxide epitaxial layer in the epitaxial groove, can improve the charge extraction capability of the interface with the higher electron mobility of the tin oxide epitaxial layer; and by arranging the source electrode and the drain electrode on the tin oxide epitaxial layer, not only can the device achieve good ohmic contact between the two electrodes (source electrode and drain electrode) and the tin oxide epitaxial layer without high-temperature activation, but also makes the ohmic contact in the device a contact between the electrode metal (the electrode metal of the source electrode and the drain electrode) and the tin oxide, thereby greatly reducing the resistance of the contact surface, and finally reducing the ohmic contact resistance of the gallium nitride HEMT device, so that the gallium nitride HEMT device has low ohmic contact resistance, high threshold voltage, high breakdown voltage, high current density and excellent pinch-off characteristics, and can meet the application requirements of high-voltage and high-power electronic devices.

[0043] In an optional specific implementation, in order to further reduce the ohmic contact resistance of the device, the gallium nitride HEMT device in this embodiment can be arranged so that its source electrode and drain electrode both include an X element structure layer and a metal structure layer, wherein the X element structure layer is arranged on the tin oxide epitaxial layer, and the metal structure layer is arranged on the X element structure layer. The X element is a group IV single metal element or a group IV alloy element.

[0044] Specifically, the X element structural layer may be set to be a tin structural layer, and the thickness of the tin structural layer may be set to be between 1 nm and 20 nm.

[0045] Specifically, the X element structure layer may also be set to be a GeSi alloy structure layer.

[0046] Specifically, the metal structure layer may be set to be a Ti / Al / Ti / Au structure layer.

[0047] In the gallium nitride HEMT device in this embodiment, the source electrode and the drain electrode include an X element structure layer provided on the tin oxide epitaxial layer and a metal structure layer provided on the X element structure layer, and the X element structure layer is provided as a group IV single metal element or a group IV alloy element, so that N-type heavy doping can be formed between the surface of the tin oxide epitaxial layer and the source and drain electrodes, thereby further reducing the ohmic contact resistance.

[0048] Example 2

[0049] This embodiment provides a method for preparing a gallium nitride HEMT device, which is the method for preparing a gallium nitride HEMT device in the above-mentioned embodiment 1. The specific content thereof can be understood by referring to the content in the above-mentioned embodiment 1. The content already described in the embodiment 1 will not be repeated in this embodiment.

[0050] S100: growing a buffer layer, a channel layer and a barrier layer on a substrate in sequence; forming a two-dimensional electron gas channel between the channel layer and the barrier layer.

[0051] In an optional specific implementation, a nucleation layer may be provided between the buffer layer and the substrate. In this case, the nucleation layer, the buffer layer, the channel layer and the barrier layer are sequentially grown on the substrate.

[0052] S200: etching two ends of the barrier layer to form two epitaxial grooves at the two ends of the barrier layer respectively; the two epitaxial grooves also extend into the channel layer to cut off the two-dimensional electron gas channel at the epitaxial grooves.

[0053] S300: growing a tin oxide epitaxial layer in the epitaxial trench.

[0054] Specifically, the tin oxide epitaxial layer may be grown by atomic layer deposition.

[0055] S400: growing a source electrode and a drain electrode on the two tin oxide epitaxial layers respectively.

[0056] S500: growing a dielectric layer on the barrier layer between the two tin oxide epitaxial layers;

[0057] S600: growing a gate electrode on the dielectric layer.

[0058] In specific implementation, the order of executing some steps in the above steps S100 to S600 can be adjusted according to the convenience in practical applications. For example, the dielectric layer can be grown in situ after the growth of the tin oxide epitaxial layer (it can be before the growth of the source and drain electrodes, or it can be after the growth of the source and drain electrodes) as mentioned above; or the dielectric layer can be grown on the barrier layer before the epitaxial groove is etched. At this time, when etching to form the epitaxial layer, the two ends of the dielectric layer are etched, and accordingly, the etching forms an epitaxial groove that penetrates the dielectric layer and the barrier layer and extends into the channel layer.

[0059] In an optional specific implementation, in order to further reduce the ohmic contact resistance of the device prepared using the method in this embodiment, the source electrode and the drain electrode can be provided to include an X element structure layer provided on the tin oxide epitaxial layer and a metal structure layer provided on the X element structure layer; wherein the X element is a group IV single metal element or a group IV alloy element.

[0060] Specifically, the X element structural layer may be set as a tin structural layer, and the thickness of the tin structural layer may be set between 1 nm and 20 nm; the X element structural layer may also be set as a GeSi alloy structural layer.

[0061] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. However, the obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims

1. A gallium nitride HEMT device, characterized in that: include: A substrate and a buffer layer, a channel layer and a barrier layer sequentially arranged on the substrate; a two-dimensional electron gas channel is formed between the channel layer and the barrier layer; two epitaxial grooves are respectively arranged at two ends of the barrier layer, and the two epitaxial grooves also extend into the channel layer to cut off the two-dimensional electron gas channel at the epitaxial grooves; Two tin oxide epitaxial layers are grown in the two epitaxial grooves respectively; A source electrode and a drain electrode are respectively grown on the two tin oxide epitaxial layers; A dielectric layer is disposed on the barrier layer and covers the surface of the barrier layer except for the areas where the two tin oxide epitaxial layers are located; The gate electrode is disposed on the dielectric layer and located between the source electrode and the drain electrode.

2. The gallium nitride HEMT device according to claim 1, characterized in that: The source electrode and the drain electrode both include an X element structure layer disposed on the tin oxide epitaxial layer and a metal structure layer disposed on the X element structure layer; wherein the X element is a simple metal element of group IV or an alloy element of group IV.

3. The gallium nitride HEMT device according to claim 2, characterized in that: The X element structural layer is a tin structural layer, and the thickness of the tin structural layer is between 1 nm and 20 nm.

4. The gallium nitride HEMT device according to claim 2, characterized in that: The metal structure layer is a Ti / Al / Ti / Au structure layer.

5. The gallium nitride HEMT device according to claim 1, characterized in that: The dielectric layer is an in-situ grown silicon nitride layer.

6. A method for preparing a gallium nitride HEMT device, characterized in that: The steps include: A buffer layer, a channel layer and a barrier layer are sequentially grown on a substrate; a two-dimensional electron gas channel is formed between the channel layer and the barrier layer; Etching two ends of the barrier layer to form two epitaxial grooves at the two ends of the barrier layer respectively; the two epitaxial grooves also extend into the channel layer to cut off the two-dimensional electron gas channel at the epitaxial grooves; growing a tin oxide epitaxial layer in the epitaxial trench; Growing a source electrode and a drain electrode on the two tin oxide epitaxial layers respectively; growing a dielectric layer on the barrier layer between the two tin oxide epitaxial layers; A gate electrode is grown on the dielectric layer.

7. The method for preparing a gallium nitride HEMT device according to claim 6, characterized in that: The tin oxide epitaxial layer is grown by atomic layer deposition.

8. The method for preparing a gallium nitride HEMT device according to claim 6, characterized in that: The source electrode and the drain electrode both include an X element structure layer disposed on the tin oxide epitaxial layer and a metal structure layer disposed on the X element structure layer; wherein the X element is a simple metal element of group IV or an alloy element of group IV.

9. The method for preparing a gallium nitride HEMT device according to claim 8, characterized in that: The X element structural layer is a tin structural layer, and the thickness of the tin structural layer is between 1 nm and 20 nm.

Images