GaN HEMT device integrated with backward diode and preparation method of GaN HEMT device

Abstract

The invention discloses a GaN HEMT device integrated with a backward diode and a preparation method of the GaN HEMT device. The GaN HEMT device comprises a two-dimensional electron gas structure, a source electrode, a drain electrode, a P-GaN grid electrode, a passivation layer, a source electrode field plate structure, Schottky contact metal, ohmic contact metal and a P-GaN layer. The Schottky contact metal and the surrounding structure of the Schottky contact metal form a Schottky diode, and the P-GaN layer and the surrounding structure of the P-GaN layer form a P-i-N diode. According to the GaN HEMT device, the Schottky diode and the P-i-N diode which are connected in parallel are integrated, and a new path is provided for reverse current of the GaN HEMT device. During reverse conduction, not only can the low reverse conduction voltage of the Schottky diode be utilized, but also the strong overcurrent capability of the P-i-N diode can be exerted; a reverse conducting loop is built by using the source field plate structure, and a reverse conducting part is formed by means of a barrier layer; therefore, the drain region is shared by the reverse conducting part and the forward conducting part, and the area is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of GaN power devices, and in particular relates to a GaN HEMT device with an integrated reverse diode and a preparation method thereof. Background Art

[0002] High electron mobility transistors (GaN HEMTs) made of GaN are widely used in various high-frequency and high-power applications due to their faster switching speed and lower on-resistance. However, in the application of power converters, new requirements are put forward for the reverse conduction capability of the device. For example, in energy storage systems and electric vehicle applications, bidirectional DC-DC converters usually need to transmit electrical energy in both directions, so these applications usually require power devices to have reverse conduction capabilities. Since electrical energy can flow in both directions between the load and the power supply, the power device must be able to maintain low power loss in both forward and reverse current states to improve energy transmission efficiency.

[0003] Although GaN HEMT has bilateral symmetry in structure and has almost no difference in forward and reverse conduction characteristics when turned on, there is a large reverse conduction voltage in the diode reverse conduction mode. This is because the reverse conduction voltage drop of the device is coupled with the gate voltage, and the reverse conduction voltage drop is related to the threshold voltage of the device.

[0004] In practical applications, a reverse-parallel Schottky diode structure is usually integrated to provide a path for reverse current to prevent current from flowing under the gate. However, Schottky diodes are prone to failure under surge current conditions, and their stability is also poor under high-temperature operating environments. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a GaN HEMT device with an integrated reverse diode and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides a GaN HEMT device with an integrated reverse diode, comprising:

[0007] Two-dimensional electron gas structure, source, drain, P-GaN gate, passivation layer, source field plate structure, Schottky contact metal, ohmic contact metal and P-GaN layer; wherein,

[0008] The source electrode and the drain electrode are respectively arranged on both sides of the barrier layer in the two-dimensional electron gas structure;

[0009] The P-GaN gate is disposed on a portion of the upper surface of the two-dimensional electron gas structure close to the source electrode;

[0010] The Schottky contact metal and the P-GaN layer are arranged in a partial area between the drain and the P-GaN gate on the upper surface of the two-dimensional electron gas structure; the Schottky contact metal and the P-GaN layer are staggered in the lateral direction of the GaN HEMT device; the Schottky contact metal and its surrounding partial structure constitute a Schottky diode, and the P-GaN layer and its surrounding partial structure constitute a PiN diode;

[0011] The ohmic contact metal is disposed on the upper surface of the P-GaN layer;

[0012] The passivation layer is disposed on the remaining area of ​​the upper surface of the two-dimensional electron gas structure and the upper surface of the P-GaN gate;

[0013] The source field plate structure is arranged in a partial area of ​​the upper surface of the passivation layer and a side area of ​​the passivation layer; the partial area of ​​the upper surface of the passivation layer includes: an area between the source and the Schottky contact metal in the upper surface of the passivation layer and a partial area between the drain and the Schottky contact metal close to the Schottky contact metal.

[0014] In one embodiment of the present invention, a two-dimensional electron gas structure comprises:

[0015] A substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer are stacked in sequence from bottom to top; wherein the channel layer and the barrier layer form a two-dimensional electron gas channel.

[0016] In one embodiment of the present invention, the material of the substrate includes silicon; the material of the nucleation layer includes AlN; the material of the buffer layer includes AlGaN; the material of the channel layer includes GaN; and the material of the barrier layer includes AlGaN.

[0017] In one embodiment of the present invention, a P-GaN gate comprises:

[0018] Partial P-GaN gate and gate metal arranged from bottom to top.

[0019] In one embodiment of the present invention, a Schottky diode comprises:

[0020] The Schottky contacts the metal and barrier layers.

[0021] In one embodiment of the present invention, a PiN diode comprises:

[0022] The P-GaN layer, the channel layer, the barrier layer and the two-dimensional electron gas between the channel layer and the barrier layer.

[0023] In one embodiment of the present invention, the remaining area of ​​the upper surface of the two-dimensional electron gas structure includes:

[0024] The upper surface of the two-dimensional electron gas structure includes a region between the source and the P-GaN gate, a region between the P-GaN gate and the source field plate structure, and a region between the source field plate structure and the drain.

[0025] In a second aspect, the present invention provides a method for preparing a GaN HEMT device with an integrated reverse diode, the method comprising:

[0026] Prepare an epitaxial wafer; the epitaxial wafer comprises from bottom to top: a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and an initial P-GaN layer; the substrate, the nucleation layer, the buffer layer, the channel layer and the barrier layer constitute a two-dimensional electron gas structure;

[0027] Defining a partial P-GaN gate and a P-GaN layer region on the initial P-GaN layer, and etching the region other than the partial P-GaN gate and the P-GaN layer region until the barrier layer is reached to obtain a partial P-GaN gate and a P-GaN layer;

[0028] Depositing SiN on the surface of the current sample to form a first passivation layer;

[0029] Defining source and drain regions on the surface of the first passivation layer, etching the source and drain regions, the etching depth extending to the channel layer, to form source and drain grooves; using PVD technology to prepare ohmic contact source and drain in the source and drain grooves;

[0030] An ohmic contact metal region is defined on the surface of the first passivation layer, etching is performed in the ohmic contact metal region until the P-GaN layer is etched to form an ohmic contact metal groove, and Ti, Al, Ni and Au are sputtered from bottom to top in the ohmic contact metal groove using PVD technology to prepare an ohmic contact metal;

[0031] A P-GaN gate region is defined on the surface of the first passivation layer, the P-GaN gate region is etched until the portion of the P-GaN gate is etched to form a gate groove, and Ti, Al and Au are sputtered from bottom to top using PVD technology to prepare a gate metal; the portion of the P-GaN gate and the gate metal constitute a P-GaN gate;

[0032] Depositing SiN on the surface of the current sample to form a second passivation layer; the first passivation layer and the second passivation layer constitute a passivation layer;

[0033] A Schottky metal region and an ohmic contact metal region are defined on the surface of the second passivation layer, and etching is performed on the Schottky metal region and the ohmic contact metal region until the barrier layer and the ohmic contact metal are respectively etched;

[0034] A metal field plate pattern is defined on the surface of the current sample, and Ti and Au are sputtered from bottom to top on the metal field plate pattern using PVD technology to prepare the source field plate structure and Schottky contact metal.

[0035] In one embodiment of the present invention, the ohmic contact source and drain are prepared in the source and drain grooves by using PVD technology, including:

[0036] Using PVD technology, Ti, Al, Ni and Au are sputtered from bottom to top in the source and drain grooves to prepare source metal and drain metal of ohmic contact;

[0037] The source electrode metal and the drain electrode metal are subjected to rapid thermal annealing in an N atmosphere at a preset temperature to obtain the source electrode and the drain electrode.

[0038] In one embodiment of the present invention, the area corresponding to the metal field plate pattern includes:

[0039] The upper surface of the two-dimensional electron gas structure includes a region between the source and the P-GaN gate, a region between the P-GaN gate and the source field plate structure, a region between the source field plate structure and the drain, and an upper surface of the P-GaN gate.

[0040] Beneficial effects of the present invention:

[0041] 1. The present invention integrates a Schottky diode and a PiN diode on the basis of the original GaN HEMT. The two diodes are connected in parallel, providing a new path for the reverse current of the GaN HEMT device. When the device is reversely conducted, it can not only take advantage of the low reverse conduction voltage of the Schottky diode, but also give play to the strong overcurrent capacity of the PiN diode.

[0042] 2. By integrating two diodes and using the source field plate structure to build a reverse conduction loop, the reverse conduction part is formed with the help of the barrier layer. This design allows the reverse conduction part to share the drain region with the forward conduction, avoiding the addition of additional structures to occupy new chip area. In addition, the staggered and parallel design of the diode structure reduces the impact on the channel two-dimensional electron gas, so it has little impact on the original forward conduction performance of the GaN HEMT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the three-dimensional structure of a GaN HEMT device with an integrated reverse diode provided by an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of a partial structure of a GaN HEMT device with an integrated reverse diode provided by an embodiment of the present invention;

[0045] Figure 3 A lateral cross-sectional view of a GaN HEMT device with an integrated reverse diode along the upper surface of a P-GaN layer provided by an embodiment of the present invention;

[0046] Figure 4 A schematic front view of a section A of a partial structure of a GaN HEMT device with an integrated reverse diode provided by an embodiment of the present invention;

[0047] Figure 5 A schematic front view of a section B of a partial structure of a GaN HEMT device with an integrated reverse diode provided by an embodiment of the present invention;

[0048] Figure 6 A schematic diagram of the steps of a method for preparing a GaN HEMT device with an integrated reverse diode provided by an embodiment of the present invention;

[0049] Figure 7A-Figure 7I A process flow chart of a GaN HEMT device with an integrated reverse diode provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0051] In order to solve the problems existing in the prior art, an embodiment of the present invention provides a GaN HEMT device with an integrated reverse diode and a method for preparing the same.

[0052] The following is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

[0053] Below, firstly, a GaN HEMT device with integrated reverse diode provided by an embodiment of the present invention is introduced.

[0054] like Figure 1 As shown, a GaN HEMT device with an integrated reverse diode provided by an embodiment of the present invention may include:

[0055] Two-dimensional electron gas structure 1, source 2, drain 3, P-GaN gate 4, passivation layer 5, source field plate structure 6, Schottky contact metal 7, ohmic contact metal 8 and P-GaN layer 9; wherein,

[0056] The source electrode 2 and the drain electrode 3 are respectively arranged on two sides of the barrier layer 105 in the two-dimensional electron gas structure 1;

[0057] The P-GaN gate 4 is disposed on a portion of the upper surface of the two-dimensional electron gas structure 1 close to the source 2;

[0058] The Schottky contact metal 7 and the P-GaN layer 9 are arranged in a partial area between the drain 3 and the P-GaN gate 4 on the upper surface of the two-dimensional electron gas structure 1; the Schottky contact metal 7 and the P-GaN layer 9 are staggered in the lateral direction of the GaN HEMT device; the Schottky contact metal 7 and its surrounding partial structure constitute a Schottky diode, and the P-GaN layer 9 and its surrounding partial structure constitute a PiN diode;

[0059] The ohmic contact metal 8 is disposed on the upper surface of the P-GaN layer 9;

[0060] The passivation layer 5 is disposed on the remaining area of ​​the upper surface of the two-dimensional electron gas structure 1 and the upper surface of the P-GaN gate 4;

[0061] The source field plate structure 6 is arranged in a partial area of ​​the upper surface of the passivation layer 5 and a side area of ​​the passivation layer 5; the partial area of ​​the upper surface of the passivation layer 5 includes: an area between the source 2 and the Schottky contact metal 7 in the upper surface of the passivation layer 5 and a partial area between the drain 3 and the Schottky contact metal 7 close to the Schottky contact metal 7.

[0062] The GaN HEMT device provided in the embodiment of the present invention integrates a Schottky diode and a PiN diode on the basis of the original GaN HEMT, and the two diodes are connected in parallel, providing a new path for the reverse current of the GaN HEMT device. When the device is reversely conducted, it can not only utilize the advantages of the low reverse conduction voltage of the Schottky diode, but also exert the strong overcurrent capacity of the PiN diode.

[0063] For ease of understanding, the following will combine Figure 2 , Figure 3 , Figure 4 and Figure 5 The structure of the GaN HEMT device with integrated reverse diode provided in the embodiment of the present invention is specifically introduced.

[0064] Specifically, in order to more clearly show the connection relationship between the source field plate structure 6, the Schottky contact metal 7, the ohmic contact metal 8 and the P-GaN layer 9, the embodiment of the present invention provides a partial structural schematic diagram of a GaN HEMT device, see Figure 2 .specific Figure 2 The partial structure of the passivation layer on the right side of the P-GaN layer 9 and the partial structure of the source field plate structure are omitted. Figure 2It can be seen that the Schottky contact metal 7 and the P-GaN layer 9 are disposed in a partial area between the drain 3 and the P-GaN gate 4 on the upper surface of the two-dimensional electron gas structure 1. In order to more clearly show the connection relationship between the Schottky contact metal 7 and the P-GaN layer 9, an embodiment of the present invention provides a transverse cross-sectional view of the GaN HEMT device along the upper surface of the P-GaN layer, see Figure 3 .from Figure 3 It can be seen that the Schottky contact metal 7 and the P-GaN layer 9 are arranged side by side and staggered in the lateral direction of the GaN HEMT device. It can be understood that the Schottky contact metal 7, the ohmic contact metal 8 and the P-GaN layer 9 constitute a fin structure. Optionally, the width of the Schottky contact metal 7 and the P-GaN layer 9 in the lateral direction of the GaN HEMT device can be equal, and the specific width can be set to 2μm.

[0065] The two-dimensional electron gas structure 1 may include:

[0066] A substrate 101 , a nucleation layer 102 , a buffer layer 103 , a channel layer 104 and a barrier layer 105 are sequentially stacked from bottom to top; wherein the channel layer 104 and the barrier layer 105 form a two-dimensional electron gas channel.

[0067] The material of the substrate 101 may include silicon; the material of the nucleation layer 102 may include AlN; the material of the buffer layer 103 may include AlGaN; the material of the channel layer 104 may include GaN; and the material of the barrier layer 105 may include AlGaN.

[0068] Optionally, the substrate 101 may be made of a P-type (1, 1, 1) crystalline silicon material, and the thickness may be 200 μm; the thickness of the nucleation layer 102 may be 200 nm; the buffer layer 103 may be made of Al 0.3 Ga 0.7 N, and may be 5 μm thick; the channel layer 104 may be 200 nm thick; the barrier layer 105 may be made of Al 0.2 Ga 0.8 N, and the thickness can be 15nm.

[0069] The P-GaN gate 4 may include:

[0070] A partial P-GaN gate 41 and a gate metal 42 are arranged sequentially from bottom to top.

[0071] The material of the P-GaN gate 41 may be GaN doped with Mg+ ions, and the Mg+ ion doping concentration may be 10 19 cm -3 , the thickness can be 70 nm, forming a Schottky contact with the gate metal 42.

[0072] The GaN HEMT device provided in the embodiment of the present invention realizes two functions, which are respectively: a lateral power device and a reverse conducting part from bottom to top. The reverse conducting part may include: a source field plate structure 6, a Schottky contact metal 7, an ohmic contact metal 8 and a P-GaN layer 9.

[0073] Schottky diodes can include:

[0074] Schottky contact metal 7 and barrier layer 105 .

[0075] The upper end of the Schottky contact metal 7 is connected to the source field plate structure 6, and the lower end is connected to the barrier layer 105 to form a Schottky barrier. The Schottky diode can prevent current from flowing through the Schottky contact metal 7 when the device is forward-conducted.

[0076] PiN diodes can include:

[0077] The P-GaN layer 9 , the channel layer 104 , the barrier layer 105 , and the two-dimensional electron gas 2DEG between the channel layer 104 and the barrier layer 105 .

[0078] The P-GaN layer 9 is disposed above the barrier layer 105, with the upper end connected to the ohmic contact metal 8 and the lower end connected to the barrier layer 105. The PiN diode can prevent current from flowing through the P-GaN layer 9 when the device is forward-conducted.

[0079] The P-GaN layer 9 may be composed of P-type doped GaN, wherein the Mg+ ion doping concentration may be 10 19 cm -3 , the thickness can be 70nm.

[0080] The GaN HEMT device provided in the embodiment of the present invention integrates two diodes and uses the source field plate structure to build a reverse conduction loop, and at the same time forms a reverse conduction part with the help of a barrier layer. This design allows the reverse conduction part to share the drain region with the forward conduction, avoiding the addition of additional structures to occupy new chip area. In addition, the staggered and parallel design of the diode structure reduces the impact on the channel two-dimensional electron gas, and therefore has little impact on the original forward conduction performance of the GaN HEMT device.

[0081] The GaN HEMT device provided by the embodiment of the present invention has a source 2 and a drain 3 arranged on a two-dimensional electron gas structure 1 from left to right, and a source field plate structure 6 is extended from the source 2 to the right above the P-GaN gate 4. The source field plate structure connected to the source 2 can adjust the electric field concentration phenomenon on the right side of the P-GaN gate 4 and the Schottky contact metal 6 and the P-GaN layer 8 according to the voltage applied to the source, so as to prevent the device from breaking down prematurely.

[0082] A schematic diagram of a front view of a section A of a partial structure of a GaN HEMT device with an integrated reverse diode provided by an embodiment of the present invention, see Figure 4 ; Front view of section B, see Figure 5 Understandably, Figure 4 and Figure 5 The schematic diagram of the remaining structure of the GaN HEMT device after omitting the partial structure of the passivation layer on the right side of the P-GaN layer 9 and the partial structure of the source field plate structure. Figure 2 , Figure 3 , Figure 4 and Figure 5 It can be seen that the passivation layer 5 is arranged on the remaining area of ​​the upper surface of the two-dimensional electron gas structure 1 and the upper surface of the P-GaN gate 4; wherein the remaining area of ​​the upper surface of the two-dimensional electron gas structure 1 may include: the area between the source 2 and the P-GaN gate 4, the area between the P-GaN gate 4 and the source field plate structure 6, and the area between the source field plate structure 6 and the drain 3 in the upper surface of the two-dimensional electron gas structure 1.

[0083] The source field plate structure 6 is arranged on a partial area of ​​the upper surface of the passivation layer 5 and a side area of ​​the passivation layer 5; the partial area of ​​the upper surface of the passivation layer 5 includes the upper surface of the passivation layer 5, the area between the source 2 and the Schottky contact metal 7, and the partial area between the drain 3 and the Schottky contact metal 7 close to the Schottky contact metal 7.

[0084] The embodiment of the present invention integrates a Schottky diode and a PiN diode on the basis of the original GaN HEMT. The two diodes are connected in parallel, providing a new path for the reverse current of the GaN HEMT device. When the device is reverse-conducting, it can not only take advantage of the low reverse conduction voltage of the Schottky diode, but also give play to the strong overcurrent capacity of the PiN diode; by integrating the two diodes and using the source field plate structure to build a reverse conduction loop, and at the same time forming a reverse conduction part with the help of the barrier layer. This design allows the reverse conduction part to share the drain area with the forward conduction, avoiding the addition of additional structures to occupy new chip area. In addition, the staggered and side-by-side design of the diode structure reduces the impact on the channel two-dimensional electron gas, and therefore has little impact on the original forward conduction performance of the GaN HEMT device.

[0085] In a second aspect, corresponding to the above-mentioned embodiment, the embodiment of the present invention further provides a method for preparing a GaN HEMT device with an integrated reverse diode, such as Figure 6 As shown, the preparation method comprises:

[0086] S1, preparing an epitaxial wafer; the epitaxial wafer includes from bottom to top: a substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105 and an initial P-GaN layer; the substrate 101, the nucleation layer 102, the buffer layer 103, the channel layer 104 and the barrier layer 105 constitute a two-dimensional electron gas structure 1.

[0087] The substrate 101, the nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105 and the initial P-GaN layer are made of Si material, AlN material, Al 0.3 Ga 0.7 N, GaN, Al 0.2 Ga 0.8 N and Mg+-doped GaN. The structure of the sample obtained after step S1 is as follows Fig. 7A shown.

[0088] Specifically, a low-temperature AlN nucleation layer is first epitaxially grown on the upper surface of the substrate 101 using MOCVD (Metal organic Chemical Vapor Deposition) technology, and then a high-temperature AlN nucleation layer is epitaxially grown on the upper surface of the low-temperature AlN nucleation layer, thereby obtaining the nucleation layer 102; wherein the thickness of the low-temperature AlN nucleation layer may be 30 nm, and the thickness of the high-temperature AlN nucleation layer may be 170 nm.

[0089] After the nucleation layer 102 is prepared, undoped Al is deposited on the upper surface of the nucleation layer 102 using MOCVD technology with trimethylaluminum as an aluminum source, trimethylgallium as a gallium source, and ammonia as an ammonia source. 0.3 Ga 0.7 N buffer layer, thereby obtaining the buffer layer 103, and the thickness of the buffer layer 103 can be 5 μm.

[0090] After the buffer layer 103 is prepared, an undoped GaN channel layer is deposited on the upper surface of the buffer layer 103 using MOCVD technology with trimethylgallium as a gallium source and ammonia as an ammonia source, thereby obtaining a channel layer 104. The thickness of the channel layer 104 may be 200 nm.

[0091] After the channel layer 104 is prepared, undoped Al is deposited on the upper surface of the channel layer 104 using MOCVD technology with trimethylgallium as a gallium source, trimethylaluminum as an aluminum source, and ammonia as an ammonia source. 0.2 Ga 0.8 N barrier layers are formed, thereby obtaining a barrier layer 105; the thickness of the barrier layer 105 may be 15 nm.

[0092] After the barrier layer 105 is prepared, a Mg+ doped GaN layer is epitaxially grown on the upper surface of the barrier layer using MOCVD technology. The epitaxially grown Mg+ doped GaN layer is annealed at high temperature to form a P-GaN layer; the thickness of the P-GaN layer can be 70nm; wherein the doping concentration of Mg+ ions in the P-GaN layer can be 10 19 cm 3 .

[0093] S2, define a partial P-GaN gate and a P-GaN layer region on the initial P-GaN layer, and etch the region other than the partial P-GaN gate and the P-GaN layer region until the barrier layer 105 is reached to obtain a partial P-GaN gate 41 and a P-GaN layer 9. The structure of the sample obtained after step S2 is as follows Figure 7B shown.

[0094] Specifically, first, a partial P-GaN gate and P-GaN layer region are defined on the initial P-GaN layer; secondly, a photoresist is spin-coated on the region outside the defined partial P-GaN gate and P-GaN layer region and exposed and developed, and an ICP (Inductively Coupled Plasma) etching process is used to etch downward the region outside the defined partial P-GaN gate and P-GaN layer region until the etching depth extends to the barrier layer 105.

[0095] S3, depositing Si3N4 on the surface of the current sample to form a first passivation layer.

[0096] S4, defining source and drain regions on the surface of the first passivation layer, etching the source and drain regions, the etching depth extending to the channel layer 104, forming source and drain grooves; using PVD technology to prepare ohmic contact source 2 and drain 3 in the source and drain grooves.

[0097] Specifically, the source and drain regions are defined on the surface of the first passivation layer, and the source and drain regions are subjected to ICP etching, and the etching depth extends to the barrier layer 105 and the channel layer 104 to form source and drain grooves. Figure 7C As shown; using PVD technology to prepare the source 2 and drain 3 of ohmic contact in the source and drain grooves, which may include:

[0098] The PVD technology is used to sputter Ti, Al, Ni and Au from bottom to top in the source and drain grooves to prepare the source and drain metals of ohmic contact. The samples obtained at this time are as follows Fig.7D shown.

[0099] The source metal and the drain metal are subjected to rapid thermal annealing in a N2 atmosphere at a preset temperature to obtain a source 2 and a drain 3. The thicknesses of Ti, Al, Ni and Au can be 20 nm, 140 nm, 50 nm and 40 nm, respectively, the preset temperature can be set to 865° C., and the rapid thermal annealing time can be set to 35 s.

[0100] S5, define an ohmic contact metal region on the surface of the first passivation layer, etch the ohmic contact metal region to the P-GaN layer 9, form an ohmic contact metal groove, and use PVD technology to sputter Ti, Al, Ni and Au from bottom to top in the ohmic contact metal groove to prepare an ohmic contact metal 8. The structure of the sample obtained after step S5 is as follows Fig. 7E shown.

[0101] Specifically, a photoresist is applied on the surface of the first passivation layer to define an ohmic contact metal area and the area is exposed and developed. The first passivation layer deposited on the surface of the P-GaN layer 9 is removed in the ohmic contact metal area by a hydrogen ion wet method to form an ohmic contact metal groove. The PVD (Physical Vapor Deposition) technology is used to sputter Ti, Al, Ni and Au from bottom to top in the ohmic contact metal groove to prepare the first metal. The thickness of each metal layer in the first metal can be 20nm, 50nm, 50nm and 30nm respectively. The first metal formed by sputtering is subjected to rapid thermal annealing for 35s in an N2 atmosphere at a temperature of 865°C to form an ohmic contact metal 8.

[0102] S6, define a P-GaN gate region on the surface of the first passivation layer, etch the P-GaN gate region until a portion of the P-GaN gate 41 is etched to form a gate groove, and use PVD technology to sputter Ti, Al and Au from bottom to top to prepare a gate metal 42; a portion of the P-GaN gate 41 and the gate metal 42 constitute a P-GaN gate 4. The structure of the sample obtained after step S6 is as follows Figure 7F shown.

[0103] Specifically, a P-GaN gate region is defined on the surface of the first passivation layer, and a portion of the first passivation layer deposited on the surface of the P-GaN gate 41 is removed from the P-GaN gate region using a hydrogen ion wet method. The etching depth extends to a portion of the P-GaN gate 41 to form a gate groove, and a second metal is prepared by sputtering Ti, Al and Au from bottom to top using PVD technology. The thickness of each metal layer can be 20nm, 50nm and 30nm, respectively. The second metal formed by sputtering is annealed for 300s in an N2 atmosphere at a temperature of 450°C to complete the preparation of the gate metal 42 of the Schottky contact.

[0104] S7, Si3N4 is deposited on the surface of the current sample to form a second passivation layer; the first passivation layer and the second passivation layer constitute a passivation layer 5. The structure of the sample obtained after step S7 is completed is as follows Figure 7G shown.

[0105] S8, defining a Schottky metal region and an ohmic contact metal region on the surface of the second passivation layer, and etching the Schottky metal region and the ohmic contact metal region to the barrier layer 105 and the ohmic contact metal 8, respectively. The structure of the sample obtained after step S8 is completed is as follows Figure 7H shown.

[0106] Specifically, the Schottky metal region and the ohmic contact metal region defined on the surface of the second passivation layer are removed in batches by using a hydrogen ion wet method, and are etched to the barrier layer 105 and the ohmic contact metal 8 respectively.

[0107] S9, a metal field plate pattern is defined on the surface of the current sample, and Ti and Au are sputtered from bottom to top on the metal field plate pattern using PVD technology to prepare a source field plate structure 6 and a Schottky contact metal 7. The structure of the sample obtained after step S9 is completed is as follows Fig.7I shown.

[0108] Specifically, a metal field plate pattern is defined on the surface of the current sample, and Ti and Au are sputtered from bottom to top on the metal field plate pattern using PVD technology to prepare the metal field plate, and the thickness of each metal layer can be 20nm and 130nm respectively, and the metal field plate formed by sputtering is annealed for 300s in N2 atmosphere at a temperature of 450°C to complete the preparation of the source field plate structure 6 and the Schottky contact metal 7. Among them, the area corresponding to the metal field plate pattern may include: the area between the source 2 and the P-GaN gate 4 in the upper surface of the two-dimensional electron gas structure 1, the area between the P-GaN gate 4 and the source field plate structure 6, the area between the source field plate structure 6 and the drain 3, and the upper surface of the P-GaN gate 4.

[0109] In summary, the embodiments of the present invention have the following advantages:

[0110] 1. The reverse conduction circuit is built using the source field plate structure, and the reverse conduction part is formed by using the barrier layer, which shares the drain area with the forward conduction, greatly reducing the area and space occupied by adding additional structures.

[0111] 2. The staggered and parallel design reduces the impact on the two-dimensional electron gas and minimizes the impact on the original forward conduction performance of the device.

[0112] 3. Combining the advantages of two types of diodes, it has the advantages of lower reverse conduction voltage of Schottky diodes and good overcurrent capability of PiN diodes.

[0113] It should be noted that, in the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0114] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0115] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A GaN HEMT device with an integrated reverse diode, characterized in that: include: Two-dimensional electron gas structure (1), source (2), drain (3), P-GaN gate (4), passivation layer (5), source field plate structure (6), Schottky contact metal (7), ohmic contact metal (8) and P-GaN layer (9); wherein, The source electrode (2) and the drain electrode (3) are respectively arranged on both sides of the barrier layer (105) in the two-dimensional electron gas structure (1); The P-GaN gate (4) is arranged on a partial area of ​​the upper surface of the two-dimensional electron gas structure (1) close to the source (2); The Schottky contact metal (7) and the P-GaN layer (9) are arranged in a partial area between the drain (3) and the P-GaN gate (4) on the upper surface of the two-dimensional electron gas structure (1); the Schottky contact metal (7) and the P-GaN layer (9) are arranged in a staggered manner in the lateral direction of the GaN HEMT device; the Schottky contact metal (7) and the surrounding partial structure form a Schottky diode, and the P-GaN layer (9) and the surrounding partial structure form a PiN diode; The ohmic contact metal (8) is arranged on the upper surface of the P-GaN layer (9); The passivation layer (5) is arranged on the remaining area of ​​the upper surface of the two-dimensional electron gas structure (1) and the upper surface of the P-GaN gate (4); The source field plate structure (6) is arranged on a partial area of ​​the upper surface of the passivation layer (5) and a side area of ​​the passivation layer (5); the partial area of ​​the upper surface of the passivation layer (5) includes: an area between the source electrode (2) and the Schottky contact metal (7) and a partial area between the drain electrode (3) and the Schottky contact metal (7) close to the Schottky contact metal (7) on the upper surface of the passivation layer (5).

2. The GaN HEMT device with integrated reverse diode according to claim 1, characterized in that: The two-dimensional electron gas structure (1) comprises: A substrate (101), a nucleation layer (102), a buffer layer (103), a channel layer (104) and a barrier layer (105) are stacked in sequence from bottom to top; wherein the channel layer (104) and the barrier layer (105) form a two-dimensional electron gas channel.

3. The GaN HEMT device with integrated reverse diode according to claim 2, characterized in that: The material of the substrate (101) includes silicon; the material of the nucleation layer (102) includes AlN; the material of the buffer layer (103) includes AlGaN; the material of the channel layer (104) includes GaN; and the material of the barrier layer (105) includes AlGaN.

4. The GaN HEMT device with integrated reverse diode according to claim 1, characterized in that: The P-GaN gate (4) comprises: A partial P-GaN gate (41) and a gate metal (42) are arranged in sequence from bottom to top.

5. The GaN HEMT device with integrated reverse diode according to claim 2, characterized in that: The Schottky diode comprises: The Schottky contact metal (7) and the barrier layer (105).

6. The GaN HEMT device with integrated reverse diode according to claim 2, characterized in that: The PiN diode comprises: The P-GaN layer (9), the channel layer (104), the barrier layer (105) and the two-dimensional electron gas between the channel layer (104) and the barrier layer (105).

7. The GaN HEMT device with integrated reverse diode according to claim 1, characterized in that: The remaining area of ​​the upper surface of the two-dimensional electron gas structure (1) comprises: The upper surface of the two-dimensional electron gas structure (1) includes an area between the source (2) and the P-GaN gate (4), an area between the P-GaN gate (4) and the source field plate structure (6), and an area between the source field plate structure (6) and the drain (3).

8. A method for preparing a GaN HEMT device with an integrated reverse diode, characterized in that: include: Preparation of epitaxial wafers; The epitaxial wafer comprises, from bottom to top, a substrate (101), a nucleation layer (102), a buffer layer (103), a channel layer (104), a barrier layer (105) and an initial P-GaN layer; the substrate (101), the nucleation layer (102), the buffer layer (103), the channel layer (104) and the barrier layer (105) constitute a two-dimensional electron gas structure (1); Defining a partial P-GaN gate and a P-GaN layer region on the initial P-GaN layer, etching the region other than the partial P-GaN gate and the P-GaN layer region until the barrier layer (105) is reached, thereby obtaining a partial P-GaN gate (41) and a P-GaN layer (9); Depositing Si3N4 on the surface of the current sample to form a first passivation layer; Defining source and drain regions on the surface of the first passivation layer, etching the source and drain regions to a depth extending to the channel layer (104) to form source and drain grooves; and using PVD technology to prepare ohmic contact source (2) and drain (3) in the source and drain grooves; An ohmic contact metal region is defined on the surface of the first passivation layer, etching is performed in the ohmic contact metal region until the P-GaN layer (9) is etched to form an ohmic contact metal groove, and Ti, Al, Ni and Au are sputtered from bottom to top in the ohmic contact metal groove using PVD technology to prepare an ohmic contact metal (8); A P-GaN gate region is defined on the surface of the first passivation layer, the P-GaN gate region is etched until the partial P-GaN gate (41) is etched to form a gate groove, and Ti, Al and Au are sputtered from bottom to top using PVD technology to prepare a gate metal (42); the partial P-GaN gate (41) and the gate metal (42) constitute a P-GaN gate (4); Depositing Si3N4 on the surface of the current sample to form a second passivation layer; the first passivation layer and the second passivation layer constitute a passivation layer (5); Defining a Schottky metal region and the ohmic contact metal region on the surface of the second passivation layer, and etching the Schottky metal region and the ohmic contact metal region to the barrier layer (105) and the ohmic contact metal (8), respectively; A metal field plate pattern is defined on the surface of the current sample, and Ti and Au are sputtered from bottom to top on the metal field plate pattern using PVD technology to prepare the source field plate structure (6) and Schottky contact metal (7).

9. The GaN HEMT device with integrated reverse diode according to claim 8, characterized in that: The method of using PVD technology to prepare an ohmic contact source (2) and a drain (3) in the source and drain grooves comprises: Using PVD technology, Ti, Al, Ni and Au are sputtered from bottom to top in the source and drain grooves to prepare source metal and drain metal of ohmic contact; The source electrode metal and the drain electrode metal are subjected to rapid thermal annealing in an N2 atmosphere at a preset temperature to obtain the source electrode (2) and the drain electrode (3).

10. The GaN HEMT device with integrated reverse diode according to claim 8, characterized in that: The area corresponding to the metal field plate pattern includes: The upper surface of the two-dimensional electron gas structure (1) includes an area between the source (2) and the P-GaN gate (4), an area between the P-GaN gate (4) and the source field plate structure (6), an area between the source field plate structure (6) and the drain (3), and an upper surface of the P-GaN gate (4).

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