Shielded gate trench MOS device and manufacturing method thereof

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a shielded gate trench MOS device, which comprises: a substrate, an epitaxial layer, a trench in the epitaxial layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a gate oxide layer, a first shielding gate field oxide layer and a second shielding gate field oxide layer in the trench, and a control gate, a first shielding gate and a second shielding gate in the trench; the control gate, the first shielding gate and the second shielding gate are in an up-and-down structure; the second shielding gate is located between the first shielding gate and the control gate; the first interlayer dielectric layer is located between the first shielding gate and the second shielding gate; the second interlayer dielectric layer is located between the second shielding gate and the control gate; the gate oxide layer is located between the control gate and the inner wall of the trench; the first shielding gate field oxide layer is located between the first shielding gate and the inner wall of the trench; and the second shielding gate field oxide layer is located between the second shielding gate and the inner wall of the trench. The device reduces gate-drain capacitance, increases gate-source capacitance, and improves EMI performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a shielded gate trench MOS device and a manufacturing method thereof. Background Art

[0002] Shielded Gate Trench MOS device (SGTMOS) is an advanced power MOSFET structure device designed to improve the performance and reliability of the device. Through the structure of the control gate and the shield gate, the shielded gate trench MOS device optimizes the electric field distribution of the device, reduces switching losses, and improves the breakdown voltage and reliability. Therefore, the shielded gate trench MOS device is widely used in high-frequency switching power supplies. Due to its structural characteristics, the shielded gate trench MOS device has a smaller parasitic capacitance, which makes the shielded gate trench MOS device have a faster turn-on and turn-off speed. However, faster switching speeds are always accompanied by extremely high current change rates di / dt and voltage change rates dv / dt, which makes the EMI (electromagnetic interference) problem of shielded gate trench MOS devices in high-frequency applications extremely serious.

[0003] The main factor affecting the switching speed of power MOS devices is the gate-drain capacitance. When the gate-drain capacitance of the device is small, the gate-drain capacitance charging and discharging time is short during the switching process of the MOS device, the switching speed is fast, and the switching loss is small. Therefore, the existing shielded gate trench MOS device achieves the purpose of improving the EMI performance during the period by reducing the manufacturing process of the gate-drain capacitance. However, the manufacturing process of reducing the gate-drain capacitance of the existing shielded gate trench MOS device often requires high etching accuracy, resulting in the existing shielded gate trench MOS device having the problems of low manufacturing efficiency and high manufacturing cost while improving the EMI performance of the device. Summary of the invention

[0004] The embodiments of the present application provide a shielded gate trench MOS device and its manufacturing method, thereby solving the technical problems in the prior art that the shielded gate trench MOS device has low manufacturing efficiency and high manufacturing cost while improving the EMI performance of the device. By merely adding a shielded gate conductive polysilicon layer between the control gate and the shielding gate on the basis of the traditional shielded gate trench MOS device, the gate-drain capacitance is reduced, the gate-source capacitance is increased, the EMI performance of the device is improved, and the manufacturing process is simple, the manufacturing cost is low, the manufacturing efficiency is high, and other technical effects are achieved.

[0005] In a first aspect, an embodiment of the present invention provides a shielded gate trench MOS device, comprising: a substrate, an epitaxial layer of a first conductivity type located on the substrate, a trench located in the epitaxial layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a gate oxide layer, a first shielding gate field oxide layer and a second shielding gate field oxide layer located in the trench, and a control gate and two shielding gates located in the trench, wherein the two shielding gates are respectively a first shielding gate and a second shielding gate;

[0006] The first shielding gate is located at the bottom of the trench; the second shielding gate is located above the first shielding gate and below the control gate; the control gate is located at the top of the trench and above the second shielding gate;

[0007] The first interlayer dielectric layer is filled between the first shielding grid and the second shielding grid;

[0008] The second interlayer dielectric layer is filled between the second shielding gate and the control gate;

[0009] The gate oxide layer is filled between the control gate and the sidewall in the trench;

[0010] The first shielding gate field oxide layer is filled between the first shielding gate and the sidewalls and bottom wall in the trench;

[0011] The second shielding gate field oxide layer is filled between the second shielding gate and the sidewall in the trench.

[0012] Optionally, the lateral width of the first shielding gate field oxide layer is greater than the lateral width of the second shielding gate field oxide layer, and the lateral width of the second shielding gate field oxide layer is greater than the lateral width of the gate oxide layer.

[0013] Optionally, a longitudinal thickness of the first interlayer dielectric layer is consistent with a lateral width of the gate oxide layer.

[0014] Optionally, a difference between a lateral width of the control gate and a lateral width of the second shield gate is consistent with a lateral width of the gate oxide layer.

[0015] Optionally, a longitudinal thickness of the second shielding grid is smaller than a longitudinal thickness of the first shielding grid.

[0016] Optionally, the longitudinal thickness of the second interlayer dielectric layer is in the range of 0.25 um to 0.35 um.

[0017] Optionally, it further includes: a body region of the second conductivity type, a source region of the first conductivity type, and a third interlayer dielectric layer;

[0018] The body region is located on the epitaxial layer and surrounds the trench;

[0019] The source region is located on the body region and surrounds the trench;

[0020] The third interlayer dielectric layer is located above the source region and the trench, and covers the source region and the trench.

[0021] Optionally, it also includes: a drain region;

[0022] The drain region is located below the substrate.

[0023] Optionally, it also includes: a metal layer and a plurality of electrode regions;

[0024] The metal layer is located on the third interlayer dielectric layer;

[0025] One end of the plurality of electrode regions contacts the metal layer, and the other end contacts the corresponding region to form electrodes of the corresponding region.

[0026] Based on the same inventive concept, in a second aspect, the present invention further provides a method for manufacturing a shielded gate trench MOS device, which is used to manufacture the shielded gate trench MOS device as described in the first aspect, and the method comprises:

[0027] forming an epitaxial layer of a first conductivity type on the substrate;

[0028] forming a trench in the epitaxial layer;

[0029] Forming a first interlayer dielectric layer, a second interlayer dielectric layer, a gate oxide layer, a first shielding gate field oxide layer and a second shielding gate field oxide layer, a control gate and two shielding gates in the groove, wherein the two shielding gates are respectively a first shielding gate and a second shielding gate;

[0030] The first shielding gate is located at the bottom of the trench; the second shielding gate is located above the first shielding gate and below the control gate; the control gate is located at the top of the trench and above the second shielding gate;

[0031] The first interlayer dielectric layer is filled between the first shielding grid and the second shielding grid;

[0032] The second interlayer dielectric layer is filled between the second shielding gate and the control gate;

[0033] The gate oxide layer is filled between the control gate and the sidewall in the trench;

[0034] The first shielding gate field oxide layer is filled between the first shielding gate and the sidewalls and bottom wall in the trench;

[0035] The second shielding gate field oxide layer is filled between the second shielding gate and the sidewall in the trench.

[0036] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0037] The embodiment of the present invention provides a shielded gate trench MOS device, in which a control gate and two shielding gates are provided in a trench of an epitaxial layer located on a substrate, and the two shielding gates are respectively a first shielding gate and a second shielding gate. In the trench, the control gate, the first shielding gate and the second shielding gate are in an up-and-down structure, that is, the first shielding gate is located at the bottom of the trench, the second shielding gate is located between the first shielding gate and the control gate, and the control gate is located at the top of the trench. A first interlayer dielectric layer is filled between the first shielding gate and the second shielding gate, and a second interlayer dielectric is filled between the second shielding gate and the control gate. A first shielding gate field oxide layer is filled between the first shielding gate and the inner wall of the trench. A second shielding gate field oxide layer is filled between the second shielding gate and the inner wall of the trench. A gate oxide layer is filled between the control gate and the inner wall of the trench.

[0038] Therefore, the embodiment of the present invention adds a shielding gate (i.e., a second shielding gate) between the control gate and the shielding gate, and the second shielding gate is electrically connected to the first shielding gate and the source, so that the shielding gate trench MOS device has a control gate and two shielding gates (referred to as the second shielding gate and the first shielding gate). According to the characteristics of the parallel plate capacitor, a charged metal plate is inserted into the dielectric layer, which is equivalent to two capacitors connected in series, thereby reducing the total parallel plate capacitance. In the lateral non-overlapping area between the control gate and the first shielding gate, the added second shielding gate reduces the oxide layer capacitance as a component of the gate-drain capacitance. In addition, the second shielding gate is also used to increase the overlapping area of ​​the gate and the source, thereby increasing the gate-source capacitance. At the same time, in the lateral overlapping area between the control gate and the first shielding gate, the added second shielding gate reduces the gate-source capacitance, so that the gate-source capacitance does not increase excessively and increase the switching loss. The shielding gate trench MOS device of the embodiment of the present invention improves the EMI performance of the device by reducing the gate-drain capacitance and increasing the gate-source capacitance. In addition, the shielded gate trench MOS device of the embodiment of the present invention only adds a shield gate conductive polysilicon layer between the control gate and the shield gate on the basis of the traditional shielded gate trench MOS device, thereby avoiding the adverse effects brought by the use of high-k dielectric for the first shield gate field oxide layer, and will not change the shape of the control gate and is not limited by the length of the control gate. It can achieve a reduction in gate-drain capacitance and an increase in gate-source capacitance, thereby achieving high EMI performance of the device; at the same time, the device has the advantages of simple manufacturing process, low manufacturing cost, and high manufacturing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, throughout the accompanying drawings, the same reference figures are used to represent the same components. In the drawings:

[0040] Figure 1 A schematic structural diagram of a shielded gate trench MOS device in an embodiment of the present invention is shown;

[0041] Figure 2 A schematic diagram showing the structure of the gate-drain capacitor and the gate-source capacitor of a conventional shielded gate trench MOS device in an embodiment of the present invention is shown;

[0042] Figure 3 A schematic structural diagram of a gate-drain capacitor and a gate-source capacitor of a shielded gate trench MOS device in an embodiment of the present invention is shown;

[0043] Figure 4 A graph showing gate-drain capacitance characteristic curves of a shielded gate trench MOS device in an embodiment of the present invention and a conventional shielded gate trench MOS device is shown;

[0044] Figure 5 A graph showing gate-source capacitance characteristic curves of a shielded gate trench MOS device in an embodiment of the present invention and a conventional shielded gate trench MOS device is shown;

[0045] Figure 6 A schematic diagram of the structure of forming an epitaxial layer on a substrate and forming a trench in the epitaxial layer in an embodiment of the present invention is shown;

[0046] Figure 7 A schematic structural diagram of forming a first shielding gate field oxide layer in a trench in an embodiment of the present invention is shown;

[0047] Figure 8 A schematic diagram of a structure in which shielding gate conductive polysilicon is formed on a first shielding gate field oxide layer in an embodiment of the present invention is shown;

[0048] Fig. 9 A schematic structural diagram of forming a first shielding gate and a first shielding gate field oxide layer in a trench in an embodiment of the present invention is shown;

[0049] Fig.10 A schematic diagram showing a structure in which a first interlayer dielectric layer and a gate oxide layer are formed on a first shielding gate in an embodiment of the present invention;

[0050] Fig.11 A schematic diagram showing a structure of forming a second shielding gate in a trench and obtaining a second shielding gate field oxide layer in an embodiment of the present invention is shown;

[0051] Fig.12A schematic diagram showing a structure of depositing a third dielectric layer on the second shielding gate and above the trench in an embodiment of the present invention is shown;

[0052] Fig.13 A schematic diagram showing a structure of forming a second interlayer dielectric layer on a second shielding grid in an embodiment of the present invention is shown;

[0053] Fig.14 A schematic structural diagram of removing the third dielectric layer above the groove in an embodiment of the present invention is shown;

[0054] Fig.15 A schematic diagram of a structure in which a control gate is formed in a trench in an embodiment of the present invention is shown;

[0055] Fig.16 A schematic diagram of a structure for forming a body region on an epitaxial layer in an embodiment of the present invention is shown;

[0056] Fig.17 A schematic diagram of a structure in which a source region is formed on a body region in an embodiment of the present invention is shown;

[0057] Fig.18 A schematic diagram showing a structure in which a third interlayer dielectric layer is formed on the source region and the trench in an embodiment of the present invention;

[0058] Fig.19 A schematic diagram showing the structure of forming an electrode region in an embodiment of the present invention is shown;

[0059] Fig. 20 A schematic flow chart of the steps of a method for manufacturing a shielded gate trench MOS device in an embodiment of the present invention is shown.

[0060] In the accompanying drawings, 110, substrate; 120, epitaxial layer; 130, trench; 131, first interlayer dielectric layer; 132, second interlayer dielectric layer; 133, gate oxide layer; 134, first shielding gate field oxide layer; 135, second shielding gate field oxide layer; 136, control gate; 137, first shielding gate; 138, second shielding gate; 140, body region; 150, source region; 160, third interlayer dielectric layer; 170, metal layer; 180, electrode region; 190, drain region. DETAILED DESCRIPTION

[0061] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0062] Embodiment 1

[0063] A first embodiment of the present invention provides a shielded gate trench MOS device, such as Figure 1 As shown, it includes: a substrate 110, an epitaxial layer 120 of the first conductive type located on the substrate 110, a trench 130 located in the epitaxial layer 120, a first interlayer dielectric layer 131, a second interlayer dielectric layer 132, a gate oxide layer 133, a first shielding gate field oxide layer 134 and a second shielding gate field oxide layer 135 located in the trench 130, and a control gate 136 and two shielding gates located in the trench 130, the two shielding gates are a first shielding gate 137 and a second shielding gate 138, respectively.

[0064] The first shielding gate 137 is located at the bottom of the trench 130; the second shielding gate 138 is located above the first shielding gate 137 and below the control gate 136; the control gate 136 is located at the top of the trench 130 and above the second shielding gate 138. The first interlayer dielectric layer 131 is filled between the first shielding gate 137 and the second shielding gate 138. The second interlayer dielectric layer 132 is filled between the second shielding gate 138 and the control gate 136. The gate oxide layer 133 is filled between the control gate 136 and the sidewalls in the trench 130. The first shielding gate field oxide layer 134 is filled between the first shielding gate 137 and the sidewalls and bottom wall in the trench 130. The second shielding gate field oxide layer 135 is filled between the second shielding gate 138 and the sidewalls in the trench 130.

[0065] It should be noted that the material of the substrate 110 includes but is not limited to a silicon substrate doped with impurities such as arsenic, red phosphorus or antimony. The epitaxial layer 120 is a lightly doped epitaxial layer 120 of the first conductivity type, and the material of the epitaxial layer 120 includes but is not limited to silicon. The shielding gate is a shielding gate conductive polysilicon, and its material is polysilicon doped with the first conductivity type. The material of the control gate 136 includes but is not limited to polysilicon doped with the first conductivity type. The gate oxide layer 133 is an insulating gate oxide layer, and the material of the gate oxide layer 133 includes but is not limited to silicon dioxide or silicon nitride. The material of the first interlayer dielectric layer 131 includes but is not limited to silicon dioxide or silicon nitride. The material of the second interlayer dielectric layer 132 includes but is not limited to silicon dioxide or silicon nitride. The first shielding gate field oxide layer 134 and the second shielding gate field oxide layer 135 are both insulating field oxide layers, and the material of the insulating field oxide layer includes but is not limited to silicon dioxide or silicon nitride. In this embodiment, for an N-type MOS field effect transistor, the first conductivity type refers to N-type, and the second conductivity type is P-type. For a P-type MOS field effect transistor, the first conductivity type and the second conductivity type refer to types that are exactly opposite to those of an N-type MOS field effect transistor, that is, the first conductivity type is P-type and the second conductivity type is N-type.

[0066] This embodiment provides a shielded gate trench MOS device, in which a control gate 136 and two shield gates are provided in a trench 130 of an epitaxial layer 120 located on a substrate 110, and the two shield gates are respectively a first shield gate 137 and a second shield gate 138. In the trench 130, the control gate 136, the first shield gate 137 and the second shield gate 138 are in a top-bottom structure, that is, the first shield gate 137 is located at the bottom of the trench 130, the second shield gate 138 is located between the first shield gate 137 and the control gate 136, and the control gate 136 is located at the top of the trench 130. A first interlayer dielectric layer 131 is filled between the first shield gate 137 and the second shield gate 138, and a second interlayer dielectric is filled between the second shield gate 138 and the control gate 136. A first shield gate field oxide layer 134 is filled between the first shield gate 137 and the inner wall of the trench 130. A second shield gate field oxide layer 135 is filled between the second shield gate 138 and the inner wall of the trench 130. A gate oxide layer 133 is filled between the control gate 136 and the inner wall of the trench 130 .

[0067] Therefore, in this embodiment, a shielding gate (i.e., the second shielding gate 138) is added between the control gate 136 and the shielding gate, and the second shielding gate 138 is electrically connected to the first shielding gate 137 and the source, so that the shielding gate trench MOS device has a control gate 136 and two shielding gates (referred to as the second shielding gate 138 and the first shielding gate 137). According to the parallel plate capacitance characteristics, a charged metal plate is inserted into the dielectric layer, which is equivalent to two capacitors connected in series, thereby reducing the total parallel plate capacitance. In the lateral non-overlapping area between the control gate 136 and the first shielding gate 137, the added second shielding gate 138 reduces the oxide layer capacitance as a component of the gate-drain capacitance. In addition, the second shielding gate 138 also increases the overlapping area of ​​the gate and the source, thereby increasing the gate-source capacitance. At the same time, in the lateral overlapping area between the control gate 136 and the first shielding gate 137, the added second shielding gate 138 reduces the gate-source capacitance, thereby preventing the gate-source capacitance from increasing excessively and increasing the switching loss. The shielded gate trench MOS device of this embodiment improves the EMI performance of the device by reducing the gate-drain capacitance and increasing the gate-source capacitance. In addition, the shielded gate trench MOS device of this embodiment only adds a shielded gate conductive polysilicon layer between the control gate 136 and the shielding gate on the basis of the traditional shielded gate trench MOS device, thereby avoiding the adverse effects caused by the use of a high-k dielectric for the first shielding gate field oxide layer 134, and does not change the shape of the control gate 136 and is not limited by the length of the control gate 136, thereby reducing the gate-drain capacitance and increasing the gate-source capacitance, thereby achieving high EMI performance of the device; at the same time, the device has the advantages of simple manufacturing process, low manufacturing cost, and high manufacturing efficiency.

[0068] Next, combine Figure 1 The structure of the shielded gate trench MOS device of this embodiment is described in detail:

[0069] In the trench 130, the lateral width of the first shielding gate field oxide layer 134 is the difference between the lateral width of the trench 130 and the lateral width of the first shielding gate 137. The lateral width of the second shielding gate field oxide layer 135 is the difference between the lateral width of the trench 130 and the lateral width of the second shielding gate 138. The lateral width of the gate oxide layer 133 is the difference between the lateral width of the trench 130 and the lateral width of the control gate 136. The shape of the control gate 136 can be selected as a rectangle or a rectangle with rounded corners or other shapes set according to actual needs. The shapes of the first shielding gate 137 and the second shielding gate 138 can be selected as a rectangle or a rectangle with rounded corners or other shapes set according to actual needs, and the shape of the first shielding gate 137 can also be selected as a bullet head shape.

[0070] Among them, the lateral width of the first shielding gate field oxide layer 134 is greater than the lateral width of the second shielding gate field oxide layer 135, and the lateral width of the second shielding gate field oxide layer 135 is greater than the lateral width of the gate oxide layer 133. Specifically, the lateral width of the first shielding gate field oxide layer 134 and the lateral width of the second shielding gate field oxide layer 135 are both greater than the lateral width of the gate oxide layer 133. The lateral width of the first shielding gate field oxide layer 134 is greater than the lateral width of the gate oxide layer 133 because the first shielding gate field oxide layer 134 needs to play a pressure-bearing role to ensure that it has a higher withstand voltage value. The lateral width of the first shielding gate field oxide layer 134 is greater than the lateral width of the second shielding gate field oxide layer 135 to ensure that the device has a higher withstand voltage value. Therefore, the device of this embodiment achieves a reduction in gate-drain capacitance and an increase in gate-source capacitance, thereby achieving high EMI performance of the MOS device.

[0071] The lateral width of the first shielding gate 137 is smaller than the lateral width of the second shielding gate 138, and the lateral width of the second shielding gate 138 is smaller than the lateral width of the control gate 136. Specifically, the lateral width of the first shielding gate 137 is smaller than the lateral width of the second shielding gate 138, and the lateral width of the first shielding gate 137 is limited by the lateral width of the trench 130 and the lateral thickness of the first shielding gate field oxide layer 134. There are two reasons why the lateral width of the first shielding gate 137 is smaller than that of the second shielding gate 138: first, because the thickness of the first shielding gate field oxide layer 134 (i.e., the lateral width and the longitudinal thickness) affects the withstand voltage of the device, the lateral width of the first shielding gate field oxide layer 134 is larger than the lateral width of the gate oxide layer 133. Second, because the first shielding gate field oxide layer 134 will form an oxide layer capacitor, so by increasing the lateral width of the second shielding gate 138, the oxide layer capacitor formed by the first shielding gate field oxide layer 134 is reduced to reduce the gate-drain capacitance.

[0072] The longitudinal thickness of the first interlayer dielectric layer 131 is consistent with the lateral width of the gate oxide layer 133. Specifically, the longitudinal thickness of the first interlayer dielectric layer 131 can be selected to be 0.05um, and the longitudinal thickness range is 0.045um~0.055um. The purpose of keeping the longitudinal thickness of the first interlayer dielectric layer 131 consistent with the lateral width of the gate oxide layer 133 is to ensure that the device has a higher withstand voltage value.

[0073] The difference between the lateral width of the control gate 136 and the lateral width of the second shielding gate 138 is consistent with the lateral width of the gate oxide layer 133, indicating that the lateral width of the control gate 136 is slightly larger than the lateral width of the second shielding gate 138. This is mainly because when the etching process is performed to form the groove 130 of the device, the etching depth-to-width ratio will cause the device to be etched horizontally when being etched vertically. Therefore, there is a difference between the lateral width of the top of the control gate 136 and the lateral width of the bottom. When forming the lateral width of the top of the second shielding gate 138, the lateral width of the bottom of the control gate 136 shall prevail. In this way, the lateral width of the top of the control gate 136 is larger than the lateral width of the second shielding gate 138, and the difference between the two is the lateral width of the gate oxide layer 133.

[0074] The longitudinal thickness of the second shielding grid 138 is less than the longitudinal thickness of the first shielding grid 137. Specifically, the longitudinal thickness of the second shielding grid 138 can be selected to be three-sixteenths of the longitudinal thickness of the first shielding grid 137, or the ratio of the two is in the range of 0.12 to 0.26. The longitudinal thickness of the second shielding grid 138 is less than the longitudinal thickness of the first shielding grid 137 to ensure that the device has a higher withstand voltage capability.

[0075] The longitudinal thickness of the second interlayer dielectric layer 132 is in the range of 0.25um to 0.35um. It should be noted that the longitudinal thickness of the second interlayer dielectric layer 132 affects the gate withstand voltage and gate-source parasitic capacitance, and can be set according to actual needs. The longitudinal thickness range of the second interlayer dielectric layer 132 is to ensure the withstand voltage performance of the device.

[0076] The longitudinal thickness of the control gate 136 is mainly affected by the depth of the receptor region 140 . The longitudinal thickness of the control gate 136 will affect the threshold voltage and parasitic capacitance of the device. The longitudinal thickness of the control gate 136 ranges from 0.4 um to 0.7 um.

[0077] The device of this embodiment further includes: a body region 140 of the second conductivity type, a source region 150 of the first conductivity type, and a third interlayer dielectric layer 160. The body region 140 is located on the epitaxial layer 120 and surrounds the trench 130. The source region 150 is located on the body region 140 and surrounds the trench 130. The third interlayer dielectric layer 160 is located on the source region 150 and the trench 130 and covers the source region 150 and the trench 130.

[0078] Specifically, the body region 140 is a heavily doped body region 140 of the second conductivity type. The material of the body region 140 includes but is not limited to silicon doped with boron impurities and silicon doped with gallium impurities. The function of the body region 140 is to serve as a channel region when the device is turned on. The source region 150 is a heavily doped source region 150 of the first conductivity type. The material of the source region 150 includes but is not limited to silicon doped with phosphorus impurities and silicon doped with arsenic impurities. The material of the third interlayer dielectric layer 160 includes but is not limited to silicon dioxide and borophosphosilicate glass. The third interlayer dielectric layer 160 is an insulating dielectric layer. The function of the third interlayer dielectric layer 160 is to serve as an electrical isolation dielectric layer between metal layers. Figure 1 As shown, the body region 140 located on the epitaxial layer 120 surrounds the trench 130, and the source region 150 located on the body region 140 surrounds the trench 130. The upper surface of the source region 150, the upper surface of the trench 130, the upper surface of the control gate 136, and the upper surface of the gate oxide layer 133 are located at the same horizontal plane. The third interlayer dielectric layer 160 is located above the source region 150 and the trench 130, that is, the third interlayer dielectric layer 160 covers the source region 150, the trench 130, the control gate 136, the oxide layer, etc.

[0079] The device of this embodiment further includes: a metal layer 170 and a plurality of electrode regions 180. The metal layer 170 is located on the third interlayer dielectric layer 160. One end of the plurality of electrode regions 180 contacts the metal layer 170 and the other end contacts the corresponding region to form electrodes of the corresponding region.

[0080] Specifically, the plurality of electrode regions 180 represent electrodes of corresponding regions respectively. Figure 1 As shown, the electrode region 180 corresponding to the source region 150 (i.e., the electrode corresponding to the source region 150) contacts the metal layer 170 at the top, passes through the third interlayer dielectric layer 160 and the source region 150, and contacts the body region 140 at the bottom. The device of this embodiment also has an electrode region 180 corresponding to the control gate 136, an electrode region 180 corresponding to the second shield gate 138, and an electrode region 180 corresponding to the first shield gate 137. The electrode region 180 corresponding to the control gate 136 contacts the metal layer 170 at the top, passes through the third interlayer dielectric layer 160 and the opening of the trench 130, and contacts the control gate 136 at the bottom. The electrode region 180 corresponding to the second shield gate 138 contacts the metal layer 170 at the top, passes through the third interlayer dielectric layer 160 and the opening of the trench 130, and contacts the second shield gate 138 at the bottom. The electrode region 180 corresponding to the first shield gate 137 contacts the metal layer 170 at the top, passes through the third interlayer dielectric layer 160 and the opening of the trench 130, and contacts the first shield gate 137 at the bottom.

[0081] Each electrode region 180 includes: a contact hole, a contact electrode and a contact region. The contact region is located at the bottom of the contact hole. The contact electrode is filled in the contact hole and is located above the contact region. Each electrode region 180 is an electrode. The contact region is of the second conductivity type.

[0082] The device of this embodiment further includes: a drain region 190. The drain region 190 is located under the substrate 110. The material of the drain region 190 includes but is not limited to a combination of titanium, nickel vanadium, and silver.

[0083] In order to facilitate understanding of the structural principle of the shielded gate trench MOS device of this embodiment, it is necessary to first explain the structure of the traditional shielded gate trench MOS device:

[0084] like Figure 2 As shown, in the trench of the conventional shielded gate trench MOS device, there is a gate (i.e., control gate) and a shield gate. The gate and the shield gate are in an up-and-down structure, i.e., the gate is located at the top of the trench, and the shield gate is located at the bottom of the trench. The lateral width of the gate is the difference between the lateral width of the trench and the lateral width of the gate oxide layer, and the lateral width of the shield gate is the difference between the lateral width of the trench and the lateral width of the field oxide layer. The lateral width of the gate oxide layer is much smaller than the lateral width of the field oxide layer. Therefore, the lateral width of the gate is much larger than the lateral width of the shield gate. The lateral overlap area between the gate and the shield gate is filled with interlayer dielectric. The oxide layer capacitance formed by this part of the interlayer dielectric is the gate-source capacitance C. gs The lateral non-overlapping area between the gate and the shield gate in the trench is filled with the interlayer dielectric and the field oxide layer. The oxide layer capacitance formed by this part of the interlayer dielectric and the field oxide layer is the gate-drain capacitance C gd part of.

[0085] The structural principle of the shielded gate trench MOS device of this embodiment is as follows: Figure 3 As shown, by adding a layer of shielding gate conductive polysilicon (i.e., second shielding gate 138) between control gate 136 and first shielding gate 137, second shielding gate 138 is electrically connected to first shielding gate 137 and source, so that shielding gate trench MOS device has one control gate 136 and two shielding gates. Second shielding gate 138 is located between control gate 136 and first shielding gate 137, and the lateral width of control gate 136 is slightly larger than the lateral width of second shielding gate 138, and the difference between the two is the same as the lateral width of gate oxide layer 133. The lateral width of control gate 136 is larger than the lateral width of first shielding gate 137, and the difference between the two is the same as the difference between the lateral width of first shielding gate field oxide layer 134 and the lateral width of gate oxide layer 133.

[0086] According to the characteristics of parallel plate capacitance, inserting a charged metal plate in the dielectric layer is equivalent to connecting two capacitors in series, thereby reducing the total parallel plate capacitance. Figure 3 As shown, in the lateral non-overlapping region between the control gate 136 and the first shield gate 137, a second shield gate 138 is added so as to serve as a gate-drain capacitor C gdThe lateral width of the second shield gate 138 is larger than the lateral width of the first shield gate 137, which increases the overlapping area of ​​the gate and the source, making the gate-source capacitance C gs At the same time, in the lateral overlap region between the control gate 136 and the first shield gate 137, the added second shield gate 138 will increase the gate-source capacitance C gs Reduce the gate-source capacitance C gs It will not increase the switching loss too much. The longitudinal thickness of the dielectric layer (i.e., the first interlayer dielectric layer 131) between the second shielding gate 138 and the first shielding gate 137 can be selected to be 0.05um, and the longitudinal thickness of the second shielding gate 138 can be selected to be three-sixteenths of the longitudinal thickness of the first shielding gate 137. Therefore, it basically does not affect the auxiliary depletion effect of the first shielding gate 137 and avoids affecting the withstand voltage of the device, thereby ensuring the reliability and stability of the device. The shielding gate trench MOS device of this embodiment can reduce the gate-drain capacitance and increase the gate-source capacitance, thereby improving the EMI performance of the device. At the same time, the manufacturing process is simple, the manufacturing capacity requirements are not high, the manufacturing cost is low, and the manufacturing efficiency is high.

[0087] The shielded gate trench MOS device of this embodiment is compared with the conventional shielded gate trench MOS device in the following test:

[0088] Figure 4 1 is a graph showing gate-drain capacitance characteristics of the shielded gate trench MOS device of this embodiment and a conventional shielded gate trench MOS device. Figure 5 Graph showing gate-source capacitance characteristics of the shielded gate trench MOS device of this embodiment and a conventional shielded gate trench MOS device. Figure 4 and Figure 5 The black curve in FIG. 1 represents the capacitance characteristic curve of the conventional shielded gate trench MOS device, and the red curve represents the capacitance characteristic curve of the shielded gate trench MOS device of this embodiment. Figure 4 and Figure 5 The horizontal axis in represents the drain-source voltage of the device. Figure 4 The vertical axis in represents the gate-drain capacitance of the device. Figure 5 The vertical axis in represents the gate-source capacitance of the device. Figure 4 It can be seen that the gate-drain capacitance of the MOS device of this embodiment is smaller than the gate-drain capacitance of the conventional MOS device. Figure 5 It can be seen that the gate-source capacitance of the MOS device of this embodiment is much larger than that of the conventional MOS device. This again shows that the shielded gate trench MOS device of this embodiment can reduce the gate-drain capacitance and increase the gate-source capacitance, so that the gate-drain capacitance C gd / Gate-source capacitance C gs The smaller the ratio of , the smaller the EMI noise. Therefore, the EMI performance of the device can be improved.

[0089] The following is an explanation of the manufacturing process of the shielded gate trench MOS device of this embodiment:

[0090] like Figure 6 As shown, a lightly doped first conductivity type epitaxial layer 120 is formed on a first conductivity type substrate 110 by an epitaxial process. Next, a first dielectric layer (silicon dioxide, silicon nitride, silicon dioxide in sequence) is grown on the epitaxial layer 120, and a masking and etching process is performed on the first dielectric layer to form a first hard mask layer for etching the trench 130. The first hard mask layer is used as an etching barrier layer to etch the trench 130 in the epitaxial layer 120.

[0091] like Figure 7 As shown, in the bottom and sidewalls of the trench 130, a second dielectric layer (i.e., silicon dioxide) is deposited by CVD (Chemical Vapor Deposition), and a first shielding gate field oxide layer 134 with a groove is formed by etching. The dot pattern area in the figure is the first shielding gate field oxide layer 134.

[0092] like Figure 8 and Fig. 9 As shown, in the first shielding gate field oxide layer 134 with grooves, shielding gate conductive polysilicon is formed by CVD deposition. And by back etching, a first shielding gate 137 and the first shielding gate field oxide layer 134 are formed in the groove 130. The oblique stripe pattern area in the figure is the first shielding gate 137.

[0093] like Fig.10 As shown, the first interlayer dielectric layer 131 is formed by thermal diffusion on the first shield gate 137, and the gate oxide layer 133 is formed by thermal diffusion on the sidewall of the trench 130. In the figure, the horizontal stripe pattern area is the first interlayer dielectric layer 131, and the vertical dotted line pattern area is the gate oxide layer 133.

[0094] like Fig.11 As shown, between the gate oxide layers 133 on the sidewalls of the trench 130, a shielding gate conductive polysilicon layer is deposited on the first interlayer dielectric layer 131, and a second shielding gate 138 is formed in the trench 130 by back etching, and a second shielding gate field oxide layer 135 is obtained. The black and white diamond pattern area in the figure is the second shielding gate field oxide layer 135.

[0095] like Figure 12 to Figure 14As shown, a third dielectric layer (i.e., silicon nitride) is deposited on the second shielding gate 138 and above the trench 130, and a masking and etching process is performed on the third dielectric layer to form a second hard mask layer. A second dielectric layer (i.e., silicon dioxide) is formed by CVD deposition in the trench 130, and an etching process is performed using the second hard mask layer as an etching barrier to form a second interlayer dielectric layer 132 on the second shielding gate 138. Next, the third dielectric layer (i.e., silicon nitride) above the trench 130 is removed. In the figure, the checkered pattern area is the third dielectric layer.

[0096] like Fig.15 As shown, a gate conductive polysilicon layer is deposited in the trench 130, and a control gate 136 is formed in the trench 130 by etching back. In the figure, the vertical stripe pattern area is the control gate 136.

[0097] like Fig.16 As shown, the body region 140 is defined by photoresist, and the second conductive type ions boron ions are ion implanted on the epitaxial layer 120, and high temperature annealing is performed to achieve the function of pushing junction and activating impurities to form the body region 140. In the figure, the brick pattern area is the body region 140.

[0098] like Fig.17 As shown, the body region 140 is ion-implanted with arsenic ions of the first conductive type and subjected to high temperature annealing to achieve the function of pushing junctions and activating impurities, thereby forming a source region 150. The shingle pattern region is the source region 150.

[0099] like Fig.18 As shown, a fourth dielectric layer (a silicon dioxide layer and a borophosphosilicate glass layer in sequence) is deposited on the source region 150 and the trench 130 to form a third interlayer dielectric layer 160 .

[0100] like Fig.19 As shown, the contact hole area is defined by photoresist, the contact hole is formed by etching in the third interlayer dielectric layer 160, and the contact area is implanted at the bottom of the contact hole, that is, the second conductive type impurity boron fluoride BF2 is implanted. Then, metal is deposited in the contact hole to form a contact electrode, and then the electrode area 180 is formed. Figure 1 As shown, metal is deposited on the back side of the substrate 110 to form a drain region 190 .

[0101] In the shielded gate trench MOS device of the present embodiment, a shielded gate conductive polysilicon layer (i.e., the second shielded gate 138 of the MOS device of the present embodiment) is added between the control gate 136 and the shielded gate (i.e., the first shielded gate 137 of the MOS device of the present embodiment) of the conventional shielded gate trench MOS device, and the shielded gate conductive polysilicon layer is electrically connected to the source and the shielded gate, i.e., it maintains the same potential as the source and the shielded gate. Therefore, the shielded gate trench MOS device of the present embodiment has a control gate 136 and two shielded gates. The lateral width of the second shielded gate 138 is smaller than the lateral width of the control gate 136, and the difference between the two can be about 0.05um. The lateral width of the first shielded gate 137 is smaller than the lateral width of the control gate 136, and the difference between the two can be about 0.1um. The longitudinal thickness of the dielectric layer (i.e., the first interlayer dielectric layer 131) between the second shielded gate 138 and the first shielded gate 137 can be 0.05um, and the longitudinal thickness of the second shielded gate 138 can be three-sixteenths of the longitudinal thickness of the first shielded gate 137.

[0102] The shielded gate trench MOS device of this embodiment is provided with a control gate 136 and two shielding gates by adding a layer of shielding gate conductive polysilicon (i.e., the second shielding gate 138) between the control gate 136 and the first shielding gate 137, and the second shielding gate 138 is electrically connected to the first shielding gate 137 and the source. The second shielding gate 138 is located between the control gate 136 and the first shielding gate 137, and the lateral width of the control gate 136 is slightly larger than the lateral width of the second shielding gate 138, and the difference between the two is the same as the lateral width of the gate oxide layer 133. The lateral width of the control gate 136 is larger than the lateral width of the first shielding gate 137, and the difference between the two is the same as the difference between the lateral width of the first shielding gate field oxide layer 134 and the lateral width of the gate oxide layer 133.

[0103] According to the parallel plate capacitance characteristics, a charged metal plate is inserted into the dielectric layer, which is equivalent to two capacitors connected in series, thereby reducing the total parallel plate capacitance. In the lateral non-overlapping area between the control gate 136 and the first shielding gate 137, the added second shielding gate 138 reduces the oxide layer capacitance as a component of the gate-drain capacitance. In addition, the second shielding gate 138 increases the overlapping area of ​​the gate and the source, thereby increasing the gate-source capacitance. At the same time, in the lateral overlapping area between the control gate 136 and the first shielding gate 137, the added second shielding gate 138 reduces the gate-source capacitance, thereby preventing the gate-source capacitance from being excessively increased and increasing the switching loss. The shielded gate trench MOS device of this embodiment improves the EMI performance of the device by reducing the gate-drain capacitance and increasing the gate-source capacitance. In addition, the shielded gate trench MOS device of the present embodiment avoids the adverse effects of using a high-k dielectric for the first shielding gate field oxide layer 134 by merely adding a shielding gate conductive polysilicon layer between the control gate 136 and the shielding gate on the basis of the traditional shielded gate trench MOS device, and will not change the shape of the control gate 136 and is not limited by the length of the control gate 136. It can achieve a reduction in gate-drain capacitance and an increase in gate-source capacitance, thereby achieving high EMI performance of the device; at the same time, the device has the advantages of simple manufacturing process, low manufacturing cost, and high manufacturing efficiency.

[0104] Embodiment 2

[0105] Based on the same inventive concept, the second embodiment of the present invention further provides a method for manufacturing a shielded gate trench MOS device, such as Fig. 20 As shown, for manufacturing the shielded gate trench MOS device as described in the first embodiment, the method includes:

[0106] S201, forming an epitaxial layer of a first conductivity type on a substrate;

[0107] S202, forming a trench in the epitaxial layer;

[0108] S203, forming a first interlayer dielectric layer, a second interlayer dielectric layer, a gate oxide layer, a first shielding gate field oxide layer and a second shielding gate field oxide layer, a control gate and two shielding gates in the trench, wherein the two shielding gates are respectively a first shielding gate and a second shielding gate;

[0109] The first shielding gate is located at the bottom of the trench; the second shielding gate is located above the first shielding gate and below the control gate; the control gate is located at the top of the trench and above the second shielding gate;

[0110] The first interlayer dielectric layer is filled between the first shielding grid and the second shielding grid;

[0111] The second interlayer dielectric layer is filled between the second shielding gate and the control gate;

[0112] The gate oxide layer is filled between the control gate and the sidewall in the trench;

[0113] The first shielding gate field oxide layer is filled between the first shielding gate and the sidewalls and bottom wall in the trench;

[0114] The second shielding gate field oxide layer is filled between the second shielding gate and the sidewall in the trench.

[0115] Since the manufacturing method of the shielded gate trench MOS device introduced in this embodiment is the manufacturing method adopted for implementing the shielded gate trench MOS device in the first embodiment of the present application, based on the shielded gate trench MOS device introduced in the first embodiment of the present application, the technical personnel of the field can understand the specific implementation method and its various variations of the manufacturing method of the shielded gate trench MOS device of the present embodiment, so how the manufacturing method of the shielded gate trench MOS device implements the shielded gate trench MOS device in the first embodiment of the present application is not introduced in detail here. As long as the technical personnel of the field implement the manufacturing method adopted by the shielded gate trench MOS device in the first embodiment of the present application, it belongs to the scope of protection of the present application.

[0116] Those skilled in the art will appreciate that, although the preferred embodiments of the present invention have been described, those skilled in the art, once informed of the basic creative concept, may make additional changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0117] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A shielded gate trench MOS device, characterized in that: include: A substrate, an epitaxial layer of a first conductivity type located on the substrate, a trench located in the epitaxial layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a gate oxide layer, a first shielding gate field oxide layer and a second shielding gate field oxide layer located in the trench, and a control gate and two shielding gates located in the trench, wherein the two shielding gates are respectively a first shielding gate and a second shielding gate; The first shielding gate is located at the bottom of the trench; the second shielding gate is located above the first shielding gate and below the control gate; the control gate is located at the top of the trench and above the second shielding gate; The first interlayer dielectric layer is filled between the first shielding grid and the second shielding grid; The second interlayer dielectric layer is filled between the second shielding gate and the control gate; The gate oxide layer is filled between the control gate and the sidewall in the trench; The first shielding gate field oxide layer is filled between the first shielding gate and the sidewalls and bottom wall in the trench; The second shielding gate field oxide layer is filled between the second shielding gate and the sidewall in the trench; The lateral width of the first shielding gate field oxide layer is greater than the lateral width of the second shielding gate field oxide layer, and the lateral width of the second shielding gate field oxide layer is greater than the lateral width of the gate oxide layer; The longitudinal thickness of the first interlayer dielectric layer is consistent with the lateral width of the gate oxide layer.

2. The shielded gate trench MOS device according to claim 1, characterized in that: The difference between the lateral width of the control gate and the lateral width of the second shield gate is consistent with the lateral width of the gate oxide layer.

3. The shielded gate trench MOS device according to claim 1, wherein: A longitudinal thickness of the second shielding grid is smaller than a longitudinal thickness of the first shielding grid.

4. The shielded gate trench MOS device according to claim 1, wherein: The longitudinal thickness of the second interlayer dielectric layer is in the range of 0.25um to 0.35um.

5. The shielded gate trench MOS device according to any one of claims 2 to 4, characterized in that: Also includes: A body region of a second conductivity type, a source region of the first conductivity type, and a third interlayer dielectric layer; The body region is located on the epitaxial layer and surrounds the trench; The source region is located on the body region and surrounds the trench; The third interlayer dielectric layer is located on the source region and the trench, and covers the source region and the trench.

6. The shielded gate trench MOS device according to claim 5, characterized in that: Also includes: drain region; The drain region is located below the substrate.

7. The shielded gate trench MOS device according to claim 5, characterized in that: Also includes: A metal layer and a plurality of electrode regions; The metal layer is located on the third interlayer dielectric layer; One end of the plurality of electrode regions contacts the metal layer, and the other end contacts the corresponding region to form electrodes of the corresponding region.

8. A method for manufacturing a shielded gate trench MOS device, characterized in that: A method for manufacturing a shielded gate trench MOS device as claimed in any one of claims 1 to 7, comprising: forming an epitaxial layer of a first conductivity type on the substrate; forming a trench in the epitaxial layer; Forming a first interlayer dielectric layer, a second interlayer dielectric layer, a gate oxide layer, a first shielding gate field oxide layer and a second shielding gate field oxide layer, a control gate and two shielding gates in the groove, wherein the two shielding gates are respectively a first shielding gate and a second shielding gate; The first shielding gate is located at the bottom of the trench; the second shielding gate is located above the first shielding gate and below the control gate; the control gate is located at the top of the trench and above the second shielding gate; The first interlayer dielectric layer is filled between the first shielding grid and the second shielding grid; The second interlayer dielectric layer is filled between the second shielding gate and the control gate; The gate oxide layer is filled between the control gate and the sidewall in the trench; The first shielding gate field oxide layer is filled between the first shielding gate and the sidewalls and bottom wall in the trench; The second shielding gate field oxide layer is filled between the second shielding gate and the sidewall in the trench.

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