Array substrate and display device

Abstract

The invention provides an array substrate and a display device. The array substrate comprises a substrate body and an initial voltage line arranged on the substrate body. The array substrate further comprises a first covering part; the orthographic projection of the first covering part on the substrate is at least partially overlapped with the orthographic projection of the initial voltage line on the substrate, and the first covering part is insulated from the initial voltage line; the first covering part is arranged on one side, far away from the substrate, of the initial voltage line; the first covering part is formed on the conductive layer, and the first covering part is suspended. According to the array substrate, charges generated in the Rubbing (friction) process can be neutralized, charge accumulation in a GOA (gate drive circuit arranged on the array substrate) area is reduced, and the risk of burning of a via hole electrically connected with the initial voltage line is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] In the related art, during the TFT-LCD (Thin Film Transistor-Liquid Crystal Display) process, the substrate is prone to accumulate static electricity when in contact, friction, extrusion, separation or heating. The substrate itself is an insulating material, and the speed of static electricity dissipation is very slow, so a large amount of static electricity is easily accumulated on the surface of the substrate. In the GOA (Gate Driver On Array, set on the array substrate) area, the line density is high, and the line connections are jumpered and cross-wiring is large. Therefore, GOA products are prone to accumulate static electricity in the densely lined and complex GOA area. When the accumulation of static electricity reaches a certain critical point, static electricity breakdown will occur, causing damage to the line, leading to short circuits or broken wires.

[0003] Related display products have problems with abnormal lighting. The main adverse phenomena of abnormal lighting are abnormal display, black screen after the startup screen flashes, horizontal stripes and flickering, etc. The cause of the problem is ESD (electrostatic discharge) causing the STV via (STV via is a via electrically connected to the starting voltage line) to burst. The cause of ESD is generated in the friction alignment process. Since there are a large number of metal wires near the starting voltage line in the GOA area of ​​the array substrate, static electricity is generated during the friction between the friction cloth and the metal wires. After friction, the static electricity generated by the metal wires is not covered on the surface, and the static electricity accumulates in large quantities and cannot be eliminated, and is evenly distributed on the substrate. After friction, the Lift Pin (lifting pin) is lifted up, and the discharge of the charge tip generates a large current, which burns the weaker STV via position on the circuit, and ESD occurs. Summary of the invention

[0004] The main purpose of the present invention is to provide an array substrate and a display device to solve the problem of the risk of STV vias being burned out in existing display products.

[0005] In one aspect, an embodiment of the present invention provides an array substrate, including a substrate, and a starting voltage line disposed on the substrate;

[0006] The array substrate further includes a first covering portion;

[0007] The orthographic projection of the first covering portion on the substrate at least partially overlaps with the orthographic projection of the starting voltage line on the substrate, and the first covering portion is insulated from the starting voltage line;

[0008] The first covering portion is disposed on a side of the starting voltage line away from the substrate;

[0009] The first covering portion is formed on the conductive layer, and the first covering portion is floating.

[0010] Optionally, the conductive layer is an ITO layer.

[0011] Optionally, the conductive layer further includes a connecting portion; the starting voltage line is electrically connected to the connecting portion through a via hole; and a minimum distance between the first covering portion and the connecting portion is greater than or equal to 5 μm.

[0012] Optionally, a ratio of an overlapping area between an orthographic projection of the first covering portion on the substrate and an orthographic projection of the starting voltage line on the substrate to an area of ​​the starting voltage line is greater than or equal to 0.8.

[0013] Optionally, an orthographic projection of the starting voltage line on the substrate is covered by an orthographic projection of the first covering portion on the substrate.

[0014] Optionally, the first covering portion includes at least two mutually independent first covering parts; the orthographic projection of the first covering part on the substrate and the orthographic projection of the starting voltage line on the substrate at least partially overlap.

[0015] Optionally, the array substrate further comprises a second covering portion and at least one signal line disposed on the substrate; the second covering portion is floating;

[0016] An orthographic projection of a transistor on the substrate is not arranged between an orthographic projection of the signal line on the substrate and an orthographic projection of the starting voltage line on the substrate.

[0017] The orthographic projection of the second covering portion on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate;

[0018] The second covering portion is disposed on a side of the signal line away from the substrate.

[0019] Optionally, the signal line is a signal line used to transmit a cascade signal.

[0020] Optionally, the first covering portion and the second covering portion are arranged in the same layer.

[0021] Optionally, a ratio of an overlapping area between an orthographic projection of the second covering portion on the substrate and an orthographic projection of the signal line on the substrate to an area of ​​the signal line is greater than or equal to 0.8.

[0022] Optionally, an orthographic projection of the signal line on the substrate is covered by an orthographic projection of the second covering portion on the substrate.

[0023] Optionally, the array substrate further includes a third covering portion and a transistor disposed on the base; the third covering portion is floating; the third covering portion and the transistor are disposed in a GOA region;

[0024] The orthographic projection of the third covering portion on the substrate at least partially overlaps with the orthographic projection of the transistor on the substrate;

[0025] The third covering portion is disposed on a side of the transistor away from the substrate.

[0026] Optionally, the first covering portion and the third covering portion are arranged in the same layer.

[0027] Optionally, a ratio of an overlapping area between an orthographic projection of the third covering portion on the substrate and an orthographic projection of an active pattern of the transistor on the substrate to an area of ​​the active pattern is greater than or equal to 0.8.

[0028] Optionally, the orthographic projection of the active pattern on the substrate is covered by the orthographic projection of the third covering portion on the substrate.

[0029] In a second aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned array substrate.

[0030] The array substrate described in the embodiment of the present invention can adopt a first covering portion formed on the conductive layer to cover the starting voltage line; the orthographic projection of the first covering portion on the substrate at least partially overlaps with the orthographic projection of the starting voltage line on the substrate, and the first covering portion is floating, and the first covering portion is insulated from the starting voltage line to neutralize the charge generated during Rubbing (friction), reduce the charge accumulation in the GOA area, prevent the charge tip discharge generated when the Lift Pin is lifted, and reduce the risk of burning of related STV vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A is a structural diagram of a related array substrate;

[0032] Figure 1B is a structural diagram of an array substrate according to at least one embodiment of the present invention;

[0033] Figure 1C is Figure 1B Based on the structure diagram of the conductive layer removed;

[0034] Figure 2 is a layout diagram of an array substrate according to at least one embodiment of the present invention;

[0035] Figure 3 is Figure 2 Based on the above, the layout diagram of the conductive layer is removed;

[0036] Figure 4 yes Figure 2 A layout diagram of the gate metal layer in FIG.

[0037] Figure 5 yes Figure 2 A layout diagram of the conductive layer in FIG.

[0038] Figure 6 yes Figure 2 Layout diagram of vias in ;

[0039] Figure 7 is a layout diagram of an array substrate according to at least one embodiment of the present invention;

[0040] Figure 8 is a layout diagram of an array substrate according to at least one embodiment of the present invention;

[0041] Fig. 9 It is a layout diagram of an array substrate according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is called the first electrode and the other electrode is called the second electrode.

[0044] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0045] The array substrate described in the embodiment of the present invention includes a substrate, and a starting voltage line arranged on the substrate;

[0046] The array substrate further includes a first covering portion;

[0047] The orthographic projection of the first covering portion on the substrate at least partially overlaps with the orthographic projection of the starting voltage line on the substrate, and the first covering portion is insulated from the starting voltage line;

[0048] The first covering portion is disposed on a side of the starting voltage line away from the substrate;

[0049] The first covering portion is formed on the conductive layer, and the first covering portion is floating.

[0050] In at least one embodiment of the present invention, a first covering portion is disposed on a side of the starting voltage line away from the substrate. The first covering portion does not overlap with other vias, which simplifies the process and can reduce ESD (electrostatic discharge) generated in the Rubbing process.

[0051] In order to solve the problems in the related art, the array substrate described in the embodiment of the present invention can adopt a first covering portion formed on the conductive layer to cover the starting voltage line; the orthographic projection of the first covering portion on the substrate at least partially overlaps with the orthographic projection of the starting voltage line on the substrate, and the first covering portion is floating, and the first covering portion is insulated from the starting voltage line to neutralize the charge generated during Rubbing (friction), reduce the charge accumulation in the GOA area, prevent the charge tip discharge generated when the Lift Pin is lifted, and reduce the risk of burning of related STV vias.

[0052] During the specific implementation, an electrostatic friction test was conducted to verify the ESD NG (failure) mechanism, and the following conclusions were drawn: There is an ITO (indium tin oxide) covered area on the surface of the metal wire, which will not cause the problem of friction static electricity accumulation; only the non-ITO covered area will have a friction static electricity accumulation problem.

[0053] Optionally, the conductive layer is an ITO layer.

[0054] In at least one embodiment of the present invention, the conductive layer further includes a connecting portion; the starting voltage line is electrically connected to the connecting portion through a via hole; and a minimum distance between the first covering portion and the connecting portion is greater than or equal to 5 μm.

[0055] In a specific implementation, the starting voltage line can be electrically connected to the connection part formed in the conductive layer through a via hole, and the minimum distance between the first covering part and the connection part is greater than or equal to 5 μm to avoid defects caused by overlapping of the connection part and the first covering part.

[0056] Optionally, a ratio of an overlapping area between an orthographic projection of the first covering portion on the substrate and an orthographic projection of the starting voltage line on the substrate to an area of ​​the starting voltage line is greater than or equal to 0.8.

[0057] In a specific implementation, the overlapping area between the orthographic projection of the first covering portion on the substrate and the orthographic projection of the starting voltage line on the substrate is set to a ratio greater than or equal to 0.8 to the area of ​​the starting voltage line, so as to ensure that the first covering portion can fully cover the starting voltage line and reduce the risk of burning the STV via.

[0058] In at least one embodiment of the present invention, an orthographic projection of the starting voltage line on the substrate is covered by an orthographic projection of the first covering portion on the substrate.

[0059] In a specific implementation, the first covering portion may completely cover the starting voltage line.

[0060] In at least one embodiment of the present invention, the first covering portion includes at least two mutually independent first covering parts; the orthographic projection of the first covering part on the substrate and the orthographic projection of the starting voltage line on the substrate at least partially overlap.

[0061] In a specific implementation, the first covering portion may include at least two mutually independent first covering portions, and the starting voltage line may be partially covered by the first covering portion.

[0062] In at least one embodiment of the present invention, the array substrate further comprises a second covering portion and at least one signal line disposed on the substrate; the second covering portion is floating;

[0063] No orthographic projection of a transistor on the substrate is arranged between the orthographic projection of the signal line on the substrate and the orthographic projection of the starting voltage line on the substrate;

[0064] The orthographic projection of the second covering portion on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate;

[0065] The second covering portion is disposed on a side of the signal line away from the substrate.

[0066] In a specific implementation, a signal line is arranged near the starting voltage line, and a floating second covering portion is arranged on a side of the signal line away from the substrate. The signal line is at least partially covered by the second covering portion, which can neutralize the charge generated during the Rubbing process, reduce the charge accumulation in the GOA area, prevent the charge tip discharge generated when the Lift Pin is lifted, and reduce the risk of burning of the related STV vias.

[0067] In at least one embodiment of the present invention, the signal line is a signal line for transmitting a cascade signal.

[0068] In a specific implementation, the signal line can be a signal line for transmitting cascade signals. For example, the signal line can be a carry signal line or a reset signal line. The carry signal line is a signal line through which the upper-level GOA circuit inputs a carry signal to the input module included in the lower-level GOA circuit. The reset signal line is a signal line through which the lower-level GOA circuit provides a reset signal to the reset module of the upper-level GOA circuit. The reset signal can be used as a reset signal for pull-up nodes, GOA output terminals, etc.

[0069] Optionally, the first covering portion and the second covering portion are arranged in the same layer.

[0070] In a specific implementation, the first covering portion and the second covering portion may both be formed on the conductive layer.

[0071] In at least one embodiment of the present invention, a ratio of an overlapping area between an orthographic projection of the second covering portion on the substrate and an orthographic projection of the signal line on the substrate to an area of ​​the signal line is greater than or equal to 0.8.

[0072] In a specific implementation, the overlapping area between the orthographic projection of the second covering portion on the substrate and the orthographic projection of the signal line on the substrate is set to have a ratio greater than or equal to 0.8 to the area of ​​the signal line to ensure that the second covering portion can fully cover the signal line.

[0073] In at least one embodiment of the present invention, an orthographic projection of the signal line on the substrate is covered by an orthographic projection of the second covering portion on the substrate.

[0074] In a specific implementation, the signal line may be completely covered by the second covering portion.

[0075] In at least one embodiment of the present invention, the array substrate further comprises a third covering portion and a transistor disposed on the base; the third covering portion is floating;

[0076] The third covering portion and the transistor are arranged in the GOA region; at least a portion of the starting voltage line is arranged in the GOA region;

[0077] The orthographic projection of the third covering portion on the substrate at least partially overlaps with the orthographic projection of the transistor on the substrate;

[0078] The third covering portion is disposed on a side of the transistor away from the substrate.

[0079] In a specific implementation, a transistor is arranged near the starting voltage line, and a floating third covering portion can be arranged on a side of the transistor away from the substrate. The transistor is at least partially covered by the third covering portion, which can neutralize the charge generated during the Rubbing process, reduce the charge accumulation in the GOA area, prevent the charge tip discharge generated when the Lift Pin is lifted, and reduce the risk of burning of related STV vias.

[0080] Optionally, the first covering portion and the third covering portion are arranged in the same layer.

[0081] In a specific implementation, the first covering portion and the third covering portion may both be formed on a conductive layer.

[0082] In at least one embodiment of the present invention, a ratio of an overlapping area between an orthographic projection of the third covering portion on the substrate and an orthographic projection of an active pattern of the transistor on the substrate to an area of ​​the active pattern is greater than or equal to 0.8.

[0083] In a specific implementation, the overlapping area between the orthographic projection of the third covering portion on the substrate and the orthographic projection of the active pattern of the transistor on the substrate is set to have a ratio greater than or equal to 0.8 to the area of ​​the active pattern to ensure that the second covering portion can fully cover the transistor.

[0084] In at least one embodiment of the present invention, an orthographic projection of the active pattern on the substrate is covered by an orthographic projection of the third covering portion on the substrate.

[0085] In a specific implementation, the active pattern may be completely covered by the third covering portion.

[0086] Figure 1A It is a structural diagram of a related array substrate.

[0087] exist Figure 1A In the embodiment, the portion labeled S1 is the first starting voltage line portion, and the portion labeled S2 is the second starting voltage line portion. The first starting voltage line portion S1 may include at least one starting voltage line, and the second starting voltage line portion S2 may include at least one starting voltage line. Optionally, only the first starting voltage line portion or the second starting voltage line portion may be provided in the present embodiment.

[0088] exist Figure 1A In the related array substrate shown, when the first starting voltage line portion S1 and the second starting voltage line portion S2 are introduced into the display area, friction alignment and other reasons cause ESD (electrostatic discharge) breakdown problems. Therefore, in at least one embodiment of the present invention, a floating covering portion formed in the conductive layer is provided on the side of the starting voltage line away from the substrate.

[0089] Figure 1B is a structural diagram of an array substrate according to at least one embodiment of the present invention, Figure 1C is Figure 1B Based on the structure diagram of the invention, the conductive layer is removed.

[0090] exist Figure 1B and Figure 1C Among them, the one labeled STVL is the starting voltage signal line, and the one labeled STV5 is the starting voltage bus;

[0091] exist Figure 1C, the line labeled STV1 is the first starting voltage line, the line labeled STV2 is the second starting voltage line, the line labeled STV3 is the third starting voltage line, and the line labeled STV4 is the fourth starting voltage line;

[0092] exist Figure 1B , the first covering part is labeled F1, the second covering part is labeled F2, the fifth covering part is labeled F5, the sixth covering part is labeled F6, and the seventh covering part is labeled F7;

[0093] Each covering portion is formed on the conductive layer, and the orthographic projections of F5, F6 and F7 on the substrate partially overlap with the orthographic projection of STVL extending in the vertical direction on the substrate, the orthographic projection of F2 on the substrate partially overlaps with the orthographic projection of STV5 extending in the vertical direction on the substrate, and the orthographic projection of F1 on the substrate partially overlaps with the orthographic projection of STV5 (STV5 includes parts in the horizontal and vertical directions) on the substrate. Optionally, when STV includes multiple starting voltage lines, for example, four starting voltage lines (STV1, STV2, STV3, STV4), the orthographic projection of F1 on the substrate at least partially overlaps with the orthographic projection of STV1 on the substrate, the orthographic projection of F1 on the substrate at least partially overlaps with the orthographic projection of STV2 on the substrate, the orthographic projection of F1 on the substrate at least partially overlaps with the orthographic projection of STV3 on the substrate, and the orthographic projection of F1 on the substrate at least partially overlaps with the orthographic projection of STV4 on the substrate.

[0094] exist Figure 1B and Figure 1C , the transistor labeled M11 is the first row and the first column, the transistor labeled M12 is the first row and the second column, the transistor labeled M13 is the first row and the third column, the transistor labeled M14 is the first row and the fourth column, the transistor labeled M21 is the second row and the first column, the transistor labeled M22 is the second row and the second column, the transistor labeled M23 is the second row and the third column, the transistor labeled M24 is the second row and the fourth column, and so on. Each level of GOA includes multiple transistors, and only some transistors (three transistors) are illustrated here;

[0095] Among them, M11 and M21 may be transistors for frame resetting, and M33, M43, M53 and M63 may be input transistors in the first four stages of driving circuits.

[0096] Figure 2 It is a layout diagram of an array substrate according to at least one embodiment of the present invention. Figure 3 is Figure 2 Based on this, the layout diagram of the conductive layer is removed.

[0097] exist Figure 2 Among them, the one labeled GOAM is a dummy driving circuit.

[0098] exist Figure 3 In the figure, the first starting voltage line is labeled STV1, the second starting voltage line is labeled STV2, the third starting voltage line is labeled STV3, and the fourth starting voltage line is labeled STV4; STV1-STV4 are connected together by a starting voltage bus STV5 to provide the same starting voltage signal. It should be noted that in this case, 4 starting voltage lines are shown from the bus to the GOA input module that introduces the GOA area, and other numbers can be used, such as 1, 2, 3, 5, 6, etc., which are not specifically limited, and the number of buses may also be unlimited.

[0099] The one labeled STV5 is the starting voltage bus;

[0100] The first starting voltage line STV1 connects the first starting voltage signal to the input module of the GOA circuit through the first STV via H1;

[0101] The second starting voltage line STV2 connects the second starting voltage signal to the input module of the GOA circuit through the second STV via H2;

[0102] The third starting voltage line STV3 connects the third starting voltage signal to the input module of the GOA circuit through the third STV via H3;

[0103] The fourth starting voltage line STV4 connects the fourth starting voltage signal to the input module of the GOA circuit through the fourth STV via H4; the STV1-STV4 signals are used to provide initial trigger signals to the input modules of the previous few levels of GOA circuits, and the input modules of the GOA circuits of other levels are provided with initial trigger signals by the output end of the upper GOA circuit or the cascade output end through the cascade signal line.

[0104] The start voltage bus STV5 is electrically connected to the fifth STV via H5, and the start voltage signal is introduced into the GOA region through the fifth STV via H5 and the start voltage bus STV5.

[0105] Figure 4 yes Figure 2 The layout diagram of the gate metal layer in Figure 5 yes Figure 2 Layout diagram of the conductive layer in Figure 6 yes Figure 2 Layout diagram of the vias in .

[0106] In the array substrate described in at least one embodiment of the present invention, the layout diagram of the gate metal layer can be as follows: Figure 3 As shown, the layout diagram of the vias can be as follows Figure 5 shown.

[0107] exist Figure 4In the embodiment, a first reset signal line RST1, a second reset signal line RST2, a third reset signal line RST3 and a fourth reset signal line RST4 are provided near each start voltage line.

[0108] exist Figure 5 Among them, the one labeled L1 is the first connecting part, the one labeled L2 is the second connecting part, the one labeled L3 is the third connecting part, the one labeled L4 is the fourth connecting part, the one labeled L5 is the fifth connecting part, the one labeled F1 is the first covering part, and the one labeled F14 is the fourth covering part.

[0109] like Figure 3-Figure 6 As shown, the first starting voltage line STV1 is electrically connected to the first connection part L1 through the first via H1, the second starting voltage line STV2 is electrically connected to the second connection part L2 through the second via H2, the third starting voltage line STV3 is electrically connected to the third connection part L3 through the third via H3, the fourth starting voltage line STV4 is electrically connected to the fourth connection part L4 through the fourth via H4, and the starting voltage bus STV5 is electrically connected to the fifth connection part L5 through the fifth via H5.

[0110] like Figure 2 As shown, in at least one embodiment of the present invention, the array substrate may include a first covering portion F1 and a fourth covering portion F14; the first covering portion F1 and the fourth covering portion F14 may be formed on a conductive layer; the conductive layer may be formed in the same layer and material as the pixel electrode or common electrode in the display area.

[0111] The orthographic projection of F1 on the substrate covers the orthographic projection of STV1 on the substrate;

[0112] The orthographic projection of F1 on the substrate covers the orthographic projection of STV2 on the substrate;

[0113] The orthographic projection of F1 on the substrate covers the orthographic projection of STV3 on the substrate;

[0114] The orthographic projection of F1 on the substrate covers the orthographic projection of STV4 on the substrate;

[0115] The orthographic projection of F1 on the substrate covers the orthographic projection of STV5 on the substrate;

[0116] The transfer vias of the F1 and STV signal lines are spaced and insulated from each other, that is, they avoid the transfer vias H1-H5. Figure 2 The covering part can be an integral structure or an independent structure. For example, STV1-STV4 are covered with a covering part respectively, and the covering parts are not connected to each other or there are at least two covering parts which are independently arranged. In this case, the covering part covers part of the starting voltage line in the process of introducing the starting voltage signal into the input module of the GOA circuit.

[0117] To neutralize the charge generated during the rubbing process, reduce the charge accumulation in the GOA area, prevent the charge tip discharge generated when the Pin is lifted, and reduce the risk of burning related STV vias.

[0118] exist Figure 2 In at least one embodiment shown,

[0119] The minimum distance between F1 and L1 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0120] The minimum distance between F1 and L2 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0121] The minimum distance between F1 and L3 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0122] The minimum distance between F1 and L4 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0123] The minimum distance between F1 and L5 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0124] This is to avoid the first covering portion F1 and the connecting portions being too close to each other and overlapping each other, thereby preventing defects.

[0125] exist Figure 2 In at least one embodiment shown, a first starting voltage line STV1 , a second starting voltage line STV2 , a third starting voltage line STV3 , a fourth starting voltage line STV4 and a starting voltage bus STV5 may be disposed between F1 and the substrate.

[0126] In a specific implementation, the thickness of the pattern formed on the conductive layer in the peripheral area can be the same as the thickness of the pattern formed on the conductive layer in the display area, without adding an array process, and only the 2ITO Mask needs to be changed.

[0127] In at least one embodiment of the present invention, the first covering portion may be formed on the conductive layer, each starting voltage line may be formed on the gate metal layer, and the conductive layer may be disposed on a side of the gate metal layer away from the substrate.

[0128] like Figure 7 As shown, in at least one embodiment of the present invention, the array substrate may include a first covering portion; the first covering portion may include a first first covering portion F11, a second first covering portion F21 and a third first covering portion F31 which are independent of each other;

[0129] F11 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the first starting voltage line STV1 on the substrate; F21 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the first starting voltage line STV1 on the substrate; F31 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the first starting voltage line STV1 on the substrate;

[0130] F11 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the second starting voltage line STV2 on the substrate; F21 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the second starting voltage line STV2 on the substrate; F31 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the second starting voltage line STV2 on the substrate;

[0131] F11 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the third starting voltage line STV3 on the substrate; F21 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the third starting voltage line STV3 on the substrate; F31 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the third starting voltage line STV3 on the substrate;

[0132] F11 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the fourth starting voltage line STV4 on the substrate; F21 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the fourth starting voltage line STV4 on the substrate; F31 and the orthographic projection on the substrate at least partially overlap with the orthographic projection of the fourth starting voltage line STV4 on the substrate;

[0133] The orthographic projection of F31 on the substrate at least partially overlaps with the orthographic projection of the starting voltage bus STV5 on the substrate;

[0134] To neutralize the charge generated during the rubbing process, reduce the charge accumulation in the GOA area, prevent the charge tip discharge generated when the Pin is lifted, and reduce the risk of burning related STV vias.

[0135] exist Figure 7 In at least one embodiment shown,

[0136] The minimum distance between F11 and L1 is greater than or equal to 5 μm;

[0137] The minimum distance between F11 and L2 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0138] The minimum distance between F21 and L3 is greater than or equal to 5 μm;

[0139] The minimum distance between F21 and L4 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0140] The minimum distance between F31 and L5 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0141] This is to avoid the first covering parts and the connecting parts being too close to each other and overlapping each other, thereby causing defects.

[0142] Figure 7 At least part of the layout diagram of the gate metal layer in Figure 3 shown.

[0143] exist Figure 7 In at least one embodiment shown, a first starting voltage line STV1 , a second starting voltage line STV2 , a third starting voltage line STV3 , a fourth starting voltage line STV4 and a starting voltage bus STV5 may be disposed between the first covering portion and the substrate.

[0144] like Figure 8 As shown, in Figure 6 On the basis of at least one embodiment shown, the array substrate described in at least one embodiment of the present invention further includes a second covering portion F2, which can be formed in the conductive layer; the second covering portion at least partially covers the cascade signal of GOA, where the cascade signal can be a reset signal or a carry signal, the carry signal refers to the upper-level GOA (output end or cascade output end) providing an input signal to the input module of the lower-level GOA, and the reset signal refers to the lower-level GOA output end (or cascade output end) providing a reset signal to the reset module of the upper-level GOA, which is used to reset the pull-up node of GOA and / or the GOA output end and / or the GOA cascade output end.

[0145] The orthographic projection of the second covering portion F2 on the substrate covers the orthographic projection of the first reset signal line RST1 on the substrate;

[0146] The orthographic projection of the second covering portion F2 on the substrate covers the orthographic projection of the second reset signal line RST2 on the substrate;

[0147] The orthographic projection of the second covering portion F2 on the substrate covers the orthographic projection of the third reset signal line RST3 on the substrate;

[0148] The orthographic projection of the second covering portion F2 on the substrate covers the orthographic projection of the fourth reset signal line RST4 on the substrate.

[0149] Figure 8 At least part of the layout diagram of the gate metal layer in Figure 3 shown.

[0150] exist Figure 8In at least one embodiment shown, a first reset signal line RST1 , a second reset signal line RST2 , a third reset signal line RST3 , and a fourth reset signal line RST4 may be disposed between the second covering portion F2 and the substrate.

[0151] like Figure 8 As shown, the distance between each starting voltage line and each reset signal line is relatively close, and each reset signal line is covered by the second covering portion F2 to neutralize the charge generated during the Rubbing process, reduce the charge accumulation in the GOA area, prevent the charge tip discharge generated when the Pin is lifted, and reduce the risk of burning the related STV vias.

[0152] exist Figure 8 In at least one embodiment shown, the first covering portion F1 and the second covering portion F2 are disposed in the same layer, and both the first covering portion F1 and the second covering portion F2 are formed in a conductive layer, and the conductive layer may be a 2ITO layer.

[0153] exist Figure 8 In at least one embodiment shown, L6 is the sixth connection portion, L7 is the seventh connection portion, L8 is the eighth connection portion, L9 is the ninth connection portion, L10 is the tenth connection portion, L11 is the eleventh connection portion, L12 is the twelfth connection portion, and L13 is the thirteenth connection portion;

[0154] L6, L7, L8, L9, L10, L11, L12, L13, F1 and F2 are all formed in the conductive layer;

[0155] The minimum distance between F2 and L6 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0156] The minimum distance between F2 and L7 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0157] The minimum distance between F2 and L8 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0158] The minimum distance between F2 and L9 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0159] The minimum distance between F2 and L10 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0160] The minimum distance between F2 and L11 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0161] The minimum distance between F2 and L12 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0162] The minimum distance between F2 and L13 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0163] This is to avoid the first covering parts and the connecting parts being too close to each other and overlapping each other, thereby causing defects.

[0164] like Fig. 9 As shown, in Figure 8 Based on at least one embodiment shown, the array substrate according to at least one embodiment of the present invention further includes a first third covering portion F13, a second third covering portion F23, a third third covering portion F33, a fourth third covering portion F43 and a fifth third covering portion F53;

[0165] Each third covering part is formed on the conductive layer, and each third covering part, the second covering part and the first covering part are arranged in the same layer;

[0166] At least one transistor is disposed between F13 and the substrate, at least one transistor is disposed between F23 and the substrate, at least one transistor is disposed between F33 and the substrate, at least one transistor is disposed between F43 and the substrate, and at least one transistor is disposed between F53 and the substrate;

[0167] Furthermore, the transistor is relatively close to each starting voltage line;

[0168] The orthographic projection of F13 on the substrate at least partially overlaps with the orthographic projection of at least one transistor on the substrate; the orthographic projection of F23 on the substrate at least partially overlaps with the orthographic projection of at least one transistor on the substrate; the orthographic projection of F33 on the substrate at least partially overlaps with the orthographic projection of at least one transistor on the substrate; the orthographic projection of F43 on the substrate at least partially overlaps with the orthographic projection of at least one transistor on the substrate; the orthographic projection of F53 on the substrate at least partially overlaps with the orthographic projection of at least one transistor on the substrate;

[0169] To neutralize the charge generated during the rubbing process, reduce the charge accumulation in the GOA area, prevent the charge tip discharge generated when the Pin is lifted, and reduce the risk of burning related STV vias.

[0170] like Fig. 9 As shown, F53 is also provided above the dummy driving circuit to improve the ESD problem.

[0171] exist Fig. 9, the one labeled L14 is the fourteenth connecting portion, the one labeled L15 is the fifteenth connecting portion, the one labeled L16 is the sixteenth connecting portion, the one labeled L17 is the seventeenth connecting portion, the one labeled L18 is the eighteenth connecting portion, the one labeled L19 is the nineteenth connecting portion, the one labeled L20 is the fourteenth connecting portion, the one labeled L21 is the fifteenth connecting portion, the one labeled L22 is the twenty-second connecting portion, and the one labeled L23 is the twenty-third connecting portion;

[0172] L14, L15, L16, L17, L18, L19, L20, L21 and L23 are all formed in the conductive layer, and each connecting line is arranged in the same layer as each third covering portion;

[0173] The minimum distance between F13 and L14 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0174] The minimum distance between F13 and L19 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0175] The minimum distance between F23 and L15 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0176] The minimum distance between F23 and L20 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0177] The minimum distance between F33 and L16 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0178] The minimum distance between F33 and L21 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0179] The minimum distance between F43 and L17 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0180] The minimum distance between F43 and L22 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0181] The minimum distance between F53 and L18 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0182] The minimum distance between F53 and L23 is greater than or equal to 5 μm and less than or equal to 8 μm;

[0183] This is to avoid the first covering parts and the connecting parts being too close to each other and overlapping each other, thereby causing defects.

[0184] The display device described in the embodiment of the present invention includes the above-mentioned array substrate.

[0185] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: It includes a substrate, and a starting voltage line disposed on the substrate; The array substrate further includes a first covering portion; The orthographic projection of the first covering portion on the substrate at least partially overlaps with the orthographic projection of the starting voltage line on the substrate, and the first covering portion is insulated from the starting voltage line; The first covering portion is disposed on a side of the starting voltage line away from the substrate; The first covering portion is formed on the conductive layer, and the first covering portion is floating.

2. The array substrate according to claim 1, characterized in that: The conductive layer is an ITO layer.

3. The array substrate according to claim 2, characterized in that: The conductive layer further includes a connecting portion; the starting voltage line is electrically connected to the connecting portion through a via hole; and a minimum distance between the first covering portion and the connecting portion is greater than or equal to 5 μm.

4. The array substrate according to claim 1, wherein: A ratio of an overlapping area between an orthographic projection of the first covering portion on the substrate and an orthographic projection of the starting voltage line on the substrate to an area of ​​the starting voltage line is greater than or equal to 0.

8.

5. The array substrate according to claim 3, characterized in that: An orthographic projection of the starting voltage line on the substrate is covered by an orthographic projection of the first covering portion on the substrate.

6. The array substrate according to claim 3, characterized in that: The first covering portion includes at least two mutually independent first covering parts; the orthographic projection of the first covering part on the substrate and the orthographic projection of the starting voltage line on the substrate at least partially overlap.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The array substrate further comprises a second covering portion and at least one signal line arranged on the substrate; the second covering portion is floating; No orthographic projection of a transistor on the substrate is arranged between the orthographic projection of the signal line on the substrate and the orthographic projection of the starting voltage line on the substrate; The orthographic projection of the second covering portion on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; The second covering portion is disposed on a side of the signal line away from the substrate.

8. The array substrate according to claim 7, characterized in that: The signal line is a signal line used to transmit a cascade signal.

9. The array substrate according to claim 7, characterized in that: The first covering portion and the second covering portion are arranged in the same layer.

10. The array substrate according to claim 7, wherein: A ratio of an overlapping area between an orthographic projection of the second covering portion on the substrate and an orthographic projection of the signal line on the substrate to an area of ​​the signal line is greater than or equal to 0.

8.

11. The array substrate according to claim 7, characterized in that: The orthographic projection of the signal line on the substrate is covered by the orthographic projection of the second covering portion on the substrate.

12. The array substrate according to any one of claims 1 to 6, characterized in that: The array substrate further comprises a third covering portion and a transistor disposed on the substrate; the third covering portion is floating; the third covering portion and the transistor are disposed in a GOA region; at least a portion of the starting voltage line is disposed in the GOA region; The orthographic projection of the third covering portion on the substrate at least partially overlaps with the orthographic projection of the transistor on the substrate; The third covering portion is disposed on a side of the transistor away from the substrate.

13. The array substrate according to claim 12, wherein: The first covering portion and the third covering portion are arranged in the same layer.

14. The array substrate according to claim 12, wherein: A ratio of an overlapping area between an orthographic projection of the third covering portion on the substrate and an orthographic projection of an active pattern of the transistor on the substrate to an area of ​​the active pattern is greater than or equal to 0.

8.

15. The array substrate according to claim 14, characterized in that: The orthographic projection of the active pattern on the substrate is covered by the orthographic projection of the third covering portion on the substrate.

16. A display device, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 15.

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