Light emitting diode for improving quantum well damage and preparation method thereof

Abstract

The invention provides a light emitting diode for improving quantum well damage and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The preparation method of the light-emitting diode comprises the following steps: forming an epitaxial layer, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are stacked in sequence; forming a transparent conductive layer on the surface of the second semiconductor layer; etching the transparent conductive layer to form a first through hole exposing the second semiconductor layer on the surface of the transparent conductive layer; and etching the second semiconductor layer in the first through hole to form a groove exposing the first semiconductor layer on the surface of the second semiconductor layer. According to the embodiment of the invention, the problem that the multi-quantum well layer is exposed and easy to damage can be improved, and the luminous efficiency of the light-emitting diode is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved quantum well damage and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is a very influential new product in the optoelectronics industry. It has the characteristics of small size, long service life, rich colors and low energy consumption. It is widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.

[0003] In the related art, when preparing a light-emitting diode, a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer are first formed in sequence; then, a groove exposing the first semiconductor layer is formed by etching the surface of the second semiconductor layer; then, a transparent conductive layer is sputtered on the surface of the second semiconductor layer and in the groove; then, the transparent conductive layer is etched so that the transparent conductive layer is located on the surface of the second semiconductor layer.

[0004] However, the grooves will expose the sidewalls of the multi-quantum well layer, which will damage the multi-quantum well layer when the transparent conductive layer is sputtered, thereby increasing the non-radiative recombination of the multi-quantum well layer, reducing the hole-electron recombination, and reducing the luminescence efficiency. Summary of the invention

[0005] The embodiments of the present disclosure provide a light-emitting diode with improved quantum well damage and a method for manufacturing the same, which can improve the problem of multiple quantum well layers being easily damaged due to exposure and improve the light-emitting efficiency of the light-emitting diode. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a method for preparing a light-emitting diode, the preparation method comprising: forming an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence; forming a transparent conductive layer on the surface of the second semiconductor layer; etching the transparent conductive layer to form a first through hole on the surface of the transparent conductive layer to expose the second semiconductor layer; etching the second semiconductor layer in the first through hole to form a groove on the surface of the second semiconductor layer to expose the first semiconductor layer.

[0007] Optionally, before etching the transparent conductive layer, the method further includes: forming a passivation layer on the surface of the transparent conductive layer; and etching the passivation layer to form a second through hole on the surface of the passivation layer that exposes the transparent conductive layer.

[0008] Optionally, etching the transparent conductive layer includes: etching the transparent conductive layer in the second through hole to form the first through hole on the surface of the transparent conductive layer.

[0009] Optionally, etching the passivation layer further includes: forming a third through hole exposing the transparent conductive layer on the surface of the passivation layer, the third through hole being arranged at intervals from the second through hole, and a diameter of the third through hole being smaller than a diameter of the second through hole.

[0010] Optionally, forming a third through hole on the surface of the passivation layer to expose the transparent conductive layer includes: forming a plurality of the third through holes arranged at intervals on the surface of the passivation layer.

[0011] Optionally, after etching the second semiconductor layer in the first through hole, the method further includes: forming a reflective layer on the surface of the passivation layer, so that the reflective layer is electrically connected to the transparent conductive layer through the third through hole; and forming a metal protective layer on the surface of the passivation layer, so that the metal protective layer covers the reflective layer.

[0012] Optionally, after forming a metal protective layer on the surface of the passivation layer, it also includes: forming a first insulating layer on the surface of the second semiconductor layer and in the groove, the first insulating layer covering the metal protective layer, the first insulating layer having a first via hole exposing the metal protective layer and the bottom of the groove respectively; forming an electrode on the surface of the first insulating layer, the electrode being electrically connected to the metal protective layer and the first semiconductor layer respectively through the first via hole.

[0013] Optionally, after forming the electrode on the surface of the first insulating layer, it also includes: forming a second insulating layer on the surface of the first insulating layer, the second insulating layer covering the electrode, the second insulating layer having a second via hole exposing the electrode; forming a solder pad on the surface of the second insulating layer, so that the solder pad is electrically connected to the electrode through the second via hole.

[0014] On the other hand, an embodiment of the present disclosure provides a light-emitting diode, which is prepared by the preparation method as described above, and includes: an epitaxial layer and a transparent conductive layer, the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, a groove is formed on the surface of the second semiconductor layer exposing the first semiconductor layer, the transparent conductive layer is located on the surface of the second semiconductor layer, and the second semiconductor layer has a first through hole exposing the groove.

[0015] Optionally, the brightness of the light emitting diode is greater than or equal to 1140 cd / m 2 .

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The method for preparing a light-emitting diode provided by the embodiment of the present disclosure first stacks a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer in sequence to form an epitaxial layer; then forms a transparent conductive layer on the surface of the second semiconductor layer; then etches the transparent conductive layer to form a first through hole exposing the second semiconductor layer; then etches the second semiconductor layer in the first through hole to form a groove exposing the first semiconductor layer. This preparation method first forms a transparent conductive layer on the second semiconductor before etching the groove exposing the side wall of the multi-quantum well layer. This avoids damage to the multi-quantum well layer due to the exposure of the side wall of the multi-quantum well layer when forming the transparent conductive layer. Therefore, the hole-electron recombination efficiency is improved, and the luminous efficiency of the light-emitting diode is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0020] Figure 2 is a flow chart of another method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 3 is a diagram of a preparation state of a light emitting diode provided by an embodiment of the present disclosure;

[0022] Figure 4 is a diagram of a preparation state of a light emitting diode provided by an embodiment of the present disclosure;

[0023] Figure 5 It is a structural schematic diagram of a light emitting diode provided in an embodiment of the present disclosure.

[0024] The descriptions of the marks in the figure are as follows:

[0025] 10. Substrate;

[0026] 20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer; 24. groove;

[0027] 30. transparent conductive layer; 31. first through hole;

[0028] 40. passivation layer; 41. second through hole; 42. third through hole;

[0029] 51. Reflective layer; 52. Metal protective layer;

[0030] 61. first insulating layer; 610. first via hole;

[0031] 62. second insulating layer; 620. second via hole;

[0032] 71. Electrode; 72. Pad. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0034] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0035] Figure 1 FIG. 1 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 1 As shown, the preparation method comprises:

[0036] Step 101: forming an epitaxial layer.

[0037] The epitaxial layer includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in sequence.

[0038] Step 102: forming a transparent conductive layer on the surface of the second semiconductor layer.

[0039] Step 103: etching the transparent conductive layer to form a first through hole on the surface of the transparent conductive layer to expose the second semiconductor layer.

[0040] Step 104: etching the second semiconductor layer in the first through hole to form a groove on the surface of the second semiconductor layer exposing the first semiconductor layer.

[0041] The method for preparing a light-emitting diode provided by the embodiment of the present disclosure first stacks a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer in sequence to form an epitaxial layer; then forms a transparent conductive layer on the surface of the second semiconductor layer; then etches the transparent conductive layer to form a first through hole exposing the second semiconductor layer; then etches the second semiconductor layer in the first through hole to form a groove exposing the first semiconductor layer. This preparation method first forms a transparent conductive layer on the second semiconductor before etching the groove exposing the side wall of the multi-quantum well layer. This avoids damage to the multi-quantum well layer due to the exposure of the side wall of the multi-quantum well layer when forming the transparent conductive layer. Therefore, the hole-electron recombination efficiency is improved, and the luminous efficiency of the light-emitting diode is enhanced.

[0042] Figure 2 FIG. 1 is a flow chart of another method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 2 As shown, the preparation method comprises:

[0043] Step 201: forming an epitaxial layer on a substrate.

[0044] Figure 3 FIG. 1 is a diagram showing the preparation state of a light emitting diode provided by an embodiment of the present disclosure. Figure 3 As shown, the following steps may be specifically included:

[0045] First, a substrate is provided.

[0046] The substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0047] As an example, in the embodiment of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0048] The sapphire substrate may be pre-treated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0049] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0050] Then, if Figure 3As shown, a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 are sequentially formed on a sapphire substrate 10 by MOCVD technology.

[0051] The first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0052] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0053] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

[0054] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0055] When growing the multi-quantum well layer 22, the pressure of the MOCVD reaction chamber is controlled at 200 torr. When growing the InGaN quantum well layer, the temperature of the reaction chamber is 760° C. to 780° C. When growing the GaN quantum barrier layer, the temperature of the reaction chamber is 860° C. to 890° C.

[0056] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0057] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0058] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0059] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0060] Step 202 : forming a transparent conductive layer 30 on the surface of the second semiconductor layer 23 .

[0061] like Figure 3 As shown, a transparent conductive layer 30 is formed on the surface of the second semiconductor layer 23 .

[0062] Exemplarily, the transparent conductive layer 30 is an indium tin oxide layer or an indium zinc oxide layer.

[0063] Exemplarily, the thickness of the transparent conductive layer 30 is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer 30 is 250 angstroms.

[0064] Step 203 : forming a passivation layer 40 on the surface of the transparent conductive layer 30 .

[0065] like Figure 3 As shown, a passivation layer 40 is formed on the surface of the transparent conductive layer 30 .

[0066] Exemplarily, the passivation layer 40 may be a silicon oxide layer.

[0067] For example, the thickness of the passivation layer 40 is 4000 angstroms to 6000 angstroms.

[0068] Step 204 : etching the passivation layer 40 to form a second through hole 41 on the surface of the passivation layer 40 to expose the transparent conductive layer 30 .

[0069] Specifically, it may include: forming a photoresist layer on the surface of the passivation layer 40. The photoresist layer has an opening, and the opening is used for photolithography to form the second through hole 41 of the passivation layer 40.

[0070] Figure 4 FIG. 1 is a diagram showing the preparation state of a light emitting diode provided by an embodiment of the present disclosure. Figure 4 As shown, after the passivation layer 40 is etched using the photoresist layer, a second through hole 41 exposing the transparent conductive layer 30 is formed on the surface of the passivation layer 40 .

[0071] For example, Figure 4 As shown, the axial cross section of the second through hole 41 is an inverted trapezoid. The angle between the hole wall of the second through hole 41 and the surface of the transparent conductive layer 30 can be 20° to 70°.

[0072] The preparation method in the disclosed embodiment forms a passivation layer 40 on the transparent conductive layer 30 before etching the groove 24 to expose the sidewall of the multi-quantum well layer 22. This avoids damage to the multi-quantum well layer 22 due to the exposure of the sidewall of the multi-quantum well layer 22 when the passivation layer 40 is formed. Therefore, the hole-electron recombination efficiency can be further improved, and the luminous efficiency of the light-emitting diode can be enhanced.

[0073] While etching the second through hole 41 in step 204 , a third through hole 42 exposing the transparent conductive layer 30 may also be formed on the surface of the passivation layer 40 , and the third through hole 42 and the second through hole 41 are arranged at intervals.

[0074] Exemplarily, the diameter of the third through hole 42 is smaller than the diameter of the second through hole 41 .

[0075] In the embodiment of the present disclosure, the second through hole 41 is a hole used for subsequently forming the first through hole 31 and the groove 24. Therefore, the diameter of the second through hole 41 on the passivation layer 40 is larger than the diameter of the third through hole 42, leaving a large enough space to facilitate etching other holes based on the second through hole 41.

[0076] The third through hole 42 is used for subsequent film layers to be connected to the transparent conductive layer 30 after passing through the passivation layer 40 .

[0077] Figure 5 Schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 5 As shown, a plurality of third through holes 42 exposing the transparent conductive layer 30 are formed on the surface of the passivation layer 40 , and the plurality of third through holes 42 are arranged at intervals.

[0078] To ensure that the film layer on the passivation layer 40 can fully contact the transparent conductive layer 30, a plurality of third through holes 42 are formed on the surface of the passivation layer 40, so that the film layer can be connected to various regions on the transparent conductive layer 30 through the plurality of third through holes 42, thereby improving connection reliability.

[0079] Step 205 : etching the transparent conductive layer 30 in the second through hole 41 to form a first through hole 31 on the surface of the transparent conductive layer 30 .

[0080] like Figure 4 As shown, after the transparent conductive layer 30 is etched by using the photoresist layer, a first through hole 31 exposing the second semiconductor layer 23 is formed on the surface of the transparent conductive layer 30 .

[0081] For example, Figure 4 As shown, the axial cross section of the first through hole 31 is an inverted trapezoid. The angle between the hole wall of the first through hole 31 and the surface of the second semiconductor layer 23 can be 20° to 70°.

[0082] This preparation method forms a transparent conductive layer 30 in the second semiconductor before etching the groove 24 to expose the side wall of the multi-quantum well layer 22. This avoids damage to the multi-quantum well layer 22 due to the exposure of the side wall of the multi-quantum well layer 22 when forming the transparent conductive layer 30. Therefore, the hole-electron recombination efficiency is improved, and the luminous efficiency of the light-emitting diode is enhanced.

[0083] Meanwhile, after the transparent conductive layer 30 is prepared, the transparent conductive layer 30 will be exposed to the air for too long, resulting in poor surface quality of the transparent conductive layer 30, which affects the photoelectric performance of the transparent conductive layer 30. In the embodiment of the present disclosure, after the transparent conductive layer 30 is prepared, it is not directly etched, but a passivation layer 40 is formed on the transparent conductive layer 30 to cover the transparent conductive layer 30, thereby preventing the transparent conductive layer 30 from being exposed to the air for too long.

[0084] Step 206 : etching the second semiconductor layer 23 in the first through hole 31 to form a groove 24 on the surface of the second semiconductor layer 23 to expose the first semiconductor layer 21 .

[0085] like Figure 4 As shown, after the epitaxial layer 20 is etched by using a photoresist layer, a groove 24 exposing the first semiconductor layer 21 is formed on the surface of the second semiconductor layer 23 .

[0086] For example, Figure 4 As shown, the axial cross section of the groove 24 is an inverted trapezoid. The angle between the groove wall of the groove 24 and the surface of the first semiconductor layer 21 can be 20° to 70°.

[0087] Step 207 : forming a reflective layer 51 on the surface of the passivation layer 40 , so that the reflective layer 51 is electrically connected to the transparent conductive layer 30 through the third through hole 42 .

[0088] Optionally, the reflective layer 51 includes an Ag layer, a Ni layer, and a TiW layer stacked in sequence.

[0089] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0090] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0091] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0092] Step 208 : forming a metal protection layer 52 on the surface of the passivation layer 40 , so that the metal protection layer 52 covers the reflective layer 51 .

[0093] like Figure 5 As shown, a metal protection layer 52 is formed on the surface of the passivation layer 40 , and the metal protection layer 52 covers the reflective layer 51 .

[0094] Optionally, the metal protection layer 52 includes at least one of a Cr layer, an Al layer, a Ti layer, and a Pt layer.

[0095] Exemplarily, the metal protection layer 52 includes a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer and a Ti layer stacked in sequence, and the thickness of each metal layer is 30 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 500 angstroms, 2000 angstroms and 500 angstroms, respectively.

[0096] Step 209 : forming a first insulating layer 61 on the surface of the second semiconductor layer 23 and in the groove 24 .

[0097] like Figure 5 As shown, the first insulating layer 61 covers the metal protection layer 52 , and the first insulating layer 61 has a first via hole 610 that exposes the metal protection layer 52 and the bottom of the groove 24 .

[0098] Exemplarily, the first insulating layer 61 may be a silicon oxide layer.

[0099] Exemplarily, the thickness of the first insulating layer 61 is 4000 angstroms to 6000 angstroms.

[0100] Step 210 : forming an electrode 71 on the surface of the first insulating layer 61 .

[0101] Alternatively, if Figure 5 As shown, the electrode 71 is electrically connected to the metal protection layer 52 and the first semiconductor layer 21 respectively through the first via hole 610 .

[0102] Exemplarily, the metal protection layer 52 is connected to the second semiconductor layer 23 , and the second semiconductor layer 23 is a p-type layer, so the electrode 71 electrically connected to the metal protection layer 52 is a p-electrode 71 .

[0103] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the electrode 71 electrically connected to the first semiconductor layer 21 is an n-electrode 71 .

[0104] Step 210 may specifically include: sequentially evaporating a Cr layer, an Al layer, a Ti layer, and a Pt layer.

[0105] Exemplarily, the thickness of the evaporated Cr layer is 1500 angstroms to 2500 angstroms.

[0106] Illustratively, the thickness of the evaporated Al layer is 1000 angstroms to 2500 angstroms.

[0107] Among them, the Ti layer and the Pt layer are used as wrapping layers, and a thicker metal layer can be used to reduce the resistance of the electrode 71, and at the same time, it can play a role in protecting the Cr layer and the Al layer.

[0108] Illustratively, the thickness of the Ti layer evaporated is 300 angstroms to 700 angstroms.

[0109] Illustratively, the thickness of the evaporated Pt layer is 1500 angstroms to 2500 angstroms.

[0110] Step 211 : forming a second insulating layer 62 on the surface of the first insulating layer 61 .

[0111] like Figure 5 As shown, the second insulating layer 62 covers the electrode 71 , and the second insulating layer 62 has a second via hole 620 exposing the electrode 71 .

[0112] Exemplarily, the second insulating layer 62 is a DBR (Distributed Bragg Reflector) layer, which includes a plurality of silicon oxide layers and a plurality of titanium oxide layers, and has a thickness of 3 μm to 4 μm.

[0113] Step 212 : forming a pad 72 on the surface of the second insulating layer 62 , and electrically connecting the pad 72 to the electrode 71 through the second via hole 620 .

[0114] like Figure 5 As shown, a pad 72 is formed on the surface of the second insulating layer 62 away from the epitaxial layer 20 , so that the pad 72 is electrically connected to the electrode 71 through the second via hole 620 .

[0115] Optionally, the pad 72 layer includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked in sequence.

[0116] Exemplarily, the thickness of the first Ti layer is 20 angstroms to 100 angstroms. For example, the thickness of the first Ti layer is 50 angstroms.

[0117] Exemplarily, the thickness of the Al layer is 10000 angstroms to 20000 angstroms. For example, the thickness of the Al layer is 15000 angstroms.

[0118] Exemplarily, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms. For example, the thickness of the second Ti layer is 1000 angstroms.

[0119] Exemplarily, the thickness of the Pt layer is 500 angstroms to 1500 angstroms. For example, the thickness of the Pt layer is 1000 angstroms.

[0120] Exemplarily, the thickness of the Ni layer is 60,000 angstroms to 80,000 angstroms. For example, the thickness of the Ni layer is 70,000 angstroms.

[0121] Exemplarily, the thickness of the Au layer is 1500 angstroms to 2500 angstroms. For example, the thickness of the Au layer is 2000 angstroms.

[0122] The present disclosure provides a light emitting diode, which is prepared by the light emitting diode preparation method as described above. Figure 5 As shown, the light emitting diode includes: an epitaxial layer 20 and a transparent conductive layer 30, the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence, a groove 24 exposing the first semiconductor layer 21 is formed on the surface of the second semiconductor layer 23, the transparent conductive layer 30 is located on the surface of the second semiconductor layer 23, and the second semiconductor layer 23 has a first through hole 31 exposing the groove 24.

[0123] When preparing the light-emitting diode, the first semiconductor layer 21, the multi-quantum well layer 22 and the second semiconductor layer 23 are stacked in sequence to form an epitaxial layer 20; then, a transparent conductive layer 30 is formed on the surface of the second semiconductor layer 23; then, the transparent conductive layer 30 is etched to form a first through hole 31 exposing the second semiconductor layer 23; then, the second semiconductor layer 23 is etched in the first through hole 31 to form a groove 24 exposing the first semiconductor layer 21. This preparation method forms a transparent conductive layer 30 in the second semiconductor before etching the groove 24 exposing the side wall of the multi-quantum well layer 22. In this way, damage to the multi-quantum well layer 22 due to the exposure of the side wall of the multi-quantum well layer 22 is avoided when the transparent conductive layer 30 is formed. Therefore, the hole-electron recombination efficiency is improved, and the luminous efficiency of the light-emitting diode is enhanced.

[0124] Alternatively, if Figure 5 As shown, the light emitting diode further includes a substrate 10 , and an epitaxial layer 20 is located on the surface of the substrate 10 .

[0125] Exemplarily, the substrate is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0126] In the embodiment of the present disclosure, the epitaxial layer 20 includes a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 which are sequentially stacked on a substrate.

[0127] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0128] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0129] In the implementation of the present disclosure, the first semiconductor layer 21 is Al x Ga 1-x N material layer, wherein X is greater than or equal to 0 and less than or equal to 1.

[0130] Exemplarily, when X is 0, the first semiconductor layer 21 is a GaN layer. For example, the first semiconductor layer 21 is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0131] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0132] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0133] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0134] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0135] Alternatively, if Figure 5 As shown, the light emitting diode further includes a passivation layer 40, a reflective layer 51 and a metal protection layer 52, wherein the passivation layer is located on the surface of the transparent conductive layer 30, and the passivation layer 40 has a second through hole 41 and a third through hole 42 exposing the transparent conductive layer 30. The third through hole 42 also exposes the groove 24.

[0136] like Figure 5 As shown, the reflective layer 51 is located on the surface of the passivation layer 40 away from the epitaxial layer 20 , and the metal protection layer 52 is located on the surface of the transparent conductive layer 30 away from the epitaxial layer 20 and covers the metal reflective layer 51 .

[0137] Optionally, the transparent conductive layer 30 may be an indium tin oxide (ITO) layer or an indium zinc oxide (IZO) layer.

[0138] Exemplarily, the transparent conductive layer 30 is an indium tin oxide layer. The indium tin oxide layer has good transmittance and low resistivity. The indium tin oxide layer has low resistivity, facilitates carrier conduction, and improves injection efficiency.

[0139] Exemplarily, the transparent conductive layer 30 is an indium zinc oxide layer. The indium zinc oxide layer has good transmittance and low resistivity. The indium zinc oxide layer has low resistivity, facilitates carrier conduction, and improves injection efficiency.

[0140] Exemplarily, the thickness of the transparent conductive layer 30 is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer 30 is 200 angstroms.

[0141] The reflective layer 51 can be used to reflect the light emitted from the epitaxial layer 20 , so that more light can be emitted from the light-emitting surface of the epitaxial layer 20 , thereby improving the light-emitting intensity of the light-emitting diode.

[0142] At the same time, the reflective layer 51 is also covered with a metal protection layer 52 to prevent the metal in the reflective layer 51 from migrating upwards.

[0143] Optionally, the reflective layer 51 includes an Ag layer, a Ni layer, and a TiW layer stacked in sequence.

[0144] Since Ag has a good reflective effect, providing an Ag layer in the reflective layer 51 can enhance the reflection of light by the reflective layer 51 and improve the light emitting brightness of the light emitting surface of the light emitting diode.

[0145] The Ni layer has good corrosion resistance and wear resistance, and the TiW layer can be successfully deposited on other films as an adhesion layer without peeling or cracking. The alternating stacked Ni and TiW layers can act as a barrier layer to protect the silver mirror.

[0146] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0147] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0148] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0149] Optionally, the metal protection layer 52 includes a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer and a Ti layer stacked in sequence, and the thickness of each metal layer is 30 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 500 angstroms, 2000 angstroms and 500 angstroms respectively.

[0150] Alternatively, if Figure 5 As shown, the light emitting diode further includes a first insulating layer 61 . The first insulating layer 61 is located on the surface of the second semiconductor layer 23 , on the surface of the transparent conductive layer 30 , and in the groove 24 .

[0151] The surface of the first insulating layer 61 has a first via hole 610 exposing the metal protection layer 52 and the bottom of the groove 24 .

[0152] Exemplarily, the first insulating layer 61 may be a silicon oxide layer.

[0153] Exemplarily, the thickness of the first insulating layer 61 is 4000 angstroms to 6000 angstroms.

[0154] Alternatively, if Figure 5 As shown, the electrode 71 is located on the surface of the first insulating layer 61 , and is electrically connected to the metal protection layer 52 and the first semiconductor layer 21 respectively through the first via hole 610 .

[0155] Optionally, the electrode 71 includes a Cr layer, an Al layer, a Ti layer and a Pt layer stacked in sequence. The thickness of the Cr layer is 1500 to 2500 angstroms. The thickness of the Al layer is 1000 to 2500 angstroms. The thickness of the Ti layer is 300 to 700 angstroms. The thickness of the Pt layer is 1500 to 2500 angstroms.

[0156] Alternatively, if Figure 5 As shown, the light emitting diode may further include a second insulating layer 62 and a pad 72, wherein the second insulating layer 62 is located on the surface of the first insulating layer 61 and covers the electrode 71. The second insulating layer 62 has a through hole exposing the electrode 71, and the pad 72 is located on the surface of the second insulating layer 62 away from the epitaxial layer 20, and the pad 72 is electrically connected to the electrode 71 through the through hole.

[0157] Optionally, the pad 72 includes at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

[0158] The above metal material has good heat dissipation performance. Therefore, the pad 72 made of the above material also has good heat dissipation performance, which can improve the heat dissipation effect of the light emitting diode.

[0159] Alternatively, the pad 72 includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked in sequence.

[0160] Exemplarily, the thickness of the first Ti layer is 20 angstroms to 100 angstroms. For example, the thickness of the first Ti layer is 50 angstroms.

[0161] Exemplarily, the thickness of the Al layer is 10000 angstroms to 20000 angstroms. For example, the thickness of the Al layer is 15000 angstroms.

[0162] Exemplarily, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms. For example, the thickness of the second Ti layer is 1000 angstroms.

[0163] Exemplarily, the thickness of the Pt layer is 500 angstroms to 1500 angstroms. For example, the thickness of the Pt layer is 1000 angstroms.

[0164] Exemplarily, the thickness of the Ni layer is 60,000 angstroms to 80,000 angstroms. For example, the thickness of the Ni layer is 70,000 angstroms.

[0165] Exemplarily, the thickness of the Au layer is 1500 angstroms to 2500 angstroms. For example, the thickness of the Au layer is 2000 angstroms.

[0166] The experimental data of the light emitting diode provided by the embodiment of the present disclosure are as follows in Table 1:

[0167] Table 1

[0168]

[0169] According to the test results in Table 1, the average brightness of the light-emitting diode provided in the embodiment of the present disclosure is greater than or equal to 1140 cd / m 2 The average brightness of the light-emitting diode in the related art is less than 1140cd / m 2 It can be seen that under the same working environment, the light-emitting diode provided by the present disclosure has a higher brightness, which is 1.3% higher than the brightness of the light-emitting diode in the related art, and the overall yield can also be improved by 2.2%.

[0170] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: forming an epitaxial layer, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence; forming a transparent conductive layer on a surface of the second semiconductor layer; Etching the transparent conductive layer to form a first through hole on the surface of the transparent conductive layer exposing the second semiconductor layer; The second semiconductor layer is etched in the first through hole to form a groove on a surface of the second semiconductor layer that exposes the first semiconductor layer.

2. The preparation method according to claim 1, characterized in that: Before etching the transparent conductive layer, the method further comprises: forming a passivation layer on the surface of the transparent conductive layer; The passivation layer is etched to form a second through hole on the surface of the passivation layer to expose the transparent conductive layer.

3. The preparation method according to claim 2, characterized in that: Etching the transparent conductive layer includes: The transparent conductive layer is etched in the second through hole to form the first through hole on the surface of the transparent conductive layer.

4. The preparation method according to claim 2, characterized in that: Etching the passivation layer further comprises: A third through hole exposing the transparent conductive layer is formed on the surface of the passivation layer, the third through hole is arranged at intervals from the second through hole, and a diameter of the third through hole is smaller than a diameter of the second through hole.

5. The preparation method according to claim 4, characterized in that: Forming a third through hole on the surface of the passivation layer to expose the transparent conductive layer includes: forming a plurality of the third through holes arranged at intervals on the surface of the passivation layer.

6. The preparation method according to claim 4, characterized in that: After etching the second semiconductor layer in the first through hole, the method further includes: forming a reflective layer on the surface of the passivation layer, so that the reflective layer is electrically connected to the transparent conductive layer through the third through hole; A metal protection layer is formed on the surface of the passivation layer so that the metal protection layer covers the reflective layer.

7. The preparation method according to claim 6, characterized in that: After forming a metal protection layer on the surface of the passivation layer, the method further comprises: forming a first insulating layer on the surface of the second semiconductor layer and in the groove, wherein the first insulating layer covers the metal protection layer, and the first insulating layer has a first via hole exposing the metal protection layer and the bottom of the groove respectively; An electrode is formed on the surface of the first insulating layer, and the electrode is electrically connected to the metal protection layer and the first semiconductor layer respectively through the first via hole.

8. The preparation method according to claim 7, characterized in that: After forming an electrode on the surface of the first insulating layer, the method further comprises: forming a second insulating layer on the surface of the first insulating layer, wherein the second insulating layer covers the electrode and has a second via hole exposing the electrode; A pad is formed on the surface of the second insulating layer, so that the pad is electrically connected to the electrode through the second via hole.

9. A light emitting diode, characterized in that: The light emitting diode is prepared by the preparation method according to any one of claims 1 to 8, and comprises: an epitaxial layer (20) and a transparent conductive layer (30), the epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22) and a second semiconductor layer (23) stacked in sequence, a groove (24) exposing the first semiconductor layer (21) is formed on the surface of the second semiconductor layer (23), the transparent conductive layer (30) is located on the surface of the second semiconductor layer (23), and the second semiconductor layer (23) has a first through hole (31) exposing the groove (24).

10. The light emitting diode according to claim 9, characterized in that: The brightness of the light emitting diode is greater than or equal to 1140 cd / m 2 .

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