Light emitting diode for improving non-radiative recombination and preparation method thereof

Abstract

The invention provides an improved non-radiative recombination light emitting diode and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The light-emitting diode comprises an epitaxial layer, an insulating protection layer and a passivation layer, the surface of the epitaxial layer is provided with a groove, the insulation protection layer is at least located on the groove wall of the groove, the passivation layer is located on the surface of the insulation protection layer, and the insulation protection layer is located between the groove wall of the groove and the passivation layer. According to the embodiment of the invention, the damage to the multi-quantum well layer during the deposition of the passivation layer can be improved, and the light-emitting efficiency of the light-emitting diode is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved non-radiative recombination and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is a very influential new product in the optoelectronics industry. It has the characteristics of small size, long service life, rich colors and low energy consumption. It is widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.

[0003] In the related art, a light-emitting diode includes an epitaxial layer and a passivation layer, and the passivation layer is located on the surface of the epitaxial layer. When preparing a light-emitting diode, a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer are first formed in sequence; then, a groove is etched on the surface of the second semiconductor layer to expose the first semiconductor layer; then, a passivation layer is deposited on the surface of the second semiconductor layer and in the groove.

[0004] However, the grooves expose the sidewalls of the multi-quantum well layer, which may damage the multi-quantum well layer when the passivation layer is deposited, thereby increasing the non-radiative recombination of the multi-quantum well layer, reducing the hole-electron recombination, and reducing the luminescence efficiency. Summary of the invention

[0005] The embodiment of the present disclosure provides a light-emitting diode with improved non-radiative recombination and a method for preparing the same, which can improve the damage to the multi-quantum well layer during the deposition of the passivation layer and improve the luminous efficiency of the light-emitting diode. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes: an epitaxial layer, an insulating protective layer and a passivation layer; the surface of the epitaxial layer has a groove, the insulating protective layer is at least located on the groove wall of the groove, the passivation layer is located on the surface of the insulating protective layer, and the insulating protective layer is located between the groove wall of the groove and the passivation layer.

[0007] Optionally, the insulating protection layer includes an aluminum oxide layer.

[0008] Optionally, the insulating protection layer has a thickness of 100 angstroms to 300 angstroms.

[0009] Optionally, an orthographic projection of the passivation layer on a surface of the epitaxial layer away from the insulating protection layer is located within an orthographic projection of the insulating protection layer on a surface of the epitaxial layer away from the insulating protection layer.

[0010] Optionally, the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in sequence, the second semiconductor layer has the groove exposing the first semiconductor layer; the light-emitting diode also includes a transparent conductive layer, a reflective layer and an insulating wrapping layer, the transparent conductive layer is located on the surface of the second semiconductor layer, the insulating protection layer is also located on the surface of the second semiconductor layer and covers the transparent conductive layer, the passivation layer is also located on the surface of the passivation layer away from the second semiconductor layer, and the surface of the passivation layer away from the second semiconductor layer has a first through hole exposing the transparent conductive layer; the reflective layer is located on the surface of the passivation layer away from the second semiconductor layer, and is electrically connected to the transparent conductive layer through the first through hole, and the insulating wrapping layer is located on the surface of the reflective layer away from the second semiconductor layer.

[0011] Optionally, the insulating wrapping layer comprises an aluminum oxide layer.

[0012] Optionally, the thickness of the insulating wrapping layer is 500 angstroms to 1200 angstroms.

[0013] Optionally, the light-emitting diode also includes a first insulating layer and an electrode, the first insulating layer is located on the surface of the insulating wrapping layer away from the second semiconductor layer and is located in the groove, the first insulating layer has a second through hole respectively exposing the reflective layer and the bottom of the groove, the electrode is located on the surface of the first insulating layer, and is electrically connected to the reflective layer and the first semiconductor layer respectively through the second through hole.

[0014] On the other hand, an embodiment of the present disclosure provides a method for preparing a light-emitting diode, the method comprising: forming an epitaxial layer, the surface of the epitaxial layer having a groove; forming an insulating protective layer on the surface of the epitaxial layer, the insulating protective layer being located at least on the wall of the groove; forming a passivation layer on the surface of the insulating protective layer, the insulating protective layer being located between the wall of the groove and the passivation layer.

[0015] Optionally, forming an epitaxial layer includes: stacking a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer in sequence on a substrate; before forming an insulating protective layer on the surface of the epitaxial layer, it also includes: forming a transparent conductive layer on the surface of the second semiconductor layer; etching the transparent conductive layer to form a via hole on the surface of the transparent conductive layer to expose the second semiconductor layer; etching the second semiconductor layer in the via hole to form the groove on the surface of the second semiconductor layer to expose the first semiconductor layer.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diode provided by the embodiment of the present disclosure is provided with an insulating protective layer on the groove wall of the groove, so that the insulating protective layer is sandwiched between the groove wall of the groove and the passivation layer, that is, the groove wall of the groove and the passivation layer are separated by the insulating protective layer. In this way, the groove wall is covered by the insulating protective layer, and when the passivation layer is subsequently prepared, the passivation layer will not contact the exposed groove wall of the groove, thereby preventing the passivation layer from damaging the exposed multi-quantum well layer on the epitaxial layer, thereby improving the hole-electron recombination efficiency and enhancing the luminous efficiency of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0020] Figure 2 It is a flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure.

[0021] The descriptions of the marks in the figure are as follows:

[0022] 10. Substrate;

[0023] 20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer; 24. groove;

[0024] 30. Insulation protective layer;

[0025] 40. passivation layer; 41. first through hole;

[0026] 51. Transparent conductive layer; 52. Reflective layer; 53. Insulating wrapping layer;

[0027] 61. first insulating layer; 610. second through hole; 62. electrode;

[0028] 71. A second insulating layer; 72. A soldering pad. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0030] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity restriction, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0031] Figure 1 Schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 As shown, the light emitting diode includes: an epitaxial layer 20 , an insulating protection layer 30 and a passivation layer 40 .

[0032] like Figure 1 As shown, the surface of the epitaxial layer 20 has a groove 24 , the insulating protection layer 30 is at least located on the groove wall of the groove 24 , the passivation layer 40 is located on the surface of the insulating protection layer 30 , and the insulating protection layer 30 is located between the groove wall of the groove 24 and the passivation layer 40 .

[0033] The light-emitting diode provided by the embodiment of the present disclosure is provided with an insulating protective layer 30 on the groove wall of the groove 24, so that the insulating protective layer 30 is sandwiched between the groove wall of the groove 24 and the passivation layer 40, that is, the groove wall of the groove 24 and the passivation layer 40 are separated by the insulating protective layer 30. In this way, the groove wall of the groove 24 is covered by the insulating protective layer 30, and when the passivation layer 40 is subsequently prepared, the passivation layer 40 will not contact the exposed groove wall of the groove 24, thereby preventing the passivation layer 40 from damaging the exposed multi-quantum well layer 22 on the epitaxial layer 20, thereby improving the hole-electron recombination efficiency and enhancing the luminous efficiency of the light-emitting diode.

[0034] Alternatively, if Figure 1 As shown, the light emitting diode further includes a substrate 10 , and an epitaxial layer 20 is located on the surface of the substrate 10 .

[0035] Exemplarily, the substrate is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0036] In the embodiment of the present disclosure, the epitaxial layer 20 includes a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 which are sequentially stacked on a substrate.

[0037] For example, Figure 1 As shown, the groove 24 is located on the surface of the second semiconductor layer 23 , and the groove 24 exposes the first semiconductor layer 21 .

[0038] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0039] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0040] In the implementation of the present disclosure, the first semiconductor layer 21 is Al x Ga 1-x N material layer, wherein X is greater than or equal to 0 and less than or equal to 1.

[0041] Exemplarily, when X is 0, the first semiconductor layer 21 is a GaN layer. For example, the first semiconductor layer 21 is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0042] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0043] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0044] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0045] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0046] Optionally, the passivation layer 40 is a silicon oxide layer.

[0047] Exemplarily, the thickness of the silicon oxide layer is 3000 angstroms to 5000 angstroms. For example, the thickness of the silicon oxide layer is 4000 angstroms.

[0048] In the disclosed embodiment, the passivation layer 40 is usually prepared by PECVD (Plasma Enhanced Chemical Vapor Deposition) technology. However, the silicon oxide layer deposited by PECVD technology will damage the exposed multi-quantum well layer 22, thereby reducing the light-emitting efficiency of the light-emitting diode.

[0049] Optionally, the insulating protection layer 30 includes an aluminum oxide layer.

[0050] In the embodiment of the present disclosure, when preparing the aluminum oxide layer, the aluminum oxide layer can be formed on the sidewalls of the multi-quantum well layer 22 exposed by the groove 24 by using the atomic layer deposition (ALD) technology. This avoids the use of the PECVD technology to damage the exposed multi-quantum well layer 22.

[0051] Furthermore, when the passivation layer 40 is subsequently formed on the aluminum oxide layer, the aluminum oxide layer will block the contact between the passivation layer 40 and the multi-quantum well layer 22 , thereby preventing the multi-quantum well layer 22 from being damaged when the passivation layer 40 is deposited.

[0052] Optionally, the thickness of the insulating protection layer 30 is 100 angstroms to 300 angstroms.

[0053] Depositing a thin insulating protective layer 30 on the sidewall of the groove 24 not only protects the multi-quantum well layer 22, but also absorbs less light, thereby preventing the total thickness of the insulating protective layer 30 and the passivation layer 40 from exceeding and affecting the light output.

[0054] Exemplarily, the thickness of the insulating protection layer 30 is 200 angstroms.

[0055] Optionally, the orthographic projection of the passivation layer 40 on the surface of the epitaxial layer 20 away from the insulating protection layer 30 is located within the orthographic projection of the insulating protection layer 30 on the surface of the epitaxial layer 20 away from the insulating protection layer 30 .

[0056] By making the orthographic projection of the passivation layer 40 outside the outer contour of the orthographic projection of the insulating protection layer 30 , the passivation layer 40 is prevented from crossing the insulating protection layer 30 and covering the epitaxial layer 20 , so that the exposed multi-quantum well layer 22 on the epitaxial layer 20 can be fully protected.

[0057] Alternatively, if Figure 1As shown, the light emitting diode also includes a transparent conductive layer 51, a reflective layer 52 and an insulating wrapping layer 53. The transparent conductive layer 51 is located on the surface of the second semiconductor layer 23. The insulating protective layer 30 is also located on the surface of the second semiconductor layer 23, and the insulating protective layer 30 covers the transparent conductive layer 51. The passivation layer 40 is also located on the surface of the passivation layer 40 away from the second semiconductor layer 23. The surface of the passivation layer 40 away from the second semiconductor layer 23 has a first through hole 41 exposing the transparent conductive layer 51.

[0058] For example, Figure 1 As shown, the first through hole 41 penetrates the passivation layer 40 and the insulating protection layer 30, and the axial section of the first through hole 41 is inverted trapezoidal, that is, the diameter of the partial hole section of the first through hole 41 located in the passivation layer 40 is smaller than the diameter of the partial hole section of the first through hole 41 located in the insulating protection layer 30. In this way, it can be ensured that the orthographic projection of the passivation layer 40 is located outside the outer contour of the orthographic projection of the insulating protection layer 30, thereby preventing the passivation layer 40 from crossing the insulating protection layer 30 and covering the transparent conductive layer 51, and fully protecting the transparent conductive layer 51.

[0059] Optionally, the transparent conductive layer 51 may be an indium tin oxide (ITO) layer or an indium zinc oxide (IZO) layer.

[0060] Exemplarily, the transparent conductive layer 51 is an indium tin oxide layer. The indium tin oxide layer has good transmittance and low resistivity. The indium tin oxide layer has low resistivity, facilitates carrier conduction, and improves injection efficiency.

[0061] Exemplarily, the transparent conductive layer 51 is an indium zinc oxide layer. The indium zinc oxide layer has good transmittance and low resistivity. The indium zinc oxide layer has low resistivity, facilitates carrier conduction, and improves injection efficiency.

[0062] Exemplarily, the thickness of the transparent conductive layer 51 is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer 51 is 200 angstroms.

[0063] like Figure 1 As shown, the reflective layer 52 is located on the surface of the passivation layer 40 away from the second semiconductor layer 23 , and the reflective layer 52 is electrically connected to the transparent conductive layer 51 through the first through hole 41 , and the insulating wrapping layer 53 is located on the surface of the reflective layer 52 away from the second semiconductor layer 23 .

[0064] The reflective layer 52 can be used to reflect the light emitted from the epitaxial layer 20 , so that more light can be emitted from the light-emitting surface of the epitaxial layer 20 , thereby improving the light-emitting intensity of the light-emitting diode.

[0065] At the same time, the reflective layer 52 is also covered with an insulating wrapping layer 53 to prevent the metal in the reflective layer 52 from migrating upward.

[0066] Compared with the related art, using a metal protective layer to cover the reflective layer 52 and using an insulating wrapping layer 53 to cover the reflective layer 52 can not only save costs, but also the insulating wrapping layer 53 and the passivation layer 40 can be prepared with different materials, so that the refractive index of the insulating wrapping layer 53 and the passivation layer 40 is different, so that the light is reflected or refracted at the junction of the insulating wrapping layer 53 and the passivation layer 40, so as to avoid the light being absorbed by the metal and increase the light output of the light-emitting diode.

[0067] Optionally, the reflective layer 52 includes an Ag layer, a Ni layer, and a TiW layer stacked in sequence.

[0068] Since Ag has a good reflective effect, providing an Ag layer in the reflective layer 52 can enhance the reflection of light by the reflective layer 52 and improve the light emitting brightness of the light emitting surface of the light emitting diode.

[0069] The Ni layer has good corrosion resistance and wear resistance, and the TiW layer can be successfully deposited on other films as an adhesion layer without peeling or cracking. The alternating stacked Ni and TiW layers can act as a barrier layer to protect the silver mirror.

[0070] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0071] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0072] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0073] Optionally, the insulating wrapping layer 53 includes an aluminum oxide layer. In this way, the insulating protection layer 30, the passivation layer 40 and the insulating wrapping layer 53 can form a composite insulating layer of alternately stacked different materials, so that light is reflected or refracted at the junction of two adjacent film layers, thereby increasing the light output.

[0074] Optionally, the thickness of the insulating wrapping layer 53 is 500 angstroms to 1200 angstroms. The thickness of the insulating wrapping layer 53 cannot be set too thin to prevent the insulating wrapping layer 53 from failing to block the metal migration in the reflective layer 52, and the thickness of the insulating wrapping layer 53 cannot be set too thick to avoid the insulating wrapping layer 53 being too thick and absorbing a large amount of light.

[0075] Exemplarily, the thickness of the insulating wrap layer 53 is 1000 angstroms.

[0076] Alternatively, if Figure 1As shown, the light emitting diode further includes a first insulating layer 61 and an electrode 62 . The first insulating layer 61 is located on a surface of the insulating wrapping layer 53 away from the second semiconductor layer 23 , and the first insulating layer 61 is located in the groove 24 .

[0077] like Figure 1 As shown, the first insulating layer 61 has a second through hole 610 that exposes the reflective layer 52 and the bottom of the groove 24 respectively. The electrode 62 is located on the surface of the first insulating layer 61 and is electrically connected to the reflective layer 52 and the first semiconductor layer 21 respectively through the second through hole 610.

[0078] The surface of the first insulating layer 61 has a second through hole 610 exposing the reflective layer 52 and the bottom of the groove 24 .

[0079] Exemplarily, the first insulating layer 61 may be a silicon oxide layer.

[0080] Exemplarily, the thickness of the first insulating layer 61 is 4000 angstroms to 6000 angstroms.

[0081] Alternatively, if Figure 1 As shown, the electrode 62 is located on the surface of the first insulating layer 61 and is electrically connected to the reflective layer 52 and the first semiconductor layer 21 respectively through the second through hole 610 .

[0082] Optionally, the electrode 62 includes a Cr layer, an Al layer, a Ti layer and a Pt layer stacked in sequence. The thickness of the Cr layer is 1500 to 2500 angstroms. The thickness of the Al layer is 1000 to 2500 angstroms. The thickness of the Ti layer is 300 to 700 angstroms. The thickness of the Pt layer is 1500 to 2500 angstroms.

[0083] Alternatively, if Figure 1 As shown, the light emitting diode may further include a second insulating layer 71 and a pad 72, wherein the second insulating layer 71 is located on the surface of the first insulating layer 61 and covers the electrode 62. The second insulating layer 71 has a through hole exposing the electrode 62, the pad 72 is located on the surface of the second insulating layer 71 away from the epitaxial layer 20, and the pad 72 is electrically connected to the electrode 62 through the through hole.

[0084] Optionally, the pad 72 includes at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

[0085] The above metal material has good heat dissipation performance. Therefore, the pad 72 made of the above material also has good heat dissipation performance, which can improve the heat dissipation effect of the light emitting diode.

[0086] Alternatively, the pad 72 includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked in sequence.

[0087] Exemplarily, the thickness of the first Ti layer is 20 angstroms to 100 angstroms. For example, the thickness of the first Ti layer is 50 angstroms.

[0088] Exemplarily, the thickness of the Al layer is 10000 angstroms to 20000 angstroms. For example, the thickness of the Al layer is 15000 angstroms.

[0089] Exemplarily, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms. For example, the thickness of the second Ti layer is 1000 angstroms.

[0090] Exemplarily, the thickness of the Pt layer is 500 angstroms to 1500 angstroms. For example, the thickness of the Pt layer is 1000 angstroms.

[0091] Exemplarily, the thickness of the Ni layer is 60,000 angstroms to 80,000 angstroms. For example, the thickness of the Ni layer is 70,000 angstroms.

[0092] Exemplarily, the thickness of the Au layer is 1500 angstroms to 2500 angstroms. For example, the thickness of the Au layer is 2000 angstroms.

[0093] Figure 2 FIG. 1 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 2 As shown, the preparation method comprises:

[0094] Step 101: forming an epitaxial layer.

[0095] like Figure 1 As shown, the epitaxial layer 20 includes a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 stacked in sequence, and the second semiconductor layer 23 has a groove 24 exposing the first semiconductor layer 21 .

[0096] Step 102 : forming an insulating protection layer 30 on the surface of the epitaxial layer 20 .

[0097] The insulating protection layer 30 is at least located on the groove wall of the groove 24 .

[0098] Step 103 : forming a passivation layer 40 on the surface of the insulating protection layer 30 , wherein the insulating protection layer 30 is located between the groove wall of the groove 24 and the passivation layer 40 .

[0099] The light-emitting diode provided by the embodiment of the present disclosure is provided with an insulating protective layer 30 on the groove wall of the groove 24, so that the insulating protective layer 30 is sandwiched between the groove wall of the groove 24 and the passivation layer 40, that is, the groove wall of the groove 24 and the passivation layer 40 are separated by the insulating protective layer 30. In this way, the groove wall of the groove 24 is covered by the insulating protective layer 30, and when the passivation layer 40 is subsequently prepared, the passivation layer 40 will not contact the exposed groove wall of the groove 24, thereby preventing the passivation layer 40 from damaging the exposed multi-quantum well layer 22 on the epitaxial layer 20, thereby improving the hole-electron recombination efficiency and enhancing the luminous efficiency of the light-emitting diode.

[0100] The step 101 of preparing the epitaxial layer 20 may include:

[0101] First, a substrate is provided.

[0102] The substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0103] As an example, in the embodiment of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0104] The sapphire substrate may be pre-treated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0105] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0106] Then, a first semiconductor layer 21 , a multi-quantum well layer 22 and a second semiconductor layer 23 are sequentially formed on the sapphire substrate by MOCVD technology.

[0107] The first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0108] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0109] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

[0110] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0111] When growing the multi-quantum well layer 22, the pressure of the MOCVD reaction chamber is controlled at 200 torr. When growing the InGaN quantum well layer, the temperature of the reaction chamber is 760° C. to 780° C. When growing the GaN quantum barrier layer, the temperature of the reaction chamber is 860° C. to 890° C.

[0112] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0113] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0114] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0115] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0116] Before step 102, the following steps are also included:

[0117] First, the transparent conductive layer 51 is formed on the surface of the second semiconductor layer 23 .

[0118] Then, the transparent conductive layer 51 is etched to form a via hole exposing the second semiconductor layer 23 on the surface of the transparent conductive layer 51 .

[0119] Next, the second semiconductor layer 23 is etched in the via hole to form a groove 24 on the surface of the second semiconductor layer 23 that exposes the first semiconductor layer 21 .

[0120] After forming the epitaxial layer 20, the disclosed embodiment then forms a transparent conductive layer 51 on the surface of the second semiconductor layer 23; then etches the transparent conductive layer 51 to form a via hole exposing the second semiconductor layer 23; then etches the second semiconductor layer 23 in the via hole to form a groove 24 exposing the first semiconductor layer 21. This preparation method forms a transparent conductive layer 51 on the second semiconductor before etching the groove 24 exposing the side wall of the multi-quantum well layer 22. This avoids damage to the multi-quantum well layer 22 due to the exposure of the side wall of the multi-quantum well layer 22 when forming the transparent conductive layer 51. Therefore, the hole-electron recombination efficiency is improved, and the luminous efficiency of the light-emitting diode is enhanced.

[0121] Exemplarily, the transparent conductive layer 51 is an indium tin oxide layer or an indium zinc oxide layer.

[0122] Exemplarily, the thickness of the transparent conductive layer 51 is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer 51 is 250 angstroms.

[0123] Step 102 may include: forming an insulating protection layer 30 on the surface of the second semiconductor layer 23 , the surface of the transparent conductive layer 51 , and in the groove 24 .

[0124] Exemplarily, the insulating protection layer 30 includes an aluminum oxide layer.

[0125] Exemplarily, the thickness of the insulating protection layer 30 is 100 angstroms to 300 angstroms.

[0126] When preparing the insulating protection layer 30 , an aluminum oxide layer may be formed on the sidewalls of the multi-quantum well layer 22 exposed by the groove 24 , the surface of the second semiconductor layer 23 , and the surface of the transparent inverted conductive layer by atomic layer deposition technology.

[0127] Step 103 may include: forming a passivation layer 40 on the surface of the insulating protection layer 30 .

[0128] Exemplarily, the passivation layer 40 may be a silicon oxide layer.

[0129] Exemplarily, the thickness of the passivation layer 40 is 4000 angstroms to 6000 angstroms. For example, the thickness of the passivation layer 40 is 5000 angstroms.

[0130] After step 103, the following steps may also be included:

[0131] First, the passivation layer 40 is etched to form a first through hole 41 exposing the transparent conductive layer 51 on the surface of the passivation layer 40 .

[0132] Specifically, it may include: forming a photoresist layer on the surface of the passivation layer 40. The photoresist layer has an opening, and the opening is used for photolithography of the passivation layer 40 and the insulating protection layer 30 to form the first through hole 41.

[0133] Exemplarily, the axial cross section of the first through hole 41 is an inverted trapezoid. The angle between the hole wall of the first through hole 41 and the surface of the transparent conductive layer 51 may be 20° to 70°.

[0134] like Figure 1 As shown, a plurality of first through holes 41 exposing the transparent conductive layer 51 are formed on the surface of the passivation layer 40 , and the plurality of first through holes 41 are arranged at intervals.

[0135] To ensure that the film layer on the passivation layer 40 can fully contact the transparent conductive layer 51, a plurality of first through holes 41 are formed on the surface of the passivation layer 40, so that the film layer can be connected to various areas on the transparent conductive layer 51 through the plurality of first through holes 41, thereby improving the connection reliability.

[0136] Then, a reflective layer 52 is formed on the surface of the passivation layer 40 , so that the reflective layer 52 is electrically connected to the transparent conductive layer 51 through the third through hole 42 .

[0137] Optionally, the reflective layer 52 includes an Ag layer, a Ni layer, and a TiW layer stacked in sequence.

[0138] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0139] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0140] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0141] Next, the insulating coating layer 53 is formed on the surface of the passivation layer 40 so that the insulating coating layer 53 covers the reflective layer 52 .

[0142] Optionally, the insulating wrapping layer 53 includes an aluminum oxide layer. In this way, the insulating protection layer 30, the passivation layer 40 and the insulating wrapping layer 53 can form a composite insulating layer of alternately stacked different materials, so that light is reflected or refracted at the junction of two adjacent film layers, thereby increasing the light output.

[0143] Optionally, the thickness of the insulating wrapping layer 53 is 500 angstroms to 1200 angstroms. The thickness of the insulating wrapping layer 53 cannot be set too thin to prevent the insulating wrapping layer 53 from failing to block the metal migration in the reflective layer 52, and the thickness of the insulating wrapping layer 53 cannot be set too thick to avoid the insulating wrapping layer 53 being too thick and absorbing a large amount of light.

[0144] Exemplarily, the thickness of the insulating wrap layer 53 is 1000 angstroms.

[0145] Then, a first insulating layer 61 is formed on the surface of the insulating wrap layer 53 and in the groove 24 .

[0146] like Figure 1 As shown, the first insulating layer 61 covers the metal protection layer, and the first insulating layer 61 has through holes that expose the reflective layer 52 and the bottom of the groove 24 respectively.

[0147] Exemplarily, the first insulating layer 61 may be a silicon oxide layer.

[0148] Exemplarily, the thickness of the first insulating layer 61 is 4000 angstroms to 6000 angstroms.

[0149] Next, the electrode 62 is formed on the surface of the first insulating layer 61 .

[0150] Alternatively, if Figure 1 As shown, the electrode 62 is electrically connected to the reflective layer 52 and the first semiconductor layer 21 through the through holes.

[0151] Exemplarily, the reflective layer 52 is connected to the second semiconductor layer 23 , and the second semiconductor layer 23 is a p-type layer, so the electrode 62 electrically connected to the reflective layer 52 is a p-electrode 62 .

[0152] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the electrode 62 electrically connected to the first semiconductor layer 21 is an n-electrode 62 .

[0153] The preparation of the electrode 62 may specifically include: sequentially evaporating a Cr layer, an Al layer, a Ti layer, and a Pt layer.

[0154] Exemplarily, the thickness of the evaporated Cr layer is 1500 angstroms to 2500 angstroms.

[0155] Illustratively, the thickness of the evaporated Al layer is 1000 angstroms to 2500 angstroms.

[0156] Among them, the Ti layer and the Pt layer are used as wrapping layers, and a thicker metal layer can be used to reduce the resistance of the electrode 62, and at the same time, it can play a role in protecting the Cr layer and the Al layer.

[0157] Illustratively, the thickness of the Ti layer evaporated is 300 angstroms to 700 angstroms.

[0158] Illustratively, the thickness of the evaporated Pt layer is 1500 angstroms to 2500 angstroms.

[0159] Then, the second insulating layer 71 is formed on the surface of the first insulating layer 61 .

[0160] like Figure 1 As shown, the second insulating layer 71 covers the electrode 62 , and the second insulating layer 71 has a through hole exposing the electrode 62 .

[0161] Exemplarily, the second insulating layer 71 is a DBR (Distributed Bragg Reflector) layer, which includes a plurality of silicon oxide layers and a plurality of titanium oxide layers, and has a thickness of 3 μm to 4 μm.

[0162] Next, a pad 72 is formed on the surface of the second insulating layer 71 , and the pad 72 is electrically connected to the electrode 62 through a through hole.

[0163] like Figure 1 As shown, a pad 72 is formed on the surface of the second insulating layer 71 away from the epitaxial layer 20 , so that the pad 72 is electrically connected to the electrode 62 through the through hole.

[0164] Optionally, the pad 72 layer includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked in sequence.

[0165] Exemplarily, the thickness of the first Ti layer is 20 angstroms to 100 angstroms. For example, the thickness of the first Ti layer is 50 angstroms.

[0166] Exemplarily, the thickness of the Al layer is 10000 angstroms to 20000 angstroms. For example, the thickness of the Al layer is 15000 angstroms.

[0167] Exemplarily, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms. For example, the thickness of the second Ti layer is 1000 angstroms.

[0168] Exemplarily, the thickness of the Pt layer is 500 angstroms to 1500 angstroms. For example, the thickness of the Pt layer is 1000 angstroms.

[0169] Exemplarily, the thickness of the Ni layer is 60,000 angstroms to 80,000 angstroms. For example, the thickness of the Ni layer is 70,000 angstroms.

[0170] Exemplarily, the thickness of the Au layer is 1500 angstroms to 2500 angstroms. For example, the thickness of the Au layer is 2000 angstroms.

[0171] The experimental data of the light emitting diode provided by the embodiment of the present disclosure are as follows in Table 1:

[0172] Table 1

[0173]

[0174] According to the test results in Table 1, the comprehensive yield of the light-emitting diode provided in the embodiment of the present disclosure is 92.6%. The comprehensive yield of the light-emitting diode in the related art is 90.5%. It can be seen that under the same working environment, the yield of the light-emitting diode provided in the present disclosure is higher, which is 2% higher than the yield of the light-emitting diode in the related art.

[0175] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises: an epitaxial layer (20), an insulating protection layer (30) and a passivation layer (40); The surface of the epitaxial layer (20) has a groove (24), the insulating protection layer (30) is at least located on the groove wall of the groove (24), the passivation layer (40) is located on the surface of the insulating protection layer (30), and the insulating protection layer (30) is located between the groove wall of the groove (24) and the passivation layer (40).

2. The light emitting diode according to claim 1, characterized in that: The insulating protective layer (30) comprises an aluminum oxide layer.

3. The light emitting diode according to claim 1, characterized in that: The thickness of the insulating protection layer (30) is 100 angstroms to 300 angstroms.

4. The light emitting diode according to any one of claims 1 to 3, characterized in that: An orthographic projection of the passivation layer (40) on a surface of the epitaxial layer (20) away from the insulating protection layer (30) is located within an orthographic projection of the insulating protection layer (30) on a surface of the epitaxial layer (20) away from the insulating protection layer (30).

5. The light emitting diode according to any one of claims 1 to 3, characterized in that: The epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22), and a second semiconductor layer (23) which are stacked in sequence, and the second semiconductor layer (23) has the groove (24) exposing the first semiconductor layer (21); The light emitting diode further comprises a transparent conductive layer (51), a reflective layer (52) and an insulating wrapping layer (53); the transparent conductive layer (51) is located on the surface of the second semiconductor layer (23); the insulating protective layer (30) is also located on the surface of the second semiconductor layer (23) and covers the transparent conductive layer (51); the passivation layer (40) is also located on the surface of the passivation layer (40) away from the second semiconductor layer (23); and the surface of the passivation layer (40) away from the second semiconductor layer (23) has a first through hole (41) exposing the transparent conductive layer (51); The reflective layer (52) is located on a surface of the passivation layer (40) away from the second semiconductor layer (23), and is electrically connected to the transparent conductive layer (51) via the first through hole (41); and the insulating wrapping layer (53) is located on a surface of the reflective layer (52) away from the second semiconductor layer (23).

6. The light emitting diode according to claim 5, characterized in that: The insulating wrapping layer (53) comprises an aluminum oxide layer.

7. The light emitting diode according to claim 5, characterized in that: The thickness of the insulating wrapping layer (53) is 500 angstroms to 1200 angstroms.

8. The light emitting diode according to claim 6 or 7, characterized in that: The light emitting diode further comprises a first insulating layer (61) and an electrode (62); the first insulating layer (61) is located on a surface of the insulating wrapping layer (53) away from the second semiconductor layer (23) and is located in the groove (24); the first insulating layer (61) has a second through hole (610) respectively exposing the reflective layer (52) and the bottom of the groove (24); the electrode (62) is located on the surface of the first insulating layer (61) and is electrically connected to the reflective layer (52) and the first semiconductor layer (21) respectively through the second through hole (610).

9. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: forming an epitaxial layer, wherein a surface of the epitaxial layer has a groove; forming an insulating protective layer on the surface of the epitaxial layer, wherein the insulating protective layer is at least located on the groove wall of the groove; A passivation layer is formed on the surface of the insulating protection layer, and the insulating protection layer is located between the groove wall of the groove and the passivation layer.

10. The preparation method according to claim 9, characterized in that: Forming the epitaxial layer includes: A first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer are sequentially stacked on a substrate; Before forming the insulating protective layer on the surface of the epitaxial layer, the method further comprises: forming a transparent conductive layer on a surface of the second semiconductor layer; Etching the transparent conductive layer to form a via hole on the surface of the transparent conductive layer exposing the second semiconductor layer; The second semiconductor layer is etched in the via hole to form the groove exposing the first semiconductor layer on the surface of the second semiconductor layer.

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