Method and apparatus for processing data associated with computing device

Abstract

A method, e.g., a computer-implemented method, for processing data associated with a computing device has providing at least one first queue in a first storage area to which a first process associated with the computing device and a second process associated with the computing device can access, e.g., exclusively access.

Description

Technical Field

[0001] The present disclosure relates to a method for processing data associated with a computing device.

[0002] The present disclosure also relates to an apparatus for processing data associated with a computing device. Summary of the invention

[0003] Exemplary embodiments relate to a method, such as a computer-implemented method, for processing data associated with a computing device, the method comprising: providing at least one first queue in a first memory area, to which a first process associated with the computing device and a second process associated with the computing device can access, such as exclusively access, the first memory area. In other exemplary embodiments, this enables efficient provision of means for exchanging data between processes, such as processes of the computing device, such as in a shared memory (Shared-Memory) (i.e., for example, "shared") memory area accessible to the relevant processes, but not to other, further processes, such as other processes.

[0004] In a further exemplary embodiment it is provided that the method comprises:

[0005] The at least one first queue is used for data exchange between the first process and the second process, wherein, for example, the use has at least one of the following elements:

[0006] a) sending data, for example in the form of at least one first message, from a first process to a second process;

[0007] b) sending data, for example in the form of at least one second message, from the second process to the first process.

[0008] In other exemplary embodiments, it is provided that at least one first queue and at least one further, for example a second queue are provided, wherein, for example, the at least one further, for example a second queue is also provided in the first memory area to which the first process associated with the computing device and the second process associated with the computing device can access, for example exclusively access. Thus, in other exemplary embodiments, efficient data communication between the first process and the second process, for example in two directions (for example from the first process to the second process and vice versa) can be achieved. The first queue can be used, for example, for a first direction of data communication between the first process and the second process, and the second queue can be used, for example, for a second direction of data communication between the first process and the second process.

[0009] In a further exemplary embodiment it is provided that the method comprises:

[0010] Preventing: For example, in addition to the first process and the second process, other processes associated with the computing device from accessing the first storage area, for example, accessing the at least one first queue (and / or the second queue).

[0011] In a further exemplary embodiment it is provided that the method comprises:

[0012] Access rights to the first memory area and / or to the at least one first queue (and / or the second queue) are assigned, for example exclusively assigned, to the first process and the second process.

[0013] In other exemplary embodiments, it is provided that the method includes: performing a plausibility check on at least one component of the at least one first queue. In other exemplary embodiments, this makes it possible to increase the security of data associated with the at least one first queue, for example. For example, in other exemplary embodiments, the plausibility check can detect the following situation, in which a storage area associated with the at least one first queue has been modified unexpectedly or due to an error, for example, or in which the content of the storage area associated with the at least one first queue has been changed in another, undesirable way (for example, a bit flip in the storage area).

[0014] In a further exemplary embodiment, it is provided that the method comprises at least one of the following elements:

[0015] a) using at least one FIFO (first in first out) memory for at least one queue, wherein, for example, the at least one FIFO memory has a first state variable, for example a tail variable, which characterizes a read position, wherein, for example, the at least one FIFO memory has a second state variable, for example a head variable, which characterizes a write position, wherein, for example, elements of the at least one FIFO memory each have a sequence number and valid data;

[0016] b) specifying the size of the FIFO memory or the at least one FIFO memory, for example specifying the number of elements;

[0017] c) statically allocate multiple or that number of elements;

[0018] d) using an index variable for the at least one state variable;

[0019] e) not using a pointer variable for the at least one state variable;

[0020] f) using a modulo operator, for example a statically encoded modulo operator, for accessing elements of the at least one FIFO memory, wherein, for example, the modulo operator is associated with the number of elements of the at least one FIFO memory, in particular without using variables to access elements of the at least one FIFO memory;

[0021] g) storing at least one component of the at least one FIFO memory, for example a size of the at least one FIFO memory, by means of a variable associated with a dedicated memory area of ​​at least one process, for example a High-ASIL process;

[0022] h) modifying at least one component of the at least one FIFO memory, such as the size of the at least one FIFO memory, such as during the runtime of the at least one process, such as reducing the size of the at least one FIFO memory during the runtime of the at least one process.

[0023] In a further exemplary embodiment, it is provided that the method comprises at least one of the following elements:

[0024] a) storing components of the at least one queue, for example the at least one FIFO memory, together with the comparison value;

[0025] b) performing a plausibility check on at least one component of the at least one queue, for example the at least one FIFO memory, based on the comparison value or the comparison value;

[0026] c) performing a plausibility check or the plausibility check during at least some read accesses, for example all read accesses, to the at least one component of the at least one queue;

[0027] d) initiating an error response, for example propagating the detected error, for example based on the plausibility check or the plausibility check, wherein for example the error response has at least one of the following elements: d1) initializing, for example reinitializing, the at least one first queue, d2) resending the message, for example in the case of defective valid data, d3) restarting at least one process;

[0028] e) atomically performing access to at least one component of the at least one queue, such as the at least one FIFO memory;

[0029] f) Access to at least one component of the at least one queue, for example the at least one FIFO memory, is performed lock-free.

[0030] In a further exemplary embodiment, it is provided that the method comprises at least one of the following elements:

[0031] a) determining at least one comparison value of at least one component of the at least one queue, such as the at least one FIFO memory; and optionally storing at least one component of the at least one queue, such as the at least one FIFO memory together with the comparison value.

[0032] In other exemplary embodiments, it is provided that the determination of the at least one comparison value has at least one of the following elements:

[0033] a) forming a value opposite to the value of at least one component of the at least one queue, for example by means of inversion;

[0034] b) performing a logic operation, such as an XOR operation, using the value of at least one component of the at least one queue;

[0035] c) Forming a checksum, for example a CRC-type checksum, for example, when the amount or size of data associated with the at least one component exceeds a predefinable threshold value.

[0036] In a further exemplary embodiment, it is provided that the method comprises at least one of the following elements:

[0037] a) incrementing the at least one state variable;

[0038] b) assigning the value of the second state variable to the sequence number or the sequence number, for example when writing into the at least one queue;

[0039] c) comparing the sequence number with a value of a first state variable, for example when reading from the at least one queue;

[0040] d) Based on the comparison, for example, an error response is initiated if necessary.

[0041] Further exemplary embodiments relate to a device for carrying out the method according to these embodiments.

[0042] Further exemplary embodiments relate to a product, for example a motor vehicle or a control unit, for example a control unit for a motor vehicle, which has at least one device according to the embodiments.

[0043] Other exemplary embodiments relate to a computer-readable storage medium comprising instructions that, when executed by a computer, cause the computer to perform the methods described in accordance with the embodiments.

[0044] Other exemplary embodiments relate to a computer program comprising instructions which, when executed by a computer, cause the computer to carry out the methods described in accordance with the embodiments.

[0045] Further exemplary embodiments relate to a data carrier signal which transmits and / or represents a computer program according to these embodiments.

[0046] Other exemplary embodiments relate to the use of the method according to these embodiments and / or the apparatus according to these embodiments and / or the product according to these embodiments and / or the computer-readable storage medium according to these embodiments and / or the computer program according to these embodiments and / or the data carrier signal according to these embodiments for at least one of the following elements:

[0047] a) processing data associated with at least one process of a computing device;

[0048] b) selectively granting access to the at least one queue to a specifiable set of processes associated with the computing device;

[0049] c) ensuring that communications between a specifiable set of processes associated with the computing device are free from interference, such as freedom from interference, such as with respect to interference caused by other processes, such as also associated with the computing device;

[0050] d) excluding, for example conceptually excluding, out-of-bounds accesses, for example out-of-bounds accesses to components of the at least one queue;

[0051] e) identifying a memory overwrite, such as an unwanted memory overwrite, such as with respect to a memory area associated with the at least one queue;

[0052] f) using a shared memory area to implement inter-process communication, e.g., non-intrusive, e.g., efficient, e.g., independent of an operating system;

[0053] g) use of the method and / or the device that implements the method in a safety-related application or system, for example in a mixed-ASIL system;

[0054] h) restricting the access rights of the process to the at least one queue.

[0055] Further features, applications and advantages of the invention are apparent from the following description of exemplary embodiments of the invention, which are shown in the figures of the accompanying drawings. All described or illustrated features form the subject matter of the invention by themselves or in any combination, regardless of their summary in the claims or their reference back to them and regardless of their expression or presentation in the description or in the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In the attached picture:

[0057] Figure 1 A simplified flow chart according to an exemplary embodiment is schematically shown;

[0058] Figure 2 schematically shows a simplified block diagram according to other exemplary embodiments;

[0059] Figure 3 schematically shows a simplified block diagram according to other exemplary embodiments;

[0060] Figure 4 schematically shows a simplified block diagram according to other exemplary embodiments;

[0061] Figure 5 schematically shows a simplified block diagram according to other exemplary embodiments;

[0062] Figure 6 Schematically shows a simplified flow chart according to other exemplary embodiments;

[0063] Figure 7 schematically shows a simplified block diagram according to other exemplary embodiments;

[0064] Figure 8 schematically shows a simplified block diagram according to other exemplary embodiments;

[0065] Fig. 9 schematically shows a simplified block diagram according to other exemplary embodiments;

[0066] Fig.10 schematically shows a simplified block diagram according to other exemplary embodiments;

[0067] Fig.11 schematically shows a simplified block diagram according to other exemplary embodiments;

[0068] Fig.12 Aspects of application according to further exemplary embodiments are schematically shown. DETAILED DESCRIPTION

[0069] For an exemplary embodiment, see Figure 1 , relates to a processing and computing device 12 ( Figure 2 ) associated with the data, such as a computer-implemented method, the method comprising: in a first storage area 14-1 ( Figure 2 ) provides 100( Figure 1) at least one first queue WS-1, to which a first process P-1 associated with the computing device 12 and a second process P-2 associated with the computing device 12 can access, for example, exclusively access. In other exemplary embodiments, this makes it possible to efficiently provide a device for exchanging data between processes P-1, P-2, for example, processes of the computing device 12, for example, in a shared memory (Shared-Memory) (i.e., for example, "shared") memory area that is accessible to the relevant processes P-1, P-2 but not to other, additional processes P-3, for example.

[0070] For example, a computing device 12 is designed and used to execute processes P-1, P-2, P-3 and forms, for example together with a storage device 14 accessible to the computing device, a device 10, such as a device for an embedded system or the like.

[0071] In other exemplary embodiments, computing device 12 is designed to at least temporarily perform at least some aspects of the methods described in accordance with these embodiments.

[0072] In a further exemplary embodiment it is provided that the method comprises:

[0073] The at least one first queue WS-1 is used 102 for data exchange A1, A2 between the first process P-1 and the second process P-2, wherein the use 102 has at least one of the following elements, for example:

[0074] a) sending 102a data, for example in the form of at least one first message, from a first process P-1 to a second process P-2;

[0075] b) Sending 102b data, for example in the form of at least one second message, from the second process P-2 to the first process P-1.

[0076] In other exemplary embodiments, it is provided that at least one first queue WS-1 and at least one further, for example, second queue WS-2 are provided, for example according to Figure 1 Block 100, wherein, for example, at least one further, for example a second queue WS-2 is also provided in the first memory area 14-1, to which the first process P-1 associated with the computing device 12 and the second process P-2 associated with the computing device 12 can access, for example exclusively access, see block arrows A1, A2. Thus, in other exemplary embodiments, efficient data communication between the first process P-1 and the second process P-2, for example in both directions (for example from the first process to the second process and vice versa) can be achieved.

[0077] The first queue WS-1 may be used, for example, for a first direction of data communication between the first process P-1 and the second process P-2, and the second queue WS-2 may be used, for example, for a second direction of data communication between the first process P-1 and the second process P-2.

[0078] In other exemplary embodiments, see Figure 1 , stipulates: This method has:

[0079] Block 105: For example, in addition to the first process P-1 and the second process P-2, other processes P-3 associated with the computing device 12 ( Figure 2 ) accesses the first storage area 14-1, for example, accesses the at least one first queue WS-1 (and / or the second queue WS-2). Figure 2 This is indicated by a crossed-out block arrow A3, which indicates that access by the other process P-3 to the first memory area 14-1 is not permitted or cannot be realized.

[0080] In other exemplary embodiments, see Figure 1 , stipulates: This method has:

[0081] Access rights to the first memory area 14-1 and / or to the at least one first queue WS-1 (and / or second queue WS-2) are assigned 106, for example exclusively, to the first process P-1 and the second process P-1.

[0082] In other exemplary embodiments, see Figure 1 , it is provided that: the method comprises: performing a rationality check 104 on at least one component of the at least one first queue WS-1. In other exemplary embodiments, this makes it possible to increase the security of data associated with the at least one first queue WS-1, for example. For example, in other exemplary embodiments, by means of the optional rationality check 104, a situation can be identified in which a storage area 14-1 associated with the at least one first queue WS-1 has been modified unexpectedly or undesirably due to an error, for example, or in which the current content of the first storage area 14-1 associated with the at least one first queue WS-1 has been changed in another, undesirable way (for example a bit flip in the storage area).

[0083] In other exemplary embodiments, see Figure 3 , stipulates: The method has at least one of the following elements:

[0084] a) using 110 at least one FIFO (first in first out) memory FIFO-1, FIFO-2 for at least one queue WS-1, WS-2 ( Figure 2), wherein, for example, the at least one FIFO memory FIFO, FIFO-1, FIFO-2, for example, see according to Figure 4 Schematic diagram, with a first state variable ZV-1, such as a tail variable, which first state variable represents a read position, wherein, for example, the at least one FIFO memory has a second state variable ZV-2, such as a head variable, which second state variable represents a write position, wherein, for example, the elements FIFO-EL-1, FIFO-EL-2, ... of the at least one FIFO memory FIFO respectively have sequence numbers SN-EL-1, SN-EL-2, ... and valid data ND-EL-1, ND-EL-2, .... For example, according to Figure 3 Each of the FIFO memories FIFO-1 and FIFO-2 of the block 110 has a Figure 4 The structure of FIFO.

[0085] In other exemplary embodiments, see Figure 3 , stipulates: The method has at least one of the following elements:

[0086] b) specifying the size FIFO-GR of the FIFO memory 111 or of the at least one FIFO memory FIFO-1, FIFO-2, for example specifying the number of elements 111a;

[0087] c) statically allocating 112 a number or number of FIFO-EL-ANZ elements;

[0088] d) using 113 index variables ZV-1-IDX, ZV-2-IDX for the at least one state variable ZV-1, ZV-2;

[0089] e) not using 114 the pointer variable POINT for the at least one state variable ZV-1, ZV-2;

[0090] f) using 115 a modulo operator MOD-OP, for example a statically encoded modulo operator, for accessing elements of the at least one FIFO memory, wherein for example the modulo operator MOD-OP is associated with the number FIFO-EL-ANZ of elements of the at least one FIFO memory FIFO-1, FIFO-2, in particular without using 115 a variable for accessing elements of the at least one FIFO memory FIFO-1, FIFO-2;

[0091] g) by means of a dedicated memory area 14-PR-1 ( Figure 2) associated variable V-FIFO-GR, storing 116 at least one component of the at least one FIFO memory, such as a size FIFO-GR of the at least one FIFO memory;

[0092] h) modifying 117 at least one component of the at least one FIFO memory, for example a size FIFO-GR of the at least one FIFO memory, for example reducing the size FIFO-GR of the at least one FIFO memory during the runtime of the at least one process.

[0093] In other exemplary embodiments, see Figure 5 , stipulates: The method has at least one of the following elements:

[0094] a) storing 120 components of at least one queue WS-1, WS-2, for example of the at least one FIFO memory, such as sequence numbers and / or valid data and / or at least one state variable, together with a comparison value VERGL-WERT;

[0095] b) performing a plausibility check 121 on at least one component of the at least one queue, for example the at least one FIFO memory, based on the comparison value or the comparison value VERGL-WERT;

[0096] c) performing 122 a plausibility check or the plausibility check 121 (see also, for example, 122 ) in the event of at least some read accesses, for example all read accesses, to the at least one component of the at least one queue WS-1, WS-2; Figure 1 , block 104);

[0097] d) initiating 123 an error response FR, for example propagating the identified error, for example based on the rationality check or the rationality check 121, wherein for example the error response FR has at least one of the following elements: d1) initializing, for example reinitializing, the at least one first queue WS-1, WS-2, d2) resending the message, for example in the case of defective valid data, d3) restarting at least one process P-1, P-2;

[0098] e) atomically executing 124 an access FIFO-ZUGR to at least one component of the at least one queue WS-1, WS-2, for example the at least one FIFO memory FIFO-1, FIFO-2;

[0099] f) Lock-free execution 125 of access to at least one component of the at least one queue WS- 1 , WS- 2 , for example FIFO-ZUGR, of the at least one FIFO memory.

[0100] In other exemplary embodiments, see Figure 6 , it is stipulated that: the method has at least one of the following elements: a) determining 130 at least one comparison value VERGL-WERT of at least one component (for example, serial number and / or valid data and / or at least one state variable) of the at least one queue WS-1, WS-2, for example, the at least one FIFO memory FIFO-1, FIFO-2; and optionally, storing 132 at least one component of the at least one queue WS-1, WS-2, for example, the at least one FIFO memory FIFO-1, FIFO-2 together with the comparison value VERGL-WERT, thereby, for example, being able to implement (for example, during a read access, for example, the next read access) the rationality check 104, 121 already described above by way of example.

[0101] In other exemplary embodiments, see Figure 6 , it is provided that the determination 130 of the at least one comparison value VERGL-WERT has at least one of the following elements:

[0102] a) forming 130a a value opposite to the value of at least one component of the at least one queue WS-1, WS-2, for example by means of an inversion;

[0103] b) performing 130b a logical operation, such as an XOR operation, using the value of at least one component of the at least one queue WS-1, WS-2;

[0104] c) For example, when the amount or size of data associated with the at least one component (for example the size of the useful data ND-EL-1, ND-EL-2, . . . ) exceeds a specifiable threshold value, a checksum, for example a CRC-type checksum, is formed 130c.

[0105] In other exemplary embodiments, see Figure 7 , stipulates: The method has at least one of the following elements:

[0106] a) incrementing 140 the at least one state variable ZV-1, ZV-2;

[0107] b) assigning 141 the value of the second state variable to the sequence number or the sequence number SN-EL-2, for example when writing into the at least one queue;

[0108] c) comparing 143 the sequence number SN-EL-2 with the value of the first state variable ZV-1, for example when reading from the at least one queue;

[0109] d) Based on the comparison 143 , for example if necessary, for example when the comparison 143 results in a deviation between the sequence number SN-EL- 2 and the value of the first state variable ZV- 1 , initiating 144 an error response FR′.

[0110] For other exemplary embodiments, see Figure 8 , relates to a device 200 for implementing the method according to these embodiments. For example, in other exemplary embodiments, according to Figure 2 The device 10 may have a subsequent reference Figure 8 The configuration 200 described exemplarily is a configuration comparable to that described above.

[0111] In other exemplary embodiments, it is provided that the device 200 ( Figure 8 ) has: a computing device ("computer") 202, which has at least one computing core 202a; a storage device 204 assigned to the computing device 202, for at least temporarily storing at least one of the following elements: a) data DAT (e.g. data associated with at least one process P-1, P-2, P-3, such as data of at least one queue WS-1, WS-2); b) a computer program PRG, for example, for executing the method according to these embodiments. In other exemplary embodiments, the storage device 204 also has, for example, Figure 2 At least one of the storage areas 14-1, 14-PR-1.

[0112] In other exemplary embodiments, see Figure 8 , the storage device 204 has: a volatile memory (e.g., a working memory (RAM)) 204a; and / or a non-volatile (NVM) memory (e.g., a flash EEPROM) 204b; or a combination thereof or a combination with other memory types not explicitly mentioned. For example, the first storage area 14-1 ( Figure 2 ) can be in RAM 204a( Figure 8 ) is implemented in .

[0113] Other exemplary embodiments relate to a computer-readable storage medium SM comprising instructions PRG which, when executed by a computer 202 , cause the computer to carry out the methods described in accordance with these embodiments.

[0114] Further exemplary embodiments relate to a computer program PRG comprising instructions which, when the program PRG is executed by the computer 202 , cause the computer to carry out the method described in accordance with the embodiments.

[0115] Other exemplary embodiments relate to a data carrier signal DCS, which represents and / or transmits a computer program PRG according to these embodiments. The data carrier signal DCS can be received, for example, via an optional data interface 206 of the device 200. Likewise, for example, data DAT can be transmitted (sent and / or received) via the optional data interface 206.

[0116] Fig. 9 A simplified block diagram according to other exemplary embodiments is schematically shown. The element Pa represents a first process associated with the computing device 12, 202 (i.e., for example, executable by the computing device 12, 202); the element Pb represents a second process associated with the computing device 12, 202 (i.e., for example, executable by the computing device 12, 202), which, for example, is to exchange data with the first process Pa when using the principles described according to these embodiments.

[0117] Each of the processes Pa and Pb is, for example, allocated a corresponding private address space pAS-a and pAS-b, and only the corresponding process Pa and Pb can access the private address space, respectively.

[0118] The element AS-ab represents an address space shared between the two processes Pa, Pb, so that each of the two processes Pa, Pb has access, e.g. read access and write access, to the address space and can be used, e.g., for secure and efficient data exchange A1, A2 between the two processes Pa, Pb (see, e.g., Figure 1 , Figure 2 ). The shared address space AS-ab is for example Figure 2 The first address area 14-1 is associated with, or is implemented or arranged in, the first storage area 14-1.

[0119] Exemplarily, a first queue WS-1 is provided for sending data, such as messages, from a first process Pa to a second process Pb, and a second queue WS-2 is provided for sending data, such as messages, from the second process Pb to the first process Pa, wherein, for example, in other exemplary embodiments, the first queue WS-1 may also be understood as a first channel ch_0 for data communication between the two processes Pa, Pb, and wherein, for example, in other exemplary embodiments, the second queue WS-2 may also be understood as a second channel ch_1 for data communication between the two processes.

[0120] In other exemplary embodiments, the two queues WS-1, WS-2 or channels ch_0, ch_1 form, for example, a socket SOCK-ab for secure data communication between the two processes Pa, Pb.

[0121] Fig.10 A simplified block diagram according to a further exemplary embodiment is schematically shown.

[0122] E1 exemplarily represents the first element of the queue WS, for example of FIFO type; E2 exemplarily represents the second element of the queue WS; E3 exemplarily represents the third element of the queue WS; and point E3' represents other possible elements of the queue WS, which are not depicted separately for the sake of clarity.

[0123] Elements E1, E2, E3, ... respectively have: a first area B1 for data data and comparison values ​​~data that may be associated with these data data; and a second area B2 for sequence numbers seq and comparison values ​​~seq that may be associated with the sequence numbers seq. In other exemplary embodiments, the comparison values ​​~data, ~seq can be, for example, Figure 6 To form, for example, as an inverted data value relative to data data, seq.

[0124] It should be pointed out that: Fig.10 In the example, for the sake of clarity, the corresponding data and serial numbers of each element E1, E2, E3, ... are represented in the same manner. Here, it should be understood that in the exemplary embodiment, the data contents of the first area B1 of different elements E1, E2, E3, ... of the exemplary queue can be the same or different from each other, for example, the same or different from each other in pairs, wherein, for example, the serial numbers of different elements E1, E2, E3, ... of the exemplary queue are different from each other.

[0125] Subsequently, a first pseudo code listing ("Listing 1") is described, which, in other exemplary embodiments, for example, describes aspects of sending data, such as messages, according to the principles described in these embodiments. Each line of Listing 1 is preceded by a line number.

[0126] *** List 1 starts ***

[0127] 1send(const&msg):

[0128] 2curHead=atomic_load(head);

[0129] 3if(corrupt(curHead))return corruption;

[0130] 4slot=slots[idx(curHead)];

[0131] 5slot.data.construct(msg);

[0132] 6slot.seq=atomic_store(curHead);

[0133] 7head=atomic_store(curHead+1);

[0134] 8return OK;

[0135] ***END OF LIST 1***.

[0136] The first line of Listing 1 describes sending a message msg, for example by means of a function call "send()", wherein a reference &msg to the message msg to be sent is passed as a parameter. The second line describes: loading, for example atomically loading, the current head variable of the queue to be used for the sending (see, for example, Figure 4 The second state variable ZV-2); and the value of the header variable is assigned to the variable curHead. Line 3 describes: Check the value of the header variable, for example, according to Figure 1 and optionally initiate an error response, in the present case returning the error code "corruption". Line 4 describes: With the help of the indexing function idx(), based on the value of the variable curHead, the value from the array slots[] is assigned to the variable slot, which indexing function uses, for example, the modulo operator MOD-OP (see Figure 3 ), such as a statically encoded modulo operator. Line 5 describes dispatching the contents of the message to be sent into the slots. Line 6 describes dispatching the updated sequence value of the message. Line 7 describes dispatching the updated header variable. Line 8 describes the return from the send() function.

[0137] Subsequently, a second pseudo code listing ("Listing 2") is described, which, in other exemplary embodiments, for example, describes aspects of receiving data, such as messages, according to the principles described in these embodiments. Each line of Listing 2 is preceded by a line number.

[0138] *** BEGINNING LIST 2 ***

[0139] 1receive(&msg):

[0140] 2curTail=atomic_load(tail);

[0141] 3if(corrupt(curTail))return corruption;

[0142] 4slot=slots[idx(curTail)];

[0143] 5curSeq=atomic_load(slot.seq));

[0144] 6if(corrupt(curSeq))return corruption;

[0145] 7if(corrupt(slot.data.copy(msg))return corruption;

[0146] 8tail=atomic_store(curTail+1);

[0147] 9return OK;

[0148] ***END OF LIST 2***.

[0149] The first line of Listing 2 describes receiving a message, for example by means of a function call "receive()", wherein a reference to a variable msg representing the message to be received &msg is passed as a parameter. The second line describes: loading, for example atomic loading, the current tail variable of the queue to be used for the reception (see, for example, Figure 4 The first state variable ZV-1); and the value of the tail variable is assigned to the variable curTail. Line 3 describes: Check the value of the tail variable, for example, according to Figure 1 and optionally initiate an error response, in the present case returning the error code "corruption". Line 4 describes: With the help of the indexing function idx(), based on the value of the variable curTail, the value from the array slots[] is assigned to the variable slot, which uses, for example, the modulo operator MOD-OP (see Figure 3 ), such as a statically encoded modulo operator. Line 5 describes: for example, atomically loading the sequence number of the time slot previously identified in line 4. Line 6 describes: checking the value of the sequence number, such as in accordance with Figure 1and optionally initiate an error response, in the present case returning the error code "corruption". Line 7 describes: Checking the content of the message to be received, for example in accordance with Figure 1 and optionally initiate an error response, in the present case returning the error code "corruption". Line 8 describes the dispatching of the updated tail variable. Line 9 describes the return from the receive() function.

[0150] For other exemplary embodiments, see Fig.11 , relates to a product, for example a motor vehicle 1000 or a control device 1002 , for example a control device for a motor vehicle 1000 , which has at least one device 10 , 200 according to the embodiments.

[0151] For other exemplary embodiments, see Fig.12 , relating to the method according to these embodiments and / or the device 10, 200 according to these embodiments and / or the product 1000, 1002 according to these embodiments and / or the computer-readable storage medium SM according to these embodiments and / or the computer program PRG according to these embodiments and / or the application 300 of the data carrier signal DCS according to these embodiments for at least one of the following elements:

[0152] a) processing 301 data associated with at least one process P-1, P-2 of the computing device 12, 202;

[0153] b) selectively granting 302 access to at least one queue WS-1, WS-2 for a specifiable set of processes P-1, P-2 associated with a computing device 12, 202;

[0154] c) ensuring 303 that the communication between the processes P-1 and P-2 associated with the computing device of a specifiable set is free from interference, such as freedom from interference (Freedom from Interference), for example, with respect to interference caused by other processes, such as P-3, which is also associated with the computing device;

[0155] d) Excluding 304, for example conceptually excluding out-of-bounds accesses, for example out-of-bounds accesses to components ZV-1, ZV-2, FIFO-EL-1, FIFO-EL-2, ... of at least one queue WS-1, WS-2;

[0156] e) identifying 305 a memory overwrite, for example an unwanted memory overwrite, for example with respect to a memory area 14-1 associated with at least one queue WS-1, WS-2;

[0157] f) using 306 the shared memory area 14-1, AS-ab to implement inter-process communication, e.g. non-interfering, e.g. efficient inter-process communication, e.g. independent of the operating system;

[0158] g) implementing 307 the method and / or the use of the device 12 , 200 for carrying out the method in a safety-related application, for example in a mixed ASIL system;

[0159] h) Restrict 308 the access rights of process P-3 to at least one queue WS-1, WS-2.

[0160] Subsequently, other exemplary aspects and embodiments are described, in which these aspects and embodiments can be combined with at least one of the aspects described above and / or with at least one of the embodiments described above, respectively, alone or in any combination with each other.

[0161] The principles described in accordance with these embodiments can be used, for example, for methods of interprocess communication A1, A2, which are not only high-performance but also suitable for use in mixed ASIL systems. Advantageously, for the principles described in accordance with these embodiments, for example, a 64-bit compare-and-swap operation of a computing device or the computing device 12, 202 can be used.

[0162] The use of shared memory, such as RAM 204a, provides speed advantages, and the control of process access rights to one or more corresponding queues WS-1, WS-2 increases security during communication or data exchange between processes P-1, P-2.

[0163] In other exemplary embodiments, the variables associated with the at least one queue WS-1, WS-2 and / or their (optional) comparison values ​​are accessed, for example atomically and / or lock-free: for example, atomically, in order to ensure a consistent state, for example, lock-free, in order to prevent the possibility of corruption of the locked variables, and thus, for example, to ensure consistent reading and writing of the variables by hardware mechanisms. In other exemplary embodiments, for this purpose, it is useful to use a 64-bit compare-and-swap operation, which is available, for example, on the computing device 12, 202, as already mentioned above.

[0164] In other exemplary embodiments, for example, in the payload (payload) (effective data, for example, see Fig.10 In the case of the reference numeral data), no atomic access is provided; in a write operation, the data is written, for example, piece by piece, together with the standard value (i.e. its actual value) and as a comparison value VERGL-WERT, for example, the corresponding reciprocal, into the shared memory 14-1, and in a read operation, for example, it is read out of the shared memory 14-1 piece by piece, for example, compared and copied, for example, to the protected memory pAS-a, pAS-b ( Fig. 9 )middle.

[0165] In other exemplary embodiments, the comparison value is, for example, the reciprocal of the original value (e.g. obtainable by bitwise inversion). Alternatively, in other exemplary embodiments, for example, an XOR operation, for example with a user-defined value, or, for example, in the case of larger data such as a payload, a CRC value is conceivable.

[0166] In other exemplary embodiments, for example for the rare case where a memory corruption indicates an assumed correct value, a cross comparison can be performed, for example with the aid of the sequence number seq of the payload element data: In other exemplary embodiments, the head (Head) and the tail (Tail) are not stored modulo, for example, but are only incremented, for example. In other exemplary embodiments, the complete value of the header variable is entered into the sequence number when writing, and in other exemplary embodiments, it can be checked when reading whether the sequence number matches the value of the tail variable. In other exemplary embodiments, if the header variable should have been assumed to be correctly overwritten during operation, an incorrect sequence number can lead to this error being recognized during the read operation.

[0167] In other exemplary embodiments, error recognition can be performed in two ways, for example: the first way is, for example, to perform a plausibility check on the sequence number in relation to two paths, for example, legal paths. In the case of an element that has been read, it is the number of the last iteration, i.e. "Tail-N" in the case of N FIFO elements, or in the case of a new readable element, it is the tail value. In other exemplary embodiments, any other value would be an error condition.

[0168] In other exemplary embodiments, the second way combines a simple comparison of the sequence number with the tail value during a read operation and a cyclic functional test between the two FIFOs FIFO-1, FIFO-2 for the communication of the communication partners. In other exemplary embodiments, the cyclic functional test, for example, comprises sending "ping-pong" messages at regular intervals. In other exemplary embodiments, in the case of an invalid sequence number, no more read operations are performed in one of the two FIFOs, so that the cyclic functional test fails due to a stop in communication in one direction.

[0169] In both described error recognition approaches according to other exemplary embodiments, there may be a certain delay between the occurrence of an error and its detection: For the first approach, the error is detected only when the reader reaches the first element with an invalid sequence number, for example. Depending on the position of the shifted header index, this may mean up to N-1 subsequent write operations.

[0170] For the second approach described in accordance with other exemplary embodiments, the detection is performed with a waiting time of the selected frequency of, for example, a cyclic functional test. If this is not fast enough, for example not fast enough in certain target systems, in other exemplary embodiments, for example, a higher-level mechanism can be used to further improve the error detection: a counter that is incremented during a write operation and decremented during a read operation shows how many new elements are in the FIFO. In a multi-producer scenario described in accordance with other exemplary embodiments, locks can then be used, for example, to serialize the write operations, for example in a dedicated address area of ​​the write process, for example in order to avoid false positives in the plausibility check logic.

Claims

1. A method, such as a computer-implemented method, for processing data associated with a computing device (12), the method comprising: At least one first queue (WS-1, WS-2) is provided (100) in a first storage area (14-1), and a first process (P-1) associated with the computing device (12) and a second process (P-2) associated with the computing device (12) can access, for example exclusively access, the first storage area.

2. The method according to claim 1, comprising: Using (102) the at least one first queue (WS-1, WS-2) for data exchange (A1, A2) between the first process (P-1) and the second process (P-2), wherein: For example, the use (102) has at least one of the following elements: a) sending (102a) data, for example in the form of at least one first message, from said first process (P-1) to said second process (P-2); b) sending (102b) data, for example in the form of at least one second message, from said second process (P-2) to said first process (P-1).

3. The method according to at least one of the preceding claims, comprising: Prevent (105): For example, in addition to the first process (P-1) and the second process (P-2), other processes (P-3) associated with the computing device (12) access the first storage area (14-1), for example, access the at least one first queue (WS-1).

4. The method according to at least one of the preceding claims, comprising: Access rights (ZR-1) to the first memory area (14-1) and / or to the at least one first queue (WS-1) are allocated (106), for example exclusively allocated, to the first process (P-1) and the second process (P-2).

5. The method according to at least one of the preceding claims, comprising: A rationality check (104) is performed on at least one component of the at least one first queue (WS-1, WS-2).

6. The method according to at least one of the preceding claims, The method has at least one of the following elements: a) using (110) at least one FIFO memory (FIFO; FIFO-1, FIFO-2) for at least one queue (WS-1, WS-2), wherein: For example, the at least one FIFO memory (FIFO; FIFO-1, FIFO-2) has a first state variable (ZV-1), for example a tail variable, which characterizes a read position, wherein, for example, the at least one FIFO memory (FIFO; FIFO-1, FIFO-2) has a second state variable (ZV-2), for example a head variable, which characterizes a write position, wherein, for example, the elements (FIFO-EL-1, FIFO-EL-2, ...) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2) respectively have a sequence number (SN-EL-1, SEN-EL-2, ...) and valid data (ND-EL-1, ND-EL-2, ...); b) specifying (111) the size (FIFO-GR) of the FIFO memory or of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), for example specifying (111a) the number of elements (FIFO-EL-1, FIFO-EL-2, ...); c) statically allocating (112) a plurality or said number (FIFO-EL-ANZ) of elements (FIFO-EL-1, FIFO-EL-2, . . . ); d) using (113) index variables (ZV-1-IDX, ZV-2-IDX) for the at least one state variable (ZV-1, ZV-2); e) not using (114) a pointer variable (POINT) for the at least one state variable (ZV-1, ZV-2); f) using (115) a modulo operator MOD-OP (MOD-OP), for example a statically encoded modulo operator, for accessing elements (FIFO-EL-1, FIFO-EL-2, ...) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), wherein, for example, the modulo operator is associated with the number (FIFO-EL-ANZ) of elements (FIFO-EL-1, FIFO-EL-2, ...) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), in particular without using (115a) a variable for accessing the elements (FIFO-EL-1, FIFO-EL-2, ...) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2); g) storing (116) at least one component of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), for example a size (FIFO-GR) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), by means of a variable (V-FIFO-GR) associated with a dedicated memory area (14-PR-1) of at least one process (P-1, P-2), for example a high ASIL process (P-1); h) modifying (118) at least one component of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), for example the size (FIFO-GR) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), for example during the runtime of the at least one process (P-1, P-2), for example reducing (117a) the size (FIFO-GR) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2) during the runtime of the at least one process (P-1, P-2).

7. The method according to at least one of the preceding claims, The method has at least one of the following elements: a) storing (120) components of the at least one queue (WS-1, WS-2), for example the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), together with a comparison value (VERGL-WERT); b) performing a plausibility check (121) on at least one component of the at least one queue (WS-1, WS-2), for example the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), based on the comparison value or the comparison value (VERGL-WERT); c) performing (122) a rationality check or the rationality check (121) when at least some read accesses, for example all read accesses, are performed on the at least one component of the at least one queue (WS-1, WS-2); d) initiating (123) an error response (FR), for example propagating the detected error, for example based on the plausibility check or the plausibility check (121), wherein For example, the error response (FR) has at least one of the following elements: d1) initializing, for example, reinitializing, the at least one first queue (WS-1, WS-2), d2) resending the message, for example, in the case of defective valid data, d3) restarting at least one process (P-1, P-2); e) atomically performing (124) access to at least one component of the at least one queue (WS-1, WS-2), for example the at least one FIFO memory (FIFO; FIFO-1, FIFO-2); f) performing (125) lock-free access to at least one component of the at least one queue (WS-1, WS-2), for example the at least one FIFO memory (FIFO; FIFO-1, FIFO-2).

8. The method according to at least one of the preceding claims, The method has at least one of the following elements: a) determining (130) at least one comparison value (VERGL-WERT) of at least one component of said at least one queue (WS-1, WS-2), for example of said at least one FIFO memory (FIFO; FIFO-1, FIFO-2); and optionally storing (132) said at least one component of said at least one queue (WS-1, WS-2), for example of said at least one FIFO memory (FIFO; FIFO-1, FIFO-2) together with said comparison value (VERGL-WERT).

9. The method according to claim 8, in, The determination (130) of the at least one comparison value (VERGL-WERT) comprises at least one of the following elements: a) forming (130a) a value opposite to the value of the at least one component of the at least one queue (WS-1, WS-2), for example by means of inversion; b) performing (130b) a logical operation, such as an XOR operation, using the value of the at least one component of the at least one queue (WS-1, WS-2); c) forming ( 130c ) a checksum, for example a checksum of the CRC type, for example when the amount or size of data associated with the at least one component exceeds a predefinable threshold value.

10. The method according to at least one of claims 6 to 9, The method has at least one of the following elements: a) incrementing (140) the at least one state variable (ZV-1, ZV-2); b) assigning (141) the value of the second state variable (ZV-2) to a sequence number or to the sequence numbers (SN-EL-1, SEN-EL-2, . . . ), for example when writing into the at least one queue (WS-1, WS-2); c) comparing (143) said sequence number (SN-EL-1, SEN-EL-2, . . . ) with the value of said first state variable (ZV-1), for example when reading from said at least one queue (WS-1, WS-2); d) Based on said comparison (143), for example, if necessary, initiating (144) an error response (FR').

11. A device (10; 200) for performing a method according to at least one of the preceding claims.

12. A product, such as a motor vehicle (1000), comprising at least one device (10; 200) according to claim 11.

13. A computer-readable storage medium (SM) comprising instructions (PRG) which, when executed by a computer (202), cause the computer to implement the method according to at least one of claims 1 to 10.

14. A computer program (PRG) comprising instructions which, when executed by a computer (202), cause the computer to carry out the method according to at least one of claims 1 to 10.

15. A data carrier signal (DCS) transmitting and / or representing a computer program (PRG) according to claim 14.

16. Use (300) of the method according to at least one of claims 1 to 10 and / or the device (10; 200) according to claim 11 and / or the product (1000) according to claim 12 and / or the computer-readable storage medium (SM) according to claim 13 and / or the computer program (PRG) according to claim 14 and / or the data carrier signal (DCS) according to claim 15 for at least one of the following elements: a) processing (301) data associated with at least one process (P1, P2) of a computing device (12); b) selectively granting (302) access to the at least one queue (WS-1, WS-2) for a specifiable set of processes (P1, P2) associated with the computing device (12); c) ensuring (303) that communications between a specifiable set of processes (P1, P2) associated with the computing device (12) are free from interference, e.g., free from interference, e.g., with respect to interference caused by other processes (P3) also associated with the computing device (12); d) excluding (304), for example conceptually excluding, out-of-bounds access, for example, out-of-bounds access to components of the at least one queue (WS-1, WS-2); e) identifying (305) a memory overwrite, such as an unwanted memory overwrite, such as with respect to a memory area (14-1) associated with the at least one queue (WS-1, WS-2); f) using (306) the shared memory area (14-1) to implement inter-process communication, e.g. non-intrusive, e.g. efficient, e.g. independent of the operating system; g) implementation (307) of the method and / or use of a device (10; 200) for carrying out the method in safety-related applications, for example in mixed ASIL systems; h) restricting (308) access rights of the processes (P-1, P-2, P-3) to the at least one queue (WS-1).

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