Back gate effect control via doping

Abstract

Methods and structures are presented for mitigating back gate effects in a radio frequency (RF) silicon-on-insulator (SOI) substrate RF-SOI. According to one aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI underlying a first circuit / device to be protected. The first implant or junction is contained entirely within the TRL. The planar surface region of the first implant and / or junction completely contains a projection of the planar surface region of the first circuit and / or device. The first implant or junction is biased via a through-BOX contact (TBC) that penetrates the BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in the region of the TRL underneath the second circuit / device. The first implant or junction and the second implant or junction are disconnected and separated by an undoped region of the TRL.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 336,920 filed on April 29, 2022 for “BACK-GATE EFFECT CONTROL VIADOPING,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to semiconductor technology, and more particularly to methods and structures for back-gate mitigation in radio frequency (RF) silicon-on-insulator (SOI) substrates via implantation of dopants. Background Art

[0004] FIG. 1A shows a cross-sectional view of an SOI substrate (100A) including a bulk (silicon) substrate (150) on which a thin layer of silicon (Si, 110, also referred to as an SOI layer) is formed covering an insulating BOX layer (120, e.g., SiO2). Circuits (also referred to as SOI circuits) including devices (e.g., SOI transistors) can be formed in and above the thin layer of silicon (110) by methods and techniques known in the art. For example, FIG. 1A shows two circuits (105a, 110a) and (105b, 110b) formed in and above respective thin silicon regions (110a) and (110b) of the thin layer of silicon (110), such regions being isolated from each other and from other circuits via one or more shallow trench isolation (STI) regions (e.g., 115a, 115b, 115c). In some cases, the circuits (105a, 110a) and / or (105b, 110b) may include RF devices (e.g., transistors) whose performance may be affected by parasitic surface conduction (PSC) effects at the interface between the BOX layer (120) and the bulk substrate (150), which are known in the art due to the capacitor-like configuration created by the SOI stack. As known to those skilled in the art, PSC may be due to fixed positive charges within the BOX layer (120) near the interface with the bulk substrate (150) attracting free (charge) carriers and thereby reducing the effective resistivity of the bulk substrate (150) and causing increased losses and nonlinearity. As shown in the cross-sectional view of the SOI substrate (100B) (also referred to as the RF-SOI substrate) of FIG1B , a trap-rich layer (130) is provided between the BOX layer and the bulk substrate (150). Due to the presence of the trap-rich layer (130) and the high resistivity (HR-Si) bulk substrate (150), the PSC effect can be reduced and the performance of the RF device can be increased. As known to those skilled in the art, the presence of the trap-rich layer (130) can produce a trap-rich effect, which includes trapping free charges (e.g., electrons, carriers) under the BOX layer (120), thereby preventing the flow of current that may generate undesirable coupling between signals to / between RF devices formed in the silicon thin layer (110).

[0005] In some cases, one or more of the two circuits (105a, 110a) or (105b, 110b) shown in FIG. 1B may operate at high voltages and / or include switching devices / transistors that may be used to turn on and off relatively high voltages at different time periods (e.g., asynchronously). Such high voltages may induce electric fields in the BOX layer (120) and the trap-rich layer (130) of FIG. 1B, which may be (e.g., capacitively) coupled to the bulk substrate (150). Thus, and as known to those skilled in the art, the bulk substrate (150) may effectively operate as a parasitic gate electrode (commonly referred to as a "back gate"), which may affect the overall performance of the devices / transistors of the circuits (105, 110a) and / or (105b, 110b). As known to those skilled in the art, the effects of such back gates may include, for example, effects on the leakage current of transistors formed in the thin layer of silicon (110), shifts in the threshold voltage of the transistors, and / or so-called "back channels" that turn on or off the transistors.

[0006] Methods and structures for mitigating / reducing back-gate effects in circuits and / or devices formed on an RF-SOI substrate similar to the RF-SOI substrate ( 100B) of FIG. 1B are described in accordance with the teachings of the present disclosure. Summary of the invention

[0007] According to a first aspect of the present disclosure, a silicon-on-insulator (SOI) structure is proposed, comprising: an RF-SOI substrate, the RF-SOI substrate comprising: a high-resistivity silicon (HR-Si) substrate; a trap-rich layer covering the HR-Si substrate; a buried oxide (BOX) layer covering the trap-rich layer; and a thin silicon layer covering the BOX layer; a first circuit formed in a first silicon region of the thin silicon layer; and a first implantation in a region of the trap-rich layer directly below the first circuit, wherein the first implantation is configured to be biased with a first voltage based on an operating state of the first circuit.

[0008] According to a second aspect, a method for reducing a back-gate effect in a silicon-on-insulator (SOI) circuit is proposed, the method comprising: doping a region of a trap-rich layer directly below the SOI circuit; based on the doping, reducing the resistivity of the region, thereby increasing a charge transfer rate in the region; and biasing the region with a voltage based on an operating state of the SOI circuit, thereby reducing the back-gate effect in the SOI circuit, wherein the SOI circuit is formed on an RF-SOI substrate, the RF-SOI substrate comprising: a high resistivity silicon (HR-Si) substrate; a trap-rich layer covering the HR-Si substrate; a buried oxide (BOX) layer covering the trap-rich layer; and a thin silicon layer covering the BOX layer.

[0009] Other aspects of the disclosure are provided in the description, drawings and claims of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of the example embodiments, serve to explain the principles and implementations of the present disclosure.

[0011] FIG. 1A shows a cross-sectional view of two circuits formed on a prior art silicon-on-insulator (SOI) substrate.

[0012] 1B shows a cross-sectional view of two circuits formed on a prior art radio frequency (RF) SOI (RF-SOI) substrate including a high resistivity substrate and a trap-rich layer.

[0013] Figure 2A A cross-sectional view of two circuits formed on an RF-SOI substrate including implants formed in regions of a trap rich layer according to an embodiment of the present disclosure is shown.

[0014] Figure 2B A cross-sectional view of two circuits formed on an RF-SOI substrate including two implants formed in separate regions of a trap rich layer is shown in accordance with an embodiment of the present disclosure.

[0015] Figure 2C Shows Figure 2B Top plan view of the two circuits.

[0016] Figure 3A A cross-sectional view of two circuits formed on an RF-SOI substrate including two junctions formed in a separated region of a trap-rich layer according to an embodiment of the present disclosure is shown.

[0017] Figure 3B Shows Figure 3A The equivalent circuit of the two junction regions.

[0018] Figure 4 is a flow chart illustrating various steps of a method for reducing back-gate effects in silicon-on-insulator (SOI) circuits according to the present disclosure.

[0019] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0020] The teachings of the present disclosure enable the back gate effect generated in the substrate (100B) of FIG. 1B to be mitigated by forming an implantation region and / or a junction region in the region of the trap-rich layer (130) directly below the circuit (105a, 110a) and / or (105b, 110b). In other words, the implantation region and / or the junction region according to the present disclosure can be formed by performing n-type and / or p-type doping on the region of the trap-rich layer (130) directly below the circuit (105a, 110a) and / or (105b, 110b).

[0021] The corresponding injection regions and / or junction regions according to the present disclosure may be completely contained / enclosed within the trap-rich layer (130). The corresponding injection regions and / or junction regions according to the present disclosure may be separated (laterally) by undoped regions of the trap-rich layer (130). Such undoped regions of the trap-rich layer (130) may help increase electrical isolation between the corresponding injection regions and / or junction regions due to the inherent property of the trap-rich layer (130) to prevent (e.g., significantly reduce) electron / carrier mobility (e.g., via sufficiently high trap density). The corresponding injection regions and / or junction regions according to the present disclosure may be separated from the HR-Si bulk substrate (150) by the undoped regions of the trap-rich layer (130).

[0022] According to the present disclosure, the junction region may include an n+ / p-type junction or a p+ / n-type junction. Other embodiments and use cases may include any combination of lightly doped and / or heavily doped first type implants and opposite type implants that can form a junction interface. The type of junction may be based on the type of circuit and / or device for preventing back gate effects (e.g., the polarity of a device such as, for example, an N-MOS or P-MOS transistor), and / or based on the polarity of a (high) voltage applied to the circuit and / or device (e.g., positive or negative relative to a reference potential). According to an embodiment of the present disclosure, the junction region includes an interface between two implant regions of opposite polarity (n-type and p-type). According to an embodiment of the present disclosure, one of the two implant regions is formed in a well provided by the other implant region. In other words, one of the two implant regions is targeted at a first depth range close to the BOX layer (120) into the trap-rich layer (130), and the other implant region is targeted at a second depth range deeper than the first depth range (and therefore away from the BOX layer 120). Therefore, the second implant region surrounds the first implant region at least within the trap rich layer (130).

[0023] According to an embodiment of the present disclosure, the injection region and / or the junction region can be biased independently of each other to control the potential at the region of the trap-rich layer (130) directly below the circuit. The biasing of the injection region and / or the junction region according to the present disclosure can be provided by one or more corresponding through BOX contacts (TBCs), which resistively couple the corresponding bias signal / voltage to the corresponding injection region and / or the junction region through the BOX contacts (TBCs). Such independent biasing can make it possible to improve the performance of the corresponding circuit / device by removing / reducing the corresponding back-gate effect. Improving performance can include, for example, improving the on-state conduction performance of the device in the first circuit while improving / reducing the off-state current leakage of the device in the second circuit.

[0024] The teachings according to the present disclosure may be applicable to any RF-SOI substrate comprising a stacked layer (110, 120, 130, 150 of FIG. 1B ), wherein the bulk substrate (150) is a high resistivity substrate (HR-Si) having a resistivity higher than / greater than 200 Ohm.cm (e.g., a typical resistivity value of 1000 Ohm.cm). The teachings according to the present disclosure may also be applicable to a deposited or implanted trap-rich layer (130). The deposited trap-rich layer (130) may include, for example, a polycrystalline material layer, such as, for example, polysilicon, which may provide a sufficiently high trap (area) density. The implanted trap-rich layer (130) may include, for example, a layer formed in a bulk substrate (150) or a prefabricated SOI substrate (e.g., 100A of FIG. 1A , where 150 is HR-Si) by implanting (trap) species (e.g., carbon, germanium, fluorine, xenon, neon) that penetrate the layered (crystalline) structure of the bulk substrate (150) or prefabricated SOI substrate, which may also provide a sufficiently high trap density. The goal of such an implantation is to create a sufficiently damaged layer or an amorphous layer (e.g., without a crystalline structure) in the silicon directly below the BOX layer (e.g., 120 of FIG. 1B ) that contains a sufficiently high trap density.

[0025] As used herein, a trap-rich layer (e.g., 130) may be characterized by its "trap density" or the areal density of traps, which is measured in atoms per square centimeter (at / cm 2 The trap-rich layer according to the present disclosure has a value greater than 1×E8 at / cm 2 (i.e., 10 8 at / cm 2 As known to those skilled in the art, a typical prior art trap-rich layer may have a trap density as high as about 1×E11 at / cm 2 The trap density is therefore greater than 1×E8 at / cm 2The trap density is high enough to enable the trap-rich layer (e.g., 130 of FIG. 1B ) to capture the above-mentioned free charges (e.g., electrons, carriers), and thus reduce / eliminate the PSC effect below the BOX layer (120). In other words, the traps in the trap-rich layer can cause the free carrier charges in the substrate to no longer flow to generate current, just as the free carrier charges would in the absence of traps.

[0026] It should be noted that although single crystal (e.g., Si) bulk substrates such as, for example, the HR-Si bulk substrate (150) of FIG. 1B may have intrinsic defects / impurities that may be likened to traps, the areal density of such defects may be less than 1×E8 at / cm2 of the trap-rich layer / region / material. 2 The specified trap density is several orders of magnitude smaller than that of . In order to maintain its desired semiconductor properties, bulk substrates including HR-Si bulk substrates (e.g., 150 of FIG. 1B ) must allow carrier charge flow. Thus, a typical (intrinsic) defect / impurity in such a substrate may have a density of about 1×E6 at / cm 2 or less, or in other words, at least two orders of magnitude less than the areal density of the trap-rich layer (e.g., 130 of FIG. 1B ). Thus, although the HR-Si bulk substrate (150) and the trap-rich layer (130) of FIG. 1B may have similar resistivities (e.g., greater than 200 Ohm.cm), they may be clearly distinguished, for example, by their respective trap densities.

[0027] Figure 2A A cross-sectional view of two circuits (105a, 110a) and (105b, 110b) formed on an RF-SOI substrate (100B) according to an embodiment of the present disclosure is shown, the RF-SOI substrate (100B) including an implantation region (210a) formed in a trap-rich layer (130). In addition, as Figure 2A As shown, the BOX contact (215a, TBC) can be used to provide (e.g., resistively couple) a bias signal / voltage to the implant region (210a). Those skilled in the art will clearly recognize that Figure 2A The configuration described above with reference to FIG. 1B with added implant regions (210a) and TBCs (215a) is shown in accordance with the present teachings. In addition, those skilled in the art will clearly be familiar with methods and techniques related to the fabrication / formation of implant regions (210a) (e.g., doping) and TBCs (215a) (e.g., stacked metal vias through BOX layers), which are outside the scope of the present disclosure.

[0028] Continue to refer to Figure 2AAccording to an embodiment of the present disclosure, the implanted region (210a) may be of n+ type or may be of p+ type. According to some exemplary embodiments of the present disclosure, the type of implantation may be based on the voltage of the circuit (105a, 110a) and / or the polarity of the target transistor (to be protected). In some embodiments, the biasing of the implanted region (210a) via a bias voltage applied by the TBC (215a) may be intended to reduce the difference between the voltage in the silicon region (110a) of the circuit (105a, 110a) and the voltage at the (doped) region of the trap-rich layer (130) directly below the circuit (105a, 110a). In other words, the bias voltage applied by the TBC (215a) may not be static, but may vary with the operating state (e.g., voltage) of the circuit (105a, 110a), which is characterized, for example, by the voltage of the circuit. Other embodiments may include n-type or p-type or even n-type or p-type dopants for the implanted region (210a).

[0029] Further references Figure 2A According to an embodiment of the present disclosure, the doping region of the trap-rich layer (130) forming the implantation region (210a) may be selected to be in a plane (perpendicular to Figure 2A The plane includes the entire projection of the circuit (105a, 110a) on the plane. In other words, according to an embodiment of the present disclosure, the doped region of the trap-rich layer (130) forming the implantation region (210a) has a surface covering the entire footprint of the circuit (105a, 110a) thereon. Figure 2C Provide further description / clarification on this.

[0030] like Figure 2A As shown, according to an embodiment of the present disclosure, the TBC (215a) can penetrate the BOX layer (120) through the STI region (115a), which defines the boundary of the thin silicon region (110a) of the circuit (105a, 110a). As known to those skilled in the art, different circuits on a substrate (e.g., circuits (105a, 110a) and (105b, 110b) formed on the RF-SOI substrate (100B)) can be isolated from each other via STI regions (e.g., 115a, 115b, 115c). For example, Figure 2A As shown, the STI region (115c) isolates the thin silicon region (110a) of the circuit (105a, 110a) from the thin silicon region (110b) of the circuit (105b, 110b). In addition, the STI regions (115a) and (115b) can respectively isolate the thin silicon regions (110a) and (110b) from the thin silicon regions (110a) and (110b) that can be formed on the RF-SOI substrate (100B) (not shown). Figure 2A ) other circuits shown in FIG. Thus, each of the circuits (105a, 110a) and (105b, 110b) can be considered to be isolated from the surrounding circuits via the walls of the STI regions, which can effectively form an isolation island of the thin silicon region (e.g., 110a, 110b, etc.). Therefore, the TBC (215a) can pass through any of the STI regions surrounding the thin silicon region (110a), including, for example, the STI region (115c) to reach the implant region (210a) and make (resistive) contact with the implant region (210a). Therefore, as Figure 2A As shown, the lateral extension of the implanted region (210a) can reach a region of the trap-rich layer (130) disposed below the STI region (e.g., 115a, 155c) that defines an isolation island of the thin silicon region (110a) of the circuit (105a, 110a). It should be noted that in some embodiments, any one or more of the STI regions (115a, 115b, 115c) can pass through the BOX layer (120) to contact the trap-rich layer (130), or further penetrate the trap-rich layer (130). In the case where the STI region (115c) can pass through the trap-rich layer (130) and through the depth of the implanted region (210a, 210b), increased isolation between subsequent implanted regions can be provided.

[0031] Continue to refer to Figure 2A According to the present teachings, doping a region (e.g., 210a) of the trap-rich layer (130) may change the local electrical properties / semiconductor properties of the region. Specifically, when compared to an undoped region of the trap-rich layer (130), doping the region (210a) may not affect the carrier mobility of the region, but rather, doping may increase the carrier density of the region (210a) and thereby reduce the resistivity of the region (e.g., to less than 200 Ohm.cm). Since the charge transfer performance (e.g., charge transfer rate) of a region (e.g., 210a) may be a function of its carrier mobility and its carrier density (and the applied bias), the increased carrier density of the doped region (210a) and thus the reduced resistivity of the doped region (210a) may increase the charge transfer performance / rate of the region. Therefore, for a bias voltage applied via the TBC (215a), the doped region (210a) may be charged to a corresponding bias potential.

[0032] Such charging of the doped region (215a) may be performed at a sufficiently fast rate (e.g., in milliseconds, 10 -3s) is performed to mitigate / reduce the above-mentioned back-gate effect. In addition, since the doped region (210a) is local to the trap-rich layer (130), as shown in FIG. 1B , the doped region (210a) is bounded by an undoped trap-rich region having very poor charge transfer performance (and a high resistivity greater than 200 Ohm.cm), and thus the leakage / circulation of mobile charge / current from the doped region (210a) to the region of the trap-rich layer (130) below the circuit (105b, 110b) can be controlled (e.g., reduced). Therefore, mitigating the back-gate effect in the circuit (105a, 110a) by applying a bias signal / voltage to the doped region (210a) of the trap-rich layer (130) may not affect the operation of the circuit (105b, 110b).

[0033] Figure 2B A cross-sectional view of two circuits (105a, 110a) and (105b, 110b) formed on an RF-SOI substrate (100B) according to an embodiment of the present disclosure is shown, the RF-SOI substrate including two implanted regions (210a) and (210b) formed in a trap-rich layer (130). In addition, as Figure 2B As shown, BOX contacts (215a) and (215b) can be used to provide (e.g., resistively couple) corresponding bias signals / voltages to implant regions (210a) and (210b). Those skilled in the art will clearly recognize that Figure 2B The above reference Figure 2A The configuration described has an added implant region (210b) and a TBC (215b, which penetrates the BOX layer 120 through the STI region 115b) for alleviating / reducing the back gate effect in the circuit (105b, 110b). Therefore, the above description of the element (210a, 215a) for alleviating / reducing the back gate effect of the circuit (105a, 110a) can also be applied to the element (210b, 215b) for alleviating / reducing the back gate effect of the circuit (105b, 110b).

[0034] Continue to refer to Figure 2B, because the two injection regions (210a, 210b) are separated by the undoped region of the trap-rich layer (130), they can be charged / discharged independently without affecting each other. In other words, as described above, because the two doped regions (210a, 210b) are not connected, the undoped region of the trap-rich layer (130) (e.g., in the lateral direction) that inherently has very poor charge transfer performance (and a high resistivity of more than 200 Ohm.cm) between the two doped regions (210a, 210b) can prevent the leakage of mobile charge / current from the doped region (210a) to the doped region (210b), and vice versa. Therefore, mitigating the back gate effect of either circuit (105a, 110a) or (105b, 110b) may not affect the operation of the other circuit.

[0035] Figure 2C The above reference Figure 2B A top plan view of two circuits (105a, 110a) and (105b, 110b) is shown. Figure 2C As shown, the main plane surface / region (shown in dashed lines) of each doped region in doped regions (210a) or (210b) completely contains / covers / encompasses (projections of) the main plane surface / region of the corresponding circuit (105a, 110a) or (105b, 110b). In addition, as Figure 2C As shown, each TBC in TBC (215a) or (215b) is connected to a corresponding STI region (eg, Figure 2C 115a or 115b (not shown) is spaced / isolated from the corresponding circuit (105a, 110a) or (105b, 110b) and (resistively) contacts the corresponding doped region (210a) or (210b). Therefore, as described above, the two doped regions (210a) and (210b) can be independently charged via a bias signal / voltage applied to the corresponding TBC (215a) and (215b). For example, during an on-state of the circuit (105a, 110a) including a high voltage at the circuit, a corresponding high voltage can be applied to the TBC (215a) to correspondingly charge the doped region (210a) below the circuit (105a, 110a) to a high potential to protect the circuit from a back gate effect. At the same time, the circuit (105b, 110b) can operate according to an off state including a low voltage at the circuit, and therefore a corresponding low voltage can be applied to the TBC (215b) to correspondingly charge the doped region (210b) below the circuit (105b, 110b) to a low potential to protect the circuit from the back gate effect independently of the protection of the circuit (105a, 110a).

[0036] Figure 3AA cross-sectional view of two circuits (105a, 110a) and (105b, 110b) formed on an RF-SOI substrate (100B) including two junction regions (210a, 310a) and (210b, 310b) formed in a trap-rich layer (130) is shown according to an embodiment of the present disclosure. Those skilled in the art will recognize that Figure 3A The embodiment shown in FIG. 1 is based on the above reference to, for example, Figure 2B An embodiment is described in which, instead of doping a local region of a trap-rich layer (130) beneath each of the circuits (105a, 110a) and (105b, 110b) with a single dopant (e.g., n+ type or p+ type), two types of dopants are used to form the corresponding local junction regions (210a, 310a) and (210b, 310b). For example, referring to the junction region (210a, 310a), it may include Figure 2A or Figure 2B A top doped region (210a) and a bottom and adjacent doped region (310a) similar to the doped region (210a) of the trap-rich layer (130), wherein both the doped regions (210a) and (310a) can be doped regions of the trap-rich layer (130) and are therefore completely covered within the trap-rich layer (130).

[0037] Specifically, Figure 3A As shown, the top doped region (310a) can be formed in a well provided by the bottom doped region (310a), for example to form an interface region of the junction (210a, 310a). In other words, the lateral extension of the bottom doped region (310a) completely encompasses the lateral extension of the top doped region (210a). Therefore, as Figure 3A As shown, the top doped region (210a) is laterally bounded by the bottom doped region (310a). Therefore, the naming convention used herein (including top and bottom when applied to doped regions (210a, 310a)) should not be interpreted as not including such lateral bounding / encirclement of doped region (210a) by doped region (310a), but rather as including such lateral bounding / encirclement of doped region (210a) by doped region (310a). Figure 3A The main transverse extension / plane is arranged at the top or bottom. Figure 3A As shown, the bottom doped region (310a) can be separated from the HR-Si bulk substrate (150) by the undoped region of the trap-rich layer (130). In other words, the junction region (210a, 310a) is completely contained within the trap-rich layer (130).

[0038] Reference above Figure 3A The same description of the junction region (210a, 310a) can be applied to Figure 3A In addition, as Figure 3A As shown, the two junction regions (210a, 310a) and (210b, 310b) may be unconnected, or in other words, separated by an undoped region of the trap-rich layer (130), which has the same characteristics as described above with reference to Figure 2B The benefits of separation of the doped regions (210a) and (210b) are similar to the benefits described above.

[0039] According to an exemplary embodiment of the present disclosure, the junction regions (210a, 310a) and (210b, 310b) may each be formed by doping adjacent local regions of the trap-rich layer (130) with dopants of opposite polarity / type and / or different doping levels. For example, according to an embodiment of the present disclosure, the doped region (210a) or (210b) may be n+ type (heavily doped region), while the doped region (310a) or (310b) may be p- type (lightly doped region). According to another exemplary embodiment of the present disclosure, the doped region (210a) or (210b) may be p+ type (heavily doped region), while the doped region (310a) or (310b) may be n- type (lightly doped region). Other combinations of types and / or doping levels of the two doped regions forming each of the junction regions (210a, 310a) or (210b, 310b) are possible depending on design goals and performance.

[0040] Figure 3B Shows the formation of Figure 3A The area marked as (300A) Figure 3A The equivalent circuit (D 10a , R 130 , D 10b ). Specifically, in Figure 3B The equivalent circuit shown in is an exemplary case where each of the two doping regions (210a) and (210b) is n+ type and each of the two doping regions (310a) and (310b) is p- type. Therefore, Figure 3B As shown, the corresponding interfaces at the corresponding junction regions (210a, 310a) and (210b, 310b) form corresponding (back-to-back) diodes D 10a and D 10b , diode D 10a and D 10b is reversed, and the equivalent resistance R of the undoped region of the trap-rich layer (130) 130 Coupled to each other, the undoped region separates the junction region (210a, 310a) from the junction region (210b, 310b).

[0041] Figure 3B The equivalent circuit (D 10a , R 130 , D 10b ) clearly shows the effect of the junction regions (210a, 310a) and (210b, 310b) in preventing leakage of current between the two (heavy) doped regions (210a) and (210b). At a first level, the current can be connected to the junction region (210a, 310a) via a (high) resistor R 130 With reference to the above, for example Figure 2A or Figure 2B The leakage of current from any of the two doped regions (210a) and / or (210b) can be prevented / reduced in a similar manner as described above. At the second level, the current can be reversed via a (back-to-back) reverse diode D formed by the two junctions (210a, 310a) and (210b, 310b). 10a and D 10b To further prevent / reduce leakage of current from any one of the two doped regions (210a) and / or (210b). Figure 3A The implementation method is relative to Figure 2B The advantages of the embodiments can be due to two levels of leakage prevention / reduction, when used with Figure 2B When compared with the configuration of , a higher isolation efficiency between the two regions (210a) and (210b) can be provided. As a result of such an improvement in isolation efficiency, for a given isolation efficiency between the two doped regions (210a) and (210b), Figure 3A The configuration may be able to have a ratio Figure 2B The configuration requires operation of a trap-rich layer (130) with low isolation efficiency (eg, lower resistivity and / or lower trap density and thus lower grade / cost).

[0042] Biasing of the junction regions (210a, 310a) and / or (210b, 310b) may include biasing according to the above references, for example Figure 2A or Figure 2B The described device (e.g., TBC 215a and / or 215b) biases the doped regions (210a) and / or (210b). Further flexibility in controlling the isolation between the two doped regions (210a) and (210b) can be provided by further biasing the two doped regions (310a) and / or (310b). Figure 3C, a non-limiting exemplary embodiment for biasing a doped region (310b) via a TBC (315b) that can also penetrate the BOX layer (120) at the STI region (115b) according to the present disclosure is shown. It should be noted that the TBC (315b) can penetrate the BOX layer (120) at different STI regions (e.g., at the STI region (115c) or other regions). The biasing of the two doped regions (210b) and (310b) of the junction (210b, 310b) can be achieved by forming an equivalent diode (e.g., Figure 3B D 10b ) terminals (anode and cathode) are properly biased to achieve better isolation. Figure 3A The doped region (310a) provides an equivalent biasing device.

[0043] It should be noted that any of the above-described doped regions and / or junction regions for mitigating / reducing back-gate effects while providing leakage isolation for (SOI) circuits formed / fabricated on an RF-SOI substrate may coexist on the same RF-SOI substrate. In other words, not all circuits formed / fabricated on an RF-SOI substrate may be protected for back-gate effects according to the present teachings, and / or one or more of such circuits may be protected by different protection schemes, including via a single doped region (e.g., Figure 2A 210a), via two doped regions forming a junction region (eg, Figure 3A 210a and 310a) protection (one of the doped regions is biased), or via two doped regions forming a junction region (e.g., Figure 3C 210b and 310b) for protection (wherein the two doped regions are biased).

[0044] Figure 4 4 is a flow chart (400) showing the various steps of a method for reducing back-gate effects in silicon-on-insulator (SOI) circuits according to the present disclosure. Figure 4 As shown, such steps include: doping a region of the trap-rich layer directly below the SOI circuit according to step (410); reducing the resistivity of the region based on the doping, thereby increasing the charge transfer rate of the region according to step (420); and biasing the region with a voltage based on the operating state of the SOI circuit according to step (430), thereby reducing the back gate effect in the SOI circuit. In such a method, the SOI circuit can be formed on an RF-SOI substrate, which includes: a high resistivity silicon (HR-Si) substrate; a trap-rich layer covering the HR-Si substrate; a buried oxide (BOX) layer covering the trap-rich layer; and a thin silicon layer covering the BOX layer.

[0045] As used in the present disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates having metal or metalloid, insulator and / or semiconductor structures. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper or other metal, or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0046] As used in this disclosure, the term "radio frequency" (RF) refers to oscillation rates in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves, or the frequency of alternating voltage or current in an electrical circuit.

[0047] Various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise specified above, selecting appropriate component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure), or in hybrid or discrete circuit form. Integrated circuit implementation can be manufactured using any suitable substrate and process (including but not limited to standard bulk silicon, high resistivity bulk CMOS and silicon on insulator (SOI)). Unless otherwise specified above, embodiments of the present invention can be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. However, embodiments of the present invention are particularly useful when manufactured using a process based on SOI or SOS or when manufactured using a process with similar characteristics. Manufacturing in CMOS using SOI process enables the circuit to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity and high frequency operation (i.e., up to and exceeding 300GHz radio frequency). Monolithic IC implementations are particularly useful because parasitic capacitances can usually be kept low (or at a minimum, or uniform across all cells, thereby allowing compensation for parasitic capacitances) by careful design.

[0048] Depending on the particular specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices), voltage levels may be adjusted and / or voltage and / or logic signal polarity may be inverted. Component voltage, current, and power handling capabilities may be adjusted as needed, such as by adjusting device size, "stacking" components (particularly FETs) in series to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0049] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. Embodiments of the present invention can be manufactured as integrated circuits (ICs), which can be encapsulated in IC packages and / or modules for ease of processing, manufacturing and / or improved performance. Specifically, IC embodiments of the present invention are typically used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into a package. Then, the IC and / or module are typically combined with other components, typically on a printed circuit board, to form a part of a final product such as a cellular phone, a laptop computer, or an electronic tablet, or to form a more advanced module that can be used in various products such as vehicles, test equipment, medical equipment, etc. Through various configurations of modules and components, such ICs typically support communication modes, typically wireless communications.

[0050] A number of embodiments of the present invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the above steps may be order-independent and therefore may be performed in an order different from that described. In addition, some of the above steps may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, and / or parallel manner.

[0051] It should be understood that the foregoing description is intended to illustrate rather than limit the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are within the scope of the claims. Specifically, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or combinations of matter set forth in the appended claims. (Note that parenthetical markings for claim elements are for convenience of reference to such elements, and they do not themselves indicate a specific required order or enumeration of elements; furthermore, such markings may be reused in dependent claims as references to additional elements without being considered to begin a conflicting marking sequence).

Claims

1. A silicon-on-insulator (SOI) structure, comprising: An RF-SOI substrate, the RF-SOI substrate comprising: High resistivity silicon (HR-Si) substrate; a trap-rich layer stacked on the HR-Si substrate; a buried oxide (BOX) layer overlying the trap-rich layer; and a thin silicon layer superimposed on the BOX layer; a first circuit formed in a first silicon region of the thin silicon layer; and a first implant in a region of the trap-rich layer directly below the first circuit; in, The first injection is configured to be biased with a first voltage based on an operating state of the first circuit.

2. The silicon-on-insulator (SOI) structure of claim 1, wherein: The first implant is a heavily doped implant including n+ type or p+ type dopants.

3. The silicon-on-insulator (SOI) structure of claim 1 , wherein: The first implant is completely contained in the trap rich layer.

4. The silicon-on-insulator (SOI) structure of claim 1, wherein: The first implant is completely contained in the trap rich layer and is separated from the HR-Si substrate by undoped regions of the trap rich layer.

5. The silicon-on-insulator (SOI) structure of claim 1 , wherein: The SOI structure further includes a first through-box contact (TBC), and The first TBC penetrates the BOX layer at a first shallow trench isolation (STI) region to contact the first implant.

6. The silicon-on-insulator (SOI) structure of claim 5, wherein: The first TBC contacts the first implant to bias the first implant with the first voltage.

7. The silicon-on-insulator (SOI) structure of claim 6, wherein: The first TBC resistively contacts the first implant.

8. The silicon-on-insulator (SOI) structure of claim 1, wherein: The SOI structure further includes a second implant in a region of the trap rich layer surrounding the first implant, and An interface between the first implant and the second implant forms a first junction.

9. The silicon-on-insulator (SOI) structure of claim 8, wherein: The first junction is a pn junction.

10. The silicon-on-insulator (SOI) structure of claim 8, wherein: The first junction is completely contained in the trap-rich layer and is separated from the HR-Si substrate by an undoped region of the trap-rich layer.

11. The silicon-on-insulator (SOI) structure of claim 8, wherein: The first implant is formed in a well of the second implant.

12. The silicon-on-insulator (SOI) structure of claim 8, wherein: The SOI structure further includes a second through-box contact (TBC), and The second TBC penetrates the BOX layer at a second shallow trench isolation (STI) region to contact the second implant.

13. The silicon-on-insulator (SOI) structure of claim 12, wherein: The second STI region is the first STI region.

14. The silicon-on-insulator (SOI) structure of claim 12, wherein: The second TBC resistively contacts the second injection to bias the second injection with a second voltage.

15. The silicon-on-insulator (SOI) structure of claim 1, wherein: The SOI structure further includes: a second circuit formed in a second silicon region of the thin silicon layer, the second silicon region being isolated from the first silicon region; and a third implantation in a region of the trap rich layer directly below the second circuit, the third implantation being separated from the first implantation by an undoped region of the trap rich layer, and The third injection is configured to be biased with a third voltage based on an operating state of the second circuit.

16. The silicon-on-insulator (SOI) structure of claim 15, wherein: The third implant is completely contained in the trap rich layer and is separated from the HR-Si substrate by undoped regions of the trap rich layer.

17. The silicon-on-insulator (SOI) structure of claim 15, wherein: The SOI structure further includes a fourth implant in a region of the trap rich layer surrounding the third implant, and An interface between the third implant and the fourth implant forms a second junction.

18. The silicon-on-insulator (SOI) structure of claim 17, wherein: The first knot and the second knot: The undoped regions are separated from each other by the trap-rich layer, and The undoped region is separated from the HR-Si by the trap-rich layer.

19. The silicon-on-insulator (SOI) structure of claim 17, wherein: The first junction and the second junction form a back-to-back reverse diode configured to reduce a flow of charge between the first injection and the third injection.

20. The silicon-on-insulator (SOI) structure of claim 1, wherein: The HR-Si has a resistivity greater than 200 ohm.cm; The trap-rich layer has a resistivity greater than 200 ohm.cm, and The first implant region has a resistivity less than 200 ohm.cm.

21. The silicon-on-insulator (SOI) structure of claim 1, wherein: The trap-rich layer has a value greater than 1×E8 at / cm 2 The trap density.

22. The silicon-on-insulator (SOI) structure of claim 1, wherein: The trap rich layer has an induced trap density at least two orders of magnitude greater than a trap density of the HR-Si substrate, the trap density of the HR-Si substrate being based on impurities.

23. A method for reducing back-gate effects in a silicon-on-insulator (SOI) circuit, the method comprising: Doping a region of the trap-rich layer directly below the SOI circuit; Based on the doping, the resistivity of the region is reduced, thereby increasing the charge transfer rate of the region; as well as biasing the region with a voltage based on an operating state of the SOI circuit to reduce a back-gate effect in the SOI circuit; in, The SOI circuit is formed on an RF-SOI substrate, and the RF-SOI substrate includes: High resistivity silicon (HR-Si) substrate; The trap-rich layer stacked on the HR-Si substrate; a buried oxide (BOX) layer overlying the trap-rich layer; and A thin silicon layer superimposed on the BOX layer.

24. The method of claim 23, wherein: The HR-Si has a resistivity greater than 200 ohm.cm; The trap-rich layer has a resistivity greater than 200 ohm.cm, and The doped region of the trap-rich layer has a resistivity less than 200 ohm.cm.

25. The method of claim 23, wherein: The trap-rich layer has a value greater than 1×E8 at / cm 2 The trap density.

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