Circuit for connecting two outputs of differential amplifier to input of single-ended amplifier

Abstract

The invention relates to a circuit (1) comprising a first terminal (T1) for a first output of a differential amplifier, a second terminal (T2) for a second output of said differential amplifier, a third terminal (T3) for an input of a single-ended amplifier, and three transistors, each comprising a first terminal, a second terminal and a third terminal. The third terminal of the first transistor is connected to the first terminal of the circuit. The third terminal of the second transistor is connected to the second terminal of the circuit. The third terminal of a third transistor is electrically connected to the second terminal of the first transistor. The second terminal of the second transistor, the first terminal of the third transistor, and the third terminal of the circuit are connected to a node. The transconductance of the second transistor is equal to the transconductance of the third transistor.

Description

Technical Field

[0001] The present invention relates to a circuit for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier, and to an amplifier circuit. Background Art

[0002] The present invention is in the field of electrically connecting the output of a differential amplifier and the input of a single-ended amplifier to each other. For example, in some applications (such as PAM4 communications), it may be desirable to provide differential to single-ended conversion at a certain point in the amplifier chain while maintaining high linearity. Summary of the invention

[0003] The inventors made the following considerations.

[0004] In order to electrically connect the input of the single-ended amplifier to the differential amplifier, a buffer may be inserted between the output of the differential amplifier and the input of the single-ended amplifier. This may isolate the differential amplifier from the single-ended amplifier and may increase the bandwidth of the combination of the differential amplifier and the single-ended amplifier. Such a buffer may be implemented by a bipolar junction transistor (BJT) or a field-effect transistor (FET) (e.g., a metal-oxide-semiconductor FET (MOSFET)), wherein the BJT may be connected to form an emitter follower and the FET may be connected to form a source follower. In the present invention, the term "electrically connected" may be abbreviated to the term "connected".

[0005] For example, differential to single-ended conversion (i.e., connecting the input of a single-ended amplifier to the output of a differential amplifier) ​​can be achieved by selecting one of the two outputs of the differential amplifier and connecting that output to the input of the single-ended amplifier, while leaving the other of the two outputs of the differential amplifier floating.

[0006] The above strategy represents a simple method to perform wideband differential to single-ended conversion. However, it results in a 6dB gain loss, which may require one or more additional amplifier stages, increasing power consumption and reducing bandwidth and / or linearity.

[0007] The above strategy is exemplified in Figure 1 , where one or more buffers 103a, 103b can be used to connect one of the two outputs of the differential amplifier 101 to the input of the single-ended amplifier (in Figure 1 The single-ended amplifier is not shown. Figure 1In (A), the two output terminals of the differential amplifier 101 are connected to buffers 103a and 103b respectively, where: Figure 1 (A) The output of the top differential amplifier 101 can be connected to the input of a single-ended amplifier via a buffer 103a. Figure 1 (A) The other output terminal of the bottom differential amplifier 101 can be connected to the buffer 103b only. Figure 1 (A) Buffers 103a and 103b are implemented using BJTs. Alternatively, buffers 103a and 103b may be implemented using MOSFETs, such as Figure 1 (B) is exemplarily shown. Optionally, only the output of the differential amplifier 101 that is selected to be connected to the input of the single-ended amplifier can be connected to the buffer 103a so as to be connected to the input of the single-ended amplifier through the buffer 103a. Figure 1 (C) and 1(D) are exemplarily shown, wherein, according to Figure 1 (C), the buffer 103a is implemented using a BJT, and according to Figure 1 (D), the buffer 103a is implemented using MOSFET. Figure 1 In (A) to 1(D), an additional amplifier stage 102a is shown connected between the output of the differential amplifier 101 and the single-ended amplifier to compensate for the above-mentioned 6dB gain loss. Figure 1 In the examples of (A) to 1(D), there may be no buffer, and one of the two output terminals of the differential amplifier may optionally be connected to the input terminal of the single-ended amplifier through an additional amplifier stage 102a without arranging a buffer between the output terminal of the differential amplifier 101 and the input terminal of the single-ended amplifier.

[0008] In the above example of implementing differential to single-ended conversion, some imbalance may occur in the differential amplifier due to uneven loading, so even-order harmonics at the output of the differential amplifier may deteriorate linearity.

[0009] A circuit that connects the input of a single-ended amplifier to the output of a differential amplifier (i.e., a circuit for differential to single-ended conversion) can be called a differential to single-ended converter or a balun (balanced to unbalanced device). Such circuits can be divided into two main categories: passive circuits (which can be called passive differential to single-ended converters or passive baluns) and active circuits (which can be called active differential to single-ended converters or active baluns).

[0010] An example of a passive circuit for connecting the input of a single-ended amplifier to the two outputs of a differential amplifier may be or may include a transformer. For example, a simple 1:1 transformer with a coupling coefficient of 1 (K=1) may act as a passive balun. The primary winding of the transformer may be differentially driven. That is, one of the two terminals of the primary winding may be connected to one of the two outputs of the differential amplifier, and the other of the two terminals of the primary winding may be connected to the other of the two outputs of the differential amplifier. At the same time, the secondary winding of the transformer may have one of its terminals connected to the input of the single-ended amplifier and the other of its terminals connected to ground (e.g., radio frequency (RF) ground). That is, one of the two terminals of the secondary winding may be connected to the input of the single-ended amplifier, and the other of the two terminals of the secondary winding may be connected to ground (e.g., radio frequency (RF) ground).

[0011] The passive circuit used to connect the input of the single-ended amplifier to the differential amplifier can be relatively narrow-band. For example, where the passive circuit is or includes a transformer, in order to have a low frequency cutoff, the inductance L1 of the primary winding and the inductance L2 of the secondary winding of the transformer need to be very large (i.e., for a given natural frequency ω, jωL 1,2 >> Output / input impedance of the pre / post amplifier (stage). On the other hand, in order to operate at high frequencies, the inductance L1 of the primary winding and the inductance L2 of the secondary winding of the transformer should be low (in order to maximize the self-resonance of the transformer). Therefore, when a transformer (integrated transformer) is used to connect the two output terminals of the differential amplifier to the input terminal of the single-ended amplifier, i.e., for differential to single-ended conversion, broadband operation cannot be achieved.

[0012] The active circuit for connecting the input of a single-ended amplifier to the output of a differential amplifier is a circuit including an active device (e.g., a transistor) for realizing the function of differential to single-ended conversion, i.e., for connecting the input of a single-ended amplifier to the output of a differential amplifier. The active circuit for connecting the input of a single-ended amplifier to the output of a differential amplifier can achieve wide bandwidth operation. However, it is not easy to achieve high broadband balanced input impedance for active circuits. In addition, linearity may be a problem. In addition, when using active circuits, the bias circuit may limit the low frequency cutoff and / or the maximum operating frequency.

[0013] In summary, the present invention aims to provide an improved circuit for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier. The present invention may be directed to providing a circuit for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier, wherein the circuit achieves wide bandwidth and / or high linearity.

[0014] These and other objects are achieved by the solutions of the invention as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

[0015] A first aspect of the present invention provides a circuit for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier. The circuit comprises: a first terminal for electrically connecting to a first output terminal of the two output terminals of the differential amplifier; a second terminal for electrically connecting to a second output terminal of the two output terminals of the differential amplifier; a third terminal for electrically connecting to the input terminal of the single-ended amplifier; and three transistors, each transistor comprising a first terminal, a second terminal and a third terminal. The third terminal of the first transistor of the three transistors is electrically connected to the first terminal of the circuit. The third terminal of the second transistor of the three transistors is electrically connected to the second terminal of the circuit. The third terminal of the third transistor of the three transistors is electrically connected to the second terminal of the first transistor. The second terminal of the second transistor, the first terminal of the third transistor and the third terminal of the circuit are electrically connected to a node. The transconductance of the second transistor is equal to the transconductance of the third transistor.

[0016] In other words, a first aspect provides a circuit comprising a first terminal for a first output of a differential amplifier, a second terminal for a second output of the differential amplifier, a third terminal for an input of a single-ended amplifier, and three transistors, each transistor comprising a first terminal, a second terminal, and a third terminal. The third terminal of the first transistor is connected to the first terminal of the circuit. The third terminal of the second transistor is connected to the second terminal of the circuit. The third terminal of the third transistor is electrically connected to the second terminal of the first transistor. The second terminal of the second transistor, the first terminal of the third transistor, and the third terminal of the circuit are connected to a node. The transconductance of the second transistor is equal to the transconductance of the third transistor.

[0017] The circuit according to the first aspect can provide high input impedance for the previous stage (i.e., the differential amplifier), and therefore, when the two output terminals of the differential amplifier are connected to the input terminals of the single-ended amplifier through the circuit according to the first aspect, the total radio frequency (RF) bandwidth (e.g., the total RF chain bandwidth) of the amplifier circuit including the differential amplifier and the single-ended amplifier can be improved.

[0018] Due to its circuit configuration, the circuit according to the first aspect can suppress common mode signals at the first terminal and the second terminal. As a result, the circuit according to the first aspect can suppress even-order harmonic distortion (eg, HD2, HD4, etc.) at the first terminal and the second terminal.

[0019] Therefore, a first aspect proposes a wide bandwidth input impedance balanced active circuit (ie, active balun) for differential to single-ended conversion with high linearity.

[0020] The circuit can be used for a broadband trans-impedance amplifier (TIA) and / or a driver. In such an amplifier and / or a driver, a signal bandwidth of the order of tens of GHz can be processed. Such an amplifier and / or a driver can be used for high data rate communications. The circuit can be a part of such an amplifier or such a driver.

[0021] The circuit can be used in a fully integrated high-frequency broadband amplifier that requires high linearity, impedance-matched output, and low AC cutoff frequency; for example (but not limited to) a broadband transimpedance amplifier (TIA) for optical communication, a broadband driver for optical communication, a broadband amplifier for a broadband RF transceiver, etc.

[0022] The circuit may be referred to as a "differential to single-ended converter" or a "balun". The circuit may have a 0 dB (differential to single-ended) gain. That is, the circuit may be a differential to single-ended converter with a 0 dB (differential to single-ended) gain.

[0023] The third terminal of each transistor may be referred to as a “control terminal”. If one transistor (e.g., of the three transistors) is a bipolar junction transistor (BJT), the third terminal is the base terminal of the BJT. If one transistor (e.g., of the three transistors) is a field-effect transistor (FET), such as a metal-oxide-semiconductor FET (MOSFET), the third terminal is the gate terminal of the FET (e.g., MOSFET).

[0024] The transconductance of the second transistor being equal to the transconductance of the third transistor can be achieved by designing the second transistor and the third transistor to be equal in size. In other words, this can be achieved by making the size of the second transistor and the size of the third transistor equal to each other. That is, the size of the second transistor and the size of the third transistor can be equal so that the transconductance of the second transistor is equal to the transconductance of the third transistor. The transconductance of a transistor can be represented by the symbol "gm "express.

[0025] If the transistor is a BJT, the size of the transistor may be the total emitter area (Ae, i.e., the area of ​​the emitter terminal), which is the product of the emitter width (We, i.e., the width of the emitter terminal), the emitter length (Le, i.e., the length of the emitter terminal), and the number of emitter subterminals or emitter fingers (Ne) forming the emitter terminal: Ae=We×Le×Ne. If the transistor is a FET (e.g., a MOSFET), the size of the transistor may be the total gate area (Ag, i.e., the area of ​​the gate terminal), which is the gate width (Wg, i.e., the width of the gate terminal), the gate length (Lg, i.e., the length of the gate terminal), and the number of gate subterminals or gate fingers (Nf) forming the gate terminal: Ag=Wg×Lg×Nf.

[0026] Since the second terminal of the second transistor and the first terminal of the third transistor are connected to each other, the same current can flow through the second transistor and the third transistor through the first terminal and the second terminal. Since the current flowing through the second transistor and the third transistor is the same, and the transconductance of the second transistor is equal to the transconductance of the third transistor, the third transistor can be used to function as a unit gain amplifier or act as a unit gain amplifier. Since the first transistor and the second transistor are connected (arranged) in the circuit, the first transistor and the second transistor can be used to function as a unit gain amplifier or act as a unit gain amplifier, respectively. In other words, the first transistor, the second transistor, and the third transistor can be used to act as a unit gain amplifier or act as a unit gain amplifier. The second terminal of the third transistor can be grounded.

[0027] In an implementation of the first aspect, each corresponding transistor of the three transistors is one of the following: a bipolar junction transistor (BJT), wherein the first terminal of the BJT is a collector terminal, the second terminal of the BJT is an emitter terminal, and the third terminal of the BJT is a base terminal; a field-effect transistor (FET), wherein the first terminal of the FET is a drain terminal, the second terminal of the FET is a source terminal, and the third terminal of the FET is a gate terminal. For example, the FET may be a MOSFET. The three transistors may be implemented in different ways, for example, by any other transistor type. The description of the three transistors may be valid for any other optional transistor of the circuit. That is, any other optional transistor of the circuit may be a BJT, a FET (such as a MOSFET), or any other transistor type or may be implemented by a BJT, a FET (such as a MOSFET), or any other transistor type.

[0028] In an implementation of the first aspect, the first terminal of the first transistor and the first terminal of the second transistor are respectively used to be electrically connected to a power source. For example, the power source may be a power source for a circuit (optionally a part of the circuit).

[0029] In an implementation manner of the first aspect, the circuit includes a bias circuit for setting a current, and the second terminal of the first transistor is electrically connected to the bias circuit.

[0030] A bias circuit may be connected between the second terminal of the first transistor and ground. The bias circuit may be used to set the current flowing through the first transistor through the first terminal and the second terminal of the first transistor.

[0031] In an implementation manner of the first aspect, the bias circuit includes a current source or a resistor.

[0032] In an implementation of the first aspect, the circuit includes a first resistor and a second resistor having equal resistances. The second terminal of the second transistor may be electrically connected to the node through the first resistor, and the second resistor may be electrically connected to the second terminal of the third transistor.

[0033] If the parasitic (intrinsic) resistors of the second terminals of the second transistor and the third transistor are negligible, the nonlinearities of the transconductances of the second transistor and the third transistor can cancel each other. For example, assuming that the second transistor and the third transistor are both BJTs, the following can be established: If the parasitic (intrinsic) emitter resistors of the second transistor and the third transistor are negligible, the nonlinearities of the transconductances of the second transistor and the third transistor can cancel each other.

[0034] However, if the parasitic resistors of the second terminals of the second transistor and the third transistor are not negligible, the linearity of the circuit can be improved by adding a first resistor and a second resistor in the circuit, i.e., electrically connecting the first resistor to the second terminal of the second transistor and electrically connecting the second resistor to the second terminal of the third transistor.

[0035] The first resistor and the second resistor may be referred to as “two degenerate resistors of equal resistance” or “two identical degenerate resistors”. The second resistor may be connected between the second terminal of the third transistor and the ground. That is, the second terminal of the third transistor may be grounded through the second resistor.

[0036] In an implementation of the first aspect, the circuit includes an inductor. The inductor may be arranged so that the second terminal of the second transistor is electrically connected to the node through the inductor. Alternatively, the inductor may be arranged so that the first terminal of the third transistor is electrically connected to the node through the inductor. Alternatively, the inductor may be arranged so that the third terminal of the circuit is electrically connected to the node through the inductor.

[0037] Inductors support extending the bandwidth of a circuit. That is, placing an inductor in a circuit creates a resonant network (e.g., a certain resonant network). Inductors can extend the maximum operating frequency of a circuit.

[0038] In an implementation of the first aspect, the circuit includes a first resistor and a second resistor having equal resistance, and an inductor. The second resistor may be electrically connected to the second terminal of the third transistor. The first resistor and the inductor may be arranged so that the second terminal of the second transistor is electrically connected to the node through the first resistor and the inductor. Alternatively, the first resistor and the inductor may be arranged so that the second terminal of the second transistor is electrically connected to the node through the first resistor, and the first terminal of the third transistor is electrically connected to the node through the inductor. Alternatively, the first resistor and the inductor may be arranged so that the second terminal of the second transistor is electrically connected to the node through the first resistor, and the third terminal of the circuit is electrically connected to the node through the inductor. The first resistor and the inductor may be connected in series.

[0039] The inductor supports extending the bandwidth of the circuit. That is, arranging the inductor in the circuit creates a resonant network (e.g., a certain resonant network). The inductor can extend the maximum operating frequency of the circuit. This is advantageous when the circuit includes a first resistor and a second resistor to improve the linearity of the circuit. Arranging the first resistor and the second resistor in the circuit may result in a reduction in bandwidth. Due to a low-pass filter that may be formed by the first resistor and a load impedance that may be present at the third terminal of the circuit, a portion of the circuit including the second transistor may be affected by the reduction in bandwidth. The load impedance may be the input impedance of the single-ended amplifier of the circuit when it is connected to the third terminal. A portion of the circuit including the third transistor may be affected by a higher load impedance, which may be formed by a series connection of the transconductance of the first resistor and the second transistor.

[0040] In an implementation of the first aspect, the circuit includes a first inductor and a second inductor. The first inductor and the second inductor may be arranged so that the second terminal of the second transistor is electrically connected to the node through the first inductor, and the third terminal of the circuit is electrically connected to the node through the second inductor. Alternatively, the first inductor and the second inductor may be arranged so that the second terminal of the second transistor is electrically connected to the node through the first inductor, and the first terminal of the third transistor is electrically connected to the node through the second inductor. Alternatively, the first inductor and the second inductor may be arranged so that the first terminal of the third transistor is electrically connected to the node through the first inductor, and the third terminal of the circuit is electrically connected to the node through the second inductor.

[0041] The first inductor and the second inductor support extending the bandwidth of the circuit for the reasons described above with respect to the optional inductor of the circuit.

[0042] In an implementation of the first aspect, the circuit includes a first resistor and a second resistor having equal resistance, a first inductor and a second inductor. The second resistor may be electrically connected to the second terminal of the third transistor. The first resistor, the first inductor and the second inductor may be arranged so that the second terminal of the second transistor is electrically connected to the node through the first resistor and the first inductor, and the third terminal of the circuit is electrically connected to the node through the second inductor. Alternatively, the first resistor, the first inductor and the second inductor may be arranged so that the second terminal of the second transistor is electrically connected to the node through the first resistor and the first inductor, and the first terminal of the third transistor is electrically connected to the node through the second inductor. Alternatively, the first resistor, the first inductor and the second inductor may be arranged so that the second terminal of the second transistor is electrically connected to the node through the first resistor, the first terminal of the third transistor is electrically connected to the node through the first inductor, and the third terminal of the circuit is electrically connected to the node through the second inductor. The first resistor and the first inductor may be connected in series.

[0043] The first inductor and the second inductor support extending the bandwidth of the circuit for the reasons described above with respect to the optional inductor of the circuit.

[0044] In an implementation of the first aspect, the circuit includes a first inductor, a second inductor, and a third inductor. The second terminal of the second transistor can be electrically connected to the node through the first inductor. The first terminal of the third transistor can be electrically connected to the node through the second inductor. The third terminal of the circuit can be electrically connected to the node through the third inductor.

[0045] Due to the reasons mentioned above regarding the optional inductors of the circuit, the first inductor, the second inductor and the third inductor support extending the bandwidth of the circuit. These three inductors can form a triple resonant network.

[0046] In an implementation of the first aspect, the circuit includes a first resistor and a second resistor having equal resistance, a first inductor, a second inductor, and a third inductor. The second resistor may be electrically connected to the second terminal of the third transistor. The second terminal of the second transistor may be electrically connected to the node through the first resistor and the first inductor. The first terminal of the third transistor may be electrically connected to the node through the second inductor. The third terminal of the circuit may be electrically connected to the node through the third inductor. The first resistor and the first inductor may be connected in series.

[0047] Due to the reasons mentioned above regarding the optional inductors of the circuit, the first inductor, the second inductor and the third inductor support extending the bandwidth of the circuit. These three inductors can form a triple resonant network.

[0048] In an implementation of the first aspect, the circuit includes a level converter circuit and a current sensing circuit for converting a current level. The third terminal of the first transistor can be electrically connected to the first terminal of the circuit through the level converter circuit. The current sensing circuit can be used to sense the current flowing through the second transistor and the third transistor. The level converter circuit can be used to change the DC voltage at the third terminal of the first transistor by changing the current supplied to the level converter circuit from the first terminal of the circuit according to the current sensed by the current sensing circuit.

[0049] The level converter circuit can be used to change the DC voltage at the third terminal of the first transistor by changing the current supplied from the first terminal of the circuit to the resistor of the level converter circuit according to the current sensed by the current sensing circuit. The larger the current supplied from the first terminal of the circuit to the level converter circuit (e.g., the resistor of the level converter circuit), the greater the DC offset, and therefore, the lower the DC voltage at the third terminal of the first transistor, and vice versa. The level converter circuit can be referred to as a "DC level converter circuit". The terms "level converter circuit" and "level converter" can be used as synonyms. The level converter circuit supports biasing the second transistor and the third transistor. This supports DC coupling (i.e., very low AC cutoff).

[0050] In one implementation of the first aspect, the circuit includes a level converter circuit and a current sensing circuit for converting a current level. The third terminal of the third transistor can be electrically connected to the second terminal of the first transistor through the level converter circuit. The current sensing circuit can be used to sense the current flowing through the second transistor and the third transistor. The level converter circuit can be used to change the current supplied from the second terminal of the first transistor to the third terminal of the third transistor according to the current sensed by the current sensing circuit. The level converter circuit can be referred to as a "DC level converter circuit". The level converter circuit supports biasing the second transistor and the third transistor. This supports DC coupling (i.e., very low AC cutoff).

[0051] In the above two optional implementations, the current sensing circuit may be or may include a sensing resistor (e.g., a shunt resistor) for sensing the current flowing through the second transistor and the third transistor. The sensing resistor may be connected to the first terminal of the second transistor. For example, the first terminal of the second transistor may be connected to a power supply through the sensing resistor. For example, the power supply may be a power supply for a circuit (optionally a part of the circuit). Optionally, the current sensing circuit may include a capacitor, which may be electrically connected to the sensing resistor in parallel. For example, if the first terminal of the second transistor may be connected to the power supply through a sensing resistor, the capacitor may be electrically connected between the first terminal of the second transistor and the power supply. A capacitor may be provided to short-circuit the sensing resistor at high frequencies (i.e., at frequencies greater than a threshold frequency).

[0052] The level converter circuit may include a series connection of two resistors. In addition, the level converter circuit may include a transistor connected to a node between two resistors of the series connection of the two resistors. The circuit may be configured so that a control signal based on the current sensed by the current sensing circuit is provided to a control terminal of the transistor. Alternatively, a capacitor may be electrically connected in parallel to the series connection of the two resistors. For example, the transistor may be a FET (e.g., a MOSFET), wherein the control terminal of the transistor is a gate terminal of the FET, and the drain terminal of the FET may be connected to a node between the two resistors. The source terminal of the FET may be grounded. The transistor may be implemented in different ways, for example, by any other transistor type.

[0053] If the level shifter circuit is used to change the DC voltage at the third terminal of the first transistor by changing the current supplied to the level shifter circuit from the first terminal of the circuit according to the current sensed by the current sensing circuit, the series connection of the two resistors may be connected between the first terminal of the circuit and the third terminal of the first transistor. That is, the first terminal of the first transistor may be electrically connected to the first terminal of the circuit through the series connection of the two resistors of the level shifter circuit.

[0054] If the level shifter circuit is used to change the current supplied from the second terminal of the first transistor to the third terminal of the third transistor according to the current sensed by the current sensing circuit, the series connection of the two resistors can be connected between the second terminal of the first transistor and the third terminal of the third transistor. That is, the third terminal of the third transistor can be electrically connected to the second terminal of the first transistor through the series connection of the two resistors of the level shifter circuit.

[0055] In an implementation of the first aspect, the circuit includes a second bias circuit and a comparator for setting an expected current. The comparator can be used to compare the current sensed by the current sensing circuit with the expected current. The level converter circuit can be used to change the current supplied from the first terminal of the circuit to the level converter circuit and the current supplied from the second terminal of the first transistor to the third terminal of the third transistor, respectively, according to the comparison result of the comparator.

[0056] The second bias circuit may be a replica bias circuit scaled by a factor Z to provide a desired current. The second bias circuit may include a scaling resistor and a current source electrically connected in series with each other, wherein the second bias circuit may be used to provide the desired current at a node between the scaling resistor and the current source. The resistance of the scaling resistor may be scaled by a factor Z, or may be greater than the resistance of the optional sense resistor by a factor Z. The desired current may be set or changed by the factor Z. Optionally, the current source may be used to provide an adjustable current for adjusting or changing the desired current.

[0057] The current sensed by the current sensing circuit (e.g., a sensing resistor) can be provided to the comparator through another resistor. The other resistor can be connected to the first terminal of the second transistor. The other resistor can be part of the current sensing circuit. The comparator may include an operational amplifier or be implemented by an operational amplifier. The current sensing circuit (e.g., a sensing resistor) can be connected to the inverting input of the operational amplifier (optionally through another resistor) for providing the sensed current to the comparator. The second bias circuit (e.g., a node between the scaling resistor and the current source) can be connected to the non-inverting input of the operational amplifier for providing the desired current to the comparator.

[0058] In an implementation of the first aspect, the circuit includes a fourth transistor, a fifth transistor, and a sixth transistor, each transistor including a first terminal, a second terminal, and a third terminal, a first level converter circuit, a second level converter circuit, and a fourth terminal. The third terminal of the second transistor can be electrically connected to the second terminal of the circuit through the fourth transistor, wherein the third terminal of the second transistor can be electrically connected to the second terminal of the fourth transistor, and the third terminal of the fourth transistor can be electrically connected to the second terminal of the circuit. The third terminal of the fifth transistor can be electrically connected to the second terminal of the first transistor. The third terminal of the fifth transistor can be electrically connected to the third terminal of the third transistor through the first level converter circuit. The second terminal of the fifth transistor, the first terminal of the sixth transistor, and the fourth terminal of the circuit can be electrically connected to a second node. The third terminal of the second transistor can be electrically connected to the third terminal of the sixth transistor through the second level converter circuit. The transconductance of the fifth transistor can be equal to the transconductance of the sixth transistor.

[0059] This supports the use of the circuit of the first aspect, depending on the functional configuration of the circuit, connecting the two outputs of the differential amplifier to the two inputs of another differential amplifier, or connecting the two outputs of the differential amplifier to the inputs of a single-ended amplifier circuit. The functional configuration of the circuit can be controlled by a first level shifter circuit and a second level shifter circuit. In other words, the circuit can be configured to be configured or reconfigured from a differential push-pull amplifier configuration to a differential to single-ended converter (or balun) configuration. When the circuit is in a different push-pull amplifier configuration, the circuit can be used to provide a 6dB differential gain.

[0060] Optionally, the first terminal of the fourth transistor and the first terminal of the fifth transistor are respectively used to be electrically connected to a power supply. For example, the power supply can be a power supply for a circuit (optionally a part of the circuit). Optionally, the circuit includes a bias circuit (e.g., a second bias circuit or a third bias circuit) for setting a current, and the second terminal of the fourth transistor can be electrically connected to the bias circuit. The bias circuit (e.g., a second bias circuit or a third bias circuit) can be connected between the second terminal of the fourth transistor and ground. The bias circuit can be used to set the current flowing through the fourth transistor through the first terminal and the second terminal of the fourth transistor. For example, the bias circuit includes a current source or a resistor.

[0061] In an implementation manner of the first aspect, the second transistor, the third transistor, the fifth transistor, and the sixth transistor have the same transconductance.

[0062] In an implementation of the first aspect, the second level shifter circuit is configured to set the current flowing through the fifth transistor and the sixth transistor to zero ampere when the single-ended amplifier is electrically connected to the third terminal of the circuit.

[0063] This supports disconnecting the second branch of the circuit including the fifth transistor and the sixth transistor. The second transistor and the third transistor can form a first branch of the circuit, and the first branch can be controlled (e.g., disconnected) by the first level converter circuit. In other words, the second level converter circuit can be used to configure the circuit as a circuit for connecting the two output ends of the differential amplifier to the input end of the single-ended amplifier by setting the current flowing through the fifth transistor and the sixth transistor to zero amperes (differential to single-ended converter or balun). The first level converter circuit can be used to set the current flowing through the second transistor and the third transistor to a current value greater than zero amperes when the second level converter circuit sets the current flowing through the fifth transistor and the sixth transistor to zero amperes. This keeps the first branch of the circuit including the second transistor and the third transistor closed.

[0064] Optionally, the first level converter circuit is used to set the current flowing through the second transistor and the third transistor to zero ampere when the single-ended amplifier is electrically connected to the fourth terminal of the circuit. This supports disconnecting the first branch of the circuit including the second transistor and the third transistor. In other words, the first level converter circuit can be used to configure the circuit as a circuit for connecting the two output ends of the differential amplifier to the input end of the single-ended amplifier (differential to single-ended converter or balun) by setting the current flowing through the second transistor and the third transistor to zero ampere. The second level converter circuit can be used to set the current flowing through the fifth transistor and the sixth transistor to a current value greater than zero ampere when the first level converter circuit sets the current flowing through the second transistor and the third transistor to zero ampere. This keeps the second branch of the circuit including the fifth transistor and the sixth transistor closed.

[0065] In an implementation of the first aspect, the second level converter circuit is configured to set the current flowing through the fifth transistor and the sixth transistor to a large level when another differential amplifier is electrically connected to the third terminal and the fourth terminal of the circuit.

[0066] In other words, the second level shifter circuit can be used to configure the circuit as a circuit for connecting two output terminals of a differential amplifier to two output terminals of another differential amplifier (for example, as a differential push-type amplifier configuration) by setting the current flowing through the fifth transistor and the sixth transistor to a current value greater than zero ampere. The first level shifter circuit can be used to set the current flowing through the second transistor and the third transistor to a current value greater than zero ampere when the other differential amplifier is electrically connected to the third terminal and the fourth terminal of the circuit.

[0067] Alternatively, the circuit may include the second level shifter circuit without the first level shifter circuit (i.e., without including the first level shifter circuit). If the second level shifter circuit sets the current flowing through the fifth transistor and the sixth transistor to a current value greater than zero ampere for connecting the further differential amplifier to the third terminal and the fourth terminal of the circuit, the circuit may be used to provide a 6 dB differential gain. This applies correspondingly to the first level shifter circuit.

[0068] In an implementation of the first aspect, the circuit includes a third resistor and a fourth resistor having equal resistance. The second terminal of the fifth transistor can be electrically connected to the second node through the third resistor. The fourth resistor can be electrically connected to the second terminal of the sixth transistor.

[0069] For the same reasons as described above with respect to the first and second resistors, the linearity of the circuit can be improved by adding a third resistor and a fourth resistor to the circuit, i.e., the third resistor is electrically connected to the second terminal of the fifth transistor, and the fourth resistor is electrically connected to the second terminal of the sixth transistor. The fourth resistor can be connected between the second terminal of the sixth transistor and ground. That is, the second terminal of the sixth transistor can be grounded through the fourth resistor.

[0070] In an implementation of the first aspect, the circuit includes a second inductor. The second inductor may be arranged so that the second terminal of the fifth transistor is electrically connected to the second node through the second inductor. Alternatively, the second inductor may be arranged so that the first terminal of the sixth transistor is electrically connected to the second node through the second inductor. Alternatively, the second inductor may be arranged so that the fourth terminal of the circuit is electrically connected to the second node through the second inductor.

[0071] The second inductor supports extending the bandwidth of the circuit. That is, arranging the second inductor in the circuit generates a resonant network (eg, a certain resonant network). The second inductor can extend the maximum operating frequency of the circuit.

[0072] The above-mentioned optional inductor connected to any one of the second transistor, the third transistor and the third terminal of the circuit and the optional second inductor connected to any one of the fifth transistor, the sixth transistor and the fourth terminal of the circuit can be arranged in the circuit so that the arrangement is symmetrical.

[0073] In an implementation of the first aspect, the circuit includes a third resistor and a fourth resistor having equal resistance, and a second inductor. The fourth resistor may be electrically connected to the second terminal of the sixth transistor. The third resistor and the second inductor may be arranged so that the second terminal of the fifth transistor is electrically connected to the second node through the third resistor and the second inductor. Alternatively, the third resistor and the second inductor may be arranged so that the second terminal of the fifth transistor is electrically connected to the second node through the third resistor, and the first terminal of the sixth transistor is electrically connected to the second node through the second inductor. Alternatively, the third resistor and the second inductor may be arranged so that the second terminal of the fifth transistor is electrically connected to the second node through the third resistor, and the fourth terminal of the circuit is electrically connected to the second node through the second inductor. The third resistor and the second inductor may be connected in series.

[0074] The second inductor supports extending the bandwidth of the circuit. That is, arranging the second inductor in the circuit generates a resonant network (eg, a certain resonant network). The second inductor can extend the maximum operating frequency of the circuit.

[0075] The first resistor and the second resistor and the third resistor and the fourth resistor can be arranged in the circuit so that the arrangement is symmetrical. The above-mentioned optional inductor connected to any one of the second transistor, the third transistor and the third terminal of the circuit and the optional second inductor connected to any one of the fifth transistor, the sixth transistor and the fourth terminal of the circuit can be arranged in the circuit so that the arrangement is symmetrical.

[0076] In an implementation of the first aspect, the circuit includes a third inductor and a fourth inductor. The third inductor and the fourth inductor may be arranged so that the second terminal of the fifth transistor is electrically connected to the second node through the third inductor, and the fourth terminal of the circuit is electrically connected to the second node through the fourth inductor. Alternatively, the third inductor and the fourth inductor may be arranged so that the second terminal of the fifth transistor is electrically connected to the second node through the third inductor, and the first terminal of the sixth transistor is electrically connected to the second node through the fourth inductor. Alternatively, the third inductor and the fourth inductor may be arranged so that the first terminal of the sixth transistor is electrically connected to the second node through the third inductor, and the fourth terminal of the circuit is electrically connected to the second node through the fourth inductor.

[0077] The optional first and second inductors connected to any two of the second transistor, the third transistor, and the third terminal of the circuit, and the optional third and fourth inductors connected to any one of the fifth transistor, the sixth transistor, and the fourth terminal of the circuit can be arranged in the circuit so that the arrangement is symmetrical. Due to the reasons described above with respect to the optional first and second inductors connected to any two of the second transistor, the third transistor, and the third terminal of the circuit, the third and fourth inductors support extending the bandwidth of the circuit.

[0078] In an implementation of the first aspect, the circuit includes a third resistor and a fourth resistor, a third inductor and a fourth inductor having equal resistance. The fourth resistor may be electrically connected to the second terminal of the sixth transistor. The third resistor, the third inductor and the fourth inductor may be arranged so that the second terminal of the fifth transistor is electrically connected to the second node through the third resistor and the third inductor, and the fourth terminal of the circuit is electrically connected to the second node through the fourth inductor. Alternatively, the third resistor, the third inductor and the fourth inductor may be arranged so that the second terminal of the fifth transistor is electrically connected to the second node through the third resistor and the third inductor, and the first terminal of the sixth transistor is electrically connected to the second node through the fourth inductor. Alternatively, the third resistor, the third inductor and the fourth inductor may be arranged so that the second terminal of the fifth transistor is electrically connected to the second node through the third resistor, the first terminal of the sixth transistor is electrically connected to the second node through the third inductor, and the fourth terminal of the circuit is electrically connected to the second node through the fourth inductor. The third resistor and the third inductor may be connected in series.

[0079] The first resistor and the second resistor and the third resistor and the fourth resistor can be arranged in the circuit so that the arrangement is symmetrical. The above-mentioned optional first inductor and second inductor connected to any two of the second transistor, the third transistor and the third terminal of the circuit, and the optional third inductor and fourth inductor connected to any one of the fifth transistor, the sixth transistor and the fourth terminal of the circuit can be arranged in the circuit so that the arrangement is symmetrical.

[0080] In an implementation of the first aspect, the circuit includes a fourth inductor, a fifth inductor, and a sixth inductor. The second terminal of the fifth transistor can be electrically connected to the second node through the fourth inductor. The first terminal of the sixth transistor can be electrically connected to the second node through the fifth inductor. The fourth terminal of the circuit can be electrically connected to the second node through the sixth inductor. The three inductors can form a triple resonant network.

[0081] The optional first, second and third inductors connected to the second transistor, third transistor and third terminal of the circuit, respectively, and the optional fourth, fifth and sixth inductors connected to the fifth transistor, sixth transistor and fourth terminal of the circuit, respectively, can be arranged in the circuit so that the arrangement is symmetrical. Due to the reasons described above with respect to the optional first, second and third inductors connected to the second transistor, third transistor and third terminal of the circuit, respectively, the fourth, fifth and sixth inductors support extending the bandwidth of the circuit.

[0082] In an implementation of the first aspect, the circuit includes a third resistor and a fourth resistor having equal resistance, a fourth inductor, a fifth inductor, and a sixth inductor. The fourth resistor may be electrically connected to the second terminal of the sixth transistor. The second terminal of the fifth transistor may be electrically connected to the second node through the third resistor and the fourth inductor. The first terminal of the sixth transistor may be electrically connected to the second node through the fifth inductor. The fourth terminal of the circuit may be electrically connected to the second node through the sixth inductor. The third resistor and the fourth inductor may be connected in series.

[0083] The first resistor and the second resistor and the third resistor and the fourth resistor can be arranged in the circuit so that the arrangement is symmetrical. The above-mentioned optional first inductor, second inductor and third inductor connected to the second transistor, third transistor and third terminal of the circuit, respectively, and the optional fourth inductor, fifth inductor and sixth inductor connected to the fifth transistor, sixth transistor and fourth terminal of the circuit, respectively, can be arranged in the circuit so that the arrangement is symmetrical.

[0084] In order to implement the circuit according to the first aspect of the present invention, as described above, part or all of the implementations and optional features of the first aspect may be combined with each other.

[0085] A second aspect of the present invention provides an amplifier circuit. The amplifier circuit comprises a differential amplifier having a first output terminal and a second output terminal, a single-ended amplifier having an input terminal, and the circuit according to the first aspect of the present invention as described above. The first output terminal of the differential amplifier is electrically connected to the first terminal of the circuit. The second output terminal of the differential amplifier is electrically connected to the second terminal of the circuit. The input terminal of the single-ended amplifier is electrically connected to the third terminal of the circuit.

[0086] The amplifier circuit can be used for a broadband trans-impedance amplifier (TIA) and / or a driver. In such an amplifier and / or a driver, a signal bandwidth of the order of tens of GHz can be processed. Such an amplifier and / or a driver can be used for high data rate communications. The amplifier circuit can be a part of such an amplifier or a part of such an amplifier. The amplifier circuit can be a part of such a driver or a part of such a driver.

[0087] The amplifier circuit may be a fully integrated high frequency broadband amplifier requiring high linearity, impedance matching output, and low AC cutoff frequency. For example, the amplifier circuit may be a broadband transimpedance amplifier (TIA) for optical communication; a broadband driver for optical communication; a broadband amplifier for a broadband RF transceiver, etc.

[0088] The amplifier circuit may be a differential to single-ended wide bandwidth amplifier circuit (may be referred to as a differential to single-ended wide bandwidth amplifier).

[0089] The differential amplifier may be N differential amplifier stages of an amplifier circuit, or may be part of N differential amplifier stages of an amplifier circuit, wherein N is an integer equal to or greater than 1 (N≥1). If N is equal to or greater than 2 (N≥2, i.e. the amplifier circuit includes two or more differential amplifiers), the differential amplifier is a differential amplifier stage of two or more differential amplifiers to be connected to a single-ended amplifier. Two or more differential amplifiers (i.e. N≥2) may be connected to each other in cascade, i.e. may be connected to each other in cascade. In other words, two or more differential amplifiers may form an N-stage cascade differential amplifier. The N differential amplifier stages may achieve or provide a desired differential signal gain of the amplifier circuit (i.e. signal gain>1). The N differential amplifier stages may form a differential amplifier chain.

[0090] The single-ended amplifier can be M differential amplifier stages of an amplifier circuit, or can be part of M differential amplifier stages of an amplifier circuit, where M is an integer equal to or greater than 1 (M≥1). If M is equal to or greater than 2 (M≥2, i.e., the amplifier circuit includes two or more single-ended amplifiers), the single-ended amplifier is a single-ended amplifier stage of two or more single-ended amplifiers to be connected to the differential amplifier. Two or more single-ended amplifiers (i.e., M≥2) can be connected to each other in cascade, i.e., can be connected to each other in cascade. In other words, two or more single-ended amplifiers can form M stages of cascaded single-ended amplifiers. The M single-ended amplifier stages can achieve or provide the desired single-ended signal gain of the amplifier circuit (i.e., signal gain>1). The M single-ended amplifier stages can form a single-ended amplifier chain. N differential amplifier stages, the circuit of the first aspect, and the M single-ended amplifier stages can form an amplifier chain.

[0091] The above description of the circuit according to the first aspect is correspondingly applicable to the amplifier circuit according to the second aspect. The above description of the amplifier circuit according to the second aspect is correspondingly applicable to the circuit according to the first aspect.

[0092] The amplifier circuit of the second aspect and its implementations and optional features achieves the same advantages as the circuit of the first aspect and its corresponding implementations and corresponding optional features.

[0093] In order to implement the amplifier circuit according to the second aspect of the present invention, as described above, some or all of the implementations and optional features of the second aspect may be combined with each other.

[0094] All steps performed by the various entities described in this application and the functions to be performed by the various entities described are intended to refer to the corresponding entities for performing the corresponding steps and functions. Although in the description of the following specific embodiments, the specific functions or steps performed by the external entity are not reflected in the description of the specific detailed elements of the entity performing the specific steps or functions, it should be clear to the technician that these methods and functions can be implemented by corresponding software or hardware elements or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] In conjunction with the accompanying drawings, the following description of specific embodiments will illustrate the above aspects and their implementation methods, wherein:

[0096] Figure 1 Different examples of connecting a single-ended amplifier to a differential amplifier are shown;

[0097] Figure 2 and Figure 3 Circuit diagrams of examples of circuits for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier provided by embodiments of the present invention are respectively shown;

[0098] Figure 4 Shown for Figure 3 The first resistor and the second resistor of the circuit have different values, Figure 3 A diagram of the total harmonic distortion (THD) of a circuit;

[0099] Figure 5 Shown for Figure 3 The first resistor and the second resistor of the circuit have different values, Figure 3 A graph showing the relationship between the output even harmonics (output HD2) and the input even harmonics (input HD2) of the circuit;

[0100] Figure 6 It is shown that for Figure 3 An example of a circuit of a portion of a circuit, a graph of the variation of input capacitance with frequency;

[0101] Figure 7 Shown for Figure 3 A graph showing the variation of input capacitance with frequency at the first terminal and the second terminal of the circuit;

[0102] Figure 8 A circuit diagram showing an example of a circuit for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier provided by an embodiment of the present invention;

[0103] Fig. 9 Shown is the Figure 2 The second and third transistors of the circuit are biased Figure 2 An example of an implementation of a circuit;

[0104] Fig.10 A circuit diagram showing an example of a circuit for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier provided by an embodiment of the present invention;

[0105] Fig.11 Shows Fig.10 An example of the operating state of a circuit;

[0106] Fig.12 and Fig.13 Circuit diagrams of examples of circuits for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier provided by embodiments of the present invention are respectively shown;

[0107] Fig.14 A block diagram showing an example of an amplifier circuit provided by an embodiment of the present invention is shown.

[0108] In the figures, corresponding elements are marked with the same reference numerals. DETAILED DESCRIPTION

[0109] Figure 2 and Figure 3 Circuit diagrams showing examples of circuits for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier according to embodiments of the present invention are shown respectively. Figure 2 and Figure 3 The circuit of is an example of the circuit according to the first aspect of the present invention. Therefore, the description of the circuit according to the first aspect of the present invention is correspondingly applicable to Figure 2 and Figure 3 circuit.

[0110] Figure 2 The circuit 1 is used to convert the differential amplifier ( Figure 2 The two output terminals of the single-ended amplifier (not shown) are connected to Figure 2 1 . The circuit 1 includes: a first terminal T1 for electrically connecting to the first output terminal of the two output terminals of the differential amplifier; a second terminal T2 for electrically connecting to the second output terminal of the two output terminals of the differential amplifier; a third terminal T3 for electrically connecting to the input terminal of the single-ended amplifier; three transistors Q1, Q2, Q3, each transistor including a first terminal (respectively 11, 21, 31), a second terminal (respectively 12, 22, 32) and a third terminal (respectively 13, 23, 33). The third terminal 13 of the first transistor Q1 of the three transistors Q1, Q2 and Q3 is electrically connected to the first terminal T1 of the circuit 1. The third terminal 23 of the second transistor Q2 of the three transistors Q1, Q2 and Q3 is electrically connected to the second terminal T2 of the circuit 1. The third terminal 33 of the third transistor Q3 of the three transistors Q1, Q2 and Q3 is electrically connected to the second terminal 12 of the first transistor Q1. The second terminal 22 of the second transistor Q2, the first terminal 31 of the third transistor Q3 and the third terminal T3 of the circuit 1 are electrically connected to the node 3. The transconductance of the second transistor Q2 is equal to the transconductance of the third transistor Q3.

[0111] according to Figure 2In the example of circuit 1, transistors Q1, Q2 and Q3 can be bipolar-junction transistors (BJTs), respectively. In this case, the first terminals (11, 21, 31, respectively) of transistors Q1, Q2 and Q3 are collector terminals, the second terminals (12, 22, 32, respectively) of transistors Q1, Q2 and Q3 are emitter terminals, and the third terminals (13, 23, 33, respectively) of transistors Q1, Q2 and Q3 are base terminals. The present invention is not limited to the example that the transistors of the circuit are BJTs. Alternatively or in addition, the circuit may include at least other known transistor types. For example, transistors Q1, Q2 and Q3 of the circuit can be field-effect transistors (FETs), such as metal-oxide-semiconductor FETs (MOSFETs), respectively. In this case, the first terminals (11, 21, 31, respectively) of transistors Q1, Q2 and Q3 are drain terminals, the second terminals (12, 22, 32, respectively) of transistors Q1, Q2 and Q3 are source terminals, and the third terminals (13, 23, 33, respectively) of transistors Q1, Q2 and Q3 are gate terminals.

[0112] For the following description of the drawings, it is assumed that BJTs are used to implement the transistors of the circuit 1. As mentioned above, this is only an example and does not limit the present invention. The description of the circuit 1 including BJTs as transistors is correspondingly applicable to the case where the transistors of the circuit 1 are implemented using at least one other transistor type or in addition.

[0113] The first terminal 11 of the first transistor Q1 and the first terminal 21 of the second transistor Q2 can be used to electrically connect to a power source ( Figure 2 For example, the power supply may be a power supply for the circuit 1 (optionally a part of the circuit 1). The circuit 1 may include a bias circuit 2 for setting a current, and the second terminal 12 of the first transistor Q1 may be electrically connected to the bias circuit 2. The optional bias circuit 2 may include a current source 2a (eg Figure 2 As shown) or a resistor (not shown). Figure 2 As shown, the optional bias circuit 2 may be connected between the second terminal 12 of the first transistor Q1 and ground. The second terminal 32 of the third transistor Q3 may be electrically connected to ground.

[0114] like Figure 2As shown, the circuit 1 includes a pair of emitter follower stages (i.e., differential emitter follower stages). The pair of emitter follower stages is implemented or provided by a first transistor Q1 and a second transistor Q2 of the circuit 1. The circuit 1 includes a common emitter amplifier in the form of a third transistor Q3, the transconductance of the third transistor Q3 being the same as the transconductance of the second transistor Q2. The transconductance of the second transistor Q2 being equal to the transconductance of the third transistor Q3 can be achieved by designing the second transistor Q2 and the third transistor Q3 to be of equal size. The second transistor Q2 and the third transistor Q3 share the same DC current. Reference Fig. 9 An example of an optional bias circuit (second bias circuit) for setting a DC current (ie, providing a DC bias of the second transistor Q2 and the third transistor Q3) is described.

[0115] according to Figure 2 For example, the AC gain from the first terminal T1 of the circuit 1 to the third terminal T3 of the circuit 1 (assuming that no signal is applied to the second terminal T2 of the circuit 1) is 1 (AC gain = 1), because the first transistor Q1 is an emitter follower and the load impedance of the third transistor Q3 is equal to 1 / g m (where g m is the transconductance of the second transistor Q2, which is equal to the transconductance of the third transistor Q3). The second transistor Q2 and the third transistor Q3 may be two transistors biased at the same current.

[0116] according to Figure 2 In the example of FIG. 1 , the AC gain of the second terminal T2 of the circuit 1 to the third terminal T3 of the circuit 1 (assuming that no signal is applied to the first terminal T1 of the circuit 1) is also 1 (AC gain=1) because the second transistor Q2 acts as an emitter follower. In addition, the first transistor Q1 acts as a buffer for the third transistor Q3, providing a high input impedance for the previous stage (e.g., a differential amplifier to be connected to the first terminal T1 and the second terminal T2). This improves the overall radio frequency (RF) chain bandwidth when the circuit is part of an amplifier chain that connects a differential amplifier of the amplifier chain to a single-ended amplifier of the amplifier chain.

[0117] also, Figure 2 The circuit 1 (ie, the differential to single-ended converter) can suppress the common-mode signal at the first terminal T1 and the second terminal T2 of the circuit 1 (ie, at its input). Therefore, Figure 2 The circuit 1 can also suppress even-order harmonic distortion (HD2, HD4, etc.). In addition, if the parasitic (intrinsic) emitter resistors of the second transistor Q2 and the third transistor Q3 are negligible, their transconductance g m The nonlinearities cancel each other out.

[0118] If the parasitic emitter resistors of the second transistor Q2 and the third transistor Q3 are not negligible, the linearity can be optionally improved by adding two resistors with equal resistance (ie, two identical resistors) to the second transistor Q2 and the third transistor Q3, as described with respect to Figure 3 described.

[0119] like Figure 2 As exemplarily shown, the circuit 1 may be implemented by combining a differential emitter follower stage (implemented or provided by the first transistor Q1 and the second transistor Q2 ) with a degenerated common emitter amplifier (implemented or provided by the third transistor Q3 ). Figure 2 Circuit 1 implements a wide bandwidth, input impedance balanced differential to single-ended converter (balun) with high linearity. Figure 2 The circuit 1 includes transistors, so it is an active differential to single-ended converter (active balun).

[0120] Figure 3 The circuit corresponds to Figure 2 circuit, including additional optional features. Therefore, Figure 2 The description applies accordingly to Figure 3 circuit, and additional optional features are primarily described below.

[0121] like Figure 3 As shown, the circuit 1 includes a first resistor R1 and a second resistor R2 having equal resistance. That is, they have the same resistance. The second terminal 22 of the second transistor Q2 is electrically connected to the node 3 through the first resistor R1, and the second resistor R2 is electrically connected to the second terminal 32 of the third transistor Q3. As described above, the two resistors R1 and R2 improve the linearity of the circuit 1. In the following, in combination Figures 4 to 7 Describe by way of example Figure 3 The characteristics of circuit 1 also apply to Figure 2 and Figures 8 to 13 circuit.

[0122] Figure 4 Shown for Figure 3 The first resistor and the second resistor of the circuit have different values, Figure 3 A graph of the total harmonic distortion (THD) of a circuit.

[0123] Figure 4 The y-axis of the middle graph shows total harmonic distortion (THD) in percentage (%), wherein the larger the THD is, the lower the linearity of the circuit is, and vice versa. Figure 4The x-axis of the middle diagram shows different values ​​of the second resistor R2 between 0Ω (ie, no second resistor R2 exists) and 5Ω. In the following table, different values ​​of the first resistor R1 for different curves S0 to S5 are shown:

[0124] Figure 4 Curve number in the middle figure Figure 3 The value of the first resistor R1 of the circuit (Ω) S0 0 S1 1 S2 2 S3 3 S4 4 S5 5

[0125] exist Figure 4 In the figure, the dashed circle of curve S0 shows Figure 2 Because at the dotted circle of the curve S0, the values ​​of the first resistor R1 and the second resistor R2 are equal to 0Ω. In other words, the dotted circle of the curve S0 shows the case where the first resistor R1 and the second resistor R2 are not part of the circuit, as shown in FIG. Figure 2 The dashed circles of curves S1 to S5 show Figure 3 Because at the dotted circle of the curves S1 to S5, the first resistor R1 and the second resistor R2 have equal resistance (ie, they have the same resistance).

[0126] from Figure 4 It can be deduced that Figure 2 The linearity of the circuit (i.e., without the first resistor R1 and the second resistor R2 connected to the second transistor Q2 and the third transistor Q3 of the circuit 1) is better than that of the circuit in which only the first resistor R1 is added Figure 2 In the case of the circuit (ie, the second resistor R2 is equal to 0Ω). In addition, Figure 4 Shown with Figure 2 Compared with the circuit Figure 3 In other words, by adding the first resistor R1 and the second resistor R2 having equal resistance to Figure 2 The circuit thus formed Figure 3 The circuit can improve Figure 2 In addition, Figure 3 The larger the same resistance of the first resistor R1 and the second resistor R2 of circuit 1, the smaller the THD, therefore, Figure 3 The larger or better the linearity of circuit 1.

[0127] Figure 5 Shown for Figure 3 The first resistor and the second resistor of the circuit have different values, Figure 3 A graph showing the relationship between the output even harmonics (output HD2) and the input even harmonics (input HD2) of the circuit.

[0128] Figure 5 The y-axis of the graph shows output even harmonics expressed in mV, such as output second harmonic distortion (HD2). Figure 5The x-axis of the graph of shows input even harmonics, such as input second harmonic distortion (HD2), expressed in mV. In the following table, different values ​​of the first resistor R1 and the second resistor R2 for different curves S6 to S9 are shown:

[0129]

[0130] from Figure 5 It can be deduced that curve S7 shows Figure 2 Because for curve S7, the values ​​of the first resistor R1 and the second resistor R2 are equal to 0Ω. In other words, curve S7 shows the case where the first resistor R1 and the second resistor R2 are not part of the circuit, as shown in FIG. Figure 2 Curve S6 shows Figure 3 Because for the curve S6, the first resistor R1 and the second resistor R2 have equal resistance of 5Ω (ie, they have the same resistance).

[0131] from Figure 5 It can be deduced that Figure 2 Compared with the case where the circuit only includes the first resistor R1 having a resistance of 5Ω (see curve S9) or the second resistor R2 having a resistance of 5Ω (see curve S8), Figure 2 circuit (see curve S7) and Figure 3 The circuit (see curve S6) has better even-order harmonic suppression (such as HD2 suppression). Figure 2 Compared with the even-order harmonic suppression (e.g., HD2 suppression) of the circuit (i.e., the first resistor R1 and the second resistor R2 do not exist), Figure 3 The even-order harmonic suppression (eg, HD2 suppression) of the circuit with a first resistor R1 and a second resistor R2 having equal resistance is better. Figure 3 The greater the equal resistance of the first resistor R1 and the second resistor R2 of the circuit, Figure 3 The better the circuit's even-order harmonic suppression (such as HD2 suppression) is ( Figure 5 not shown).

[0132] Figure 6 It is shown that for Figure 3 An example of a circuit of a portion of a circuit, with a graph of the input capacitance varying with frequency.

[0133] Figure 6 The circuit showing the variation of input capacitance with frequency corresponds to Figure 3A circuit of the type shown in FIG. 1 does not include a left branch including a first transistor Q1 and an optional bias circuit 2. Therefore, in this circuit example, the third terminal 33 of the third transistor Q3 is connected to the first terminal T1 of the circuit. The first resistor R1 and the second resistor R2 of this circuit example have equal resistance. In other words, Figure 6 Shows that for Figure 3 Circuit 1 removes the input emitter follower formed by the first transistor Q1 for driving the common emitter stage formed by the third transistor Q3, and the input capacitance varies with frequency. This circuit example is Figure 6 is shown on the right side. Figure 6 The y-axis of the graph shows the input capacitance expressed in fF. Figure 6 The x-axis of the graph shows the frequency in GHz. Curve S10 shows Figure 6 The input capacitance of the second terminal T2 of the circuit shown on the right varies with frequency. Curve S11 shows Figure 6 The circuit on the right shows the frequency-dependent input capacitance of the first terminal T1.

[0134] from Figure 6 The curves S10 and S11 can be deduced, Figure 6 The input capacitances of the two terminals T1 and T2 of the circuit are different from each other, and the two output terminals of the differential amplifier can be connected to these two terminals. The smaller the frequency, the greater the difference between the two input capacitances. In other words, Figure 6 The two input impedances (i.e., input capacitances) of the circuit are unbalanced. In contrast, Figure 3 The circuit can achieve a balance between the two input impedances (i.e., input capacitances) until very high frequencies, such as Figure 7 This applies to Figure 2 and Figures 8 to 13 circuit.

[0135] Figure 7 Shown for Figure 3 A graph of the first and second terminals of the circuit, and the variation of input capacitance with frequency.

[0136] Figure 7 The y-axis of the graph shows the input capacitance expressed in fF. Figure 7 The x-axis of the graph shows the frequency in GHz. Curve S12 shows Figure 3 The input capacitance of the first terminal T1 of the circuit 1 varies with frequency. Curve S13 shows Figure 3 The input capacitance of the second terminal T2 of circuit 1 varies with frequency. Figure 3In the circuit of , there is an emitter follower in the form of a first transistor Q1 driving a common emitter stage in the form of a third transistor Q3, so that a good balance (almost perfect balance) can be achieved between the two input impedances (i.e. input capacitances) up to very high frequencies. This applies correspondingly to Figure 2 and Figures 8 to 13 circuit.

[0137] Figure 8 A circuit diagram showing an example of a circuit for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier provided by an embodiment of the present invention.

[0138] Figure 8 The circuit corresponds to Figure 3 circuit, including additional optional features. Therefore, Figures 2 to 7 The description applies accordingly to Figure 8 circuit, and additional optional features are primarily described below.

[0139] like Figure 8 As shown, circuit 1 may include three inductors, namely a first inductor L1, a second inductor L2, and a third inductor L3. The second terminal 22 of the second transistor Q2 may be electrically connected to node 3 via an optional first resistor R1 and the first inductor L1. The first resistor R1 and the first inductor L1 may be electrically connected in series. The first terminal 31 of the third transistor Q3 may be electrically connected to node 3 via the second inductor L2. The third terminal T3 of circuit 1 may be electrically connected to node 3 via the third inductor L3. The three inductors L1, L2, and L3 may be present in circuit 1, while the optional first resistor R1 and the optional second resistor R2 are not present in circuit 1. In this case, the second terminal 22 of the second transistor Q2 may be electrically connected to node 3 via the first inductor L1. This optional case (without resistors R1 and R2) corresponds to Figure 2 The circuit includes Figure 8 The optional three inductors L1, L2 and L3.

[0140] Inductors L1, L2 and L3 support extending the bandwidth of circuit 1. That is, arranging inductors L1, L2 and L3 in circuit 1 creates a resonant network (eg, some kind of resonant network). Inductors L1, L2 and L3 can extend the maximum operating frequency of circuit 1.

[0141] Circuit 1 is not limited to Figure 8 According to an alternative solution ( Figure 8 not shown), Figure 8 The circuit 1 may include only two inductors, for example, Figure 8 a first inductor L1 and a second inductor L2; or Figure 8A first inductor L1 and a third inductor L3; or Figure 8 The second inductor L2 and the third inductor L3 are respectively provided. The two inductors can be configured as follows: Figure 8 In the optional case above with only two inductors, Figure 8 The circuit 1 may include or not include the first resistor R1 and the second resistor R2. According to another optional alternative ( Figure 8 not shown), Figure 8 The circuit may consist of only one inductor, for example Figure 8 a first inductor L1; or Figure 8 a second inductor L2; or Figure 8 The corresponding inductor can be as follows: Figure 8 In another optional case where there is only one inductor, Figure 8 The circuit may include or exclude the first resistor R1 and the second resistor R2.

[0142] Fig. 9 Shown is the Figure 2 The second and third transistors of the circuit are biased Figure 2 An example of an implementation of a circuit. Figure 2 The above description applies accordingly to Fig. 9 In the following, the main description is Fig. 9 Additional optional features that can be added to Figure 2 The circuit is used to realize Figure 2 An example of biasing the second transistor Q2 and the third transistor Q3 of the circuit 1. Fig. 9 The description of Figure 3 and Figure 8 An example of biasing the second transistor Q2 and the third transistor Q3 of the circuit.

[0143] Fig. 9 The circuit 1 includes a current sensing circuit 5 and a level converter circuit 4 for converting a current level. The third terminal 13 of the first transistor Q1 is connected to the first terminal T1 of the circuit 1 through the level converter circuit 4. The current sensing circuit 5 is used to sense the current flowing through the second transistor Q2 and the third transistor Q3. The level converter circuit 4 is used to change the DC voltage at the third terminal 13 of the first transistor Q1 by changing the current supplied from the first terminal T1 of the circuit 1 to the level converter circuit 4 according to the current sensed by the current sensing circuit 5.

[0144] like Fig. 9As shown, the level converter circuit 4 may include a series connection of two resistors R5 and R6. The optional series connection of the two resistors R5 and R6 may be connected between the first terminal T1 of the circuit 1 and the third terminal 13 of the first transistor Q1. That is, the first terminal 11 of the first transistor Q1 may be electrically connected to the first terminal T1 of the circuit 1 through the series connection of the two resistors R5 and R6 of the level converter circuit 4. In addition, the level converter circuit 4 may include a transistor Q7 connected to a node between the two resistors R5 and R6 of the series connection of the two resistors R5 and R6. The circuit 1 may be configured such that a control signal based on the current sensed by the current sensing circuit 5 is provided to the control terminal 73 of the transistor Q7. Optionally, the capacitor C1 may be electrically connected in parallel to the series connection of the two resistors R5 and R6. As Fig. 9 As shown, transistor 7 can be a FET (e.g., a MOSFET), wherein the control terminal 73 of the transistor is the gate terminal of the FET, and the drain terminal of the FET can be connected to the node between the two resistors R5 and R6. Transistor 7 can be implemented in different ways, for example, by any other transistor type.

[0145] like Fig. 9 As shown, the current sensing circuit 5 may include a sensing resistor R7 (e.g., a shunt resistor) for sensing the current flowing through the second transistor Q2 and the third transistor Q3. The sensing resistor R7 is connected to the first terminal 21 of the second transistor Q2. For example, the first terminal 21 of the second transistor Q2 may be connected to a power source through the sensing resistor R7. For example, the power source may be a power source for the circuit (optionally a part of the circuit). Optionally, the current sensing circuit 5 may include a capacitor C2, which is electrically connected in parallel to the sensing resistor R7, such as Fig. 9 A capacitor C2 may be provided to short-circuit the sensing resistor R7 at high frequencies (ie, at frequencies greater than a threshold frequency).

[0146] like Fig. 9 As shown, the circuit 1 may include a comparator 7 for setting a desired current and a second bias circuit 6. The comparator 7 may be used to compare the current sensed by the current sensing circuit 5 with the desired current. The level converter circuit 4 may be used to change the current supplied from the first terminal T1 of the circuit 1 to the level converter circuit 4 according to the comparison result of the comparator 7.

[0147] The second bias circuit 6 may be a replica bias circuit scaled by a factor Z to provide a desired current. The second bias circuit 6 may include a scaling resistor R9 and a current source 6a electrically connected in series to each other, wherein the second bias circuit 6 may be used to provide a desired current at a node between the scaling resistor R9 and the current source 6a. The resistance of the scaling resistor R9 may be scaled by a factor Z, or may be greater than the resistance of the sensing resistor R7 of the current sensing circuit 5 by a factor Z (R9=Z*R7). The desired current may be set or changed by the factor Z. Optionally, the current source 6a may be used to provide an adjustable current for adjusting or changing the desired current.

[0148] like Fig. 9 As shown, the current sensed by the current sensing circuit 5 (e.g., the sensing resistor R7) can be provided to the comparator 7 through another resistor R8. The other resistor R8 can be connected to the first terminal 21 of the second transistor Q2. Optionally, the other resistor R8 can be part of the current sensing circuit 5, such as Fig. 9 The comparator 7 may include an operational amplifier or be implemented by an operational amplifier, such as Fig. 9 As shown. The current sensing circuit 5 (e.g., sensing resistor R7) can be connected to the inverting input of the operational amplifier (optionally through another resistor R8) for providing the sensed current to the comparator 7. The second bias circuit 6 (e.g., a node between the scaling resistor R9 and the current source 6a) can be connected to the non-inverting input of the operational amplifier for providing the desired current to the comparator 7.

[0149] Optionally, the level converter circuit 4 may be arranged with Figure 8 For example, the third terminal 33 of the third transistor Q3 can be connected to the level converter circuit 4 ( Fig. 9 The level converter circuit 4 is electrically connected to the second terminal 12 of the first transistor Q1 (not shown). In this case, the level converter circuit 4 can be used to change the current supplied from the second terminal 12 of the first transistor Q1 to the third terminal 33 of the third transistor Q3 according to the current sensed by the current sensing circuit 5. To this end, the optional series connection of the two resistors R5 and R6 of the level converter circuit 4 can be connected between the second terminal 12 of the first transistor Q1 and the third terminal 33 of the third transistor Q3. That is, the third terminal 33 of the third transistor Q3 can be electrically connected to the second terminal 12 of the first transistor Q1 through the series connection of the two resistors R5 and R6 of the level converter circuit 4. In the above optional case, the level converter circuit 4 can be used to change the current supplied from the second terminal 12 of the first transistor Q1 to the third terminal 33 of the third transistor Q3 according to the comparison result of the optional comparator 7.

[0150] Level converter circuit 4 (whether it is Fig. 9As shown in the arrangement, or as in Fig. 9 The above different examples of arranging the level shifter circuit in the circuit of FIG. 1 support biasing the second transistor Q2 and the third transistor Q3. This supports DC coupling (ie very low AC cutoff).

[0151] Fig.10 The circuit diagram of the embodiment of the present invention for connecting two output terminals of a differential amplifier to the input terminal of a single-ended amplifier is shown.

[0152] Fig.10 The circuit corresponds to Figure 2 circuit, including additional optional features. Therefore, Figures 2 to 9 The description applies to Fig.10 circuit, and additional optional features are primarily described below.

[0153] like Fig.10 As shown, except Figure 2 In addition to the components of Circuit 1, Fig.10 The circuit 1 also includes a fourth transistor Q4, a fifth transistor Q5 and a sixth transistor Q6, each of which includes a first terminal (41, 51, 61, respectively), a second terminal (42, 52, 62, respectively) and a third terminal (43, 53, 63, respectively). The circuit 1 includes a first level converter circuit 10, a second level converter circuit 11 and a fourth terminal T4. The third terminal 23 of the second transistor Q2 is electrically connected to the second terminal T2 of the circuit 1 through the fourth transistor Q4, wherein the third terminal 23 of the second transistor Q2 is electrically connected to the second terminal 42 of the fourth transistor Q4, and the third terminal 43 of the fourth transistor Q4 is electrically connected to the second terminal T2 of the circuit 1. The third terminal 53 of the fifth transistor Q5 is electrically connected to the second terminal 12 of the first transistor Q1. The third terminal 53 of the fifth transistor Q5 is electrically connected to the third terminal 33 of the third transistor Q3 through the first level converter circuit 10. That is, the third terminal 33 of the third transistor Q3 is connected to the second terminal 12 of the first transistor Q1 through the first level converter circuit 10. The second terminal 52 of the fifth transistor Q5, the first terminal 61 of the sixth transistor Q6, and the fourth terminal T4 of the circuit 1 are electrically connected to the second node 8. The third terminal 23 of the second transistor Q2 is electrically connected to the third terminal 63 of the sixth transistor Q3 through the second level converter circuit 11. That is, the third terminal 63 of the sixth transistor Q6 is connected to the second terminal 42 of the fourth transistor Q2 through the second level converter circuit 11. The transconductance of the fifth transistor Q5 is equal to the transconductance of the sixth transistor Q6.

[0154] Fig.10The circuit 1 can be used to connect the two output terminals of the differential amplifier to the two input terminals of another differential amplifier, or to connect the two output terminals of the differential amplifier to the input terminals of a single-ended amplifier circuit, according to the functional configuration of the circuit 1. The functional configuration of the circuit 1 can be controlled by the first level shifter circuit 10 and the second level shifter circuit 11. In other words, the circuit can be configured to change from a differential push-pull amplifier configuration (such as Fig.10 ) or reconfigured as a differential to single-ended converter (or balun) configuration (as shown Fig.11 exemplarily shown).

[0155] exist Fig.10 In the circuit 1 (i.e., in the differential push-to-disconnect amplifier configuration), the second transistor Q2 and the fifth transistor Q5 can act as differential emitter followers, and the third transistor Q3 and the sixth transistor Q6 (connected to the first level converter circuit 10 and the second level converter circuit 11) can act as differential degenerate common emitter amplifiers. When the circuit 1 is in the differential push-to-disconnect amplifier configuration, the circuit can be used to provide a 6dB differential gain.

[0156] like Fig.10 As shown, optionally, the first terminal 41 of the fourth transistor Q4 and the first terminal 51 of the fifth transistor Q5 are respectively used to be electrically connected to a power source ( Fig.10 1 ). For example, the power supply may be a power supply for the circuit 1 (optionally a part of the circuit 1). Optionally, the circuit 1 includes a bias circuit 9 (e.g., a second bias circuit or a third bias circuit) for setting a current, and the second terminal 42 of the fourth transistor Q4 may be electrically connected to the bias circuit 9. The bias circuit 9 may be used to set a current flowing through the fourth transistor Q4 via the first terminal 41 and the second terminal 42 of the fourth transistor Q4. The optional bias circuit 9 may include a current source (e.g., Fig.10 As shown) or a resistor (not shown). Fig.10 As shown, an optional bias circuit 9 may be connected between the second terminal 42 of the fourth transistor Q4 and ground. A second terminal 62 of the sixth transistor Q6 may be electrically connected to ground.

[0157] Optionally, the second transistor Q2 , the third transistor Q3 , the fifth transistor Q5 , and the sixth transistor Q6 have the same transconductance.

[0158] The second level shifter circuit 11 may be used to set the current flowing through the fifth transistor Q5 and the sixth transistor Q6 to zero ampere in case a single-ended amplifier is to be electrically connected to the third terminal T3 of the circuit 1 . Fig.11This state is exemplarily shown. To this end, the first level converter circuit 10 can be used to set the current flowing through the second transistor Q2 and the third transistor Q3 to a current value greater than zero ampere. In the above example, in the case where the single-ended amplifier is to be electrically connected to the fourth terminal T4 of the circuit 1, the operations of the second level converter circuit 11 and the first level converter circuit 10 can be switched.

[0159] The second level converter circuit 11 may be used to set the current flowing through the fifth transistor Q5 and the sixth transistor Q6 to a current value greater than zero ampere when another differential amplifier is electrically connected to the third terminal T3 and the fourth terminal T4 of the circuit 1. To this end, the first level converter circuit 11 may be used to set the current flowing through the second transistor Q2 and the third transistor Q3 to a current value greater than zero ampere.

[0160] Therefore, the first level shifter circuit 10 can be used to open the first branch of the circuit 1 including the second transistor Q2 and the third transistor Q3 by setting the current flowing through the second transistor Q2 and the third transistor Q3 to zero ampere. Therefore, the first level shifter circuit 10 can be used to close the first branch of the circuit 1 including the second transistor Q2 and the third transistor Q3 by setting the current flowing through the second transistor Q2 and the third transistor Q3 to a current value greater than zero ampere. The second level shifter circuit 11 can be used to open the second branch of the circuit 1 including the fifth transistor Q5 and the sixth transistor Q6 by setting the current flowing through the fifth transistor Q5 and the sixth transistor Q6 to zero ampere. Therefore, the second level shifter circuit 11 can be used to close the second branch of the circuit 1 including the fifth transistor Q5 and the sixth transistor Q6 by setting the current flowing through the fifth transistor Q5 and the sixth transistor Q6 to a current value greater than zero ampere.

[0161] Fig.11 Shows Fig.10 An example of the operating state of the circuit. Fig.11 In the operating state of the second level converter circuit 11, by setting the current flowing through the fifth transistor Q5 and the sixth transistor Q6 to zero ampere, the second level converter circuit 11 has disconnected the second branch of the circuit 1 including the fifth transistor Q5 and the sixth transistor Q6. Therefore, with regard to its function, Fig.11 The circuit 1 corresponds to Figure 2 Circuit 1, because Fig.11 The circuit 1 supports differential to single-ended conversion (ie, the two output terminals of the differential amplifier can be connected to the first terminal T1 and the second terminal T2 of the circuit 1 , and the input terminal of the single-ended amplifier can be connected to the third terminal T3 of the circuit 1 ).

[0162] Fig.12 and Fig.13Circuit diagrams showing examples of circuits for connecting two output terminals of a differential amplifier to an input terminal of a single-ended amplifier according to embodiments of the present invention are shown respectively.

[0163] Fig.12 The circuit corresponds to Fig.10 The circuit, except Figure 3 In addition to the optional features of the first resistor R1 and the second resistor R2 of the circuit, additional optional features are included. Therefore, Figures 2 to 11 The description applies to Fig.12 circuit, and additional optional features are primarily described below.

[0164] like Fig.12 As shown, the circuit 1 may include a third resistor R3 and a fourth resistor R4 having equal resistance. The second terminal 52 of the fifth transistor Q5 may be electrically connected to the second node 8 through the third resistor R3. The fourth resistor R4 may be electrically connected to the second terminal 62 of the sixth transistor Q6. By adding the optional first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 to the circuit 1, the linearity of the circuit 1 may be improved.

[0165] Fig.13 The circuit corresponds to Fig.12 The circuit, except Figure 8 In addition to the optional features of the first inductor L1, the second inductor L2 and the third inductor L3 of the circuit, additional optional features are included. Therefore, Figures 2 to 12 The description applies to Fig.13 circuit, and additional optional features are primarily described below.

[0166] like Fig.13 As shown, circuit 1 may include three additional inductors, namely a fourth inductor L4, a fifth inductor L5 and a sixth inductor L6. The second terminal 52 of the fifth transistor Q5 may be electrically connected to the second node 8 via the third resistor R3 and the fourth inductor L4. The third resistor R3 and the fourth inductor L4 may be electrically connected in series. The first terminal 61 of the sixth transistor Q6 may be electrically connected to the second node 8 via the fifth inductor L5. The fourth terminal T4 of circuit 1 may be electrically connected to the second node 8 via the sixth inductor L6. The three inductors L4, L5 and L6 may be present in circuit 1, while the optional third resistor R3 and the optional fourth resistor R4 are not present in circuit 1. In this case, the second terminal 52 of the fifth transistor Q5 may be electrically connected to the second node 8 via the fourth inductor L4. In this case, the optional first resistor R1 and the second resistor R2 may not be part of the circuit. This optional case (without resistors R1, R2, R3 and R4) corresponds to Fig.10 The circuit includes Figure 8 or Fig.13 The optional three inductors L1, L2 and L3 and Fig.13 The optional three inductors L4, L5 and L6.

[0167] Inductors L4, L5 and L6 support extending the bandwidth of circuit 1. That is, arranging inductors L4, L5 and L6 in the circuit creates a resonant network (eg, some kind of resonant network). Inductors L4, L5 and L6 can extend the maximum operating frequency of circuit 1.

[0168] Circuit 1 is not limited to Fig.13 According to an alternative embodiment, Fig.13 The circuit may consist of only four inductors, for example, Fig.13 a first inductor L1, a second inductor L2, a fourth inductor L4 and a fifth inductor L5; or Fig.13 a first inductor L1, a third inductor L3, a fourth inductor L4 and a sixth inductor L6; or Fig.13 The second inductor L2, the third inductor L3, the fifth inductor L5 and the sixth inductor L6. In other words, Fig.13 The circuit may include only four inductors among the inductors L1, L2, L3, L4, L5 and L6, so that the four inductors are arranged symmetrically. Fig.13 In the optional case above with only four inductors, Fig.13 The circuit may include or exclude the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4.

[0169] According to another optional alternative, Fig.13 The circuit may consist of only two inductors, for example, Fig.13 a first inductor L1 and a fourth inductor L4; or Fig.13 a second inductor L2 and a fifth inductor L5; or Fig.13 The third inductor L3 and the sixth inductor L6. In other words, Fig.13 The circuit may include only two inductors among the inductors L1, L2, L3, L4, L5 and L6, so that the two inductors are arranged symmetrically. Fig.13 In another alternative case where there are only two inductors, Fig.13 The circuit may include or exclude the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4.

[0170] about Figure 2 , Figure 3 and Figures 8 to 13For further details of the circuit, refer to the description of the circuit according to the first aspect of the invention.

[0171] Fig.14 A block diagram showing an example of an amplifier circuit provided by an embodiment of the present invention is shown. Fig.14 The amplifier circuit of is an example of the amplifier circuit according to the second aspect of the present invention. Therefore, the description of the amplifier circuit according to the second aspect of the present invention applies to Fig.14 Amplifier circuit.

[0172] Fig.14 The amplifier circuit 100 comprises a differential amplifier 101 having a first output terminal OUT1 and a second output terminal OUT2 according to the first aspect of the present invention, a single-ended amplifier 102 having an input terminal IN3, and a circuit 1. The circuit 1 may be Figure 2 , Figure 3 and Figures 8 to 13 Therefore, for further information about the circuit 1 of the amplifier circuit 100, reference is made to the description of the circuit according to the first aspect and Figures 2 to 13 Description of Fig.14 As shown, the first output terminal OUT1 of the differential amplifier 101 can be electrically connected to the first terminal T1 of the circuit 1. The second output terminal OUT2 of the differential amplifier 101 can be electrically connected to the second terminal T2 of the circuit 1. The input terminal IN3 of the single-ended amplifier 102 can be electrically connected to the third terminal T3 of the circuit 1. Therefore, in the amplifier circuit 100, the circuit 1 supports differential to single-ended conversion, that is, the two output terminals OUT1 and OUT2 of the differential amplifier 101 are connected to the input terminal IN3 of the single-ended amplifier 102. This connection is provided by the circuit 1.

[0173] Optionally, the two input terminals IN1 and IN2 of the differential amplifier 101 may be electrically connected to another differential amplifier ( Fig.14 That is, optionally, the amplifier circuit 100 may include two or more differential amplifier stages (e.g., differential amplifier 101 and the above-mentioned other differential amplifiers), which may be connected to each other in cascade, i.e., they may be connected to each other in cascade. The differential amplifier 101 or the above-mentioned optional two or more differential amplifier stages may achieve or provide the desired differential signal gain (i.e., signal gain>1) of the amplifier circuit 100.

[0174] Optionally, the output terminal OUT3 of the single-ended amplifier 102 can be electrically connected to another single-ended amplifier ( Fig.14That is, optionally, the amplifier circuit 100 may include two or more single-ended amplifier stages (e.g., the single-ended amplifier 102 and the other single-ended amplifiers described above), which may be connected to each other in cascade, i.e., they may be connected to each other in cascade. The single-ended amplifier 102 or the optional two or more single-ended amplifier stages described above may achieve or provide a desired single-ended signal gain (i.e., signal gain>1) of the amplifier circuit 100.

[0175] The invention has been described in conjunction with various embodiments. However, from study of the invention, other variations of the invention will be understood and implemented by those skilled in the art when implementing the claimed subject matter. In the claims and in the specification, the word "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. A single element or other unit may fulfil the functions of several entities or items described in the claims. The enumeration of certain measures in mutually different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A circuit (1) for connecting two output terminals (OUT1, OUT2) of a differential amplifier (101) to an input terminal (IN3) of a single-ended amplifier (102), characterized in that: The circuit (1) comprises: - a first terminal (T1) for electrically connecting to a first output terminal (OUT1) of the two output terminals (OUT1, OUT2) of the differential amplifier (101); - a second terminal (T2) for being electrically connected to a second output terminal (OUT2) of the two output terminals (OUT1, OUT2) of the differential amplifier (101); - a third terminal (T3) for electrically connecting to the input terminal (IN3) of the single-ended amplifier (102); - three transistors (Q1, Q2, Q3), each transistor comprising a first terminal (11; 21; 31), a second terminal (12; 22; 32) and a third terminal (13; 23; 33); wherein - the third terminal (13) of the first transistor (Q1) of the three transistors (Q1, Q2, Q3) is electrically connected to the first terminal (T1) of the circuit (1), - the third terminal (23) of the second transistor (Q2) of the three transistors (Q1, Q2, Q3) is electrically connected to the second terminal (T2) of the circuit (1), - the third terminal (33) of the third transistor (Q3) of the three transistors (Q1, Q2, Q3) is electrically connected to the second terminal (12) of the first transistor (Q1), - the second terminal (22) of the second transistor (Q2), the first terminal (31) of the third transistor (Q3) and the third terminal (T3) of the circuit (1) are electrically connected to a node (3), - the transconductance of the second transistor (Q2) is equal to the transconductance of the third transistor (Q3).

2. The circuit (1) according to claim 1, characterized in that Each respective one of the three transistors (Q1, Q2, Q3) is one of the following: - a bipolar junction transistor (BJT), wherein the first terminal of the BJT is a collector terminal, the second terminal of the BJT is an emitter terminal, and the third terminal of the BJT is a base terminal; - A field-effect transistor (FET), wherein the first terminal of the FET is a drain terminal, the second terminal of the FET is a source terminal, and the third terminal of the FET is a gate terminal.

3. The circuit (1) according to claim 1 or 2, characterized in that The first terminal (11) of the first transistor (Q1) and the first terminal (21) of the second transistor (Q2) are respectively adapted to be electrically connected to a power source.

4. The circuit (1) according to any one of the preceding claims, characterized in that - the circuit (1) comprises a bias circuit (2) for setting a current, - the second terminal (12) of the first transistor (Q1) is electrically connected to the bias circuit (2).

5. The circuit (1) according to claim 4, characterized in that - The bias circuit (2) comprises a current source (2a) or a resistor.

6. The circuit (1) according to any one of the preceding claims, characterized in that - the circuit (1) comprises a first resistor (R1) and a second resistor (R2) having equal resistance, - the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor (R1), - said second resistor (R2) is electrically connected to said second terminal (32) of said third transistor (Q3).

7. The circuit (1) according to any one of claims 1 to 5, characterized in that The circuit (1) comprises an inductor, wherein the inductor is arranged such that one of the following is true: - the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the inductor, - the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the inductor, - the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the inductor.

8. The circuit (1) according to any one of claims 1 to 5, characterized in that - the circuit (1) comprises a first resistor and a second resistor having equal resistance, and an inductor, - the second resistor is electrically connected to the second terminal (32) of the third transistor (Q3), - the first resistor and the inductor are arranged such that one of the following holds true: - the second terminal (22) of the second transistor (Q2) is electrically connected to the - the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor, and the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the inductor; The second terminal (22) of the second transistor is electrically connected to the node (3) via the first resistor, and the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the inductor.

9. The circuit (1) according to any one of claims 1 to 5, characterized in that The circuit comprises a first inductor and a second inductor, wherein the first inductor and the second inductor are arranged such that one of the following is true: - the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first inductor, and the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the second inductor; - the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first inductor, and the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the second inductor; - the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the first inductor, and the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the second inductor.

10. The circuit (1) according to any one of claims 1 to 5, characterized in that - the circuit (1) comprises a first resistor and a second resistor having equal resistance, a first inductor and a second inductor, - the second resistor is electrically connected to the second terminal (32) of the third transistor (Q3), - the first resistor, the first inductor and the second inductor are arranged such that one of the following holds true: - the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor and the first inductor, and the third terminal (T3) of the circuit is electrically connected to the node (3) via the second inductor; - the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor and the first inductor, and the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the second inductor; - the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor, the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the first inductor, and the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the second inductor.

11. The circuit (1) according to any one of claims 1 to 5, characterized in that The circuit (1) comprises a first inductor, a second inductor and a third inductor, wherein: - the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first inductor, - the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the second inductor, - the third terminal (T3) of the circuit (1) is electrically connected to the node (3) via the third inductor.

12. The circuit (1) according to any one of claims 1 to 5, characterized in that - the circuit (1) comprises a first resistor (R1) and a second resistor (R2) having equal resistance, a first inductor (L1), a second inductor (L2) and a third inductor (L3), - the second resistor (R2) is electrically connected to the second terminal (32) of the third transistor (Q3), - the second terminal (22) of the second transistor (Q2) is electrically connected to the node (3) via the first resistor (R1) and the first inductor (L1), - the first terminal (31) of the third transistor (Q3) is electrically connected to the node (3) via the second inductor (L2), - the third terminal (T3) of the circuit is electrically connected to the node (3) via the third inductor (L3).

13. The circuit (1) according to any one of the preceding claims, characterized in that - the circuit (1) comprises a level converter circuit (4) for converting a current level and a current sensing circuit (5), - the third terminal (13) of the first transistor (Q1) is electrically connected to the first terminal (T1) of the circuit (1) via the level converter circuit (4), - the current sensing circuit (5) is used to sense the current flowing through the second transistor (Q2) and the third transistor (Q3), - the level converter circuit (4) is used to change the DC voltage at the third terminal (13) of the first transistor (Q1) by changing the current supplied from the first terminal (T1) of the circuit (1) to the level converter circuit (4) according to the current sensed by the current sensing circuit (5).

14. The circuit (1) according to any one of claims 1 to 12, characterized in that - the circuit comprises a level converter circuit (4) for converting a current level and a current sensing circuit (5), - the third terminal (33) of the third transistor (Q3) is electrically connected to the second terminal (12) of the first transistor (Q1) via the level shifter circuit (4), - the current sensing circuit (5) is used to sense the current flowing through the second transistor (Q2) and the third transistor (Q3), - the level converter circuit (4) is used to change the current supplied from the second terminal (12) of the first transistor (Q1) to the third terminal (33) of the third transistor (Q3) according to the current sensed by the current sensing circuit (5).

15. The circuit (1) according to claim 13 or 14, characterized in that - the circuit (1) comprises a second bias circuit (6) for setting a desired current and a comparator (7), - the comparator (7) is used to compare the current sensed by the current sensing circuit (5) with the expected current, - the level converter circuit (4) is used to change the current supplied from the first terminal (T1) of the circuit (1) to the level converter circuit (4) and the current supplied from the second terminal (12) of the first transistor (Q1) to the third terminal (33) of the third transistor (Q3) respectively according to the comparison result of the comparator (7).

16. The circuit (1) according to any one of claims 1 to 12, characterized in that - the circuit comprises a fourth transistor (Q4), a fifth transistor (Q5) and a sixth transistor (Q6), each transistor comprising a first terminal (41; 51; 61), a second terminal (42; 52; 62) and a third terminal (43; 53; 63), a first level shifter circuit (10), a second level shifter circuit (11) and a fourth terminal (8); - the third terminal (23) of the second transistor (Q2) is electrically connected to the second terminal (T2) of the circuit (1) via the fourth transistor (Q4), wherein the third terminal (23) of the second transistor (Q2) is electrically connected to the second terminal (42) of the fourth transistor (Q4), and the third terminal (43) of the fourth transistor (Q4) is electrically connected to the second terminal (T2) of the circuit (1); - said third terminal (53) of said fifth transistor (Q5) is electrically connected to said second terminal (12) of said first transistor (Q1); - the third terminal (53) of the fifth transistor (Q5) is electrically connected to the third terminal (33) of the third transistor (Q3) through the first level converter circuit (10); - the second terminal (52) of the fifth transistor (Q5), the first terminal (61) of the sixth transistor (Q6) and the fourth terminal (T4) of the circuit (1) are electrically connected to a second node (8); - the third terminal (23) of the second transistor (Q2) is electrically connected to the third terminal (63) of the sixth transistor (Q6) via the second level shifter circuit (11); - the transconductance of the fifth transistor (Q5) is equal to the transconductance of the sixth transistor (Q6).

17. The circuit (1) according to claim 16, characterized in that The second transistor (Q2), the third transistor (Q3), the fifth transistor (Q5) and the sixth transistor (Q6) have the same transconductance.

18. The circuit (1) according to claim 16 or 17, characterized in that - the second level shifter circuit (11) is used to set the current flowing through the fifth transistor (Q5) and the sixth transistor (Q6) to zero ampere when the single-ended amplifier is electrically connected to the third terminal (T3) of the circuit (1).

19. The circuit (1) according to any one of claims 16 to 18, characterized in that - the second level converter circuit (11) is used to set the current flowing through the fifth transistor (Q5) and the sixth transistor (Q6) to a current value greater than zero ampere when another differential amplifier is electrically connected to the third terminal (T3) and the fourth terminal (T4) of the circuit (1).

20. The circuit (1) according to any one of claims 16 to 19, characterized in that As claimed in claim 6, - the circuit (1) comprises a third resistor (R3) and a fourth resistor (R4) having equal resistance, - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor (R3), - the fourth resistor (R4) is electrically connected to the second terminal (62) of the sixth transistor (Q6).

21. The circuit (1) according to any one of claims 16 to 19, characterized in that When according to claim 7, the circuit (1) comprises a second inductor, wherein the second inductor is arranged such that one of the following is true: - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the second inductor, - the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the second inductor, - the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) via the second inductor.

22. The circuit (1) according to any one of claims 16 to 19, characterized in that As claimed in claim 8, - the circuit (1) comprises a third resistor and a fourth resistor having equal resistance, and a second inductor, - said fourth resistor is electrically connected to said second terminal (62) of said sixth transistor (Q6), - the third resistor and the second inductor are arranged such that one of the following holds true: - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor and the second inductor; - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor, and the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the second inductor; - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) through the third resistor, and the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) through the second inductor.

23. The circuit (1) according to any one of claims 16 to 19, characterized in that When according to claim 9, the circuit (1) comprises a third inductor and a fourth inductor, wherein the third inductor and the fourth inductor are arranged such that one of the following holds true: - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third inductor, and the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) via the fourth inductor; - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third inductor, and the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the fourth inductor; - the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the third inductor, and the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) via the fourth inductor.

24. The circuit (1) according to any one of claims 16 to 19, characterized in that As claimed in claim 10, - the circuit (1) comprises a third resistor and a fourth resistor having equal resistance, a third inductor and a fourth inductor, - said fourth resistor is electrically connected to said second terminal (62) of said sixth transistor (Q6), - the third resistor, the third inductor and the fourth inductor are arranged such that one of the following holds true: - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor and the third inductor, and the fourth terminal (T4) of the circuit is electrically connected to the second node (8) via the fourth inductor; - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) through the third resistor and the third inductor, and the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) through the fourth inductor; - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) through the third resistor, the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) through the third inductor, and the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) through the fourth inductor.

25. The circuit (1) according to any one of claims 16 to 19, characterized in that When according to claim 11, the circuit (1) comprises a fourth inductor, a fifth inductor and a sixth inductor, wherein: - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the fourth inductor, - the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the fifth inductor, - the fourth terminal (T4) of the circuit (1) is electrically connected to the second node (8) via the sixth inductor.

26. The circuit (1) according to any one of claims 16 to 19, characterized in that As claimed in claim 12, - the circuit (1) comprises a third resistor (R3) and a fourth resistor (R4) having equal resistance, a fourth inductor (L4), a fifth inductor (L5) and a sixth inductor (L6), - the fourth resistor (R4) is electrically connected to the second terminal (62) of the sixth transistor (Q6), - the second terminal (52) of the fifth transistor (Q5) is electrically connected to the second node (8) via the third resistor (R3) and the fourth inductor (L4), - the first terminal (61) of the sixth transistor (Q6) is electrically connected to the second node (8) via the fifth inductor (L5), - the fourth terminal (T4) of the circuit is electrically connected to the second node (8) through the sixth inductor (L6).

27. An amplifier circuit (100), characterized in that: include - a differential amplifier (101) having a first output terminal (OUT1) and a second output terminal (OUT2), - a single-ended amplifier (102) having an input terminal (IN3), - Circuit (1) according to any of the preceding claims, wherein - the first output terminal (OUT1) of the differential amplifier (101) is electrically connected to the first terminal (T1) of the circuit (1), - the second output (OUT2) of the differential amplifier (101) is electrically connected to the second terminal (T2) of the circuit (1), - the input (IN3) of the single-ended amplifier (102) is electrically connected to the third terminal (T3) of the circuit (1).

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