Multi-die-to-wafer hybrid bonding

Abstract

Integrated circuit structures and methods for high precision die-to-wafer bonding technology for manufacturing three-dimensional (3-D) stacked IC dies. Embodiments include precise alignment structures and methods, and also provide rapid manufacturing techniques using simultaneous multi-die picking and placement of single dies from a die source wafer onto a receiving wafer. The yield of stacked dies is improved by enabling the test and selection of known good die source dies prior to bonding the chip to the receiving wafer, and by providing an optional physical alignment structure on the receiving wafer and / or the die source wafer, compared to wafer-to-wafer bonding techniques. For example, embodiments enable high power, high performance devices to be fabricated on an IC formed on a GaAs or GaN die source wafer, and each die source IC die to be bonded to an IC that includes CMOS control and drive circuitry formed on an SOI receive wafer. The resulting three-dimensional (3-D) stacked IC die may provide advantages including scalability, reliability, and form factor reduction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 346,949, filed on May 30, 2022, entitled “MULTI-DIE-TO-WAFER HYBRID BONDING,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to three-dimensional integrated circuit structures and circuits. Background Art

[0004] The electronics industry continues to strive for ever-increasing electronic functionality and performance in a wide variety of products, including, by way of example only, personal electronic devices (e.g., "smart" watches and fitness wearables), personal computers, tablet computers, wireless networking components, televisions, cable system "set-top" boxes, radar systems, and cellular phones. The increased functionality and / or performance generally translates into more transistors and other electronic components on an integrated circuit (IC) die. Although the number of transistors per unit area of ​​an IC die has increased over time as IC manufacturing processes have reduced device sizes, the two-dimensional (2-D) planar form factor or "footprint" of some IC dies has not decreased at the same rate, primarily due to the use of more (albeit smaller) transistors to achieve the increased functionality and / or performance. The 2-D footprint of an IC die is a limitation to reducing the size of circuit modules and circuit boards within a product.

[0005] In order to reduce the 2-D footprint of IC dies, many three-dimensional (3-D) technologies have been developed, which focus on stacking and bonding aligned IC dies from different wafers (also known as wafer-to-wafer bonding), stacking and bonding individual IC dies on undivided IC dies on a wafer (also known as die-to-wafer bonding), and stacking and bonding individual IC dies on another IC die (also known as die-to-die bonding). The bonding of two wafers / dies typically uses dielectric materials (e.g., silicon dioxide, SiCN, SiCOH, and / or similar alloys) and conductive interconnect materials (e.g., copper, aluminum, and / or their alloys) as bonding elements in a mating joint. Typically, high-density interconnects between the combined wafers / dies are desired to achieve good communication between them. One such bonding technology may be referred to as "hybrid bond interconnect (HBI). HBI technology has demonstrated high interconnect density, is a planar technology that does not require underfill or carrier wafer integration, and is capable of forming interconnects between two IC wafers / dies at relatively low temperatures (e.g., ≤~450°C) during a bond annealing stage.

[0006] The problem with wafer-to-wafer bonding is that, in the worst case, the defects may just be additive. So, for example, if both the receiving wafer and the die source wafer exhibit a 10% die defect rate, when the two wafers are bonded together, the resulting bonded die set may have as much as a 20% defect rate. In addition, the two bonded wafers typically need to be the same size, thus limiting the candidates for die source wafers. The problem with die-to-die bonding is that it is difficult and time consuming to manipulate, align and bond two very small dies. Therefore, die-to-wafer bonding is preferred for many applications.

[0007] FIG. 1A is a perspective view of a receiving wafer 100 on which a plurality of individual dies 102 singulated from different die source wafers have been secured using hybrid bonding interconnection techniques. In the illustrated example, the receiving wafer 100 has not yet been singulated and the gaps between the dies 102 comprise cut “streets” (also referred to as cut “lanes”). FIG. 1B is a top view of a single die 104 singulated from the receiving wafer 100 on which the dies 102 from the die source wafer are secured. The bonded die source die 102 and the receiving wafer die 104 together form a single three-dimensional (3-D) stacked IC die. A plurality of mating conductive interconnects 106 or vias connecting the die source die 102 to the receiving wafer die 104 are shown in perspective view.

[0008] A problem with current die-to-wafer bonding technology is that its alignment accuracy is only about 5 μm to 10 μm, compared to about 1 μm of wafer-to-wafer bonding. Therefore, higher bonding accuracy of the die-to-wafer bonding technology is required. Summary of the invention

[0009] The present invention includes integrated circuit structures and methods for high precision die-to-wafer bonding techniques for manufacturing 3-D stacked IC dies. Embodiments of the present invention include precision alignment structures and methods, and also provide rapid manufacturing techniques using simultaneous multi-die picking and placement of individual dies from a die source wafer onto a receiving wafer. Compared to wafer-to-wafer bonding techniques, the yield of stacked dies is improved by being able to test and select a known good die source wafer before bonding to a receiving wafer.

[0010] The die source wafer may be made of compound semiconductor materials, which may include III-V semiconductor materials such as gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP), II-VI semiconductor materials such as cadmium selenide (CdSe), zinc sulfide (ZnS), and zinc telluride (ZnTe), I-III-VI semiconductor materials, and other compound semiconductor materials. Alternatively, the die source wafer may include silicon-based materials, including bulk silicon, high resistivity (HR) silicon, silicon on insulator (SOI), and silicon on sapphire (SOS).

[0011] The receiving wafer may include (by way of example only) a compound semiconductor material or a silicon-based material. The receiving wafer and the die source wafer need not (but may) be made of the same material, and the die source wafer may have a different size (e.g., 150 mm diameter) than the receiving wafer (e.g., 300 mm diameter).

[0012] One aspect of the present invention is a method for manufacturing 3-D stacked integrated circuit (IC) dies, the method comprising: manufacturing die source IC dies on a die source wafer; forming conductive through holes on a bonding surface of each die source IC die; segmenting the die source IC dies; testing the die source IC dies before and / or after segmenting the die source IC dies to determine known good die source IC dies; selecting known good die source IC dies from the segmented dies; and contacting the selected known good die source IC dies with a corresponding receiving wafer IC formed as part of a receiving wafer, thereby bonding the known good die source IC dies to the corresponding receiving wafer IC on the receiving wafer to form a 3-D stacked IC die.

[0013] For example, embodiments of the present invention enable the fabrication of high power, high performance devices on ICs formed on GaAs or GaN die source wafers, and die bonding the individual die source ICs to a receiving wafer IC including complementary metal oxide semiconductor (CMOS) control and drive circuits formed on an SOI receiving wafer. The resulting 3-D stacked IC die can provide advantages including scalability, reliability, and form factor reduction.

[0014] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] 1A is a perspective view of a receiving wafer onto which a plurality of individual dies singulated from different die source wafers have been secured using hybrid bonding interconnect technology.

[0016] 1B is a top view of individual die being singulated from a receiving wafer on which the die from the die source wafer are secured.

[0017] 2A is a cross-sectional view of a set of pre-singulated 3-D stacked IC dies showing individual die source IC dies bonded to corresponding ICs (represented by dashed ovals) formed on a receiving wafer.

[0018] 2B is a cross-sectional view of a group of singulated 3-D stacked IC dies showing individual die source IC dies bonded to corresponding ICs (represented by dashed ovals) formed from a receiving wafer.

[0019] FIG. 3A to FIG. 3B is a process flow diagram illustrating a method for manufacturing the structure shown in FIGS. 2A and 2B .

[0020] 4A is a cross-sectional view of a die source wafer containing multiple fully fabricated ICs prior to singulation.

[0021] Figure 4B is a cross-sectional view of a die source wafer after deposition of dielectric layers and conductive vias.

[0022] Figure 4C is a cross-sectional view of a singulated die source IC die attached to a dicing tape.

[0023] Figure 4D is a cross-sectional view of a die tape containing a plurality of die source IC dies, a "pick and place" apparatus, a plasma source, and a receiving wafer in an early stage of placing the die source IC dies.

[0024] Figure 4E is a cross-sectional view of a receiving wafer 206 with a plurality of die source IC dies placed on the receiving wafer.

[0025] Figure 4F is a cross-sectional view of a receiving wafer having a plurality of die source IC dies bonded thereon.

[0026] Figure 4G is a cross-sectional view of a receiving wafer on which a plurality of die source IC dies encapsulated by a filler material have been bonded.

[0027] Figure 4H is a cross-sectional view of a set of singulated 3-D stacked IC dies showing individual source IC dies bonded to corresponding receiving wafer ICs (represented by dashed ovals).

[0028] Fig. 4I is a top view of four die source IC dies bonded on a single receiving wafer IC.

[0029] Figure 5Ais a cross-sectional view of a receiving wafer having one embodiment of an alignment structure designed to guide placement of die source IC dies relative to corresponding receiving wafer ICs.

[0030] Figure 5B yes Figure 5A A close-up of a portion of.

[0031] Figure 5C is a top view of a first embodiment of a pattern of alignment structures defining a grid structure that abuts and contacts all sides of a die source IC die.

[0032] Figure 5D is a top view of a second embodiment of a pattern of alignment structures defining an edge bonding structure that will contact only a portion of an edge of a die source IC die.

[0033] Figure 5E is a top view of a third embodiment of an alignment structure pattern defining corner bond structures that contact only the four corners of a die source IC die.

[0034] Fig. 5F is a top view of a fourth embodiment of an alignment structure pattern defining a "sparse" corner bond structure that contacts only two opposing corners of a die source IC die.

[0035] Figure 6 is a process flow diagram illustrating one method for forming an alignment structure.

[0036] Figure 7 is a cross-sectional view of a die source IC die and a receiving wafer IC configured with complementary shaped alignment structure protrusions and recesses.

[0037] Figure 8 is a top view of a substrate which may be, for example, a printed circuit board or a chip module substrate (eg, a thin film sheet).

[0038] Unless context requires otherwise, like reference numbers and designations in the various drawings identify like elements. DETAILED DESCRIPTION

[0039] The present invention includes integrated circuit structures and methods for high precision die-to-wafer bonding techniques for manufacturing 3-D stacked IC dies. Embodiments of the present invention include precision alignment structures and methods, and also provide rapid manufacturing techniques using simultaneous multi-die picking and placement of individual dies from a die source wafer onto a receiving wafer. Stacked wafer yield is improved compared to wafer-to-wafer bonding techniques by being able to test and select known good die source wafers before bonding to a receiving wafer.

[0040] For example, embodiments of the present invention enable the fabrication of high power, high performance devices on ICs formed on GaAs or GaN die source wafers, and die bonding the individual die source ICs to a receiving wafer IC including CMOS control and drive circuits formed on an SOI receiving wafer. The resulting 3-D stacked IC die can provide advantages including scalability, reliability, and form factor reduction.

[0041] For purposes of this disclosure, a "wafer" includes a starting substrate, and also includes a substrate on which circuits, electronic and / or optical components and / or conductive connections have been formed.

[0042] Example Structure and Methods

[0043] First, it may be useful to understand the end product resulting from the application of one embodiment of the method of the present invention. FIG. 2A is a cross-sectional view of a set 200 of pre-singulated 3-D stacked IC dies showing individual die source IC dies 202a-202e bonded to corresponding receiving wafer ICs 204a-204e (represented by dashed ovals) formed on a receiving wafer 206. The receiving wafer ICs 204a-204e (generally, "204x") include active devices and interconnects 208 formed on a substrate 210. As shown in FIG. 2A, the interconnects of the die source IC die 202x are aligned with matching / corresponding interconnects within the receiving wafer 206 (also shown in FIG. 2A). Figure 4D FIG. 2B is a cross-sectional view of a group of segmented 3-D stacked IC dies 220 showing individual die source IC dies 202a-202c (indicated by dashed ovals) bonded to corresponding receiving wafer ICs 204a-204c. In both figures, the left and right arrows indicate the bonding planes between the receiving wafer IC and the die source IC. In some applications, such as wafer scale integration, it is not necessary to segment the receiving wafer 206 into individual 3-D stacked IC dies. Further details of the structure of the die source IC and the receiving wafer IC are as follows.

[0044] FIG. 3A to FIG. 3B FIG. 4A to FIG. 4B are process flow diagrams 300 illustrating a method for manufacturing the structure shown in FIG. 2A and FIG. 2B . Fig. 4I An example of an intermediate level structure resulting from the application of one embodiment of the method of the present invention is shown.

[0045] exist Figure 3A4A is a cross-sectional view of a die source wafer 212 containing a plurality of fully fabricated die source IC dies 202a-202e (generally, "202x") prior to singulation. Vertical dashed lines 214 indicate the side-to-side boundaries of the individual ICs (five die source IC dies are shown by way of example). The die source wafer 212 may be made of compound semiconductor materials, which may include III-V semiconductor materials such as gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP), II-VI semiconductor materials such as cadmium selenide (CdSe), zinc sulfide (ZnS), and zinc telluride (ZnTe), I-III-VI semiconductor materials, and other compound semiconductor materials. Alternatively, the die source wafer may include silicon-based materials, including bulk silicon, high resistivity (HR) silicon, silicon on insulator (SOI), and silicon on sapphire (SOS). For the purposes of this example, it is assumed that the die source wafer 212 is made of GaAs or GaN.

[0046] In the example shown, the initial die source wafer 212 may not be sufficiently flat for the requirements of the selected hybrid bond interconnect (HBI) process. For example, surface irregularities may occur during the manufacture of the die source IC when various devices and interconnect structures are formed. In addition, conductive vias need to be formed to enable the circuitry of the die source IC die 202x to be connected to the circuitry of the corresponding receiving wafer die 204x. Figure 4B 2 is a cross-sectional view of the die source wafer 212 after the dielectric layer 216 is deposited and the conductive via 218 is formed. The dielectric layer 216 can be deposited on the die source wafer 212 in a known manner and planarized, for example, by chemical mechanical polishing (CMP) [box 304]. The conductive via 218 can then be formed, for example, by masking and etching, and then planarized, for example, by CMP, as needed [box 306]. The material of the conductive via 218 can be, for example, copper (Cu), but any conductive material compatible with the selected HBI process can be used. The process shown in boxes 304 and 306 can be iterated as needed, for example, to form additional vias.

[0047] At this point, the individual ICs on the die source wafer 212 can be tested. Testing at this stage of the process benefits from the fact that the die source IC dies 202x have not yet been singulated so that the entire die source wafer 212 can be processed through a test apparatus to identify known good dies [block 308]. This can be an important step because the yield of 3-D stacked IC dies should be significantly increased compared to a wafer-to-wafer bonding process.

[0048] Next, an optional final planarization may be performed as required by the selected hybrid bonding interconnect process [block 310]. This step may be necessary in some cases because testing may create defects / non-uniformities on the surface (e.g., when test probes are pressed against pads). The planarized surface of the die source wafer 212 may be referred to as a "bonding surface" 220.

[0049] The individual die source IC dies 202x of the planarized, HBI-ready die source wafer 212 may then be singulated ("diced") [block 312]. As one method of singulation, the bonding surface 220 of the die source wafer 212 may be adhered to a dicing tape (typically by "flipping" the die source wafer 212 onto the bonded dicing tape, as indicated by twisting arrow 222), and the substrate of the die source wafer 212 may then be back-grinded in a known manner to thin the substrate. At this stage, scribing may be performed by any suitable means, including sawing and / or laser scribing, and the dicing tape extended to separate the dies. For example, Figure 4C is a cross-sectional view of singulated die source IC die 202 x adhered to dicing tape 224 .

[0050] Figure 4D is a cross-sectional view of a die strip 224 including a plurality of die source IC dies 202x, a "pick and place" apparatus 226, a plasma source 228, and a receiving wafer 206 in an early stage of placement of a die source IC die 202x. Figure 4E is a cross-sectional view of a receiving wafer 206 on which a plurality of die source IC dies 202x have been placed. Figure 3A , one or more die source IC dies 202x may be picked from dicing tape 224 using a "pick and place" device 226 [block 314]. The "pick and place" device 226 may be configured to pick or place one or more dies at a time. Using a multi-die "pick and place" device capable of picking and placing two or more dies at a time increases throughput. If the die source IC dies 202x have been previously tested, only known good dies need be picked.

[0051] Reference Figure 3B , the individual die source IC dies 202x picked from the dicing tape 224 can be tested again or for the first time [block 316]. Post-singulation testing enables the identification of known good dies after the stress of the dicing process. This can be an important step because the yield of 3-D stacked IC dies can be significantly increased compared to a wafer-to-wafer bonding process. However, testing can be skipped when the yield of the known die source wafer is high enough.

[0052] As an optional process, the bonding surface 220 of the selected die source IC die 202x can be subjected to a pre-placement process to activate the bonding surface 220 for better adhesion to the receiving wafer 206 [box 318]. It is known that plasma activation of copper conductive vias 218 is particularly useful in providing good bonding of the die to the wafer. Specifically, plasma activation reduces the thermal requirements for bond formation when the die is in contact with the receiving wafer. As an example of a plasma activation process, an argon plasma can be applied to remove native Cu oxides and surface contaminants, and then a nitrogen plasma can be applied on the Cu surface to produce an ultra-thin copper nitride layer, which has been found to be beneficial for controlling the Cu surface and facilitating low temperature (e.g., room temperature) bonding. In a similar manner and for similar reasons, the bonding surface of the receiving wafer 206 can be plasma activated. Alternatives to plasma activation can include processes such as surface assembled monolayer (SAM), chemical modification, or dedicated CMP (e.g., "touch" CMP).

[0053] The selected die source IC die 202x can then be placed onto the bonding surface 229 of the receiving wafer 206 in alignment with the corresponding receiving wafer IC 204x (see Figure 4D ) on [frame 320].

[0054] The receiving wafer 206 may include, for example, a compound semiconductor material or a silicon-based material, and may contain active devices (e.g., transistors, diodes) and / or passive devices (e.g., inductors, resistors, capacitors). Note that the receiving wafer 206 and the die source wafer 212 need not (but may) be made of the same material, and the die source wafer 212 may have a different size (e.g., 150 mm diameter) than the receiving wafer 206 (e.g., 300 mm diameter).

[0055] Typically, some pressure is applied during placement to create a bond between the placed die source IC die 202x and the corresponding receiving wafer IC 204x, such as a force of about 10 N for about 10 seconds. Bonds between the dielectric layer 216 of the placed die source IC die 202x and the corresponding dielectric regions of the receiving wafer IC 204x, and between the conductive vias 218 of the placed die source IC die 202x and the corresponding conductive vias 230 of the receiving wafer IC 204x (see FIG. Figure 4D ) is typically formed at ambient temperature. Stronger bonds can be formed at room temperature, but typically only for very long periods of time. Therefore, to increase throughput, the receiving wafer 206 and its bonded die source IC die 202x are preferably subjected to an annealing step to ensure strong bonds [block 322]. For example, the annealing may be performed at a temperature between about 200° C. and 450° C. for a few minutes to a few hours (e.g., two hours). The annealing does not have to be performed immediately after placement.

[0056] Once strong bonding is achieved, in some applications, the bonded 3-D die stack may be singulated and directed to its final use. For such applications, the bonded 3-D die stack may be tested again or for the first time [block 328] and then singulated [block 330], see Figure 3B However, for many applications, it may be useful to fill the area around the die source IC die 202x with dielectric and / or conductive material [block 324]. For example, Figure 4F is a cross-sectional view of a receiving wafer 206 onto which a plurality of die source IC dies 202x have been bonded. The bonded die source IC dies 202x are shown encapsulated by a fill material 232, which may be selected from a variety of types of dielectrics and / or conductors known in the art.

[0057] If underfill is used, in some applications it may be useful to perform backside processing to form additional metallization connections on and / or through the underfill material [block 326]. Figure 4G 2 is a cross-sectional view of a receiving wafer 206 to which a plurality of die source IC dies 202x encapsulated by fill material 232 have been bonded. Conductive connections, such as vias and horizontal traces, may be formed using conventional back-end-of-line (BEOL) processes. Figure 4G , connection 234 is to the receiving wafer IC 204x, and connection 236 is to the die source IC die 202x (not all connections are labeled to avoid clutter).

[0058] Optionally, the bonded 3-D die stack may be tested again or for the first time [block 328 ].

[0059] In some applications, such as wafer scale integration, it is not necessary to singulate the receiving wafer 206 with the bonded die source IC die 202x. However, typically, the 3D stacked IC die including the die source IC die 202x bonded to the corresponding receiving wafer IC 204x will be singulated [block 330] and directed to their end use. For example, Figure 4H is a cross-sectional view of a set of singulated 3D stacked IC dies showing individual die source IC dies 202a-202c bonded to corresponding receiving wafer ICs 204a-204c (indicated by dashed ovals).

[0060] It should be noted that there need not be a one-to-one correspondence of die source IC dies to receiving wafer ICs. For example, in some applications, two or more die source IC dies 202x may be bonded to one receiving wafer IC 204x. This may be useful, for example, where the receiving wafer IC 204x contains low power control and driver circuitry (e.g., Si-CMOS) that is capable of operating multiple RF components (e.g., power amplifiers, low noise amplifiers, filters, switches, etc.) contained in two or more die source IC dies 202x (e.g., GaAs or GaN), which may, for example, be configured to have different operating characteristics. For example, Fig. 4I is a top view of four die source IC dies 252a-252d bonded on a single receiving wafer IC 254. In this example, the first two of the die source IC dies 252a-252b are shown as being smaller in size than the second two of the die source IC dies 252c-252d, which illustrates another advantage of die-to-wafer bonding: the bonded dies can be of different types and / or sizes and come from different die source wafers.

[0061] Die Alignment Structure

[0062] A key aspect of an economically viable HBI technique is the final yield of the 3-D stacked IC die, and a key determinant of the yield is the alignment of the die source IC die 202x with the receiving wafer IC 204x. Misalignment occurs primarily during the HBI bonding step and can be caused by rotational offset (primarily yaw) and / or XY axis offset between the die source IC die 202x and the corresponding receiving wafer IC 204x. As described above, a problem with current die-to-wafer bonding techniques is that the alignment accuracy is only about 5 μm to 10 μm, compared to the alignment accuracy of about 1 μm for wafer-to-wafer bonding.

[0063] To mitigate alignment issues, embodiments of the present invention may advantageously utilize alignment or guiding structures formed as part of the receiving wafer 206 (or receiving wafer IC 204x) and / or the die source IC die 202x. Typically, an alignment structure is a physical modification that provides guidance and / or engagement of the die source IC die 202x relative to the corresponding receiving wafer IC 204x in order to reduce relative misalignment between the two ICs. Embodiments of the present invention utilizing alignment structures may improve alignment between two such ICs by as much as 2 μm.

[0064] Figure 5Ais a cross-sectional view of a receiving wafer 206 having one embodiment of an alignment structure 502 designed to guide the placement of a die source IC die 202x relative to a corresponding receiving wafer IC 204x. Figure 5B yes Figure 5A In the example shown, the alignment structure 502 is configured to be positioned when the alignment structure 502 is positioned by the "pick and place" device 226 ( Figure 5B The alignment structure 502 is used to physically guide and align the die source IC die 202x by interference when the die source IC die 202x is placed into contact with the corresponding receiving wafer IC 204x (not shown in the figure). It is advantageous for the side surface S of the alignment structure 502 to have a certain slope or bevel so that when the "pick and place" device 226 moves the die source IC die 202x into bonding engagement with the corresponding receiving wafer IC 204x, the edge of the die source IC die 202x can contact the side surface S. When the die source IC die 202x approaches bonding contact, the interference of the inclined side surface provides rotational and / or translational movement to the die source IC die 202x to better orient the rotation and XY positioning of the die source IC die 202x relative to the receiving wafer IC 204x. As should be apparent, the alignment structure 502 enables the die source IC die 202x to self-align with respect to the receiving wafer IC 204x. The result is a significantly improved alignment between the two ICs, up to 2 μm.

[0065] A plurality of different bonding surface patterns may be used to define the alignment structures 502 on the bonding surface of the receiving wafer 206. For example, Figure 5C is a top view of a first embodiment of an alignment structure pattern defining a grid structure 502a that will abut and contact all sides of the die source IC die 202x. Figure 5D is a top view of a second embodiment of an alignment structure pattern defining an edge bonding structure 502b that will contact only a portion of the edge of the die source IC die 202x. Figure 5E is a top view of a third embodiment of an alignment structure pattern defining corner bond structures 502c that will contact only the four corners of the die source IC die 202x. Fig. 5F 5 is a top view of a fourth embodiment of an alignment structure pattern defining a "sparse" corner bonding structure 502d that will contact only two opposing corners of a die source IC die 202x. As should be appreciated, other patterns of alignment structures (including combinations of patterns) may be defined to provide similar functionality with respect to enabling a die source IC 202x to self-align relative to a receiving wafer IC 204x during the placement process.

[0066] The alignment structure 502 can be formed on the bonding surface of the receiving wafer 206 in several ways, and it is often beneficial to select a method that is compatible with common BEOL processes. For example, Figure 6 6 is a process flow diagram 600 illustrating one method for forming the alignment structure 502. In an embodiment, the embodiment may include depositing a nitride layer [block 602] on the bonding surface of the receiving wafer, followed by depositing a thick oxide layer [block 604]. The nitride layer may also be the actual patterned layer used to form the alignment structure 502. In both cases, the nitride layer may be patterned using, for example, conventional photolithography steps. The nitride layer may also be used as an etch stop. The nitride may also be used as a hard mask. The thickness of the oxide layer determines the height of the alignment structure 502 above the bonding surface 229 of the receiving wafer 206 (and therefore the receiving wafer IC 204x), and may be, for example, about a few microns to tens of microns.

[0067] The oxide layer is patterned (e.g., using a photomask or hard mask deposition, such as nitride deposition) to define the alignment structure 502 [block 606], and the patterned oxide layer is then etched down to the nitride layer (per [block 602]) to remove the oxide portions that do not define the alignment structure 502 [block 608]. The exposed nitride layer is then removed [block 610], typically by an etchant (e.g., hot phosphoric acid) or a process that is very selective with respect to the remaining oxide that remains to define the alignment structure 502 (and in some cases, the previous thin oxide layer that protects the metal contacts of the receiving wafer). (Such a thin oxide layer will enable bonding after plasma activation, and should be thin enough to allow copper to pass through when the annealing step is performed, creating contact between the metal of the two dies by breaking through the thin oxide layer).

[0068] Optionally, as a post-formation step, the bonding surface of the receiving wafer 206 carrying the alignment structure 502 in place may now be cleaned to remove oxidation from the surface of the conductive (eg, copper) HBI vias [block 612].

[0069] It should be appreciated that many other materials and processes may be used to form the alignment structure 502 in a known manner, including polyimide-based alignment structures 502 .

[0070] Figure 5A and Figure 5B The raised alignment structures 502 shown in FIG. 5 provide guidance of the die source IC die 202x relative to the corresponding receiving wafer IC 204x by lateral interference so as to reduce relative misalignment between the two ICs. In an alternative embodiment, the alignment structures may be formed on both the die source IC die 202x and the receiving wafer IC 204x to provide positive engagement of the two dies, a "lock and key" arrangement. For example, Figure 7 is a cross-sectional view of a source IC die 202x and a receiving wafer IC 204x configured with complementary shaped alignment structure protrusions 702 and recesses 704. Figure 7 The protrusion 702 is shown as being formed on the bonding surface of the die source IC die 202x and the recess 704 is shown as being formed on the bonding surface of the receiving wafer IC 204x, but the positions of the two alignment features may be reversed. Figure 6 or any other convenient process, and may be formed FIG. 5C to FIG. 5F The recess 704 may be formed by conventional masking and etching techniques known in the art and may be formed in any pattern shown in FIG. FIG. 5C to FIG. 5F Advantageously, the alignment structure protrusions 702 and recesses 704 have a certain slope relative to their respective side surfaces to improve mutual alignment.

[0071] Overall Benefits

[0072] Embodiments of the present invention generally provide one or more of the following advantages (note that this list is not exhaustive):

[0073] Reduced power consumption when using high-performance die-source IC dies (e.g., power amplifiers based on III-V semiconductor materials such as GaAs or GaN, low-noise amplifiers (LNAs), high-speed switches, etc.) with low-power receive die ICs (e.g., CMOS on SOI for baseband transceiver controller / logic);

[0074] Compact 3-D stacked IC dies with reduced 2D planar “footprint” and reduced die-to-die wiring lengths (advantageously reducing RF interference and / or distortion);

[0075] Improved thermal performance (and power efficiency) through relatively short heat conduction paths within 3-D stacked IC dies;

[0076] Used to test multiple process points of known good dies, thereby improving yield;

[0077] Achieving higher yields of 3-D stacked IC dies by screening out defective dies before bonding; and

[0078] • Obtaining higher yield of 3D stacked IC dies by improving the alignment of the die source IC die 202x and the corresponding receiving wafer IC 204x during bonding.

[0079] Circuit Implementation

[0080] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. In order to facilitate processing, manufacturing and / or improve performance, embodiments of the present invention can be packaged in IC packages and / or modules. Specifically, 3-D stacked IC die embodiments of the present invention are typically used in modules in which one or more such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components and possible additional ICs) into a package. The ICs and / or modules are then typically combined with other components, typically on a printed circuit board, to form part of a final product (e.g., a cellular phone, a laptop computer, or an electronic tablet), or to form a more advanced module that can be used in a variety of products (e.g., vehicles, test equipment, medical devices, etc.). Through various configurations of modules and components, such ICs typically implement a communication mode, typically wireless communication.

[0081] As an example of further integration of embodiments of the present invention with other components, Figure 8 800, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin film sheet). In the example shown, the substrate 800 includes a plurality of ICs 802a-802d, any of which may be a 3-D stacked IC, having terminal pads 804 that are interconnected by conductive vias and / or traces on and / or within the substrate 800 or on the opposite (rear) surface of the substrate 800 (to avoid clutter, surface conductive traces are not shown, and not all terminal pads are labeled). The ICs 802a-802d may include, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuits.

[0082] The substrate 800 may also include one or more passive devices 806 embedded in, formed on, and / or attached to the substrate 800. Although shown as a general rectangular shape, the passive device 806 may be, for example, a filter, a capacitor, an inductor, a transmission line, a resistor, a planar antenna element, a transducer (including, for example, a MEMS-based transducer such as an accelerometer, a gyroscope, a microphone, a pressure sensor, etc.), a battery, etc., which are interconnected to other passive devices 806 and / or the various ICs 802a-802d via conductive traces on or in the substrate 800.

[0083] The front or rear surface of substrate 800 can be used as a location for forming other structures. For example, one or more antennas (not shown) can be formed on or attached to the front or rear surface of substrate 800. Thus, by including one or more antennas on substrate 800, a complete radio receiver, transmitter, or transceiver can be created.

[0084] System

[0085] Embodiments of the present invention may be used in a variety of larger radio frequency (RF) circuits and systems for implementing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low noise amplifiers (LNAs), phase shifters, attenuators, antenna beam steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0086] Radio system usage includes wireless RF systems (including base stations, relay stations, and handheld transceivers) that use a variety of technologies and protocols, including various types of Orthogonal Frequency Division Multiplexing (“OFDM”), Quadrature Amplitude Modulation (“QAM”), Code Division Multiple Access (“CDMA”), Time Division Multiple Access (“TDMA”), Wideband Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G and WiFi (e.g., 802.11a, 802.11b, 802.11g, 802.11ac, 802.11ax, 802.11be) protocols and other radio communication standards and protocols.

[0087] As described above, the present invention reduces power consumption, reduces 2D planar "footprint", improves thermal performance, and improves yield of 3-D stacked IC dies by pre-testing die source IC dies and improving die alignment during HBI bonding. As will be appreciated by those of ordinary skill in the art, system architectures are beneficially impacted by the present invention in key aspects, including lower power, longer battery life, smaller size, lower cost, etc. The present invention specifically achieves these system-level improvements. Therefore, the present invention specifically encompasses higher-level systems that are creatively achieved by including embodiments of the present invention in such systems.

[0088] Manufacturing Techniques and Options

[0089] As used in the present disclosure, the term "metal oxide semiconductor field effect transistor (MOSFET)" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor and includes an insulated gate having a metal or metalloid, insulator and / or semiconductor structure. The term "metal" or "metalloid" includes at least one conductive material (e.g., aluminum, copper or other metal, or highly doped polysilicon, graphene or other electrical conductor), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0090] As used in this disclosure, the term "radio frequency" (RF) refers to oscillation rates in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves or alternating voltages or currents in electrical circuits.

[0091] With respect to the drawings cited in this disclosure, the dimensions of the various elements are not drawn to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., "top," "bottom," "above," "below," "lateral," "vertical," "horizontal," etc.) are relative to the exemplary drawings and are not necessarily absolute orientations or directions.

[0092] Various embodiments of the present invention can be implemented to meet a wide variety of specifications. Unless otherwise stated above, the selection of appropriate component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures) or a combination of such technologies. Any suitable substrate and process can be used to manufacture the die source IC die and the receiving wafer IC embodiment, which substrate and process include but are not limited to standard bulk silicon, high resistivity bulk CMOS, silicon on insulator (SOI) and silicon on sapphire (SOS), and other transistor technologies such as bipolar, bipolar complementary metal oxide semiconductor (BiCMOS), lateral diffusion metal oxide semiconductor (LDMOS), bipolar transistor-complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD), gallium arsenide heterojunction bipolar transistor (GaAsHBT), gallium nitride high electron mobility transistor (GaN HEMT), gallium arsenide pseudo heterojunction field effect transistor (GaAspHEMT) and metal semiconductor field effect transistor (MESFET) technology.

[0093] Depending on the particular specifications and / or implementation technology (e.g., N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (PMOS), or complementary metal oxide semiconductor (CMOS), and enhancement mode or depletion mode transistor devices), voltage levels may be adjusted, and / or voltage and / or logic signal polarity may be reversed. Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device size, "stacking" components (particularly FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0094] in conclusion

[0095] A number of embodiments of the present invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may be order-independent and therefore may be performed in an order different from that described. In addition, some of the steps described above may be optional. The various activities described with respect to the above method may be performed in a repetitive, serial and / or parallel manner.

[0096] It should be understood that the foregoing description is intended to illustrate rather than limit the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are also within the scope of the claims. Specifically, the scope of the invention includes any and all feasible combinations of one or more processes, machines, manufactures, or compositions of matter set forth in the following claims. (Note that parenthetical markings of claim elements are for convenience of reference to such elements and do not themselves indicate a specific desired ordering or enumeration of elements; furthermore, such markings may be reused in dependent claims as references to additional elements without being considered to begin a conflicting marking sequence).

Claims

1. A method of manufacturing a three-dimensional (3-D) stacked integrated circuit (IC) die, the method comprising: (a) manufacturing a die source IC die on a die source wafer; (b) forming a conductive via on the bonding surface of each die source IC die; (c) dividing the die source IC die; (d) testing the Die Source IC Dies before and / or after singulating the Die Source IC Dies to determine known good Die Source IC Dies; (e) selecting a known good die source IC die from the singulated die; as well as (f) contacting the selected known good die source IC die with a corresponding receiving wafer IC formed as part of a receiving wafer, thereby bonding the known good die source IC die to the corresponding receiving wafer IC on the receiving wafer to form a three-dimensional (3-D) stacked IC die.

2. The method of claim 1 further comprising annealing the receiving wafer after placing the selected known good die source IC die on the corresponding receiving wafer IC on the receiving wafer.

3. The method of claim 1, further comprising adding a fill material around the selected known good die source IC die after placing the IC die on the corresponding receiving wafer IC of the receiving wafer. 4 . The method of claim 3 , further comprising performing backside processing to form additional metallization connections on and / or through the fill material.

5. The method of claim 1, further comprising testing the three-dimensional (3-D) stacked IC die after bonding occurs.

6. The method of claim 1, further comprising singulating the three-dimensional (3-D) stacked IC die from the receiving wafer after bonding occurs.

7. The method of claim 1, further comprising plasma activating the bonding surfaces of the selected known good die source IC die prior to placing the selected known good die source IC die on the corresponding receiving wafer IC.

8. The method of claim 1, further comprising plasma activating a bonding surface of the receiving wafer prior to placing the selected known good die source IC die on the corresponding receiving wafer IC.

9. The method of claim 1, further comprising planarizing the chip source IC die after fabricating the chip source IC die on the chip source wafer and before forming the conductive vias.

10. The method of claim 1, further comprising planarizing the chip source IC die after forming the conductive vias and before singulating the chip source IC die.

11. The method of claim 1 further comprising forming alignment structures on the bonding surface of the receiving wafer, the alignment structures being shaped and positioned to guide placement of the selected known good die source IC die relative to the corresponding receiving wafer IC.

12. The method according to claim 11, wherein: The alignment structure has an angled side surface that can be contacted by an edge of a selected known good die source IC die.

13. The method of claim 12 further comprises forming the alignment structure in one of: a grid pattern configured to abut and contact all sides of the selected known good die source IC die; an edge bonding pattern configured to contact only a portion of the edge of the selected known good die source IC die; a corner bonding pattern configured to contact only four corners of the selected known good die source IC die, or a sparse corner bonding pattern configured to contact only two opposite corners of the selected known good die source IC die.

14. The method of claim 11, further comprising forming the alignment structure in a grid pattern configured to abut and contact all sides of the selected known good die source IC die.

15. The method of claim 11, further comprising forming the alignment structure in an edge bonding pattern configured to contact only a portion of the edge of the selected known good die source IC die.

16. The method of claim 11, further comprising forming the alignment structure in a corner bonding pattern configured to contact only the four corners of the selected known good die source IC die.

17. The method of claim 11, further comprising forming the alignment structure in a sparse corner bond pattern configured to contact only two opposing corners of the selected known good die source IC die.

18. The method according to claim 1, wherein: The die source IC die is formed from a compound semiconductor material die source wafer.

19. The method according to claim 1, wherein: The die source IC die is formed from a silicon-based die source wafer.

20. The method according to claim 1, wherein: The die source IC die is formed from a gallium arsenide or gallium nitride die source wafer.

21. The method according to claim 1, wherein: The receiver wafer IC is formed on a compound semiconductor material receiver wafer.

22. The method according to claim 1, wherein: The receiver wafer IC is formed on a silicon-based receiver wafer.

23. The method according to claim 1, wherein: The receiver wafer IC is a CMOS circuit formed on a silicon-on-insulator receiver wafer.

24. A method of manufacturing a three-dimensional (3-D) stacked integrated circuit (IC) die, the method comprising: (a) manufacturing a die source IC die on a die source wafer; (b) planarizing the die source IC die; (c) forming a conductive via on the bonding surface of each die source IC die; (d) planarizing the die source IC die; (e) dividing the die source IC die; (f) testing the Die Source IC Dies before and / or after singulating the Die Source IC Dies to determine known good Die Source IC Dies; (g) selecting a known good die source IC die from the singulated die; (h) plasma activating at least one of the bonding surface of the selected known good die source IC die and / or the bonding surface of the receiving wafer; (i) contacting the selected known good die source IC die with a corresponding receiving wafer IC formed as part of a receiving wafer, thereby bonding the known good die source IC die to the corresponding receiving wafer IC on the receiving wafer to form a three-dimensional (3-D) stacked IC die; (j) annealing the receiving wafer; as well as (k) singulating the three-dimensional (3-D) stacked IC dies from the receiving wafer.

25. The method of claim 24, further comprising forming alignment structures on the bonding surface of the receiving wafer, the alignment structures being shaped and positioned to guide placement of the selected known good die source IC die relative to the corresponding receiving wafer IC.

26. The method according to claim 25, wherein: The alignment structure has an angled side surface that can be contacted by an edge of a selected known good die source IC die.

27. The method according to claim 26 also includes forming the alignment structure in one of the following: a grid pattern, wherein the grid pattern is configured to abut and contact all sides of the selected known good die source IC die; an edge bonding pattern, wherein the edge bonding pattern is configured to contact only a portion of the edge of the selected known good die source IC die; a corner bonding pattern, wherein the corner bonding pattern is configured to contact only four corners of the selected known good die source IC die, or a sparse corner bonding pattern, wherein the sparse corner bonding pattern is configured to contact only two opposite corners of the selected known good die source IC die.

28. The method of claim 25, further comprising forming the alignment structure in a grid pattern configured to abut and contact all sides of the selected known good die source IC die.

29. The method of claim 25, further comprising forming the alignment structure in an edge bonding pattern configured to contact only a portion of an edge of the selected known good die source IC die.

30. The method of claim 25, further comprising forming the alignment structure in a corner bond pattern configured to contact only four corners of the selected known good die source IC die.

31. The method of claim 25, further comprising forming the alignment structure in a sparse corner bond pattern configured to contact only two opposing corners of the selected known good die source IC die.

32. The method of claim 24, wherein: The die source IC die is formed from a compound semiconductor material die source wafer.

33. The method of claim 24, wherein: The die source IC die is formed from a silicon-based die source wafer.

34. The method of claim 24, wherein: The die source IC die is formed from a gallium arsenide or gallium nitride die source wafer.

35. The method of claim 24, wherein: The receiver wafer IC is formed on a compound semiconductor material receiver wafer.

36. The method of claim 24, wherein: The receiver wafer IC is formed on a silicon-based receiver wafer.

37. The method of claim 24, wherein: The receiver wafer IC is a CMOS circuit formed on a silicon-on-insulator receiver wafer.

38. A three-dimensional (3-D) stacked integrated circuit (IC) die, the three-dimensional (3-D) stacked integrated circuit (IC) die comprising: (a) a die source IC die including a bonding surface and conductive vias; as well as (b) a receiving wafer IC die, the receiving wafer IC die comprising: (1) a bonding surface and a conductive via, wherein the bonding surface and the conductive via are aligned and contacted with the bonding surface and the conductive via of the die source IC die; as well as (2) an alignment structure formed on the bonding surface of the receiving wafer IC die and shaped and positioned to guide placement of the bonding surface and conductive vias of the die source IC die into bonding engagement with the bonding surface and conductive vias of the receiving wafer IC die.

39. The invention according to claim 38, wherein: The alignment structure has an inclined side surface that can be contacted by an edge of the die source IC die.

40. The invention of claim 39, wherein: The alignment structure is configured as one of: a grid pattern configured to abut and contact all sides of the die source IC die; an edge bonding pattern configured to contact only a portion of the edge of the die source IC die; a corner bonding pattern configured to contact only four corners of the die source IC die, or a sparse corner bonding pattern configured to contact only two opposing corners of the die source IC die.

41. The invention of claim 38, wherein: The alignment structures are configured in a grid pattern configured to abut and contact all sides of the die source IC die.

42. The invention of claim 38, wherein: The alignment structure is configured as an edge bonding pattern configured to contact only a portion of an edge of the die source IC die.

43. The invention of claim 38, wherein: The alignment structure is configured as a corner bonding pattern configured to contact only four corners of the die source IC die.

44. The invention of claim 38, wherein: The alignment structure is configured as a sparse corner bond pattern configured to contact only two opposing corners of the die source IC die.

45. The invention of claim 38, wherein: The die source IC die is formed from a compound semiconductor material die source wafer.

46. ​​The invention of claim 38, wherein: The die source IC die is formed from a silicon-based die source wafer.

47. The invention of claim 38, wherein: The die source IC die is formed from a gallium arsenide or gallium nitride die source wafer.

48. The invention of claim 38, wherein: The receiver wafer IC die is formed on a compound semiconductor material receiver wafer.

49. The invention of claim 38, wherein: The receiver wafer IC die is formed on a silicon-based receiver wafer.

50. The invention of claim 38, wherein: The receiver wafer IC die includes CMOS circuitry formed on a silicon-on-insulator receiver wafer.

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