A fast jump and pre-fetch device and method for conditional instructions

Abstract

The present invention relates to the field of conditional instruction operation, and discloses a fast jump and pre-fetch device and method for conditional instructions. The device includes a program storage space, a bus, an instruction fetch controller, an instruction fetch counter, a control storage, an instruction stack 1, an instruction stack 2, a control selector, a decoder and a condition judgement device; the instruction stack 1 is used to store instructions for sequential execution; the instruction stack 2 is used to store instructions pre-fetched by fast jump instructions, that is, jump destination instructions; the control selector is used to select to continue fetching instructions from the instruction stack 1 or the instruction stack 2, and the condition judgement device is used to judge whether the fast jump condition is established, and generate control conditions for the control storage device and the control selector. The device and method disclosed by the present invention save the time period between the decoder and the condition judgement device by giving the jump destination address at the decoder stage, and solve the problem of low execution efficiency of jump instructions.

Description

Technical Field

[0001] The present invention relates to the field of conditional instruction operation, and in particular to a fast jump and pre-fetch device and method for conditional instructions. Background Art

[0002] In the design of modern ultra-high performance processors, improving instruction operation efficiency is the key to improving performance, among which instruction prefetching and prediction are key technologies. There are often jump instructions in instructions. When a conditional jump occurs, the processor usually needs to determine whether the jump condition of the jump instruction is met. If the jump condition is met, the jump address is input to the instruction prefetch device for instruction fetching; otherwise, the instructions are executed sequentially. This traditional conditional instruction processing method obviously cannot meet high performance requirements, so how to improve the branch jump instruction prefetching and processing method is a meaningful research issue.

[0003] The prior art usually requires the processor to spend several cycles to determine whether the condition is met before giving the destination address of the jump instruction. After receiving the new address, the instruction prefetch device needs to refresh the existing instructions in the instruction prefetch stack and send the jump address to the bus to fetch the new instruction. Although this process is accurate and reliable, it has the problem of slow processing, which reduces the efficiency of instruction execution. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a fast jump and pre-fetch device and method for conditional instructions, which pre-fetches the jump destination instruction in advance and solves the problem of low execution efficiency of jump instructions.

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] A fast jump and pre-fetch device for conditional instructions, comprising a program storage space, a bus, an instruction fetch controller, an instruction fetch counter, a control storage, an instruction stack 1, an instruction stack 2, a control selector, a decoder and a condition judge;

[0007] The program storage space is used to store instructions;

[0008] The bus is used to transmit instructions;

[0009] The instruction fetch controller is used to control the reception and transmission of the instruction fetch address, and find and fetch the corresponding instruction from the program storage space according to the instruction fetch address;

[0010] The instruction fetch counter is used to generate and receive program addresses. When the program is executed sequentially, the instruction fetch counter generates sequential instruction addresses using a self-increment function; when the program takes discontinuous actions, it receives a jump instruction address sent by a decoder;

[0011] The control storage device is used to control the fast jump instruction to be stored in instruction stack 1 or instruction stack 2;

[0012] The instruction stack 1 is used to store instructions to be executed sequentially;

[0013] The instruction stack 2 is used to store instructions pre-fetched by fast jump instructions, i.e. jump destination instructions;

[0014] The control selector is used to select to continue fetching instructions from instruction stack 1 or instruction stack 2. When the fast jump instruction completes conditional judgment after several cycles, if the condition is not met, the instruction stack used when the fast jump instruction enters the decoder will continue to be used. If the condition is met, another instruction stack storing the jump destination instruction will be switched to be used.

[0015] The decoder is used to decode and identify whether the instruction is a fast jump instruction, and when it is a fast jump instruction, decode the jump destination address and pass it to the instruction fetch counter, and pass the condition information to the subsequent condition judgement;

[0016] The condition judger is used to judge whether the fast jump condition is met and generate control conditions for the control storage and the control selector.

[0017] A fast jump and prefetch method for conditional instructions, using the fast jump and prefetch device for conditional instructions as described above, includes the following process:

[0018] (1) The instruction fetch controller finds and fetches the corresponding instruction from the program storage space via the bus according to the sequential instruction address sent by the instruction fetch counter;

[0019] (2) The control register stores the instruction in instruction stack 1 or instruction stack 2 according to the control condition sent by the condition judgement device; by default, the instruction is stored in instruction stack 1. If the instruction is a pre-fetched instruction of a fast jump instruction, that is, the jump destination instruction, it is stored in instruction stack 2;

[0020] (3) The control selector selects to continue fetching instructions from instruction stack 1 or instruction stack 2 according to the control condition sent by the condition judgement device, and sends it to the decoder; when the fast jump instruction completes the condition judgment after several cycles, if the condition is not met, the instruction stack used when the fast jump instruction entered the decoder will continue to be used; if the condition is met, it will switch to another instruction stack that stores the jump destination instruction;

[0021] (4) The decoder determines whether the instruction fetched is a fast jump instruction. If it is a fast jump instruction, it decodes the jump destination address and passes it to the instruction fetch counter, and passes the condition information to the subsequent condition judgement;

[0022] (5) The conditional judgement device judges whether the fast jump condition is met and generates control conditions for the control register and the control selector.

[0023] Through the above technical solution, the fast jump and prefetch device and method of conditional instructions provided by the present invention have the following beneficial effects:

[0024] The present invention designs two groups of instruction storage stacks, and designs a fast jump instruction to provide a jump address mechanism. One of the instruction stacks is used to store the fast instructions being executed and the instructions for sequential instruction fetching. When the decoder encounters a fast jump instruction, it decodes the destination address to be jumped and passes it to the instruction fetch counter. The new jump instruction retrieved by the instruction prefetch device is stored in the second stack. In the subsequent cycle, the instruction is judged whether the jump condition is met, and the instruction is selected from stack one or stack two. This technology pre-fetches the jump destination instruction in advance, solving the problem of low execution efficiency of jump instructions.

[0025] The present invention saves the time period between the decoder and the conditional judge by giving the jump destination address at the decoder stage. After the conditional judge is completed, the new jump instruction can be immediately sent to the decoder for decoding, which is equivalent to executing the jump destination instruction multiple machine cycles in advance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0027] Figure 1 A schematic diagram of a fast jump and pre-fetch device for conditional instructions disclosed in an embodiment of the present invention;

[0028] Figure 2 The fast jump instruction pipeline timing cycle diagram of embodiment 1 of the present invention;

[0029] Figure 3 This is the non-fast jump pipeline timing cycle diagram of the jump instruction of comparative example 1. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0031] The present invention provides a fast jump and pre-fetch device for conditional instructions, such as Figure 1 As shown, it includes program storage space, bus, instruction fetch controller, instruction fetch counter, control storage, instruction stack 1, instruction stack 2, control selector, decoder and condition judge; the functions of each unit are as follows:

[0032] The program memory space is used to store instructions.

[0033] The bus is used to transfer instructions.

[0034] The instruction fetch controller is used to control the reception and transmission of the instruction fetch address, and find and fetch the corresponding instruction from the program storage space according to the instruction fetch address.

[0035] The instruction fetch counter is used to generate and receive program addresses. When the program is executed sequentially, the instruction fetch counter uses the self-increment function to generate sequential instruction addresses; when the program takes discontinuous actions, it receives the jump instruction address sent by the decoder.

[0036] The control register is used to control whether the fast jump instruction is stored in instruction stack one or instruction stack two.

[0037] Instruction stack - used to store instructions to be executed sequentially.

[0038] Instruction stack 2 is used to store instructions pre-fetched by fast jump instructions, that is, jump destination instructions.

[0039] The control selector is used to select to continue fetching instructions from instruction stack one or instruction stack two. After the fast jump instruction completes the condition judgment after several cycles, if the condition is not met, the instruction stack used when the fast jump instruction enters the decoder will continue to be used. If the condition is met, it will switch to another instruction stack that stores the jump destination instruction.

[0040] The decoder is used to decode and identify whether the instruction is a fast jump instruction. If it is a fast jump instruction, the decoded jump destination address is passed to the instruction fetch counter, and the condition information is passed to the subsequent condition judge.

[0041] The conditional judgement device is used to judge whether the fast jump condition is established and generate control conditions for the control register and the control selector.

[0042] A fast jump and prefetch method for conditional instructions, using the fast jump and prefetch device for conditional instructions as above, includes the following process:

[0043] (1) The instruction fetch controller finds and fetches the corresponding instruction from the program storage space via the bus according to the sequential instruction address sent by the instruction fetch counter;

[0044] (2) The control register stores the instruction in instruction stack 1 or instruction stack 2 according to the control condition sent by the condition judgement device; by default, the instruction is stored in instruction stack 1. If the instruction is a pre-fetched instruction of a fast jump instruction, that is, the jump destination instruction, it is stored in instruction stack 2;

[0045] (3) The control selector selects to continue fetching instructions from instruction stack 1 or instruction stack 2 according to the control condition sent by the condition judgement device, and sends it to the decoder; when the fast jump instruction completes the condition judgment after several cycles, if the condition is not met, the instruction stack used when the fast jump instruction entered the decoder will continue to be used; if the condition is met, it will switch to another instruction stack that stores the jump destination instruction;

[0046] (4) The decoder determines whether the instruction fetched is a fast jump instruction. If it is a fast jump instruction, it decodes the jump destination address and passes it to the instruction fetch counter, and passes the condition information to the subsequent condition judgement;

[0047] (5) The conditional judgement device judges whether the fast jump condition is met and generates control conditions for the control register and the control selector.

[0048] Example 1

[0049] Assume that a program includes a jump instruction but does not execute the fast jump solution: the instruction decoded by the decoder is I1, which is a jump instruction. I1 is stored in instruction stack 1, and the subsequent instructions entering the pipeline are I2, I3, and I4. Assume that instruction stack 1 can only store 4 instructions.

[0050] like Figure 2 As shown, the steps are as follows:

[0051] 1. When cycle = 1, the decoder decodes the I1 instruction as a jump instruction, and the information generated by the decoding is passed to the subsequent pipeline stage;

[0052] 2. At cycle = 2, the I1 instruction is passed to the next pipeline stage;

[0053] 3. At cycle = 3, the I1 instruction is passed to the next pipeline stage;

[0054] 4. At cycle = 4, the I1 instruction is conditionally judged in the conditional judger. If the condition is met, the jump destination address is passed to the instruction fetch counter; if the condition is not met, the I1 instruction is executed sequentially;

[0055] 5. At cycle = 5, if condition I1 is met, instructions I2, I3, and I4 stored in instruction stack 1 are cleared and no longer used, and the retrieved new instruction D1 is stored in instruction stack 1. At this time, no instruction enters the decoder. If condition I1 is not met, the existing instruction I2 is taken out of instruction stack 1 and enters the decoder, and the new instruction I5 is stored in instruction stack 1;

[0056] 6. At cycle = 6, if the I1 condition is met, the new instruction D2 is stored in instruction stack 1, and no instruction enters the decoder at this time; if the I1 condition is not met, the existing instruction I3 is taken out from instruction stack 1 and enters the decoder, and the new instruction I6 is stored in instruction stack 1 at the same time;

[0057] 7. At cycle = 7, if the I1 condition is met, the new instruction D3 is stored in instruction stack 1, and no instruction enters the decoder at this time; if the I1 condition is not met, the existing instruction I4 is taken out from instruction stack 1 and enters the decoder, and the new instruction I7 is stored in instruction stack 1 at the same time;

[0058] 8. At cycle = 8, if the I1 condition is met, the new instruction D4 is stored in instruction stack 1, and the D1 instruction enters the decoder; if the I1 condition is not met, the existing instruction I5 is taken out from instruction stack 1 and enters the decoder, and the new instruction I8 is stored in instruction stack 1.

[0059] Comparative Example 1

[0060] Assume that a program includes a jump instruction: Assume that the instruction decoded by the decoder is I1, which is a jump instruction. I1 is stored in instruction stack 1, and the subsequent instructions entering the pipeline are I2, I3, and I4. Assume that instruction stack 1 and instruction stack 2 can only store 4 instructions.

[0061] like Figure 3 As shown, the steps are as follows:

[0062] 1. Assume that we start the analysis from the decoder in the flowchart. When the decoder decoding cycle (the clock cycle of the kernel on the hardware system) = 1, it is determined that it is a jump instruction. Then, the jump destination address is sent to the instruction fetch counter, and the instruction fetch controller starts to fetch new instructions from the program storage space pointed to by the destination address.

[0063] 2. At cycle = 2, the bus fetches the new instruction D1 from the program storage space and arrives at the instruction fetch controller, which controls the storage to put the instruction into instruction stack 2;

[0064] 3. At cycle = 3, the bus continues to fetch new instruction D2 from the program storage space and places it. The instruction fetch controller assumes that instruction D1 is one cycle away from entering the conditional judgement. At this time, the control storage continues to store new instruction D2 into instruction stack 2;

[0065] 4. At cycle = 4, instruction I1 enters the conditional judgement to determine whether the condition is met. At the same time, the bus takes the new instruction D3 from the program storage space and stores it in instruction stack 2;

[0066] 5. At cycle = 5, the conditional judgment result of the conditional judge is fed back to the control selector, which is used to select which stack to output instructions to the decoder. If the condition is met, the instruction is output from instruction stack 2. If the condition is not met, the instruction continues to be output from instruction stack 1.

[0067] From the comparison between Example 1 of the present invention and Comparative Example 1, it can be seen that the fast jump and prefetch device and method of conditional instructions of the present invention can send new instructions to the decoder stage at least 3 machine cycles faster than the existing non-fast processing method.

[0068] In summary, the device and method of the present invention can effectively process jump instructions, while also improving the efficiency of obtaining jump instruction execution.

[0069] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A fast jump and prefetch device for conditional instructions, characterized in that: It includes program storage space, bus, instruction fetch controller, instruction fetch counter, control storage, instruction stack 1, instruction stack 2, control selector, decoder and condition judgement; The program storage space is used to store instructions; The bus is used to transmit instructions; The instruction fetch controller is used to control the reception and transmission of the instruction fetch address, and find and fetch the corresponding instruction from the program storage space according to the instruction fetch address; The instruction fetch counter is used to generate and receive program addresses. When the program is executed sequentially, the instruction fetch counter generates sequential instruction addresses using a self-increment function; when the program takes discontinuous actions, it receives a jump instruction address sent by a decoder; The control storage device is used to control the fast jump instruction to be stored in instruction stack 1 or instruction stack 2; The instruction stack 1 is used to store instructions to be executed sequentially; The instruction stack 2 is used to store instructions pre-fetched by fast jump instructions, i.e. jump destination instructions; The control selector is used to select to continue fetching instructions from instruction stack 1 or instruction stack 2. When the fast jump instruction completes conditional judgment after several cycles, if the condition is not met, the instruction stack used when the fast jump instruction enters the decoder will continue to be used. If the condition is met, another instruction stack storing the jump destination instruction will be switched to be used. The decoder is used to decode and identify whether the instruction is a fast jump instruction, and when it is a fast jump instruction, decode the jump destination address and pass it to the instruction fetch counter, and pass the condition information to the subsequent condition judgement; The condition judger is used to judge whether the fast jump condition is met and generate control conditions for the control storage and the control selector.

2. A method for fast jump and prefetch of conditional instructions, using a fast jump and prefetch device for conditional instructions as claimed in claim 1, characterized in that: The process includes the following: (1) The instruction fetch controller finds and fetches the corresponding instruction from the program storage space via the bus according to the sequential instruction address sent by the instruction fetch counter; (2) The control register stores the instruction in instruction stack 1 or instruction stack 2 according to the control condition sent by the condition judgement device; by default, the instruction is stored in instruction stack 1. If the instruction is a pre-fetched instruction of a fast jump instruction, that is, the jump destination instruction, it is stored in instruction stack 2; (3) The control selector selects to continue fetching instructions from instruction stack 1 or instruction stack 2 according to the control condition sent by the condition judgement device, and sends it to the decoder; when the fast jump instruction completes the condition judgment after several cycles, if the condition is not met, the instruction stack used when the fast jump instruction entered the decoder will continue to be used; if the condition is met, it will switch to another instruction stack that stores the jump destination instruction; (4) The decoder determines whether the instruction fetched is a fast jump instruction. If it is a fast jump instruction, it decodes the jump destination address and passes it to the instruction fetch counter, and passes the condition information to the subsequent condition judgement; (5) The conditional judgement device judges whether the fast jump condition is met and generates control conditions for the control register and the control selector.

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