Pixel circuit, display panel and display device

Abstract

The invention relates to a pixel circuit, a display panel and a display device. The pixel circuit comprises a driving transistor T1; the double-gate transistor T3 comprises a first transistor T3-2 and a second transistor T3-1, and the first transistor T3-2 and the second transistor T3-1 are electrically connected between the gate electrode and the drain electrode of the driving transistor T1; and the adjusting unit X is connected to a first node A between the first transistor T3-2 and the second transistor T3-1 and is used for writing an adjusting signal into the first node A so as to adjust the potential of the first node A. According to the pixel circuit provided by the invention, the potential of the first node A can be adjusted in the light emitting stage, so that the current leakage condition caused by large voltage difference of the double-gate transistor T3 is reduced, the gate potential of the driving transistor T1 is further stabilized, and the display brightness of a display panel where the pixel circuit is located is more uniform.

Description

Technical Field

[0001] The present disclosure relates to the field of screen display, and in particular to a pixel circuit, a display panel and a display device. Background Art

[0002] With the rapid development of technology, active matrix organic light emitting diode (AMOLED), as a current-type light-emitting device, is increasingly being used in the field of high-performance displays due to its characteristics of self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates.

[0003] The AMOLED display panel includes a plurality of pixel circuits arranged in a matrix. Each pixel circuit is provided with a plurality of transistors. The light-emitting element is driven to emit light through the cooperation between the plurality of transistors.

[0004] However, when the display panel is displaying in a low-frequency state, there is a leakage problem in the transistor connected between the gate and drain of the driving transistor of the pixel circuit, which causes fluctuations in the gate potential of the driving transistor during the light-emitting stage, resulting in unstable driving current transmitted by the pixel circuit, causing uneven brightness of the display panel and affecting the display effect. Summary of the invention

[0005] In order to overcome the problems existing in the related art, the present disclosure provides a pixel circuit, a display panel and a display device. Through the pixel circuit proposed in the present disclosure, the potential of the first node can be adjusted in the light-emitting stage to reduce the leakage current caused by the large voltage difference of the dual-gate transistor, further stabilize the gate potential of the driving transistor, and make the display brightness of the display panel where the pixel circuit is located more uniform.

[0006] The present disclosure provides a pixel circuit, including:

[0007] Driver transistor;

[0008] A dual-gate transistor, comprising a first transistor and a second transistor, wherein the first transistor and the second transistor are electrically connected between a gate and a drain of the driving transistor;

[0009] The regulating unit is connected to a first node between the first transistor and the second transistor, and is used for writing a regulating signal into the first node to regulate the potential of the first node.

[0010] In some embodiments, the adjusting unit comprises:

[0011] a third transistor connected to the first node;

[0012] Wherein, when the third transistor is turned on, the third transistor outputs the regulating signal.

[0013] In some embodiments, the pixel circuit further includes: a regulating voltage terminal and a first scanning signal terminal;

[0014] The gate of the third transistor is connected to the first scanning signal terminal, the source of the third transistor is connected to the regulating voltage terminal, and the drain of the third transistor is connected to the first node;

[0015] Wherein, when the first scanning signal terminal outputs the first pulse signal, the third transistor is turned on;

[0016] When the second pulse signal is outputted at the first scanning signal terminal, the third transistor is turned off, and the level of the first pulse signal is lower than the level of the second pulse signal.

[0017] In some embodiments, the regulating voltage terminal is connected to an AC signal source;

[0018] Wherein, when the first scanning signal terminal switches to outputting the first pulse signal, the third transistor outputs a high-level AC signal;

[0019] Before the first scanning signal terminal switches from outputting the first pulse signal to outputting the second pulse signal, the third transistor switches to outputting a low-level AC signal.

[0020] In some embodiments, the source of the first transistor is connected to the drain of the driving transistor, the drain of the first transistor is connected to the source of the second transistor, and the drain of the second transistor is connected to the gate of the driving transistor;

[0021] The first node is located between the drain of the first transistor and the source of the second transistor.

[0022] In some embodiments, the pixel circuit further includes a fourth transistor;

[0023] The fourth transistor is connected to a second node between the second transistor and the gate of the driving transistor;

[0024] When the fourth transistor is turned on, the drain of the fourth transistor outputs a first reset signal, and writes the first reset signal into the second node.

[0025] In some embodiments, the fourth transistor and the regulating unit are connected to the same AC signal source;

[0026] Wherein, when the fourth transistor is turned on, the first reset signal and the adjustment signal are the same low-level signal.

[0027] In some embodiments, the pixel circuit further includes: a light emitting element and a fifth transistor;

[0028] The anode of the light emitting element is connected to a third node between the drain of the dual-gate transistor and the drain of the driving transistor;

[0029] The drain of the fifth transistor is connected between the third node and the anode of the light emitting element;

[0030] When the fifth transistor is turned on, the drain of the fifth transistor outputs a second reset signal, and writes the second reset signal into the anode of the light-emitting element.

[0031] In some embodiments, the pixel circuit further includes: a driving signal source, a sixth transistor and a seventh transistor;

[0032] The sixth transistor is connected between the driving signal source and the source of the driving transistor;

[0033] The seventh transistor is connected between the fifth transistor and the third node;

[0034] The sixth transistor, the seventh transistor and the regulating unit are all connected to the first scanning signal terminal of the pixel circuit;

[0035] When the driving transistor, the sixth transistor and the seventh transistor are all turned on, the driving signal output by the driving signal source is input to the light-emitting element through the sixth transistor, the driving transistor and the seventh transistor to drive the light-emitting element to emit light.

[0036] In some embodiments, the pixel circuit further includes: a data signal terminal, an eighth transistor, a second scan signal terminal and a capacitor element;

[0037] The source of the eighth transistor is connected to the data signal terminal, and the drain of the eighth transistor is connected to the source of the driving transistor;

[0038] The gate of the eighth transistor, the gate of the first transistor, and the gate of the second transistor are all connected to the second scanning signal terminal;

[0039] The capacitor is connected to a second node between the second transistor and the gate of the driving transistor;

[0040] When the driving transistor, the first transistor and the second transistor are all turned on, the data signal output by the data signal terminal is sequentially written into the capacitor through the driving transistor, the first transistor and the second transistor.

[0041] The embodiment of the present disclosure further provides a display panel, comprising the pixel circuit proposed in the above embodiment.

[0042] The embodiment of the present disclosure further provides a display device, comprising the display panel proposed in the above embodiment.

[0043] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0044] The pixel circuit proposed in the embodiment of the present disclosure includes a driving transistor, a dual-gate transistor and an adjustment unit, and the adjustment unit is set on the first node between the first transistor and the second transistor in the dual-gate transistor; in this way, when the pixel circuit operates in the light-emitting stage, the potential of the first node can be adjusted by adjusting the signal to reduce the voltage difference between the two electrodes of the first transistor and the voltage difference between the two electrodes of the second transistor, so as to further reduce the leakage of the dual-gate transistor caused by the large voltage difference, thereby stabilizing the gate potential of the driving transistor, improving the stability of the driving current in the pixel circuit, making the display brightness of the display panel where the pixel circuit is located more uniform, and improving the display effect of the display panel.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0047] Figure 1 is a simplified structural diagram of a pixel circuit according to an exemplary embodiment;

[0048] Figure 2 is a schematic diagram of a pixel circuit according to an exemplary embodiment. Figure 1 ;

[0049] Figure 3 is a schematic structural diagram of an adjustment unit according to an exemplary embodiment;

[0050] Figure 4 is a schematic diagram of a pixel circuit according to an exemplary embodiment. Figure 2 ;

[0051] Figure 5 is a driving timing diagram of a pixel circuit according to an exemplary embodiment;

[0052] Figure 6 is a schematic structural diagram of a traditional pixel circuit according to an exemplary embodiment;

[0053] Figure 7 is a driving timing diagram of a conventional pixel circuit according to an exemplary embodiment;

[0054] Figure 8 is a schematic diagram of a leakage path of a traditional pixel circuit according to an exemplary embodiment.

[0055] Fig. 9 is a structural block diagram of a display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0056] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0057] See also Figure 1 , Figure 1 is a simplified structural diagram of a pixel circuit according to an exemplary embodiment; Figure 1 As shown, the pixel circuit of the display panel includes: a data writing unit a, a threshold compensation unit b, a reset unit c and a light emitting unit d. A driving transistor T1 and a capacitor C0. Here, when the pixel circuit is in the light emitting stage, the light emitting brightness of the light emitting unit d is determined by the magnitude of the driving current flowing to the light emitting unit d, and when the power supply of the pixel circuit is a constant voltage power supply, the gate potential of the driving transistor T1 affects the magnitude of the driving current.

[0058] In some actual light-emitting working processes of the pixel circuit, for example, when the display panel is displaying a low-frequency picture, since the duration t of the low-frequency display is long, according to the charge formula CV=It, when the leakage current in the transistor in the threshold compensation unit b is the same, the gate potential V of the driving transistor T1 increases, causing the leakage current problem of the transistor in the threshold compensation unit b to become more serious, and affecting the size of the driving current, thereby causing the low-frequency flicker problem of the display panel.

[0059] In order to overcome the low-frequency flicker problem of the above-mentioned display panel, an embodiment of the present disclosure provides a pixel circuit. Figure 2 , Figure 2 is a schematic diagram of a pixel circuit according to an exemplary embodiment. Figure 1 ;like Figure 2 As shown, the pixel circuit proposed in the present disclosure at least includes:

[0060] Driving transistor T1;

[0061] A dual-gate transistor T3, comprising a first transistor T3-2 and a second transistor T3-1, wherein the first transistor T3-2 and the second transistor T3-1 are electrically connected between a gate and a drain of the driving transistor T1;

[0062] The regulating unit X is connected to the first node A between the first transistor T3 - 2 and the second transistor T3 - 1 , and is used to write the regulating signal into the first node A to regulate the potential of the first node A.

[0063] Here, the pixel circuit proposed in the present disclosure can be applied in a display panel, for example, it can be applied in an organic light emitting diode (OLED) display panel, where the OLED display panel includes a passive matrix organic light emitting diode (PMOLED) display panel and an AMOLED display panel.

[0064] AMOLED display panels can be used in the field of low-frequency display. At present, AMOLED display panels use a pixel design composed of a hybrid transistor of low-temperature polysilicon technology LTPS and indium zinc oxide IZO, wherein LTPS is made using a PMOS transistor process and IZO is made using an NMOS transistor process. Taking an AMOLED display panel as an example, the AMOLED display panel includes a plurality of pixel circuits proposed in the embodiments of the present disclosure. The pixel circuit is a circuit based on semiconductor technology and is composed of a plurality of transistors, which are arranged on a plane to form a matrix. Each pixel circuit is used to realize the luminous display of one or more pixel points. Here, when the pixel circuit is in the luminous stage, the adjustment unit proposed in the present disclosure can adjust the potential of the first node by adjusting the signal to reduce the leakage of the dual-gate transistor located in the threshold compensation unit due to the excessive voltage difference between the gate of the driving transistor and the anode of the light-emitting element, further stabilizing the gate potential of the driving transistor, so that the display brightness of the display panel where the pixel circuit is located is more uniform.

[0065] In the present disclosure, the driving transistor T1, the first transistor T3-2 and the second transistor T3-1 can all be field effect transistors or other devices with the same characteristics. According to the role in the circuit, the driving transistor T1, the first transistor T3-2 and the second transistor T3-1 used in the embodiments of the present disclosure can all be thin film transistors (TFT) or metal-oxide semiconductor field-effect transistors (MOSFET).

[0066] Taking the driving transistor T1, the first transistor T3-2 and the second transistor T3-1 as MOSFET tubes (hereinafter referred to as MOS tubes) as an example, the MOS tube has three electrodes, namely a gate (gate, G), a drain (drain, D) and a source (source, S); the MOS tube includes a P-channel MOS tube (hereinafter referred to as PMOS tube) and an N-channel MOS tube (hereinafter referred to as NMOS tube). The driving transistor T1, the first transistor T3-2 and the second transistor T3-1 proposed in the embodiment of the present disclosure can all be PMOS tubes or NMOS tubes, or some can be PMOS tubes and some can be NMOS tubes, and the present disclosure does not limit this.

[0067] Optionally, the driving transistor T1, the first transistor T3-2 and the second transistor T3-1 are all PMOS transistors.

[0068] It should be noted that the POMS tube is turned on when the gate potential is low (the corresponding gate-source voltage Vgs is small), and is cut off when the gate potential is high (the corresponding gate-source voltage Vgs is large). The NOMS tube is turned on when the gate potential is high (the corresponding gate-source voltage Vgs is large), and is cut off when the gate potential is low (the corresponding gate-source voltage Vgs is small).

[0069] Exemplary, combined Figure 2 In the pixel circuit shown, the source of the driving transistor T1 is connected to the data writing unit a; the gate and drain of the driving transistor T1 are respectively connected to the first transistor T3-2 and the second transistor T3-1; in addition, the gate of the driving transistor T1 is also connected to the reset unit c, and the drain of the driving transistor T1 is also connected to the light-emitting unit d; the driving transistor T1 is a POMS tube, which is turned on when the gate potential is low and turned off when the gate potential is high. When displaying different pixel frames, the pixel circuit works in the corresponding working process; here, one working process has multiple working stages. In different working stages, the reset unit c can reset the potential of the gate of the driving transistor T1, the data writing unit a can write the data signal into the capacitor element inside the pixel circuit through the driving transistor T1, and the light-emitting unit d can emit light under the action of the driving transistor T1.

[0070] In some examples, the first transistor T3 - 2 and the second transistor T3 - 1 proposed in the present disclosure are both PMOS transistors.

[0071] It should be noted that the first transistor T3-2 and the second transistor T3-1 can be transistors of the same specifications or transistors of different specifications, and the setting positions of the first transistor T3-2 and the second transistor T3-1 can be exchanged. For example, the first transistor T3-2 can be set at the position connected to the drain of the driving transistor T1, or it can be set at the position connected to the gate of the driving transistor T1. The present disclosure does not impose further restrictions on this.

[0072] In some embodiments, the source of the first transistor T3-2 is connected to the drain of the driving transistor T1, the drain of the first transistor T3-2 is connected to the source of the second transistor T3-1, and the drain of the second transistor T3-1 is connected to the gate of the driving transistor T1; the first node A is located between the drain of the first transistor T3-2 and the source of the second transistor T3-1.

[0073] Here, the gate and drain between the first transistor T3-2 and the second transistor T3-1 are interconnected, so that the dual-gate transistor T3 has a higher input impedance and a lower output impedance. The insulating layer between the first transistor T3-2 and the second transistor T3-1 can reduce current leakage, so that the dual-gate transistor T3 has higher reliability and longer life.

[0074] In other examples, the first transistor T3-2 and the second transistor T3-1 can also be a PMOS transistor and an NMOS transistor respectively; in this case, the source of the first transistor T3-2 is connected to the drain of the driving transistor T1, the drain of the first transistor T3-2 is connected to the drain of the second transistor T3-1, and the source of the second transistor T3-1 is connected to the gate of the driving transistor T1; the first node A is located between the drain of the first transistor T3-2 and the drain of the second transistor T3-1.

[0075] In some other examples, both the first transistor T3 - 2 and the second transistor T3 - 1 are NMOS transistors. In this way, since the leakage current of NMOS is small, low-frequency display can be further achieved.

[0076] In the embodiment of the present disclosure, taking the first transistor T3-2 and the second transistor T3-1 both being PMOS transistors as an example, Figure 2In the illustrated pixel circuit, when the pixel circuit operates in the light-emitting stage, there is a large voltage difference between the second node B between the gate of the driving transistor T1 and the second transistor T3-1 and the light-emitting unit d. Therefore, the embodiment of the present disclosure outputs an adjustment signal through the adjustment unit X in the light-emitting stage. The adjustment signal can be a high-level potential signal at this time to increase the potential of the first node A point. In this way, since the voltage difference between the second node B and the first node A is smaller than the voltage difference between the original second node B and the light-emitting unit d, the leakage current of the second transistor T3-1 is further reduced, and the voltage difference between the first node A and the light-emitting unit d is also smaller than the voltage difference between the original first node A and the light-emitting unit d, the leakage current of the first transistor T3-2 is further reduced.

[0077] It should be noted that, in the light-emitting stage of the pixel circuit, the adjustment signal output by the adjustment unit X can be a constant voltage signal or a dynamic signal, which is dynamically adjusted according to the potential of the second node B; at this time, the above-mentioned constant voltage signal or the above-mentioned dynamic signal is a high-level signal, and the potential written at the first node A is less than the potential of the second node B in the actual light-emitting stage.

[0078] It should also be noted that before the light-emitting phase of the current pixel frame is about to end and all working phases of the next pixel frame begin, it is necessary to change the potential of the adjustment signal and perform a low-level reset process on the first node A so that the dual-gate transistor T3 can conduct the data signal and realize the threshold compensation of the driving transistor T1 in the working phase of the next pixel frame.

[0079] In the embodiment of the present disclosure, the adjustment unit X may include a switch element, which is closed in the light-emitting stage so that the adjustment signal can be written to the first node A through the adjustment unit, and the switch element is disconnected in other working stages; the adjustment unit X may also include a variable electronic element (such as a variable resistor, a variable capacitor, etc.), which may adjust the output impedance in the light-emitting stage, and change the voltage of the output adjustment signal through the voltage division of the variable electronic element to further adjust the potential written to the first node A.

[0080] The pixel circuit proposed in the embodiment of the present disclosure includes a driving transistor, a dual-gate transistor and an adjustment unit, and the adjustment unit is set on the first node between the first transistor and the second transistor in the dual-gate transistor; in this way, when the pixel circuit operates in the light-emitting stage, the potential of the first node can be adjusted by adjusting the signal to reduce the voltage difference between the two electrodes of the first transistor and the voltage difference between the two electrodes of the second transistor, so as to further reduce the leakage of the dual-gate transistor caused by the large voltage difference, thereby stabilizing the gate potential of the driving transistor, improving the stability of the driving current in the pixel circuit, making the display brightness of the display panel where the pixel circuit is located more uniform, and improving the display effect of the display panel.

[0081] In some embodiments, see Figure 3 , Figure 3 is a schematic diagram of the structure of an adjustment unit according to an exemplary embodiment; Figure 3 As shown, the adjustment unit proposed in the embodiment of the present disclosure includes:

[0082] A third transistor T8 connected to the first node A;

[0083] When the third transistor T8 is turned on, the third transistor T8 outputs a regulating signal.

[0084] Here, the third transistor T8 can be a separate field effect transistor, such as the PMOS transistor or NMOS transistor described above in the present disclosure, or a thin film transistor TFT; the third transistor T8 can also be a dual-gate insulated transistor, which is not further limited in the present disclosure.

[0085] Here, taking the third transistor T8 as a PMOS tube as an example, the third transistor T8 has a gate, a source and a drain. When the gate potential of the third transistor T8 is low, the third transistor T8 is turned on, and the third transistor T8 outputs the adjustment signal and writes it between the first transistor T3-2 and the second transistor T3-1 in the dual-gate transistor T3. Exemplarily, the third transistor T8 is connected between the drain of the first transistor T3-2 and the source of the second transistor T3-1.

[0086] It should be noted that when the pixel circuit operates in the light-emitting stage, the third transistor T8 is turned on; during the conduction of the third transistor T8, the first transistor T3-2 and the second transistor T3-1 are both in the cut-off state, so that the adjustment signal only adjusts the potential of the first node A (combined with the above example, that is, adjusts the drain potential of the first transistor T3-2 and the source potential of the second transistor T3-1), and cannot further affect the source potential of the first transistor T3-2 and the drain potential of the second transistor T3-1 through the first transistor T3-2 and the second transistor T3-1.

[0087] In the embodiment of the present disclosure, a third transistor is provided and the unidirectional conduction performance of the third transistor is utilized to write an adjustment signal between the first transistor and the second transistor during the light-emitting phase of the pixel circuit, thereby reducing leakage current caused by the voltage difference between the first transistor and the second transistor and further stabilizing the gate potential of the driving transistor.

[0088] In some embodiments, in combination Figure 3 As shown, the pixel circuit further includes: an adjustment voltage terminal VI-1 and a first scanning signal terminal EM;

[0089] The gate of the third transistor T8 is connected to the first scanning signal terminal EM, the source of the third transistor T8 is connected to the adjustment voltage terminal VI-1, and the drain of the third transistor T8 is connected to the first node A;

[0090] Wherein, when the first scanning signal terminal EM outputs the first pulse signal, the third transistor T8 is turned on;

[0091] When the first scanning signal terminal EM outputs the second pulse signal, the third transistor T8 is turned off, and the level of the first pulse signal is lower than the level of the second pulse signal.

[0092] It should be noted that the regulating voltage terminal VI-1 is connected to at least one signal source and can output a regulating signal. When the third transistor T8 is turned on, the regulating signal can be written to the first node A through the third transistor T8.

[0093] In the embodiment of the present disclosure, the regulating voltage terminal VI-1 can be connected to a signal source or multiple signal sources. When the pixel circuit operates in the light-emitting stage, the size of the regulating signal can be adjusted to further adjust the potential change of the first node A.

[0094] Here, the third transistor T8 is a PMOS tube; when the pixel circuit works in the light-emitting stage, the first scanning signal terminal EM outputs a first pulse signal, the first pulse signal is a low-level signal, at this time, the gate-source voltage Vgs of the third transistor T8 is less than zero, the third transistor T8 is turned on, and the adjustment signal output by the adjustment voltage terminal VI-1 passes through the third transistor T8 and is written into the first node A. When the pixel circuit works in the reset stage, data writing and threshold compensation stage, the first scanning signal terminal EM outputs a second pulse signal, the second pulse signal is a high-level signal, at this time, the gate-source voltage Vgs of the third transistor T8 is greater than zero, the third transistor T8 is turned off, and the adjustment signal output by the adjustment voltage terminal VI-1 cannot pass through the third transistor T8.

[0095] In this way, by setting the first scanning signal terminal, the regulating voltage terminal and the conduction characteristic of the third transistor to work in coordination, the regulating unit can output a corresponding regulating signal at a suitable time node, thereby further improving the luminous effect of the pixel circuit.

[0096] In some embodiments, the regulated voltage terminal VI-1 is connected to an AC signal source;

[0097] Wherein, when the first scanning signal terminal EM switches to outputting the first pulse signal, the third transistor T8 outputs a high-level AC signal;

[0098] Before the first scanning signal terminal EM switches from outputting the first pulse signal to outputting the second pulse signal, the third transistor T8 switches to outputting a low-level AC signal.

[0099] Here, the adjustment voltage terminal VI-1 is connected to an AC signal source, which generates the adjustment signal, and the AC signal source can switch the level state of the adjustment signal at any time according to the working stage of the pixel circuit, for example, from a low level signal to a high level signal, or from a high level signal to a low level signal.

[0100] It should be noted that when the display panel displays images, different frames are played in sequence; the pixel circuit completes a light-emitting operation process in sequence, so that the pixels corresponding to each frame emit light in each light-emitting operation process. Here, a light-emitting operation process includes the following working stages: reset stage, data writing and threshold compensation stage, and light-emitting stage (including the early light-emitting stage and the late light-emitting stage).

[0101] The third transistor T8 proposed in the present disclosure is turned on during the entire light-emitting stage; when entering the early light-emitting stage, the first scanning signal terminal EM switches from the second pulse signal to outputting the first pulse signal, at which time the AC signal source generates a high-level AC signal, the third transistor T8 is turned on and outputs a high-level AC signal, and the first node A is written as a high potential. When entering the late light-emitting stage, the AC signal source switches to generate a low-level AC signal, the third transistor T8 is still in the on state, and switches from outputting a high-level AC signal to outputting a low-level AC signal, and the first node A is written as a low potential, so as to complete the reset process for the first node A.

[0102] Here, when the late light-emitting stage of the current frame ends and before the reset stage of the next frame starts, the first scanning signal terminal EM switches from outputting the first pulse signal to outputting the second pulse signal, at which time the third transistor T8 is turned off, and the adjustment signal cannot be written into the first node A again. Here, because the potential of the first node A is a low-level potential at the end of the late light-emitting stage of the current frame, the data writing and threshold compensation stages in the light-emitting operation process of the next frame can proceed smoothly.

[0103] In the disclosed embodiment, the regulating voltage terminal is connected to an AC signal source, which can switch the level state of the regulating signal at any time according to the working stage of the pixel circuit, so that the regulating signal output by the regulating unit is more flexible. Compared with the combination of separately connecting two DC signal sources and switches, it is more convenient and improves the working efficiency and flexibility of the pixel circuit.

[0104] In some embodiments, see Figure 4 , Figure 4 is a schematic diagram of a pixel circuit according to an exemplary embodiment. Figure 2 ; Combine Figure 4 As shown, the pixel circuit further includes a fourth transistor T5;

[0105] The fourth transistor T5 is connected to the second node B between the gate of the second transistor T3-1 and the driving transistor T1;

[0106] When the fourth transistor T5 is turned on, the drain of the fourth transistor T5 outputs the first reset signal, and writes the first reset signal into the second node.

[0107] The pixel circuit proposed in the embodiment of the present disclosure also includes: a third scan signal terminal G1 and a first reset voltage terminal VI-2; the gate of the fourth transistor T5 is connected to the third scan signal terminal G1, and the source of the fourth transistor T5 is connected to the first reset voltage terminal VI-2.

[0108] It should be noted that the fourth transistor T5 is set at Figure 2 The reset unit c is shown.

[0109] Here, the fourth transistor T5 is a PMOS tube, the third scan signal terminal G1 can output the third pulse signal or the fourth pulse signal, and the first reset voltage terminal VI-2 outputs the first reset signal. When the third scan signal tube G1 outputs the third pulse signal, the fourth transistor T5 is turned on; when the third scan signal tube G1 outputs the fourth pulse signal, the fourth transistor T5 is turned off. Here, the level of the third pulse signal is less than the level of the fourth pulse signal.

[0110] Specifically, in combination with the above disclosure, in a light-emitting operation process, the first is the reset stage, at which time the first scanning signal terminal EM outputs the second pulse signal, and the third transistor T8 is turned off; the third scanning signal terminal G1 outputs the third pulse signal, and the third pulse signal is a low-level signal. At this time, the gate-source voltage Vgs of the fourth transistor T5 is less than zero, the fourth transistor T5 is turned on, and the first reset signal output by the first reset voltage terminal VI-2 passes through the fourth transistor T5 and is written into the second node B. When the pixel circuit operates in the data writing and threshold compensation stage and the light-emitting stage, the third scanning signal terminal G1 outputs the fourth pulse signal, and the fourth pulse signal is a high-level signal. At this time, the gate-source voltage Vgs of the fourth transistor T5 is greater than zero, the fourth transistor T5 is turned off, and the first reset signal output by the first reset voltage terminal VI-2 cannot pass through the fourth transistor T5.

[0111] It should be noted that in order to ensure data writing and threshold compensation during the light-emitting operation, in the reset stage, when the fourth transistor T5 is turned on, the first reset signal is a low-level signal, so that the data signal can drive the transistor T1, the dual-gate transistor T3 and the capacitor element in the pixel circuit in sequence.

[0112] The fourth transistor provided in the embodiment of the present disclosure can perform low-potential resetting processing on the gate of the driving transistor in the pixel circuit, so that the data signal in the pixel circuit can be normally written into the pixel circuit, ensuring the orderly progress of the light emitting process.

[0113] In the present disclosure, in combination Figure 4 The first reset voltage terminal VI-2 and the adjustment voltage terminal VI-1 can be connected to the same signal source, or connected to different signal sources, and the present disclosure does not limit this.

[0114] In some embodiments, the fourth transistor T5 and the regulating unit X are connected to the same AC signal source;

[0115] When the fourth transistor T5 is turned on, the first reset signal and the adjustment signal are the same low-level signal.

[0116] In the present disclosure, the regulating unit includes the third transistor T8, so the fourth transistor T5 and the third transistor T8 can be connected to the same AC signal source. Specifically, the first reset voltage terminal and the regulating voltage terminal are both connected to the AC signal source.

[0117] Here, in the reset stage, the fourth transistor T5 is turned on, and the first reset signal is written into the second node B through T5 (i.e., the gate potential of the driving transistor T1 is pulled down for reset processing). At this time, the third transistor T8 is turned off, and the adjustment signal is also a low-level signal, but cannot be written into the first node A.

[0118] In the data writing and threshold compensation stage, the first scanning signal terminal EM outputs a second pulse signal, the third scanning signal terminal G1 outputs a fourth pulse signal, the fourth transistor T5 and the third transistor T8 are both turned off, the first reset signal is a low level signal, but cannot pass through the fourth transistor T5, and the adjustment signal is also the same low level signal, but cannot pass through the third transistor T8;

[0119] In the light-emitting stage, the first scanning signal terminal EM outputs a first pulse signal, the third scanning signal terminal G1 outputs a fourth pulse signal, the fourth transistor T5 is cut off, the first reset signal is a high-level signal, but cannot pass through the fourth transistor T5. At this time, the third transistor T8 is turned on, and the adjustment signal is also the same high-level signal, which can be written to the first node through the third transistor T8.

[0120] The present disclosure can reduce the number of signal sources to be set, simplify circuit design, and increase the convenience of pixel circuit control by setting the fourth transistor and the adjustment unit to be connected to the same AC signal source.

[0121] In some other embodiments, the fourth transistor T5 is connected to the first DC signal source, and the regulating unit X is connected to the AC signal source.

[0122] Here, the first reset voltage terminal VI-2 is connected to the first DC signal source, and the adjustment voltage terminal VI-1 is connected to the AC signal source.

[0123] The first reset signal generated by the first DC signal source is a low-level DC signal, wherein in the reset stage, the fourth transistor T5 is turned on, and the low-level DC signal is written into the second node through the fourth transistor T5; in the data writing and threshold compensation stage and the light emitting stage, the fourth transistor T5 is turned off, and the low-level DC signal cannot pass through the fourth transistor T5.

[0124] In some embodiments, in combination Figure 4 As shown, the pixel circuit proposed in the embodiment of the present disclosure further includes: a light emitting element EL and a fifth transistor T4;

[0125] The anode of the light emitting element EL is connected to a third node D between the double gate transistor T3 and the drain of the driving transistor T1;

[0126] The drain of the fifth transistor T4 is connected between the third node D and the anode of the light emitting element EL;

[0127] When the fifth transistor T4 is turned on, the drain of the fifth transistor T4 outputs the second reset signal, and writes the second reset signal into the anode of the light emitting element EL.

[0128] Here, the light emitting element EL can emit light in the light emitting phase, thereby realizing effective brightness display of the pixel frame.

[0129] The pixel circuit proposed in the present disclosure further includes a second reset voltage terminal VI-3; the gate of the fifth transistor T4 is connected to the third scan signal terminal G1, and the source of the fifth transistor T4 is connected to the second reset voltage terminal VI-3.

[0130] It should be noted that the fifth transistor T4 and the light emitting element EL are both arranged Figure 2 The light emitting unit d is shown.

[0131] Here, the fifth transistor T4 is a PMOS tube, and the second reset voltage terminal VI-3 outputs the second reset signal. When the third scanning signal terminal G1 outputs the third pulse signal, the fifth transistor T4 is turned on; when the third scanning signal terminal G1 outputs the fourth pulse signal, the fifth transistor T4 is turned off.

[0132] Specifically, in combination with the above disclosure, in the reset stage of a light-emitting operation process, at this time, the first scanning signal terminal EM outputs the second pulse signal, and the third transistor T8 is turned off; the second scanning signal terminal G1 outputs the third pulse signal, at this time, the gate-source voltage Vgs of the fifth transistor T4 is less than zero, the fifth transistor T4 is turned on, and the second reset signal output by the second reset voltage terminal VI-3 passes through the fifth transistor T4 and is written into the fourth node C (the anode of the light-emitting element EL). When the pixel circuit works in the data writing and threshold compensation stage and the light-emitting stage, the second scanning signal terminal G1 outputs the fourth pulse signal, and the fourth pulse signal is a high-level signal. At this time, the gate-source voltage Vgs of the fifth transistor T4 is greater than zero, the fifth transistor T4 is turned off, and the second reset signal output by the second reset voltage terminal VI-3 cannot pass through the fifth transistor T4.

[0133] It should be noted that, in order to ensure data writing and threshold compensation during the light-emitting operation, in the reset stage, when the fifth transistor T4 is turned on, the second reset signal is a low-level signal, so that the subsequent drive current can be input into the light-emitting element.

[0134] It should also be noted that the second reset voltage terminal VI-3 is connected to a second DC signal source, and the second reset signal generated by the second DC signal source is a low-level DC signal. In the present disclosure, the first reset signal and the second reset signal are both low-level signals, but the voltage values ​​can be the same or different.

[0135] In some examples, when the pixel circuit operates in the reset phase, the voltage value of the first reset signal written into the second node B is the same as the voltage value of the second reset signal written into the fourth node C. At this time, the gate potential of the driving transistor T1 is the same as the anode potential of the light-emitting element EL. In other examples, the voltage value of the first reset signal written into the second node B is less than the voltage value of the second reset signal written into the fourth node C. At this time, the gate potential of the driving transistor T1 is less than the anode potential of the light-emitting element EL.

[0136] Here, the pixel circuit further includes a ground terminal VSS, and the cathode of the light emitting element EL is connected to the ground terminal VSS to ensure the potential balance of the pixel circuit.

[0137] The disclosed embodiment provides a fifth transistor capable of performing a low-potential reset process on the anode of the light-emitting element in the pixel circuit, so that the driving current in the pixel circuit can be input to the light-emitting element, thereby ensuring the orderly progress of the light-emitting process.

[0138] In some embodiments, the pixel circuit further includes: a driving signal source VDD, a sixth transistor T6 and a seventh transistor T7;

[0139] The sixth transistor T6 is connected between the driving signal source VDD and the source of the driving transistor T1;

[0140] The seventh transistor T7 is connected between the fifth transistor T4 and the third node D;

[0141] The sixth transistor T6, the seventh transistor T7 and the adjustment unit are all connected to the first scanning signal terminal EM of the pixel circuit;

[0142] When the driving transistor T1, the sixth transistor T6 and the seventh transistor T7 are all turned on, the driving signal output by the driving signal source VDD is sequentially input to the light emitting element EL through the sixth transistor T6, the driving transistor T1 and the seventh transistor T7 to drive the light emitting element EL to emit light.

[0143] Here, the driving signal source VDD is a constant voltage signal source in the pixel circuit, and is used to output a driving signal, and the driving signal is used to control the light emission brightness of the light emitting element EL.

[0144] In the embodiment of the present disclosure, the gate of the sixth transistor T6 is connected to the first scanning signal terminal EM, the source of the sixth transistor T6 is connected to the driving signal source VDD, and the drain of the sixth transistor T6 is connected to the source of the driving transistor T1; the gate of the seventh transistor T7 is connected to the first scanning signal terminal EM, the source of the seventh transistor T7 is connected to the third node D, and the drain of the seventh transistor T7 is connected to the anode of the light-emitting element EL.

[0145] It should be noted that the seventh transistor T7 is set at Figure 2 The light emitting unit d is shown.

[0146] Here, the sixth transistor and the seventh transistor T7 are both PMOS tubes. When the first scanning signal terminal EM outputs the first pulse signal, the driving transistor T1, the sixth transistor T6, and the seventh transistor T7 are all turned on; when the first scanning signal terminal EM outputs the second pulse signal, the sixth transistor T6 and the seventh transistor T7 are both turned off.

[0147] When the pixel circuit works in a light-emitting stage of a light-emitting process, the third scanning signal terminal G1 outputs a fourth pulse signal, and the fourth transistor T5 and the fifth transistor T4 are both in the cut-off state; the first scanning signal terminal EM outputs a first pulse signal, the first pulse signal is a low-level signal, the gate-source voltage Vgs of the sixth transistor T6 is less than zero, and the gate-source voltage Vgs of the seventh transistor T7 is less than zero. At this time, the sixth transistor T6, the seventh transistor T7 and the driving transistor T1 are all turned on, and the driving signal output by the driving signal source VDD is input to the light-emitting element EL through the sixth transistor T6, the driving transistor T1 and the seventh transistor T7 to drive the light-emitting element EL to emit light; when the pixel circuit works in the reset stage, the data writing and the threshold compensation stage, when the first scanning signal tube EM outputs a second pulse signal, the gate-source voltage Vgs of the sixth transistor T6 is greater than zero, the gate-source voltage of the seventh transistor T7 is greater than zero, the sixth transistor T6 and the seventh transistor T7 are both cut off, and the driving signal cannot pass through the sixth transistor T6 and the seventh transistor T7.

[0148] In the embodiment of the present disclosure, the sixth transistor, the seventh transistor and the driving transistor are arranged to work in coordination, so that the light-emitting element of the pixel circuit can emit light in a suitable working phase.

[0149] In some embodiments, the pixel circuit further includes: a data signal terminal SD, an eighth transistor T2, a second scan signal terminal G2 and a capacitor element C1;

[0150] The source of the eighth transistor T2 is connected to the data signal terminal SD, and the drain of the eighth transistor T2 is connected to the source of the driving transistor T1;

[0151] The gate of the eighth transistor T2, the gate of the first transistor T3-2, and the gate of the second transistor T3-1 are all connected to the second scanning signal terminal G2;

[0152] The capacitor element C1 is connected to a second node B between the second transistor T3-1 and the gate of the driving transistor T1;

[0153] When the driving transistor T1, the first transistor T3-2 and the second transistor T3-1 are all turned on, the data signal output by the data signal terminal SD is sequentially written into the capacitor element C1 through the driving transistor T1, the first transistor T3-2 and the second transistor T3-1.

[0154] Here, the capacitor element C1 can store charges, and the data signal in the present disclosure can be written into the capacitor element C1 for charge storage, thereby completing the charging process of the capacitor element C1.

[0155] The data signal terminal SD is connected to a data signal source and is used to output a data signal generated by the data signal source. Here, the data signal source may be located in a control module of the display device, such as a system-level chip disposed in a mainboard.

[0156] It should be noted that the eighth transistor T2 is set at Figure 2 The data shown is written into unit a.

[0157] Here, the eighth transistor T2 is a PMOS tube, the first transistor T3-2 and the second transistor T3-1 are also PMOS tubes, and the source of the first transistor T3-2 is connected to the drain of the driving transistor T1, the drain of the first transistor T3-2 is connected to the source of the second transistor T3-1, and the drain of the second transistor T3-1 is connected to the gate of the driving transistor T1; when the second scanning signal terminal G2 outputs the fifth pulse signal, the eighth transistor T2, the first transistor T3-2 and the second transistor T3-1 are turned on; when the second scanning signal terminal G2 outputs the sixth pulse signal, the eighth transistor T2, the first transistor T3-2 and the second transistor T3-1 are turned off. Here, the level of the fifth pulse signal is less than the level of the sixth pulse signal.

[0158] Specifically, in combination with the above disclosure, in the data writing and threshold compensation stage of a light-emitting working process, the third scanning signal terminal G1 outputs a fourth pulse signal, and the fourth transistor T5 and the fifth transistor T4 are both turned off; the first scanning signal terminal EM outputs a second pulse signal, and the third transistor T8, the sixth transistor T6, and the first transistor T7 are all turned off; at this time, the second scanning signal terminal G2 outputs a fifth pulse signal, and the fifth pulse signal is a low-level signal. At this time, the gate-source voltage Vgs corresponding to the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are all less than zero, and the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are all turned on. The data signal output by the data signal terminal SD passes through the source and drain of the eighth transistor T2 and the driving transistor T1, and the sixth transistor T3-1 is turned on. T6, the first transistor T7, write to the second node B (that is, the gate of the driving transistor), and compensate the threshold voltage Vth of the driving transistor T1, so that the node B has both the SD data information and the threshold compensation information of the driving transistor T1, and at the same time writes the SD data information into the capacitor element C1 to charge the capacitor element C1; when the pixel circuit works in the reset stage and the light-emitting stage, the second scanning signal terminal G2 outputs the sixth pulse signal, and the sixth pulse signal is a high-level signal. At this time, the gate-source voltage Vgs corresponding to the eighth transistor T2, the first transistor T3-2 and the second transistor T3-1 are all greater than zero, the eighth transistor T2, the first transistor T3-2 and the second transistor T3-1 are all cut off, and the data signal output by the data signal terminal SD cannot pass through the fourth transistor T5.

[0159] The disclosed embodiment provides that the second transistor, the driving transistor and the dual-gate transistor work in coordination, so that the data signal corresponding to the pixel circuit can be written into the capacitor element and the threshold compensation of the driving transistor is completed.

[0160] According to the pixel circuit proposed in the above embodiment of the present disclosure, the specific light-emitting operation process of the pixel circuit in the actual pixel frame display stage is described. Figure 5 , Figure 5 is a driving timing diagram of a pixel circuit according to an exemplary embodiment; Figure 5 As shown, the working stages of the pixel circuit include: the late light-emitting stage (t1) corresponding to the previous pixel frame, the reset stage (t2) of the current pixel frame, the data writing and threshold compensation stage (t3) of the current pixel frame, and the early light-emitting stage (t4) of the current pixel frame.

[0161] First of all, it should be explained that the light-emitting working process corresponding to each pixel frame is the reset stage, the data writing and threshold compensation stage, the early light-emitting stage and the late light-emitting stage. The driving timing diagram shown in the present invention captures part of the working stages in the previous pixel frame and the current pixel frame.

[0162] Here, in combination with the pixel circuit proposed in the above embodiment of the present disclosure and Figures 2 to 4 The pixel circuit shown in FIG. Figure 5 The working status of each device in the pixel circuit in each working stage.

[0163] In the late light-emitting stage (t1 stage) corresponding to the previous pixel frame:

[0164] The first scanning signal terminal EM outputs a first pulse signal and is in a low voltage on state; at this time, the third transistor T8, the sixth transistor T6, and the seventh transistor T7 are all turned on;

[0165] The second scanning signal terminal G2 outputs the sixth pulse signal and is in a high voltage cut-off state; at this time, the eighth transistor T2, the first transistor T3-2 and the second transistor T3-1 are all cut off;

[0166] The third scanning signal terminal G1 outputs a fourth pulse signal and is in a high voltage cut-off state; at this time, the fifth transistor T4 and the fourth transistor T5 are both cut off;

[0167] Here, in the early stage of light emission corresponding to the previous pixel frame (i.e., before stage t1), the regulating signal output by the regulating voltage terminal VI-1 is a high-level AC signal, and the first node A of the pixel circuit is at a relatively high potential, reducing the voltage difference between the second node B and the first node A. At this time, the leakage current of the second transistor T3-1 is reduced, making the potential of the second node B relatively stable. In stage t1, the regulating voltage terminal VI-1 switches from outputting the regulating signal to outputting a low-level AC signal, and the first node A of the pixel circuit becomes a low potential, and the first node A is pulled down and reset. Prepare for subsequent data writing and threshold compensation actions.

[0168] During the reset phase (t2 phase) of the current pixel frame:

[0169] The first scanning signal terminal EM outputs a second pulse signal and is in a high voltage cut-off state; at this time, the third transistor T8, the sixth transistor T6, and the seventh transistor T7 are all cut off;

[0170] The second scanning signal terminal G2 outputs the sixth pulse signal and is in a high voltage cut-off state; at this time, the eighth transistor T2, the first transistor T3-2 and the second transistor T3-1 are all cut off;

[0171] The third scanning signal terminal G1 outputs a third pulse signal and is in a low voltage on state; at this time, the fifth transistor T4 and the fourth transistor T5 are both turned on;

[0172] It should be noted that after the end of the late luminescence phase (phase t1) corresponding to the previous pixel frame and before the beginning of the reset phase (phase t2) of the current pixel frame, the first scanning signal terminal EM switches from outputting the first pulse signal to outputting the second pulse signal.

[0173] Here, the first reset voltage terminal VI-2 outputs a first reset signal, the first reset signal is a low-level signal, and the first reset signal is pulled down to reset the second node B through the fourth transistor T5; the second reset voltage terminal VI-3 outputs a second reset signal, the second reset signal is a low-level signal, and the second reset signal is pulled down to reset the fourth node C through the fifth transistor T4.

[0174] In the data writing and threshold compensation phase of the current pixel frame (t3 phase):

[0175] The first scanning signal terminal EM outputs a second pulse signal and is in a high voltage cut-off state; at this time, the third transistor T8, the sixth transistor T6, and the seventh transistor T7 are all cut off;

[0176] The second scanning signal terminal G2 outputs a fifth pulse signal and is in a low voltage on state; at this time, the eighth transistor T2, the first transistor T3-2 and the second transistor T3-1 are all turned on;

[0177] The third scanning signal terminal G1 outputs a fourth pulse signal and is in a high voltage cut-off state; at this time, the fifth transistor T4 and the fourth transistor T5 are both cut off;

[0178] It should be noted that at the end of the reset phase (phase t2) of the current pixel frame and before the start of the data writing and threshold compensation phase (phase t3) of the current pixel frame, the third scanning signal terminal G1 switches from outputting the third pulse signal to outputting the fourth pulse signal.

[0179] Here, the data signal output by the data signal terminal SD passes through the eighth transistor T2, the source and drain of the driving transistor T1, the sixth transistor T6, and the first transistor T7, and is written to the second node B (i.e., the gate of the driving transistor T1), and the threshold voltage Vth of the driving transistor T1 is compensated, so that the node B has both the SD data information and the threshold compensation information of the driving transistor T1, and the SD data information is written into the capacitor element C1 at the same time to charge the capacitor element C1.

[0180] In the early stage of light emission of the current pixel frame (t4 stage):

[0181] The first scanning signal terminal EM outputs a first pulse signal and is in a low voltage on state; at this time, the third transistor T8, the sixth transistor T6, and the seventh transistor T7 are all turned on;

[0182] The second scanning signal terminal G2 outputs the sixth pulse signal and is in a high voltage cut-off state; at this time, the eighth transistor T2, the first transistor T3-2 and the second transistor T3-1 are all cut off;

[0183] The third scanning signal terminal G1 outputs a fourth pulse signal and is in a high voltage cut-off state; at this time, the fifth transistor T4 and the fourth transistor T5 are both cut off;

[0184] It should be noted that, at the end of the data writing and threshold compensation stage (t3 stage) of the current pixel frame and before the beginning of the pre-luminescence stage (t4 stage) of the current pixel frame, the second scanning signal terminal G2 outputs the fifth pulse signal and switches to outputting the sixth pulse signal, and the adjustment signal output by the adjustment voltage terminal VI-1 switches from a low-level AC signal to a high-level AC signal, so that the first node A of the pixel circuit is at a relatively high potential in the pre-luminescence stage (t4 stage) of the current pixel frame.

[0185] Here, the driving signal output by the driving signal source VDD is input to the light emitting element EL through the sixth transistor T6, the driving transistor T1 and the seventh transistor T7, forming a current loop from VDD-T6-T1-T7-EL-VSS to drive the light emitting element EL to emit light. Here, the gate potential of the driving transistor T1 (the potential of the second node B) affects the size of the driving current and determines the brightness of the light emitting element.

[0186] Through the pixel circuit proposed in the present disclosure, when the pixel circuit displays a low grayscale image, the first node A is a high potential corresponding to the adjustment voltage terminal VI-1, and the voltage difference between this potential and the voltage of the second node B is small, less than Figure 1 The voltage difference between the gate potential of the driving transistor T1 and the light-emitting unit d in the pixel circuit shown can reduce the leakage of the second transistor T3-1. At the same time, the voltage difference between the first node A and the fourth node C is also smaller than the voltage difference between the original first node A and the light-emitting unit d, further reducing the leakage of the first transistor T3-2; at the same time, the leakage path of the first transistor T3-2 is node C-T7-T3-2-T8-VI-1, reducing the impact on the second node B and stabilizing the potential of the second node B; therefore, through the adjustment unit set in the pixel circuit proposed in the present disclosure, the potential of the second node B can be stabilized in the early stage of light emission, and the stability of the driving current in the pixel circuit can be improved, so that the display brightness of the display panel where the pixel circuit is located is more uniform, the low grayscale flicker problem is improved, and the display effect of the display panel is improved, which is more suitable for application in ultra-low frequency display devices.

[0187] See also Figure 6 , Figure 7 and Figure 8 , Figure 6 is a schematic structural diagram of a traditional pixel circuit according to an exemplary embodiment; Figure 7 is a driving timing diagram of a conventional pixel circuit according to an exemplary embodiment; Figure 8 is a schematic diagram of a leakage path of a traditional pixel circuit according to an exemplary embodiment.

[0188] like Figure 6 As shown, the conventional pixel circuit is a 7T1C pixel compensation circuit, which is a high-precision, low-power memory circuit, consisting of 7 MOSFET tubes (here, the dual-gate transistor is understood as a transistor, and the same applies below) and 1 capacitor (capacitor element C0) in each storage unit. Figure 6 and Figure 7In the traditional pixel circuit, the traditional data input terminal SD-0, the first traditional scanning signal terminal EM-0, the second traditional scanning signal input terminal G2-0, and the third traditional scanning signal input terminal G1-0 input corresponding signals in different working stages to control the conduction or cutoff of each transistor; the traditional reset voltage terminal VI-0 outputs a reset signal in the corresponding working stage to control the reset of the corresponding node of the pixel circuit. The working process of the traditional pixel circuit may include the following stages:

[0189] Reset stage (t1′ stage): the third traditional scanning signal input terminal G1-0 is in a low-voltage on state. Under the action of the third traditional scanning signal input terminal G1-0, transistors T4 and T5 are turned on, and the traditional reset voltage terminal VI-0 outputs a low-level DC signal written to the second node B and the fourth node C, resetting the capacitor element C0 and the light-emitting element anode EL.

[0190] Data writing and threshold compensation stage (t2′ stage): The second conventional scanning signal input terminal G2 is in the low voltage start stage. Under the action of the second conventional scanning signal input terminal G2-0, transistors T2 and T3 are turned on; thus, the data signal is sequentially written to node B through transistors T2, T1 and T3 to charge capacitor C0. At this time, the gate and drain of transistor T1 are connected to form a diode mode, and the gate potential of transistor T1 contains the threshold voltage signal of transistor T1, which performs the threshold voltage compensation function.

[0191] Light-emitting stage (t3′ stage): the first conventional scanning signal terminal EM-0 is in a low voltage on state. Under the action of the first conventional scanning signal terminal EM-0, transistors T6 and T7 are turned on, and a light-emitting current is formed in the VDD-T6-T1-T7-EL-VSS loop. The magnitude of the light-emitting current is determined by the gate potential of transistor T1. This light-emitting stage lasts until the t1 stage of the next frame, thereby realizing light-emitting display of the display panel.

[0192] Combination Figure 8 When the display panel where the pixel circuit is located displays a low grayscale image, because the potential of the second node B is greater than the potential of the third node C, and the voltage difference is large, leakage current is generated in the dual-gate transistor T3 (including T3-2 and T3-1). The leakage path caused by the leakage current of the dual-gate transistor T3 is the second node B-T3-1-A-T3-2-T7-the fourth node C-EL-VSS, that is, Figure 8 When the display panel where the pixel circuit is located displays a high grayscale image, the potential of the fourth node C is higher than that of the first node A, and the leakage path caused by the leakage of the dual-gate transistor T3 is the fourth node C-T7-T3-2-A-T3-1-B, that is, Figure 8In the above situation, the leakage action of the leakage path I_1 increases the current flowing through the light emitting element EL, making the light emitting element EL brighter; the path I_2 increases the potential of the second node B, making the driving current output by the transistor T1 lower, making the brightness of the light emitting element EL lower; the above situation all cause the problem of unstable light emitting brightness of the light emitting element EL.

[0193] In order to alleviate the leakage current in the above-mentioned traditional pixel compensation circuit and reduce the light flickering problem, the present disclosure proposes an 8T1C pixel compensation circuit, in which a third transistor T8 is added. Figure 4 The pixel circuit structure diagram shown, and Figure 5 As shown in the driving timing diagram, the third transistor T8 is provided in the 8T1C pixel compensation circuit proposed in the present disclosure, which can output an adjustment signal; compared with the traditional pixel compensation circuit, the light-emitting stage in the present disclosure includes an early light-emitting stage and a late light-emitting stage. In the early light-emitting stage, the adjustment signal is a high-level signal, which pulls up the potential of the first node A, and in the late light-emitting stage, the adjustment signal is a low-level signal, which reduces the potential of the first node A to reset it.

[0194] Thus, when the display panel where the pixel circuit is located displays a low grayscale image, the first node A is a high potential corresponding to the adjustment voltage terminal VI-1, and the voltage difference between this potential and the voltage of the second node B is small, less than Figure 1 The voltage difference between the gate potential of the driving transistor T1 and the light-emitting unit d in the pixel circuit shown can reduce the leakage of the second transistor T3-1. At the same time, the voltage difference between the first node A and the fourth node C is also smaller than the voltage difference between the original first node A and the light-emitting unit d, further reducing the leakage of the first transistor T3-2; at the same time, the leakage path of the first transistor T3-2 is node C-T7-T3-2-T8-VI-1, reducing the impact on the second node B and stabilizing the potential of the second node B; when the pixel circuit displays a high grayscale image, the leakage path of the first transistor T3-2 is node C-T7-T3-2-T8-VI-1, reducing the impact on the second node B. Therefore, the pixel circuit proposed in the present disclosure can effectively adjust the potential of the first node through the third transistor and the adjustment signal, reduce the voltage difference between the source and the drain of the first transistor and the voltage difference between the source and the drain of the second transistor when the pixel circuit is working in the light-emitting stage, so as to further reduce the leakage of the dual-gate transistor due to the large voltage difference, thereby stabilizing the gate potential of the driving transistor, improving the stability of the driving current in the pixel circuit, making the display brightness of the display panel where the pixel circuit is located more uniform, improving the low grayscale flicker problem, improving the display effect of the display panel, and being more suitable for application in ultra-low frequency display devices.

[0195] It should be noted that the driving transistor and the first to eighth transistors in the above embodiments of the present disclosure are discussed using PMOS transistors as examples. In some other examples, the driving transistor and the first to eighth transistors may all be NMOS transistors, or some may be PMOS transistors and some may be NMOS transistors. Since the PMOS transistor is turned on when the gate is at a low potential and the NMOS transistor is turned on when the gate is at a high potential, the present disclosure only needs to ensure that the conduction conditions of the driving transistor and the first to eighth transistors are the same as those in the examples described above, and the signals output by the adjustment voltage terminal, the first reset voltage signal terminal and the second reset voltage signal terminal are the same as those in the examples described above, and the corresponding pulse signals output by the first scanning signal terminal EM, the second scanning signal terminal G2, and the third scanning signal segment G1 can be adjusted accordingly, or connected to other scanning signal terminals. The present disclosure will not further elaborate on this.

[0196] The embodiment of the present disclosure further provides a display panel, comprising the pixel circuit proposed in the above embodiment.

[0197] Here, the display panel includes an organic light emitting diode (OLED) display panel, and the OLED display panel includes a passive matrix organic light emitting diode (PMOLED) display panel and an AMOLED display panel.

[0198] In the present disclosure, the display panel includes multiple pixel circuits, each pixel circuit is used to individually control one or several pixels for brightness display, here, each pixel circuit includes at least multiple functional elements proposed in the above-mentioned embodiments of the present disclosure, and the multiple functional elements include at least a driving transistor, a dual-gate transistor, an adjustment unit, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a light-emitting element, a capacitor element and other devices.

[0199] Through the pixel circuit proposed in the present invention, when a pixel light-emitting display is performed in a display panel, the potential of the first node in the middle of the dual-gate transistor can be adjusted during the light-emitting stage to reduce the leakage of the dual-gate transistor due to the large voltage difference, further stabilize the gate potential of the driving transistor, and make the display brightness of the display panel more uniform.

[0200] The embodiment of the present disclosure further provides a display device, comprising the display panel proposed in the above embodiment.

[0201] Here, the display device includes an electronic device with a display function, and the electronic device includes but is not limited to a computer, a mobile terminal, and a portable electronic device. The mobile terminal includes but is not limited to a mobile phone and a tablet computer; the portable electronic device includes but is not limited to a smart watch; here, the embodiment of the present disclosure does not further limit the type of the display device.

[0202] In the present disclosure, the display device includes a display panel, a mainboard, a battery, etc. The battery is used to provide power to the display panel. A system-level chip is provided on the mainboard, and the system-level chip is connected to the display panel to control the pixel display on the display panel.

[0203] Fig. 9 9 is a block diagram of a display device according to an exemplary embodiment. For example, the display device 900 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0204] Reference Fig. 9 , the display device 900 may include one or more of the following components: a processing component 902 , a memory 904 , a power component 906 , a multimedia component 908 , an audio component 910 , an input / output (I / O) interface 912 , a sensor component 914 , and a communication component 916 .

[0205] The processing component 902 generally controls the overall operation of the display device 900, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 902 may include one or more processors 920 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 902 may include one or more modules to facilitate the interaction between the processing component 902 and other components. For example, the processing component 902 may include a multimedia module to facilitate the interaction between the multimedia component 908 and the processing component 902.

[0206] The memory 904 is configured to store various types of data to support the operation of the display device 900. Examples of such data include instructions for any application or method operating on the display device 900, contact data, phone book data, messages, pictures, videos, etc. The memory 904 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0207] The power supply component 906 provides power to various components of the display device 900. The power supply component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the display device 900.

[0208] The multimedia component 908 includes a screen that provides an output interface between the display device 900 and the user. The pixel circuit proposed in the present disclosure is applied on the screen. In some embodiments, the screen may include an OLED display panel, such as an AMOLED display panel, and may also be a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 908 includes a front camera and / or a rear camera. When the display device 900 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0209] The audio component 910 is configured to output and / or input audio signals. For example, the audio component 910 includes a microphone (MIC), and when the display device 900 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 904 or sent via the communication component 916. In some embodiments, the audio component 910 also includes a speaker for outputting audio signals.

[0210] I / O interface 912 provides an interface between processing component 902 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0211] The sensor assembly 914 includes one or more sensors for providing various aspects of status assessment for the display device 900. For example, the sensor assembly 914 can detect the open / closed state of the display device 900, the relative positioning of components, such as the display and keypad of the display device 900, and the sensor assembly 914 can also detect the position change of the display device 900 or a component of the display device 900, the presence or absence of user contact with the display device 900, the orientation or acceleration / deceleration of the display device 900, and the temperature change of the display device 900. The sensor assembly 914 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 914 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 914 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0212] The communication component 916 is configured to facilitate wired or wireless communication between the display device 900 and other devices. The device 900 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 916 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 916 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0213] In an exemplary embodiment, the display device 900 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0214] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions, which can be executed by a processor 920 of the display device 900. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0215] The pixel circuit proposed in the present disclosure is applied in a display panel of a display device, and can adjust the potential of the first node A during the light-emitting stage to reduce the leakage of the dual-gate transistor due to the large voltage difference, further stabilize the gate potential of the driving transistor, and make the display brightness of the display panel where the pixel circuit is located more uniform.

[0216] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0217] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A pixel circuit, characterized in that: include: Driver transistor; A dual-gate transistor, comprising a first transistor and a second transistor, wherein the first transistor and the second transistor are electrically connected between a gate and a drain of the driving transistor; The regulating unit is connected to a first node between the first transistor and the second transistor, and is used for writing a regulating signal into the first node to regulate the potential of the first node.

2. The pixel circuit according to claim 1, characterized in that: The adjustment unit comprises: a third transistor connected to the first node; Wherein, when the third transistor is turned on, the third transistor outputs the regulating signal.

3. The pixel circuit according to claim 2, characterized in that: The pixel circuit further includes: a voltage adjustment terminal and a first scanning signal terminal; The gate of the third transistor is connected to the first scanning signal terminal, the source of the third transistor is connected to the regulating voltage terminal, and the drain of the third transistor is connected to the first node; Wherein, when the first scanning signal terminal outputs the first pulse signal, the third transistor is turned on; When the second pulse signal is outputted at the first scanning signal terminal, the third transistor is turned off, and the level of the first pulse signal is lower than the level of the second pulse signal.

4. The pixel circuit according to claim 3, characterized in that: The voltage regulating terminal is connected to an AC signal source; Wherein, when the first scanning signal terminal switches to outputting the first pulse signal, the third transistor outputs a high-level AC signal; Before the first scanning signal terminal switches from outputting the first pulse signal to outputting the second pulse signal, the third transistor switches to outputting a low-level AC signal.

5. The pixel circuit according to claim 1, characterized in that: The source of the first transistor is connected to the drain of the driving transistor, the drain of the first transistor is connected to the source of the second transistor, and the drain of the second transistor is connected to the gate of the driving transistor; The first node is located between the drain of the first transistor and the source of the second transistor.

6. The pixel circuit according to any one of claims 1 to 5, characterized in that: The pixel circuit further includes a fourth transistor; The fourth transistor is connected to a second node between the second transistor and the gate of the driving transistor; When the fourth transistor is turned on, the drain of the fourth transistor outputs a first reset signal, and writes the first reset signal into the second node.

7. The pixel circuit according to claim 6, characterized in that: The fourth transistor and the regulating unit are connected to the same AC signal source; Wherein, when the fourth transistor is turned on, the first reset signal and the adjustment signal are the same low-level signal.

8. The pixel circuit according to any one of claims 1 to 5, characterized in that: The pixel circuit further includes: a light emitting element and a fifth transistor; The anode of the light emitting element is connected to a third node between the drain of the dual-gate transistor and the drain of the driving transistor; The drain of the fifth transistor is connected between the third node and the anode of the light emitting element; When the fifth transistor is turned on, the drain of the fifth transistor outputs a second reset signal, and writes the second reset signal into the anode of the light-emitting element.

9. The pixel circuit according to claim 8, characterized in that: The pixel circuit further includes: a driving signal source, a sixth transistor and a seventh transistor; The sixth transistor is connected between the driving signal source and the source of the driving transistor; The seventh transistor is connected between the fifth transistor and the third node; The sixth transistor, the seventh transistor and the regulating unit are all connected to the first scanning signal terminal of the pixel circuit; When the driving transistor, the sixth transistor and the seventh transistor are all turned on, the driving signal output by the driving signal source is input to the light-emitting element through the sixth transistor, the driving transistor and the seventh transistor to drive the light-emitting element to emit light.

10. The pixel circuit according to any one of claims 1 to 5, characterized in that: The pixel circuit further includes: a data signal terminal, an eighth transistor, a second scanning signal terminal and a capacitor element; The source of the eighth transistor is connected to the data signal terminal, and the drain of the eighth transistor is connected to the source of the driving transistor; The gate of the eighth transistor, the gate of the first transistor, and the gate of the second transistor are all connected to the second scanning signal terminal; The capacitor is connected to a second node between the second transistor and the gate of the driving transistor; When the driving transistor, the first transistor and the second transistor are all turned on, the data signal output by the data signal terminal is sequentially written into the capacitor through the driving transistor, the first transistor and the second transistor.

11. A display panel, characterized in that: Comprising the pixel circuit as claimed in any one of claims 1 to 10.

12. A display device, characterized in that: Comprising the display panel as claimed in claim 11.

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