Display driving method, display driving circuit and display panel

Abstract

The invention discloses a display driving method, a display driving circuit and a display panel, and the method comprises the steps: obtaining a low-brush display region, carrying out the frequency reduction of a first clock signal corresponding to the low-brush display region according to the low-brush display region, and obtaining a second clock signal; a pixel driving unit corresponding to the low-brush display area is controlled to generate a corresponding pixel driving signal according to a grid scanning signal and a second clock signal, and the frequency of the second clock signal is set to be greater than or equal to the frequency of the pixel driving signal, so that the power consumption of the low-brush display area is reduced when the display picture is subjected to refresh rate partition display; the power consumption income in a partition refreshing application scene is improved, and the purpose of reducing display power consumption is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a display driving method, a display driving circuit, and a display panel. Background Art

[0002] As people's living standards improve, electronic products play an important role in people's lives. Display panels are important components of electronic products, so the demand for display panels is increasing.

[0003] Nowadays, ordinary display effects can no longer meet people's quality of life, and people's demand for high refresh rate display panels is increasing. However, high refresh rate display panels also have high power consumption, which has a negative effect on the usage time of electronic products and is not conducive to reducing the power consumption of display terminals. Summary of the invention

[0004] In view of the above problems, the present application provides a display driving method, a display driving circuit, and a display panel, aiming to provide a partition refresh solution to solve the problem that the current full-screen refresh display has a single display and is not conducive to reducing power consumption.

[0005] A first aspect of an embodiment of the present application provides a display driving method, the display driving method comprising:

[0006] Get the low refresh display area;

[0007] According to the low refresh display area, a first clock signal corresponding to the low refresh display area is down-converted to obtain a second clock signal;

[0008] Controlling the pixel driving unit corresponding to the low refresh display area to generate a corresponding pixel driving signal according to the gate scanning signal and the second clock signal;

[0009] Wherein, the frequency of the second clock signal is greater than or equal to the frequency of the pixel driving signal.

[0010] In some embodiments, a rising edge or a falling edge of the second clock signal is consistent with a rising edge of the pixel driving signal.

[0011] In some embodiments, a rising edge or a falling edge of the second clock signal is consistent with a falling edge of the pixel driving signal.

[0012] In some embodiments, the step of down-converting a first clock signal corresponding to the low refresh display area to obtain a second clock signal according to the low refresh display area includes:

[0013] When the pixel driving signal is at a low level, the level of the first clock signal is pulled low.

[0014] In some embodiments, the display driving method further includes:

[0015] A corresponding partition enable signal is generated according to the low refresh display area to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal.

[0016] A second aspect of the embodiments of the present application further provides a display driving circuit, the display driving circuit comprising a plurality of pixel driving units and a main control circuit, the main control circuit being used to execute the display driving method as described in any one of the above embodiments;

[0017] The plurality of pixel driving units are used to respectively drive a plurality of display pixels to light up.

[0018] In some embodiments, the display driving circuit further includes a plurality of scanning driving modules, and the plurality of gate scanning lines are respectively connected to the plurality of scanning driving modules;

[0019] The scanning driving module is controlled by the main control circuit to provide gate scanning signals for the plurality of gate scanning lines, and the plurality of pixel driving units are respectively connected to corresponding gate scanning lines;

[0020] Each of the pixel driving units is used to drive the corresponding display pixel to light up according to the received gate scanning signal and data signal.

[0021] In some embodiments, the pixel driving unit includes: a first driving tube, a second switching tube, a third switching tube, a fourth switching tube, a fifth switching tube, a sixth switching tube and a storage capacitor;

[0022] The first end of the second switch tube is used to receive a display data signal, and the control end of the second switch tube is used to receive a first data control signal;

[0023] The control end of the fourth switch tube is used to receive the first scan control signal, and the control end of the third switch tube is used to receive the second scan control signal;

[0024] The control end of the fifth switch tube and the control end of the sixth switch tube are connected together to receive a light-emitting control signal;

[0025] The control end of the seventh switch tube is commonly connected with the control end of the eighth switch tube for receiving a second data control signal;

[0026] The first end of the fifth switch tube and the first end of the storage capacitor are connected to the first power supply end in common, the second end of the second switch tube, the second end of the fifth switch tube, and the first end of the first drive tube are connected in common, the second end of the storage capacitor, the control end of the first drive tube, and the first end of the third switch tube are connected in common, the second end of the third switch tube, the first end of the fourth switch tube, the second end of the first drive tube, the first end of the sixth switch tube, and the first end of the eighth switch tube are connected in common, the second end of the fourth switch tube is connected to the first reference signal end, the second end of the sixth switch tube and the first end of the seventh switch tube are connected in common to the positive electrode of the display pixel, the negative electrode of the display pixel is connected to the reference ground, the second end of the seventh switch tube is connected to the second reference signal end, and the second end of the eighth switch tube is connected to the third reference signal end.

[0027] In some embodiments, the second switch tube, the seventh switch tube, the eighth switch tube, the fifth switch tube and the sixth switch tube are P-type MOS tubes; the third switch tube and the fourth switch tube are N-type MOS tubes.

[0028] A third aspect of the embodiments of the present application further provides a display panel, which includes the display driving circuit as described in any one of the above embodiments.

[0029] The beneficial effects of the embodiments of the present application are as follows: by obtaining a low refresh display area, and down-converting the first clock signal corresponding to the low refresh display area to obtain a second clock signal according to the low refresh display area; controlling the pixel driving unit corresponding to the low refresh display area to generate a corresponding pixel driving signal according to the gate scan signal and the second clock signal, and setting the frequency of the second clock signal to be greater than or equal to the frequency of the pixel driving signal, thereby reducing the power consumption of the low refresh display area when the display screen is displayed in partitioned refresh rate, improving the power consumption benefit in the partition refresh application scenario, and achieving the purpose of reducing display power consumption.

[0030] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0032] Figure 1A first schematic diagram of a display driving method provided in an embodiment of the present application;

[0033] Figure 2a A schematic diagram of a first waveform of a second clock signal SCK2 and a pixel driving signal SCAN provided in an embodiment of the present application;

[0034] Figure 2b A second waveform diagram of the second clock signal SCK2 and the pixel driving signal SCAN provided in an embodiment of the present application;

[0035] Figure 3a A third waveform diagram of the second clock signal SCK2 and the pixel driving signal SCAN provided in an embodiment of the present application;

[0036] Figure 3b A fourth waveform diagram of the second clock signal SCK2 and the pixel driving signal SCAN provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of the effect of a clock signal before frequency reduction provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of the effect of clock signal frequency reduction provided in an embodiment of the present application;

[0039] Figure 6 A second schematic diagram of the display driving method provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of a display driving circuit provided in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of a pixel driving unit provided in an embodiment of the present application;

[0042] Fig. 9 A schematic diagram of a partition enable signal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0045] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0046] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present application. The phrase "second connection port" at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0047] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0048] In the description of the embodiments of the present application, the term "multi-frame" refers to more than two (including two).

[0049] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0050] In the related art, when the display screen of the display panel is refreshed in partitions, if the refresh rates of various display areas are different, frequency reduction processing in the low-refresh display area is usually not supported. For example, in an application scenario where the refresh rate of the upper, middle and lower displays is 1HZ-120HZ-1HZ, frequency reduction measures are not supported in the upper and lower 1HZ refresh areas. The 1HZ display area needs to maintain the same behavior as the GOA signal in the 120HZ area. Therefore, there is a problem of small power consumption benefit in the common partition refresh scenario of 1HZ-120HZ-1HZ.

[0051] In order to solve the above technical problems, the present application embodiment provides a display driving method, see Figure 1 As shown, the display driving method in this embodiment includes steps S100 to S300.

[0052] In step S100, a low refresh display area is obtained.

[0053] In this embodiment, the low refresh display area refers to an area in the display panel that uses a lower refresh rate for display. When the display panel displays a picture, the picture can be displayed at a low refresh rate in some areas according to user needs or picture display needs. For example, in an area where only text needs to be displayed, the display refresh rate of the area can be reduced to achieve the purpose of reducing display power consumption.

[0054] In some embodiments, the image refresh rate of the low-refresh display area may be less than 30 Hz.

[0055] In some embodiments, the image refresh rate of the low refresh display area may be 1 Hz.

[0056] In step S200, a first clock signal corresponding to the low refresh display area is frequency-reduced according to the low refresh display area to obtain a second clock signal.

[0057] In the present embodiment, since the partition refresh function of the display panel is turned on, the refresh frequencies of the display images in various areas may be inconsistent. For example, the refresh frequencies of the display images in the upper, middle and lower areas of the display panel are 1Hz, 120Hz and 1Hz respectively, and all the pixel driving units will still receive the clock signal with the highest frequency. For example, the frequency of the clock signal is 120Hz. Then, using a higher clock signal frequency in the low refresh display area will result in energy waste. Therefore, by selecting to down-convert the first clock signal received by the corresponding pixel driving unit in the low refresh display area to obtain a low-frequency second clock signal, the frequency of the pixel driving signal is related to the refresh rate of the display image of the display area. For example, the refresh rate of the display image of the display area is equal to the frequency of the pixel driving signal. Since the frequency of the second clock signal is greater than or equal to the frequency of the pixel driving signal, it will not affect the image display in the low refresh display area, and will not affect the normal signal output of the pixel driving unit, which can greatly improve the power consumption benefit of the display panel under partition refresh.

[0058] In step S300, the pixel driving unit corresponding to the low refresh display area is controlled to generate a corresponding pixel driving signal according to the gate scanning signal and the second clock signal.

[0059] In this embodiment, the display panel includes a plurality of display pixels, and the plurality of display pixels may be arranged in an array, and each display pixel is driven by a corresponding pixel driving unit, and the pixel driving unit may generate a corresponding pixel driving signal according to the received gate scanning signal and the second clock signal, so as to drive the display pixels in the low refresh display area to light up. In the high refresh display area, the pixel driving unit may generate a corresponding pixel driving signal according to the received gate scanning signal and the first clock signal, so as to drive the display pixels in the high refresh display area to light up, and the plurality of display pixels in the high refresh display area and the low refresh display area may display corresponding pictures when driven to light up.

[0060] In some embodiments, the main control circuit can control the corresponding pixel driving unit according to the low refresh display area to generate a pixel driving signal with a lower duty cycle, thereby reducing the display screen refresh rate of the low refresh display area.

[0061] In some embodiments, the frequency reduction processing in step S200 can be to reduce the duty cycle of the first clock signal to obtain a second clock signal with a lower duty cycle. For example, when the display screen refresh frequency is 1Hz, the frequency of the first clock signal is 120Hz. Then, by performing frequency reduction processing on the first clock signal, a second clock signal of 30Hz or 1Hz can be obtained. Since the frequency of the second clock signal of 30Hz is greater than the current display screen refresh frequency, and the frequency of the second clock signal of 1Hz is equal to the current display screen refresh frequency, it will not affect the screen display in the low refresh display area, and will not affect the normal signal output of the pixel driving unit, which can greatly improve the power consumption benefit of the display panel under partition refresh.

[0062] In some embodiments, a rising edge or a falling edge of the second clock signal is consistent with a rising edge of the pixel driving signal.

[0063] In this embodiment, the gray scale of the display pixel is related to its lighting time, and the lighting time of the display pixel is related to the duty cycle of the pixel driving signal, that is, it is related to the time when the pixel driving signal is at a high level in each display cycle. The rising edge of the second clock signal is the interval in which the second clock signal is converted from a low level to a high level, and the falling edge of the second clock signal is the interval in which the second clock signal is converted from a high level to a low level. Since there is a sudden change in level between the rising edge and the falling edge of the second clock signal, by setting the rising edge or the falling edge of the second clock signal to be consistent with the rising edge of the pixel driving signal, the display integrity of the pixel driving signal SCAN in each display cycle can be guaranteed, and the problem of picture display distortion caused by the refresh rate switching or the frequency switching of the clock signal can be avoided.

[0064] See also Figure 2aAs shown, by setting the rising edge of the second clock signal SCK2 to be consistent with the rising edge of the pixel driving signal SCAN, the display integrity of the pixel driving signal SCAN in each display cycle can be guaranteed, avoiding the problem of picture display distortion caused by refresh rate switching or clock signal frequency switching.

[0065] In some embodiments, see Figure 2b As shown, by setting the falling edge of the second clock signal SCK2 to be consistent with the rising edge of the pixel driving signal SCAN, the display integrity of the pixel driving signal SCAN in each display cycle can be guaranteed, avoiding the problem of picture display distortion caused by refresh rate switching or clock signal frequency switching.

[0066] In some embodiments, a rising edge or a falling edge of the second clock signal SCK2 is consistent with a falling edge of the pixel driving signal.

[0067] In this embodiment, the gray scale of the display pixel is related to its lighting time, and the lighting time of the display pixel is related to the duty cycle of the pixel driving signal, that is, the time when the pixel driving signal is at a high level in each display cycle. Figure 3a As shown, by setting the rising edge of the second clock signal SCK2 to be consistent with the falling edge of the pixel driving signal SCAN, the display integrity of the pixel driving signal SCAN in each display cycle can be guaranteed, avoiding the problem of picture display distortion caused by refresh rate switching or clock signal frequency switching.

[0068] In some embodiments, see Figure 3b As shown, by setting the falling edge of the second clock signal SCK2 to be consistent with the falling edge of the pixel driving signal SCAN, the display integrity of the pixel driving signal SCAN in each display cycle can be guaranteed, avoiding the problem of picture display distortion caused by refresh rate switching or clock signal frequency switching.

[0069] In some embodiments, in step S200, a first clock signal corresponding to the low refresh display area is down-converted to obtain a second clock signal according to the low refresh display area, including: lowering the level of the first clock signal when the pixel drive signal is at a low level.

[0070] In this embodiment, when the duty cycle of the pixel driving signal output by the pixel driving unit corresponding to the low refresh display area decreases, it indicates that the low refresh display area of ​​the display panel has adopted a low refresh rate to display the picture. In this way, the first clock signal can be down-converted by matching the first clock signal with the pixel driving signal. That is, when the pixel driving signal is at a low level, the level of the first clock signal is lowered, and when the pixel driving signal is at a high level, the level of the first clock signal is raised. In this way, the waveform of the first clock signal can be ensured to be consistent with the waveform of the pixel driving signal, which can not only reduce the power consumption of the first clock signal, but also will not affect the picture display of the display panel.

[0071] In some embodiments, when the partition refresh function of the display panel is turned on, the following description is based on a screen resolution of 1316*2832.

[0072] In a specific application, the high refresh display area can be determined by the starting coordinates and the ending coordinates. In the related art, for example Figure 4 As shown, the timing behavior of the GOA signal in the 1HZ area of ​​the display panel is consistent with the GOA timing behavior in the middle 120HZ area of ​​the display panel, resulting in no obvious power consumption benefit in common scenarios when the display screen refresh rates of the upper, middle and lower areas of the display panel are 120Hz, 1Hz and 1Hz respectively.

[0073] like Figure 4 To enable partition refresh, the refresh frequencies of the upper, middle and lower areas of the display panel are 120HZ-1HZ-1HZ respectively. When the partition enable signal VFE in channel 1 is high, it is a high refresh display area. When the partition enable signal VFE is low, it is a low refresh display area. Channel 2 is SINP1 signal, and channel 3 is clock signal SCKIP1. Figure 4 Only the clock signal SCK1P1 is captured, and the behaviors of the clock signals SCK2P1, SCK3P1, and SCK4P1 are consistent with the clock signal SCK1P1, all of which are the clocks of SINP1, and the 4 channels are the source signals source. Combined with Figure 2, it can be seen that in the first frame display, the source signal source, the clock signal SCK1P1, and the partition enable signal VFE are all working normally, and this frame display is refreshed in full screen; in the next frame display time, the partition enable signal VFE and the source signal source are high level in 1-960 lines, the partition enable signal VFE and the source signal source are high refresh 120HZ in 1-960 lines, and the partition enable signal VFE and the source signal source are low refresh 1HZ in 961-2832 lines, but in the 1HZ area, the clock signal SCK1P1 is still working normally in the low refresh display area.

[0074] like Figure 5As shown, in the first frame display, the source signal source, the clock signal SCK1P1, and the partition enable signal VFE are all working normally, and this frame display is refreshed in full screen; in the next frame display time, the partition enable signal VFE and the source signal source are high level in rows 1-960, the partition enable signal VFE and the source signal source are high refresh 120HZ in rows 1-960, and the partition enable signal VFE and the source signal source are low refresh 1HZ in rows 961-2832, but in the 1HZ area, the clock signal SCK1P1 of rows 961-2832 will not affect the level of the source signal source in the low refresh display area by lowering the level of the clock signal SCK1P1.

[0075] Table 1:

[0076]

[0077] Scheme 1 in Table 1 is the power consumption obtained by executing the display driving method in the embodiment of the present application, and Scheme 2 in Table 1 is the power consumption obtained by executing the traditional display driving method. VDD1, VDDD / DVDD, VCI, AVDD, and VGL represent the power consumption of the corresponding nodes, DDIC-SUM represents the total power consumption, digital-SUM represents the total power consumption of digital signals, and analog-SUM represents the total power consumption of analog signals. As shown in Table 1, by Figure 5 In the low refresh display area, by lowering the level of the clock signal SCK1P1, the power consumption of the GOA part is significantly improved, and the power consumption benefit is about 14mW. Similarly, the waveform diagrams of SCK2P1, SCK3P1, and SCK4P1 are similar to the waveform diagram of SCK1P1. Figure 1 If the four clock signals SCK1P1, SCK2P1, SCK3P1, and SCK4P1 of SCANP1 can be pulled to the PVGL_N level for frequency reduction below the partition end coordinates under partition refresh (the same applies to 60HZ / 30HZ / 10HZ), this measure can effectively reduce the GOA power consumption under partition refresh.

[0078] In some embodiments, see Figure 6 As shown, the display driving method in this embodiment also includes step S400. In step S400, a corresponding partition enable signal is generated according to the low refresh display area to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal.

[0079] In this embodiment, the scanning area where the display refresh rate needs to be reduced is determined by the low refresh display area, thereby generating a corresponding partition enable signal, and the partition enable signal is used to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal, thereby reducing the switching duty cycle of the pixels in the corresponding area, thereby partitioning the display panel and reducing the display refresh rate in the low refresh display area.

[0080] In some embodiments, in combination Figure 7 As shown, the partition enable signal can also be logically processed with the scan drive signal output by the scan drive module 520, so as to adjust the duty cycle of the scan drive signal output to the gate scan line 501, thereby achieving the purpose of controlling the corresponding pixel drive unit to reduce the duty cycle of the pixel drive signal, thereby realizing the partition refresh display of the display panel.

[0081] In some embodiments, the main control circuit 510 can provide a corresponding partition scanning signal to the scanning driving module 520 according to the content to be displayed on the display panel, so as to adjust the refresh rate of the corresponding display screen. For example, according to the coordinates of the display screen and the refresh rate requirements, by providing a corresponding partition scanning signal to the display driving method, the refresh rate of the display screen is set according to a frequency distribution such as 60hz-120hz-60hz, 30hz-120hz-30hz, 1hz-120hz-1hz, etc. Specifically, in realizing the function of displaying different refresh rates in multiple regions of a mobile phone, if the mobile phone is watching a video (requiring a high refresh rate display) and reading text (low refresh rate display) at the same time, the refresh rate of the text display area in the display screen is set to a low refresh rate (such as 1Hz, 30Hz, etc.), thereby reducing the power consumption of the display panel without affecting the display effect.

[0082] The present application also provides a display driving circuit. Figure 7 As shown, the display driving circuit in the embodiment of the present application includes multiple pixel driving units 530 and a main control circuit 510. The main control circuit 510 is used to execute the display driving method in any of the above embodiments; the multiple pixel driving units 530 are used to drive multiple display pixels to light up respectively.

[0083] In this embodiment, the display panel includes a plurality of display pixels, and the plurality of display pixels may be arranged in an array, each display pixel is driven by a corresponding pixel driving unit 530, and the pixel driving unit 530 may generate a pixel driving signal according to a received gate scanning signal, thereby driving the corresponding display pixel to light up, and the plurality of display pixels may display corresponding images when driven to light up. The main control circuit 510 may control the corresponding pixel driving unit 530 to generate a pixel driving signal with a low duty cycle according to the low refresh display area, thereby reducing the refresh rate of the display image in the low refresh display area.

[0084] In some embodiments, in combination Figure 7 As shown, the display driving circuit also includes multiple scanning driving modules 520, and multiple gate scanning lines 501 are respectively connected to the multiple scanning driving modules 520; the scanning driving modules 520 are controlled by the main control circuit 510 to provide gate scanning signals for the multiple gate scanning lines 501, and multiple pixel driving units 530 are respectively connected to the corresponding gate scanning lines 501; each pixel driving unit 530 is used to drive the corresponding display pixel to light up according to the received gate scanning signal and data signal.

[0085] In this embodiment, combined with Figure 7 As shown, the display panel may include N+1 rows of display pixels, each row of display pixels corresponds to a gate scanning line 501, each gate scanning line 501 is connected to a corresponding scanning driving module 520, and the main control circuit 510 may provide a partition scanning signal to the corresponding scanning driving module 520, thereby adjusting the display refresh rate of the display area of ​​the display panel. Figure 7 As shown, the main control circuit 510 provides a partition enable signal SWN for the Nth scan drive module 520, and the main control circuit 510 provides a partition enable signal SWN+1 for the N+1th scan drive module 520. The N+1 scan drive modules 520 provide gate scan signals for multiple gate scan lines 501 according to the corresponding partition enable signals.

[0086] In some embodiments, see Figure 8 As shown, the pixel driving unit 530 includes: a first driving tube T1, a second switching tube T2, a third switching tube T3, a fourth switching tube T4, a fifth switching tube T5, a sixth switching tube T6 and a storage capacitor Cst.

[0087] In this embodiment, the first end of the second switch tube T2 is used to receive the display data signal, and the control end of the second switch tube T2 is used to receive the first data control signal Data; the control end of the fourth switch tube T4 is used to receive the first scan control signal SN1, and the control end of the third switch tube T3 is used to receive the second scan control signal SN2. In some embodiments, the second scan control signal SN2 can be provided by a level conversion circuit composed of the seventeenth switch tube T17 and the eighteenth switch tube T18, and the partition enable signal VFE can be output as the second scan control signal SN2 to the control end of the third switch tube T3 via the output end GOUT of the level conversion circuit, so as to realize the partition refresh control of the pixel driving unit 530.

[0088] The control end of the fifth switch tube T5 and the controller of the sixth switch tube T6 are connected together to receive the light control signal EM; the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8 are connected together to receive the second data control signal SP2. The first end of the fifth switch tube T5 and the first end of the storage capacitor Cst are commonly connected to the first power supply terminal ELVDD, the second end of the second switch tube T2, the second end of the fifth switch tube T5, and the first end of the first driving tube T1 are commonly connected, the second end of the storage capacitor Cst, the control end of the first driving tube T1, and the first end of the third switch tube T3 are commonly connected, the second end of the third switch tube T3, the first end of the fourth switch tube T4, the second end of the first driving tube T1, the first end of the sixth switch tube T6, and the first end of the eighth switch tube T8 are commonly connected, the second end of the fourth switch tube T4 is connected to the first reference signal terminal Vrefn1, the second end of the sixth switch tube T6 and the first end of the seventh switch tube T7 are commonly connected to the positive electrode of the display pixel, the negative electrode of the display pixel is connected to the reference ground, the second end of the seventh switch tube T7 is connected to the second reference signal terminal Vrefn2, and the second end of the eighth switch tube T8 is connected to the third reference signal terminal Vrefp.

[0089] In some embodiments, the second switch tube T2 , the seventh switch tube T7 , the eighth switch tube T8 , the fifth switch tube T5 and the sixth switch tube T6 are P-type MOS tubes; the third switch tube T3 and the fourth switch tube T4 are N-type MOS tubes.

[0090] In some embodiments, the main control circuit 510 is also used to execute step S400 in the above embodiment. The main control circuit 510 generates a corresponding partition enable signal according to the low refresh display area, and the partition enable signal controls the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal, thereby achieving the purpose of reducing the switching duty cycle of the pixels in the corresponding area.

[0091] In some embodiments, the display driving circuit is used to drive a display panel, which may include multiple partitioned refresh areas. The main control circuit 510 in the display driving circuit may provide multiple partitioned enable signals to pixel driving units in multiple partitioned refresh areas, thereby adjusting the refresh rate in each partitioned refresh area to achieve the partitioned refresh function of the display panel.

[0092] See also Fig. 9 As shown, the display driving circuit may include four partition refresh areas. The partition refresh function of the display panel in this embodiment may be controlled by four partition enable signals VFE (VFE_1, VFE_2, VFE_3, VFE_4), wherein each partition enable signal VFE may drive 16 rows of display pixels, and the four partition enable signals VFE complete a cycle of 64 rows. Fig. 9As shown, the refresh rate of the display pixels of rows 1-16 (1-16H) is controlled by the first partition enable signal VFE_1, the refresh rate of the display pixels of rows 17-32 is controlled by the second partition enable signal VFE_2, the refresh rate of the display pixels of rows 33-48 (33-48H) is controlled by the third partition enable signal VFE_3, the refresh rate of the display pixels of rows 49-64 is controlled by the fourth partition enable signal VFE_4, the refresh rate of the display pixels of rows 65-84 is controlled by the first partition enable signal VFE_1, and so on.

[0093] In some embodiments, the output terminal GOUT of the level conversion circuit is connected to the third switch tube T3, the high level of the partition enable signal VFE is PVGH_N, and the low level of the partition enable signal VFE is PVGL_N. Figure 8 , the output of the partition enable signal VFE can directly act on the gate of the third switch tube T3. If the voltage of the partition enable signal VFE is PVGL_N, the voltage acting on the third switch tube T3 is always negative. The third switch tube T3 can be NMOS, so the third switch tube T3 is always closed, and the voltage of the storage capacitor Cst remains unchanged (equivalent to the 1Hz area in 1Hz-120Hz-1Hz). If the voltage of the partition enable signal VFE is PVGH_N, it is basically the same as the ordinary display drive circuit and works normally (equivalent to the non-local brush mode or the 120HZ area in 1-120-1).

[0094] An embodiment of the present application further provides a display panel, which includes a display driving circuit as described in any one of the above embodiments.

[0095] In this embodiment, the display panel includes a display panel and a display driving circuit. The display panel includes a plurality of display pixels, each display pixel includes at least one display pixel, and the display pixel can emit a corresponding color when it is lit. For example, the display pixel can emit one of red light, blue light or green light, and display pixels of three colors can constitute a display pixel. By obtaining a low refresh display area, the pixel driving unit corresponding to the low refresh display area is controlled according to the low refresh display area to generate a corresponding pixel driving signal, and then the first clock signal received by the pixel driving unit corresponding to the low refresh display area is frequency-reduced to obtain a second clock signal, so that the frequency of the second clock signal is greater than or equal to the frequency of the pixel driving signal, thereby reducing the power consumption of the low refresh display area when the display screen is displayed in a refresh rate partition, improving the power consumption benefit in the partition refresh application scenario, and achieving the purpose of reducing display power consumption.

[0096] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0097] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0098] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the electronic device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0099] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0100] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0101] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A display driving method, characterized in that: The display driving method comprises: Get the low refresh display area; According to the low refresh display area, a first clock signal corresponding to the low refresh display area is down-converted to obtain a second clock signal; Controlling the pixel driving unit corresponding to the low refresh display area to generate a corresponding pixel driving signal according to the gate scanning signal and the second clock signal; Wherein, the frequency of the second clock signal is greater than or equal to the frequency of the pixel driving signal.

2. The display driving method according to claim 1, characterized in that: A rising edge or a falling edge of the second clock signal is consistent with a rising edge of the pixel driving signal.

3. The display driving method according to claim 1, characterized in that: A rising edge or a falling edge of the second clock signal is consistent with a falling edge of the pixel driving signal.

4. The display driving method according to claim 1, characterized in that: The step of down-converting a first clock signal corresponding to the low refresh display area to obtain a second clock signal includes: When the pixel driving signal is at a low level, the level of the first clock signal is pulled low.

5. The display driving method according to claim 1, characterized in that: The display driving method further includes: A corresponding partition enable signal is generated according to the low refresh display area to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal.

6. A display driving circuit, characterized in that: The display driving circuit comprises a plurality of pixel driving units and a main control circuit, and the main control circuit is used to execute the display driving method according to any one of claims 1 to 5; The plurality of pixel driving units are used to respectively drive a plurality of display pixels to light up.

7. The display driving circuit according to claim 6, characterized in that: The display driving circuit further comprises a plurality of scanning driving modules, and the plurality of gate scanning lines are respectively connected to the plurality of scanning driving modules; The scanning driving module is controlled by the main control circuit to provide gate scanning signals for the plurality of gate scanning lines, and the plurality of pixel driving units are respectively connected to corresponding gate scanning lines; Each of the pixel driving units is used to drive the corresponding display pixel to light up according to the received gate scanning signal and data signal.

8. The display driving circuit according to claim 6 or 7, characterized in that: The pixel driving unit comprises: a first driving tube, a second switching tube, a third switching tube, a fourth switching tube, a fifth switching tube, a sixth switching tube and a storage capacitor; The first end of the second switch tube is used to receive a display data signal, and the control end of the second switch tube is used to receive a first data control signal; The control end of the fourth switch tube is used to receive the first scan control signal, and the control end of the third switch tube is used to receive the second scan control signal; The control end of the fifth switch tube and the control end of the sixth switch tube are connected together to receive a light-emitting control signal; The control end of the seventh switch tube is commonly connected with the control end of the eighth switch tube for receiving a second data control signal; The first end of the fifth switch tube and the first end of the storage capacitor are connected to the first power supply end in common, the second end of the second switch tube, the second end of the fifth switch tube, and the first end of the first drive tube are connected in common, the second end of the storage capacitor, the control end of the first drive tube, and the first end of the third switch tube are connected in common, the second end of the third switch tube, the first end of the fourth switch tube, the second end of the first drive tube, the first end of the sixth switch tube, and the first end of the eighth switch tube are connected in common, the second end of the fourth switch tube is connected to the first reference signal end, the second end of the sixth switch tube and the first end of the seventh switch tube are connected in common to the positive electrode of the display pixel, the negative electrode of the display pixel is connected to the reference ground, the second end of the seventh switch tube is connected to the second reference signal end, and the second end of the eighth switch tube is connected to the third reference signal end.

9. The display driving circuit according to claim 8, characterized in that: The second switch tube, the seventh switch tube, the eighth switch tube, the fifth switch tube and the sixth switch tube are P-type MOS tubes; the third switch tube and the fourth switch tube are N-type MOS tubes.

10. A display panel, characterized in that: The display panel comprises the display driving circuit as claimed in any one of claims 6 to 9.

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