SAR-SS type ADC circuit and module based on adjacent pixel prediction

Abstract

The invention relates to the technical field of image sensor design, and particularly discloses an SAR-SS type ADC circuit and module based on adjacent pixel prediction. The SAR-SS type ADC circuit comprises a signal input part, a gain amplifier, a sampling and holding and voltage lifting part, a prediction control part, an SAR-ADC part, an SS-ADC part and a data processing part. According to the invention, the number of ADCs is reduced by adopting a mode of sharing the ADCs in multiple columns; meanwhile, 11-bit quantization is decomposed into 5-bit division quantization through an SAR-ADC part and 6-bit fine quantization through an SS-ADC part, and a prediction control part is additionally arranged to judge whether 5-bit coarse quantization needs to be carried out or not, so that unnecessary time consumption and power consumption of the 5-bit coarse quantization are reduced. According to the invention, the problem that the total number of ADCs is too large due to the fact that one column is matched with one traditional column-level ADC is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensor design, and more specifically to: 1. a SAR-SS type ADC circuit based on adjacent pixel prediction; 2. a SAR-SS type ADC module based on adjacent pixel prediction. Background Art

[0002] Image sensor (Complementary Metal Oxide Semiconductor Image Sensor, CMOS) is an image sensor widely used in digital cameras, mobile phone cameras, surveillance cameras and other fields. Its function is to convert optical signals into digital signals. The analog-to-digital converter (ADC) is one of the most important parts of CMOS. It is responsible for converting the electrical signals generated by the photosensitive element into digital signals. The performance of ADC directly affects the imaging quality of CMOS.

[0003] At present, there are three main types of ADCs used in CMOS: pixel type, column level, and chip level. The column level has more obvious advantages than the other two types due to its advantages of low power consumption, low design difficulty, and high conversion efficiency. The commonly used column-level ADCs include primary and secondary approximation type, cyclic type, and monoslope type. Each structure has different performance characteristics, and has its own advantages and disadvantages in terms of accuracy, speed, and power consumption. ADCs with different structures can be selected according to different needs. Among them, SS ADC has the advantages of simple structure, low power consumption, and small area, and has become the mainstream ADC choice for CMOS.

[0004] However, traditional column-level ADCs generally use one ADC per column. Although this can ensure processing efficiency, the total number of ADCs is too large, which leads to a large occupied area. In addition, there is an obvious exponential relationship between the conversion speed, power consumption and bit number of traditional SS ADCs. Improving the conversion accuracy of 1 bit requires a nearly exponential increase in speed and power consumption, and these indicators are particularly important for CMOS. Therefore, increasing speed and reducing power consumption has become an important research point for improving SS ADCs. Summary of the invention

[0005] Based on this, it is necessary to provide a SAR-SS ADC circuit and module based on adjacent pixel prediction to address the problem that the total number of ADCs is too large due to the traditional column-level ADC using one ADC per column.

[0006] The present invention is implemented by the following technical solutions:

[0007] In a first aspect, the present invention provides a SAR-SS type ADC circuit based on adjacent pixel prediction, comprising: a signal input unit, a gain amplifier, a sampling and holding and voltage raising unit, a prediction control unit, a SAR-ADC unit, a SS-ADC unit, and a data processing unit.

[0008] 1. The signal input unit is used to control the N-column pixel signal [V sig,1 ,V ref,1 ]~[V sig,N ,V ref,N ]Enter sequentially for 11-bit quantization.

[0009] Among them, in [V sig,a ,V ref,a ]After completing 11-bit quantization, enter [V sig,a+1 ,V ref,a+1 ]; a∈[1,N-1].

[0010] 2. Gain amplifier is used for: When [V sig,n ,V ref,n ]After inputting, V ref,n With V sig,n Subtract and amplify to generate pixel voltage V pixel,n ; n∈[1,N].

[0011] 3. The sampling and holding and voltage raising parts are used for:

[0012] ①According to V pixel,n Output hold voltage signal V at 5bit coarse quantization s1,n ;

[0013] ②According to V pixel,n Combined with a fixed voltage V at 6-bit fine quantization end , reference voltage V x To output the boost voltage signal V s2,n .

[0014] 4. The predictive control unit is used to: When [V sig,b ,V ref,b ]After input, predict whether 5-bit coarse quantization is needed; b∈[2,N].

[0015] 5. SAR-ADC is used for:

[0016] ①When [V sig,1 ,V ref,1 ]After input, based on V s1,1 Perform 5-bit coarse quantization to obtain code value D1<6:0>;

[0017] ②When [V sig,b ,V ref,b]After input, the corresponding operation is performed according to the prediction result of the prediction control unit:

[0018] If the prediction control unit predicts that 5-bit coarse quantization is not necessary, D b-1 <6:0> as D b <6:0>;

[0019] If the prediction control unit predicts that 5-bit coarse quantization is required, then based on V s1,b Perform 5-bit coarse quantization to obtain the code value D b <6:0>.

[0020] 6. SS-ADC is used for:

[0021] ①When [V sig,1 ,V ref,1 ] After the SAR-ADC part completes the 5-bit coarse quantization, based on V s2,1 Perform 6-bit fine quantization to obtain the code value D1<10:6>;

[0022] ②When [V sig,b ,V ref,b ]After input, the corresponding operation is performed according to the prediction result of the prediction control unit:

[0023] If the prediction control unit predicts that 5-bit coarse quantization is not necessary, the V s2,b Perform 6-bit fine quantization to obtain the code value D b <10:6>;

[0024] If the prediction control unit predicts that 5-bit coarse quantization is required, the SAR-ADC unit will complete the 5-bit coarse quantization and then s2,b Perform 6-bit fine quantization to obtain the code value D b <10:6>.

[0025] 7. The data processing unit is used to: n <6:0>, D n <10:6> Perform 11-bit numerical correction to obtain 11-bit quantization result D n <10:0>.

[0026] Among them, D n <10:0>=D n <10:6> -D n <6:0>+D n <4:0>;

[0027] D n <4:0> indicates the correction value, D n <4:0>=V end -Vpixel,n .

[0028] The implementation of the SAR-SS type ADC circuit based on adjacent pixel prediction is a method or process according to an embodiment of the present disclosure.

[0029] In a second aspect, the present invention discloses a SAR-SS type ADC module based on adjacent pixel prediction, which adopts the layout of a SAR-SS type ADC circuit based on adjacent pixel prediction disclosed in the first aspect.

[0030] The implementation of the SAR-SS type ADC module based on adjacent pixel prediction is a method or process according to an embodiment of the present disclosure.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] According to the principle that adjacent pixels have similarities and the values ​​of adjacent pixels converted into voltage signals may be close, the present invention adopts a method of sharing ADCs with multiple columns to reduce the number of ADCs; at the same time, 11-bit quantization is decomposed into 5-bit division quantization by a SAR-ADC part and 6-bit fine quantization by a SS-ADC part, and a prediction control part is added to judge whether 5-bit coarse quantization is needed, so as to reduce unnecessary time and power consumption of 5-bit coarse quantization. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0034] Figure 1 This is a schematic diagram of processing of a multi-column shared ADC proposed by the present invention;

[0035] Figure 2 A schematic diagram of the structure of a SAR-SS type ADC circuit based on adjacent pixel prediction provided by the present invention;

[0036] Figure 3 for Figure 2 Circuit connection diagram of signal input part and gain amplifier part;

[0037] Figure 4 for Figure 2 Circuit connection diagram of the sampling and holding and voltage raising part;

[0038] Figure 5 for Figure 4 Circuit connection diagram of 7-bit ramp generator;

[0039] Figure 6 for Figure 2 Circuit connection diagram of SAR-ADC part and prediction control part;

[0040] Figure 7 for Figure 6 Circuit connection diagram of the prediction control unit;

[0041] Figure 8 for Figure 2 Circuit connection diagram of SS-ADC part;

[0042] Fig. 9 for Figure 2 Schematic diagram of SAR-SS type ADC circuit for prediction;

[0043] Fig.10 for Figure 2 Circuit diagram of the data processing unit. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0047] The design basis of the present invention is that because adjacent pixels have similarities, the values ​​of voltage signals converted from adjacent columns of pixels are also similar; therefore, a method of sharing ADCs among multiple columns can be adopted.

[0048] See also Figure 1That is, it shows that every 8 columns of pixels are a group, sharing a SAR-SS type ADC (SAR-SS-ADC for short) proposed by the present invention based on adjacent pixel prediction. It should be noted that although the composition of 8 columns of pixels can be increased or decreased, 8 columns of pixels as a group can achieve a better balance between efficiency and area.

[0049] Example 1

[0050] See also Figure 2 , Figure 2 A structural schematic diagram of a SAR-SS type ADC circuit based on adjacent pixel prediction provided in this embodiment 1 is shown, which includes: a signal input unit, a gain amplification unit, a sampling and holding and voltage raising unit, a prediction control unit, a SAR-ADC unit, a SS-ADC unit, and a data processing unit.

[0051] The following are introduced separately (considering that the prediction control unit, SAR-ADC unit, and SS-ADC unit are closely related, they form the ADC processing unit and are introduced together):

[0052] 1. The signal input unit is used to control the N-column pixel signal [V sig,1 ,V ref,1 ]~[V sig,N ,V ref,N ] are input sequentially for 11-bit quantization. See above, the best value of N is 8.

[0053] It should be noted that [V sig,n ,V ref,n ] includes: pixel reset signal V sig,n , pixel readout signal V ref,n ; n∈[1,N].

[0054] Among them, in [V sig,a ,V ref,a ]After completing 11-bit quantization, enter [V sig,a+1 ,V ref,a+1 ]; a∈[1,N-1].

[0055] That is to say, one working cycle of SAR-SS-ADC is the processing time of N columns of pixel signals: N columns of pixel signals complete 11-bit quantization in sequence——[V sig,1 ,V ref,1 ] input, and complete 11-bit quantization, then start [V sig,2 ,V ref,2 ] input, and complete 11-bit quantization until [V sig,8 ,V ref,8 ] input and complete 11-bit quantization.

[0056] See also Figure 3 In order to ensure the above working order, the signal input part adopts the following design:

[0057] The signal input unit includes: N switches S P,1 ~S P,N .

[0058] Among them, S P,n The first end of the connection [V sig,n ,V ref,n ], and the second end is connected to the gain amplifier.

[0059] In this way, only S P,1 ~S P,N Control them so that they are not closed simultaneously but in sequence. Specifically, first close S P,1 , S P,2 ~S P,N Keep disconnected, [V sig,1 ,V ref,1 ] is input; in [V sig,1 ,V ref,1 ]After completing 11-bit quantization, close S P,2 , S P,1 , S P,3 ~S P,N Keep disconnected, [V sig,2 ,V ref,2 ] is input, and so on, until all columns have completed 11-bit quantization.

[0060] 2. Gain amplifier is used for: When [V sig,n ,V ref,n ]After inputting, V ref,n With V sig,n Subtract and amplify to generate pixel voltage V pixel,n .

[0061] See also Figure 3 , the input of the gain amplifier is connected to S P,n The second end is connected to the output terminal for outputting V pixel,n The gain amplifier can use a programmable gain amplifier, which has the function of reducing the effect of the pixel output bus on the subsequent ADC noise and ref,n With V sig,n Subtract and amplify to generate pixel voltage V pixel,n This enables the function of analog multi-sampling and reduces the noise caused by pixels.

[0062] 3. The sampling and holding and voltage raising parts are used for:

[0063] ①According to V pixel,n Output hold voltage signal V at 5bit coarse quantization s1,n;

[0064] ②According to V pixel,n Combined with a fixed voltage V at 6-bit fine quantization end , reference voltage V x To output the boost voltage signal V s2,n .

[0065] See also Figure 4 The sampling and holding and voltage raising part includes: 3 switches S0~S2, 2 switches S h0 ~S h1 , 1 capacitor C H , 1 7-bit ramp generator.

[0066] The first end of S0 is connected to the output end of the gain amplifier, and the second end is connected to C H The first end of S1, the first end of S2; the second end of S1 is used to output V s1,n ; The second end of S2 is used to output V s2,n ; C H The second end is connected to S h0 The first end, S h1 The first end of S h0 The second terminal is used to input V end ; S h1 The second end is connected to the output end of the 7-bit ramp generator; the output end of the 7-bit ramp generator is used to output the ramp signal V ramp .

[0067] Among them, V end It is a fixed voltage value of external input, which is used to pull down the V in 6-bit fine quantization. ramp . V end V x (i.e. V ramp The starting voltage) is higher than a predetermined value.

[0068] S0 Control C H S1 and S2 control the connection of SAR-ADC and SS-ADC.

[0069] For the 7-bit ramp generator, it is used to provide a ramp signal V ramp The 7-bit ramp generator can be used as follows: Figure 5 The design includes: a conversion circuit part, a current source part, a differential switch part, and an operational amplifier array part.

[0070] The conversion circuit includes: 1 resistor R, 1 resistor R dummy ; The second end of R is connected to R dummy The second end of

[0071] The current source section includes: 18 current sources I0~I 17 ; Among them, I0 is i0 current source (i0 represents standard current), I1 is 2i0 current source, I2 is 4i0 current source, I3~I 17 is 8i0 current source;

[0072] The differential switch section includes: 36 switches S W,0 ~S W,35 ; Among them, I e By S W,c Connect the first end of R through S W,d Connect R dummy The first end of; c∈[0,2,4,…,34], d∈[1,3,5,…,35];

[0073] The operational amplifier array includes: 2 operational amplifiers A0~A1, 1 capacitor C x , 1 NMOS tube N1; the positive input end of A0 is connected to the first end of R; the negative input end of A0 is connected to the output end of A0 and serves as the output end of the 7-bit ramp generator to output V ramp ; The positive input of A1 is connected to C x The first end of R, the second end of R, the drain of N1, and the negative input end are connected to V x , the output terminal is connected to C x The second end of N1 and the gate of N1; the source of N1 is grounded.

[0074] The design of the above 7-bit ramp generator adopts a combination of binary coding and thermometer coding, which can combine the advantages of low complexity and small area of ​​binary coding circuit with high linearity and small burrs of thermometer decoding: the lower 3 bits adopt binary coding, which can reduce the number of thermometer coding bits, thereby reducing the area of ​​the thermometer coding circuit, and at the same time add an inverter chain to transmit the input signal to ensure delay synchronization; the upper 4 bits adopt thermometer coding to reduce the noise generated by too many flipping bits during the carry process; and an operational amplifier A1 and an NMOS tube N1 are used to form a negative feedback circuit, and the negative feedback principle of the operational amplifier is used to clamp the initial voltage of the ramp to a fixed value V x , so that V ramp V x It gradually rises as the starting point and is connected to the output through operational amplifier A0.

[0075] 4. The ADC processing unit includes: prediction control unit, SAR-ADC unit, and SS-ADC unit.

[0076] 401, the prediction control unit is used to: when [V sig,b ,V ref,b ]After input, predict whether 5-bit coarse quantization is needed; b∈[2,N].

[0077] It should be noted that in the quantification [V sig,1 ,V ref,1 ], since there is no pre-coarse quantization data, [V sig,1 ,V ref,1 ] quantization cycle only includes 5-bit coarse quantization stage and 6-bit fine quantization stage; while in quantization [V sig,2 ,V ref,2 ]~[V sig,N ,V ref,N ], a quantization cycle includes a prediction stage (must be performed), a 5-bit coarse quantization stage (whether to perform is determined based on the result of the prediction stage), and a 6-bit fine quantization stage (must be performed).

[0078] See also Figure 7 In general, when the prediction control unit is working, it generates a control signal IN, a control signal IP, and a reset signal RST according to a comparison signal VP (which is the output signal of the comparator Comp0 of the SAR-ADC unit) and a control signal CTL.

[0079] The prediction control unit adopts the following design, including: 5 sub-latches Latch1~Latch5, 1 inverter INV, 1 buffer BUF, 1 XNOR gate XNOR, 1 OR gate OR, and 1 AND gate AND1~AND2.

[0080] The input end of Latch1 and the input end of Latch2 are connected to VP; the output end of Latch1 is used to output the latch value VP1; the output end of Latch1 is connected to the input end of INV; the output end of INV is used to output the control signal IN1; the output end of INV is connected to the input end 1 of AND1; the output end of Latch2 is used to output the latch value VP2; the output end of Latch1 is connected to the input end of BUF; the output end of BUF is connected to the input end 2 of AND1; the output end of AND1 is used to output the control signal IN2; the input end 1 of XNOR is connected to VP1, the input end 2 is connected to VP2, and the output end is connected to the input end of Latch3; the output end of Latch3 is used to output the reset signal RST; the input end of Latch4 is connected to VP1, and the output end is used to output the control signal IP; the input end of Latch5 is connected to IN1, and the output end is connected to the input end 1 of OR; the input end 1 of AND2 is connected to IN2, the input end 2 is connected to CTL, and the output end is connected to the input end 2 of OR; the output end of OR is used to output the control signal IN.

[0081] 402, SAR-ADC section is used for:

[0082] ①When [V sig,1 ,V ref,1 ]After input, based on V s1,1Perform 5-bit coarse quantization to obtain code value D1<6:0>;

[0083] ②When [V sig,b ,V ref,b ]After input, the corresponding operation is performed according to the prediction result of the prediction control unit:

[0084] If the prediction control unit predicts that 5-bit coarse quantization is not necessary, D b-1 <6:0> as D b <6:0>;

[0085] If the prediction control unit predicts that 5-bit coarse quantization is required, then based on V s1,b Perform 5-bit coarse quantization to obtain the code value D b <6:0>.

[0086] See also Figure 6 The SAR-ADC unit includes: a SAR logic unit, a capacitor array unit, a switch array unit, a coarse quantization power consumption controller, a comparator Comp0, a 5-bit latch, and three switches S3 to S5.

[0087] The first terminal of S3 is connected to the control voltage V cm , the second end is connected to the first end of S5 and the first end of S4;

[0088] The second end of S5 is used to output the array voltage V sar1 ; The second end of S4 is used to output the array voltage V sar0 ;

[0089] The negative input terminal of Comp0 is connected to the second terminal of S1 , the positive input terminal is connected to the second terminal of S4 , and the output terminal is used to output comparison signals VP and VN.

[0090] The capacitor array includes five capacitors C connected in parallel. A ~C E ; C A ~C E The first end of S3 is connected to the second end of S4. A ~C E The capacitance ratio is 1:1:2:4:8.

[0091] The switch array section includes: 15 switches S A0 ~S E0 , S A1 ~S E1 , S A2 ~S E2 ; Among them, S σ0 The first end, S σ1 The first end, S σ2 The first end is connected to Cσ The second end of S σ0 The second end is connected to the control voltage V cm ; S σ1 The second end is connected to the control voltage V l ; S σ2 The second end is connected to the control voltage V h ;σ∈[A,B,C,D,E].

[0092] The SAR logic section is an asynchronous SAR logic, which is used to:

[0093] ① When the 5-bit coarse quantization is performed, the switch array part and S3 are adjusted according to VP and VN;

[0094] ② When the predictive control unit is working, adjust S according to IN, IP, and RST A0 ~S A2 and S3.

[0095] For details, see Figure 6 , the SAR logic unit generates a signal Ctrl_S3 to control S3 and a signal group Ctrl_S to control the switch array unit. It should be noted that since there are 15 switches in the switch array unit, Ctrl_S also includes 15 corresponding switch control signals (i.e., Ctrl_S = {Ctrl_S A0 ~Ctrl_S E0 , Ctrl+S A1 ~Ctrl_S E1 , Ctrl+S A2 ~Ctrl_S E2}), to respectively A0 ~S E0 , S A1 ~S E1 , S A2 ~S E2 Take control.

[0096] The coarse power consumption control unit is used to control Comp0 to be shut down in time to reduce power consumption (by setting a time threshold: when Comp0 reaches the time threshold, Comp0 can be shut down);

[0097] The 5-bit latch is used to latch the output signal of the SAR logic unit and output D n <10:6>.

[0098] That is to say, the capacitor array part cooperates with the switch array part and S3 to adjust the first terminal voltage of S4 and S5; the SAR logic part controls the switch array part and S3; S4 and S5 are turned on at different stages to complete the work of the corresponding stage.

[0099] It should be noted that the SAR-ADC unit works in both the prediction stage and the 5-bit coarse quantization stage.

[0100] 403, SS-ADC section is used for:

[0101] ①When [V sig,1 ,V ref,1 ] After the SAR-ADC part completes the 5-bit coarse quantization, based on V s2,1 Perform 6-bit fine quantization to obtain the code value D1<10:6>;

[0102] ②When [V sig,b ,V ref,b ]After input, the corresponding operation is performed according to the prediction result of the prediction control unit:

[0103] If the prediction control unit predicts that 5-bit coarse quantization is not necessary, the V s2,b Perform 6-bit fine quantization to obtain the code value D b <10:6>;

[0104] If the prediction control unit predicts that 5-bit coarse quantization is required, the SAR-ADC unit will complete the 5-bit coarse quantization and then s2,b Perform 6-bit fine quantization to obtain the code value D b <10:6>.

[0105] See also Figure 8 ,The SS-ADC part includes: 1 comparator Comp1, 1 7-bit counter, 1 7-bit latch, and 1 fine-scale power consumption controller.

[0106] The positive input terminal of Comp1 is connected to the second terminal of S5, the negative input terminal is connected to the second terminal of S2, and the output terminal is used to output the control signal Counter_run;

[0107] The control end of the 7-bit counter is connected to the output end of Comp1, and the output end is connected to the 7-bit latch;

[0108] The 7-bit latch is used to latch the output signal of the 7-bit counter and output D n <6:0>;

[0109] The fine-grained power consumption control unit is used to control Comp1 to be turned off in time to reduce power consumption (through feedback control: when Counter_run is reversed, Comp1 can be turned off).

[0110] It should be noted that the SS-ADC section only works in the 6-bit fine quantization stage. Although the fine quantization is designed to be 6 bits, in order to compensate for the errors that may occur between coarse and fine quantization, a 1-bit redundancy method is adopted, that is, a 7-bit ramp generator is used in the sampling and holding and voltage boosting section, and a 7-bit counter is used in the SS-ADC, and then correction is performed in the data processing section.

[0111] In addition, in the above-mentioned SAR-ADC section and SS-ADC section, although Comp0 and Comp1 are both dynamic comparators, they are different: Comp0 has only one stage of pre-amplifier, and a kickback voltage reduction circuit is added to reduce the impact of kickback noise on Comp0; Comp1 adopts a three-stage pre-amplifier structure and uses output offset elimination to reduce the offset voltage.

[0112] In addition, for the above-mentioned S1, S2, S4, and S5, a unified control signal Ctrl_cmp can be used (that is, their control ends are connected to the control signal Ctrl_cmp); but it should be noted that: when Ctrl_cmp is at a low level, S1 and S4 are closed, and S2 and S5 are disconnected; when Ctrl_cmp is at a high level, S1 and S4 are disconnected, and S2 and S5 are closed.

[0113] So far, based on the above-mentioned sampling and holding and voltage boosting unit, prediction control unit, SAR-ADC unit, and SS-ADC unit:

[0114] ① In the 5-bit coarse quantization stage (in quantization [V sig,1 ,V ref,1 ] must be carried out when quantizing [V sig,2 ,V ref,2 ]~[V sig,N ,V ref,N ] is determined based on the results of the prediction phase):

[0115] S0, S h0 , S1 is closed, S h0 Disconnect, C H Storage V pixel,n With V end The difference voltage ΔV (in this case, ΔV = V pixel,n -V end ), V pixel,n Directly as V s1,n ;

[0116] S3, S4 are closed, S A0 ~S E0 Closed, S A1 ~S E1 , S A2 ~S E2 Disconnect, CA ~C E Both connected to V cm , V sar0 Connect to Comp0 and connect to V s1,n Compare and output VP and VN to the SAR logic unit. The prediction control unit does not work at this time.

[0117] On the one hand, the SAR logic part adjusts the switch array part and S3 according to VP and VN based on the asynchronous SAR logic, and then adjusts V sar0 The specific method is as follows: the SAR logic generates Ctrl_S3 according to VP and VN to keep S3 disconnected, and also generates Ctrl_S to control S E0 Disconnect, S E1 or S E2 Closed, the other switches in the switch array remain in their previous state, i.e. S A0 ~S D0 Closed, S A1 ~S D1 , S A2 ~S D2 Disconnect; S E1 or S E2 After closing, V sar0 When the value changes, VP and VN will also change. The SAR logic will first generate a new Ctrl_S based on the new VP and VN to control S D0 Disconnect, S D1 or S D2 Closed, the other switches in the switch array remain in their previous state, i.e. S A0 ~S C0 Closed, S A1 ~S C1、 S A2 ~S C2 Disconnect; the following is analogous to the previous one until S B0 ~S B2 Complete strobe; in S B0 ~S B2 After the selection is completed, the SAR logic unit will first generate a new Ctrl_S according to the new VP and VN to control S A1 Disconnect, S A0 or S A2 closure.

[0118] On the other hand, the 5-bit latch latches the output signal of the SAR logic unit and outputs D n <10:6>; until the coarse quantization is completed.

[0119] It should be noted that when the 5-bit coarse quantization reaches the last bit, in order to ensure the connection between coarse and fine quantization, the final output voltage of the 5-bit coarse quantization must be above the input voltage of Comp0. However, due to non-ideal characteristics such as comparator offset voltage, Comp0 flip errors may occur. Therefore, in the 6-bit fine quantization stage, the signal is pulled down by a certain amount of voltage to compensate for possible flip errors. The correction value is: V end -V x .

[0120] ② In the 6-bit fine quantization stage (in quantization [V sig,1 ,V ref,1 ]~[V sig,N ,V ref,N ] must be carried out):

[0121] S h1 , S2 is closed, S0, S1 are disconnected, C H The second terminal is connected to V ramp , C H The voltage at the first terminal is V s2,n ——The difference voltage ΔV retained by the 5-bit coarse quantization in the previous stage plus V ramp (At this time, V s2,n =ΔV+V ramp ), thereby pulling the slope downward;

[0122] S4 is open, S5 is closed, V sar1 Connect to Comp1 and connect to V s2,n The comparison is performed to output Counter_run to drive the 7-bit counter to start counting until Counter_run reverses and the 7-bit counter stops counting; the 7-bit latch latches the count value of the 7-bit counter and outputs D n <6:0>.

[0123] ③ In the prediction stage (in the quantization [V sig,2 ,V ref,2 ]~[V sig,N ,V ref,N ] must be carried out):

[0124] The sampling and holding and voltage raising parts also adopt the 5-bit coarse quantization stage control method: S0, S h0 , S1 is closed, S h1 Disconnect, C H Storage V pixel,b With V end The difference voltage (in this case, ΔV = V pixel,b -V end ), V pixel,b Directly as Vs1,b .

[0125] The prediction phase will go through Fig. 9 The first 2 periods shown: T p0 , T p1 ;also, Fig. 9 The last two periods T are also shown coarse (5bit coarse quantization), T fine (6bit fine quantization):

[0126] There are four situations in the prediction stage:

[0127] (a) If Fig. 9 As shown in a:

[0128] In T p0 During this period, S3 is open, S4 is closed, S A0 Closed, S A1 , S A2 Disconnect, S B0 ~S B2 , S E0 ~S E2 Keep the switch state of the previous coarse quantization unchanged. At this time, Comp0 is sar0 、V s1,n Compare and output VP and VN. Different from the 5-bit coarse quantization stage, the prediction control unit works at this time and processes VP and CTL, and outputs IP, IN and RST to the SAR logic unit.

[0129] The SAR logic unit is still based on asynchronous SAR logic, and controls S according to IP, IN, and RST. A0 ~S A2 and S3 to adjust V sar0 The 5-bit latch does not work at this time and temporarily stores the result of the last 5-bit coarse quantization.

[0130] In T p1 During this period, S3 remains disconnected, S A2 Closed, S A0 , S A1 Disconnect, C A Connect to V h ; If V s1,b <V sar0 , we can determine the pixel voltage value V s1,b If the pixel voltage value is close to the previous column, the 5-bit coarse quantization stage is skipped: that is, at T coarse During this period, the SAR logic unit does not need to take any action and remains unchanged; during T fine During this period, 6-bit fine quantization is normally performed.

[0131] (ii) Fig. 9 As shown in b:

[0132] In T p0 During this period, S3 is open, 4 is closed, S A0 Closed, S A1 , S A2 Disconnect, S B0 ~S B2 , S E0 ~S E2 Keep the switch state of the previous coarse quantization unchanged. At this time, Comp0 is sar0 、V s1,n Compare and output VP and VN. Different from the 5-bit coarse quantization stage, the prediction control unit works at this time and processes VP and CTL, and outputs IP, IN and RST to the SAR logic unit.

[0133] The SAR logic unit is still based on asynchronous SAR logic, and controls S according to IP, IN, and RST. A0 ~S A2 and S3 to adjust V sar0 The 5-bit latch does not work at this time and temporarily stores the result of the last 5-bit coarse quantization.

[0134] In T p1 During this period, S3 remains disconnected, S A1 Closed, S A0 , S A2 Disconnect, C A Connect to V1; if V s1,b >V sar0 , we can determine the pixel voltage value V s1,b If the pixel voltage value is close to the previous column, the 5-bit coarse quantization stage is skipped: that is, at T coarse During this period, the SAR logic unit does not need to take any action and remains unchanged; during T fine During this period, 6-bit fine quantization is normally performed.

[0135] (III) Fig. 9 As shown in c:

[0136] In T p0 During this period, S3 is open, S4 is closed, S A0 Closed, S A1 , S A2 Disconnect, S B0 ~S B2 , S E0 ~S E2 Keep the switch state of the previous coarse quantization unchanged. At this time, Comp0 is sar0 、V s1,nCompare and output VP and VN. Different from the 5-bit coarse quantization stage, the prediction control unit works at this time and processes VP and CTL, and outputs IP, IN and RST to the SAR logic unit.

[0137] The SAR logic unit is still based on asynchronous SAR logic, and controls S according to IP, IN, and RST. A0 ~S A2 and S3 to adjust V sar0 The 5-bit latch does not work at this time and temporarily stores the result of the last 5-bit coarse quantization.

[0138] In T p1 period, S3 closed, S A1 Closed, S A0 , S A2 Disconnect, C A Connect to V1; if V s1,b <V sar0 , we can determine the pixel voltage value V s1,b If the pixel voltage value is not near the previous column, the 5-bit coarse quantization stage cannot be skipped: the prediction control unit resets the SAR-ADC unit; at T coarse During the period, 5-bit coarse quantization is performed normally; during T fine During this period, 6-bit fine quantization is normally performed.

[0139] (IV) Fig. 9 As shown in D:

[0140] In T p0 During this period, S3 is open, S4 is closed, S A0 Closed, S A1 , S A2 Disconnect, S B0 ~S B2 , S E0 ~S E2 Keep the switch state of the previous coarse quantization unchanged. At this time, Comp0 is sar0 、V s1,n Compare and output VP and VN. Different from the 5-bit coarse quantization stage, the prediction control unit works at this time and processes VP and CTL, and outputs IP, IN and RST to the SAR logic unit.

[0141] The SAR logic unit is still based on asynchronous SAR logic, and controls S according to IP, IN, and RST. A0 ~S A2 and S3 to adjust V sar0 The 5-bit latch does not work at this time and temporarily stores the result of the last 5-bit coarse quantization.

[0142] In T p1period, S3 closed, S A2 Closed, S A0 , S A1 Disconnect, C A Connect to V h ; If V s1,b >V sar0 , we can determine the pixel voltage value V s1,b If the pixel voltage value is not near the previous column, the 5-bit coarse quantization stage cannot be skipped: the prediction control unit resets the SAR-ADC unit; at T coarse During the period, 5-bit coarse quantization is performed normally; during T fine During this period, 6-bit fine quantization is normally performed.

[0143] Combining the above four situations, we can successfully get D n <6:0>, D n <10:6>.

[0144] 5. The data processing unit is used to: n <6:0>, D n <10:6> Perform 11-bit numerical correction to obtain 11-bit quantization result D n <10:0>.

[0145] Among them, D n <10:0>=D n <10:6> -D n <6:0>+D n <4:0>;

[0146] D n <4:0> indicates the correction value, D n <4:0>=V end -V x .

[0147] See also Fig.10 The data processing unit can be designed to include: 1 subtractor, 1 value corrector, and 1 10-bit latch.

[0148] The numerical modifier is used to provide D n <4:0>; the input of the subtractor is connected to D n <10:6>, input terminal 2 is connected to D n <6:0>, input terminal three connection D n <4:0>, the output end is connected to a 10-bit latch; the 10-bit latch is used to latch the output signal of the subtractor and output D n <10:0>.

[0149] That is, the subtractor implements D n<10:6> -D n <6:0>+D n <4:0> and output to the 10-bit latch, which outputs the final data as D n <10:0>.

[0150] The SAR-SS-ADC circuit based on the above design can realize [V sig,1 ,V ref,1 ]~[V sig,N ,V ref,N ]Perform 11-bit quantization sequentially, reduce the number of ADCs, and reduce unnecessary time and power consumption of 5-bit coarse quantization.

[0151] Example 2

[0152] This embodiment 2 discloses a SAR-SS type ADC module based on adjacent pixel prediction, which adopts the layout of a SAR-SS type ADC circuit based on adjacent pixel prediction disclosed in embodiment 1. The packaging mode makes it easier to promote and apply the above circuit.

[0153] The SAR-SS ADC module based on adjacent pixel prediction includes: a signal input module (corresponding to the signal input part), a gain amplification module (corresponding to the gain amplification part), a sampling and holding and voltage raising module (corresponding to the sampling and holding and voltage raising part), a prediction control module (corresponding to the prediction control part), a SAR-ADC module (corresponding to the SAR-ADC part), a SS-ADC module (corresponding to the SS-ADC), and a data processing module (corresponding to the data processing part). For specific circuit distribution, please refer to Example 1, which will not be repeated here.

[0154] This embodiment 2 also simultaneously discloses a CMOS image sensor, which adopts the above-mentioned SAR-SS type ADC module based on adjacent pixel prediction.

[0155] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A SAR-SS type ADC circuit based on adjacent pixel prediction, characterized in that: include: The signal input part is used to control the N-column pixel signal [V sig,1 ,V ref,1 ]~[V sig,N ,V ref,N ] are input sequentially for 11-bit quantization; where [V sig,a ,V ref,a ]After completing 11-bit quantization, enter [V sig,a+1 ,V ref,a+1 ]; a∈[1,N-1]; The gain amplifier is used for: When [V sig,n ,V ref,n ]After inputting, V ref,n With V sig,n Subtract and amplify to generate pixel voltage V pixel,n ; n∈[1,N]; The sampling and holding and voltage raising section is used to: pixel,n Output hold voltage signal V at 5bit coarse quantization s1,n , combined with a fixed voltage V when quantizing 6 bits end , reference voltage V x To output the boost voltage signal V s2,n ; The predictive control unit is used to: when [V sig,b ,V ref,b ]After input, predict whether 5-bit coarse quantization is needed; b∈[2,N]; SAR-ADC section, which is used for: When [V sig,1 ,V ref,1 ]After input, based on V s1,1 Perform 5-bit coarse quantization to obtain the code value D1<6:0>; when [V sig,b ,V ref,b ] is input, and corresponding operations are performed according to the prediction results of the prediction control unit; if the prediction control unit predicts that 5-bit coarse quantization is not required, D is retained. b-1 <6:0> as D b <6:0>; If the prediction control unit predicts that 5-bit coarse quantization is required, then based on V s1,b Perform 5-bit coarse quantization to obtain the code value D b <6:0>; SS-ADC section, which is used for: When [V sig,1 ,V ref,1 ] After the SAR-ADC part completes the 5-bit coarse quantization, it will then be based on V s2,1 Perform 6-bit fine quantization to obtain the code value D1<10:6>; when [V sig,b ,V ref,b ] is input, and corresponding operations are performed according to the prediction results of the prediction control unit; if the prediction control unit predicts that 5-bit coarse quantization is not required, the V s2,b Perform 6-bit fine quantization to obtain the code value D b <10:6>; If the prediction control unit predicts that 5-bit coarse quantization is required, wait until the SAR-ADC unit completes the 5-bit coarse quantization, and then based on V s2,b Perform 6-bit fine quantization to obtain the code value D b <10:6>; as well as A data processing unit is used to process the n <6:0>, D n <10:6> Perform 11-bit numerical correction to obtain 11-bit quantization result D n <10:0>; Among them, D n <10:0>=D n <10:6> -D n <6:0>+D n <4:0>; D n <4:0> indicates the correction value, D n <4:0>=V end -V x .

2. A SAR-SS type ADC circuit based on adjacent pixel prediction according to claim 1, characterized in that: The signal input unit comprises: N switches S P,1 ~S P,N ; Among them, S P,n The first end of the connection [V sig,n ,V ref,n ]; The input end of the gain amplifier is connected to S P,n The second end, the output end, is used to output V pixel,n .

3. The SAR-SS type ADC circuit based on adjacent pixel prediction according to claim 1, characterized in that: The sampling, holding and voltage raising unit includes: 3 switches S0-S2, 2 switches S h0 ~S h1 , 1 capacitor C H , 1 7-bit ramp generator; The first end of S0 is connected to the output end of the gain amplifier, and the second end is connected to C H a first end of S1, a first end of S2; The second end of S1 is used to output V s1,n ; The second end of S2 is used to output V s2,n ; C H The second end is connected to S h0 The first end, S h1 The first end of S h0 The second terminal is used to input V end ; S h1 The second end is connected to the output end of the 7-bit ramp generator; the output end of the 7-bit ramp generator is used to output the ramp signal V ramp .

4. The SAR-SS type ADC circuit based on adjacent pixel prediction according to claim 3, characterized in that: The 7-bit ramp generator includes: a conversion circuit part, a current source part, a differential switch part, and an operational amplifier array part; The conversion circuit includes: 1 resistor R, 1 resistor R dummy ; The second end of R is connected to R dummy The second end of The current source section includes: 18 current sources I0~I 17 ; Among them, I0 is i0 current source, I1 is 2i0 current source, I2 is 4i0 current source, I3~I 17 is 8i0 current source; The differential switch section includes: 36 switches S W,0 ~S W,35 ; Among them, I e By S W,c Connect the first end of R through S W,d Connect R dummy The first end of; c∈[0,2,4,…,34], d∈[1,3,5,…,35]; The operational amplifier array includes: 2 operational amplifiers A0~A1, 1 capacitor C x , 1 NMOS tube N1; the positive input end of A0 is connected to the first end of R; the negative input end of A0 is connected to the output end of A0 and serves as the output end of the 7-bit ramp generator to output V ramp ; The positive input of A1 is connected to C x The first end of R, the second end of R, the drain of N1, and the negative input end are connected to V x , the output terminal is connected to C x The second end of N1 and the gate of N1; the source of N1 is grounded.

5. A SAR-SS type ADC circuit based on adjacent pixel prediction according to claim 3 or 4, characterized in that: The SAR-ADC unit includes: a SAR logic unit, a capacitor array unit, a switch array unit, a coarse quantization power consumption controller, a comparator Comp0, a 5-bit latch, and three switches S3-S5; The first terminal of S3 is connected to the control voltage V cm , the second end is connected to the first end of S5 and the first end of S4; The second end of S5 is used to output the array voltage V sar1 ; The second end of S4 is used to output the array voltage V sar0 ; The negative input terminal of Comp0 is connected to the second terminal of S1, the positive input terminal is connected to the second terminal of S4, and the output terminal is used to output comparison signals VP and VN; wherein, when the prediction control unit works, it generates a control signal IN, a control signal IP, and a reset signal RST according to VP and a control signal CTL; The capacitor array includes five capacitors C connected in parallel. A ~C E ; C A ~C E The first end of is connected to the second end of S3; The switch array section includes: 15 switches S A0 ~S E0 , S A1 ~S E1 , S A2 ~S E2 ; Among them, S σ0 The first end, S σ1 The first end, S σ2 The first end is connected to C σ The second end of S σ0 The second end is connected to the control voltage V cm ; S σ1 The second end is connected to the control voltage V l ; S σ2 The second end is connected to the control voltage V h ;σ∈[A,B,C,D,E]; The SAR logic unit is an asynchronous SAR logic, which is used to adjust the switch array unit and S3 according to VP and VN during 5-bit coarse quantization, and adjust S according to IN, IP, and RST when the prediction control unit is working. A0 ~S A2 and S3; The coarse power consumption control unit is used to control Comp0 to shut down in time to reduce power consumption; The 5-bit latch is used to latch the output signal of the SAR logic unit and output D n <10:6>.

6. The SAR-SS type ADC circuit based on adjacent pixel prediction according to claim 5, characterized in that: The prediction control unit includes: 5 sub-latches Latch1 to Latch5, 1 inverter INV, 1 buffer BUF, 1 XNOR gate XNOR, 1 OR gate OR, and 1 AND gates AND1 to AND2; The input end of Latch1 and the input end of Latch2 are connected to VP; The output end of Latch1 is used to output the latch value VP1; the output end of Latch1 is connected to the input end of INV; the output end of INV is used to output the control signal IN1; the output end of INV is connected to the input end 1 of AND1; The output end of Latch2 is used to output the latch value VP2; the output end of Latch1 is connected to the input end of BUF; the output end of BUF is connected to the second input end of AND1; the output end of AND1 is used to output the control signal IN2; The input terminal 1 of XNOR is connected to VP1, the input terminal 2 is connected to VP2, and the output terminal is connected to the input terminal of Latch3; the output terminal of Latch3 is used to output the reset signal RST; The input end of Latch4 is connected to VP1, and the output end is used to output the control signal IP; The input of Latch5 is connected to IN1, and the output is connected to input 1 of OR; Input 1 of AND2 is connected to IN2, input 2 is connected to CTL, and the output is connected to input 2 of OR; The output terminal of OR is used to output a control signal IN.

7. The SAR-SS type ADC circuit based on adjacent pixel prediction according to claim 5, characterized in that: The control terminals of S1, S2, S4 and S5 are connected to the control signal Ctrl_cmp; Among them, when Ctrl_cmp is low level, S1 and S4 are closed, and S2 and S5 are open; When Ctrl_cmp is high, S1 and S4 are open, and S2 and S5 are closed.

8. The SAR-SS type ADC circuit based on adjacent pixel prediction according to claim 5, characterized in that: The SS-ADC unit includes: a comparator Comp1, a 7-bit counter, a 7-bit latch, and a fine-quantization power consumption controller; The positive input terminal of Comp1 is connected to the second terminal of S5, the negative input terminal is connected to the second terminal of S2, and the output terminal is used to output the control signal Counter_run; The control end of the 7-bit counter is connected to the output end of Comp1, and the output end is connected to the 7-bit latch; The 7-bit latch is used to latch the output signal of the 7-bit counter and output D n <6:0>; The fine-grained power consumption control unit is used to control Comp1 to be turned off in time to reduce power consumption.

9. The SAR-SS type ADC circuit based on adjacent pixel prediction according to claim 1, characterized in that: The data processing unit includes: a subtractor, a value corrector, and a 10-bit latch; The numerical modifier is used to provide D n <4:0>; The input of the subtractor is connected to D n <10:6>, input terminal 2 is connected to D n <6:0>, input terminal three connection D n <4:0>, the output is connected to a 10-bit latch; The 10-bit latch is used to latch the output signal of the subtractor and output D n <10:0>.

10. A SAR-SS type ADC module based on adjacent pixel prediction, characterized in that: A layout of a SAR-SS type ADC circuit based on adjacent pixel prediction as described in any one of claims 1 to 9 is adopted.

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