Transistor and preparation method thereof

Abstract

The invention provides a transistor and a preparation method thereof, and belongs to the field of power electronics. The transistor comprises an epitaxial wafer, a source electrode, a drain electrode and a gate electrode, the epitaxial wafer comprises a channel layer and a barrier layer, and the epitaxial wafer is provided with an active region and an ineffective region; the drain electrode is located on the surface, away from the channel layer, of the barrier layer, is located in the active region and is electrically connected with the channel layer through the first through hole; the source electrode and the gate electrode are both located on the surface, away from the channel layer, of the barrier layer, the source electrode of the first part is electrically connected with the channel layer through the second through hole, and the source electrode of the second part extends to the side, away from the barrier layer, of the channel layer through the first via hole; the gate electrode of the first part is connected with the barrier layer, and the gate electrode of the second part extends to the side, away from the barrier layer, of the channel layer through the second via hole. According to the embodiment of the invention, the applicability of the transistor is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics, and in particular to a transistor and a method for preparing the same. Background Art

[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field effect transistor that is widely used in various electrical appliances.

[0003] In the related art, the transistor includes a channel layer and a barrier layer stacked in sequence on a substrate, a source and a drain connected to the channel layer through the barrier layer, and a gate located between the source and the drain in the barrier layer. The channel layer and the barrier layer are GaN layer and AlGaN layer, respectively. A high-concentration two-dimensional electron gas channel can be formed at the AlGaN / GaN heterojunction interface. The high-concentration and high-electron-mobility two-dimensional electron gas channel is the biggest advantage of GaN high-electron-mobility transistors over traditional field-effect transistors.

[0004] In order to take advantage of the two-dimensional electron gas channel, transistors are usually designed as planar structures, where the source, drain and gate are distributed on the same side of the barrier layer. However, planar transistors have poor compatibility with traditional electronic devices, resulting in poor applicability of transistors. Summary of the invention

[0005] The disclosed embodiment provides a transistor and a method for manufacturing the same, which can not only take advantage of the two-dimensional electron gas channel, but also design the transistor into a vertical structure to meet the applicability of the transistor. The technical solution is as follows:

[0006] On the one hand, the embodiment of the present disclosure provides a transistor, the transistor comprising: an epitaxial wafer, a source electrode, a drain electrode, and a gate electrode; the epitaxial wafer comprises a channel layer and a barrier layer stacked in sequence, the epitaxial wafer has an active region and an inactive region, the active region and the inactive region are insulated, the inactive region has a first via hole and a second via hole penetrating the epitaxial wafer; the drain electrode is located on a surface of the barrier layer away from the channel layer, and the drain electrode is located in the active region, the barrier layer has a first via hole exposing the channel layer, and the drain electrode is electrically connected to the channel layer through the first via hole; the source electrode and the gate electrode are both located on a surface of the barrier layer away from the channel layer On the surface of the channel layer, the first part of the source electrode is located in the active area, the second part of the source electrode is located in the inactive area, the barrier layer also has a second through hole exposing the channel layer, the first part of the source electrode is electrically connected to the channel layer through the second through hole, and the second part of the source electrode extends to the side of the channel layer away from the barrier layer through the first via hole; the first part of the gate electrode is located in the active area, the second part of the gate electrode is located in the inactive area, the first part of the gate electrode is connected to the barrier layer, and the second part of the gate electrode extends to the side of the channel layer away from the barrier layer through the second via hole.

[0007] Optionally, the epitaxial wafer further has an isolation channel region, the isolation channel region surrounds the active region, and the isolation channel region is located between the active region and the inactive region.

[0008] Optionally, N+ ions are implanted into the isolation channel region.

[0009] Optionally, the transistor also includes a dielectric layer and a drain solder joint, the dielectric layer is located on a surface of the barrier layer away from the channel layer, and the dielectric layer covers the drain electrode, the source electrode and the gate electrode, the surface of the dielectric layer away from the barrier layer has a through hole exposing the drain electrode, and the drain solder joint is electrically connected to the drain electrode through the through hole.

[0010] Optionally, the transistor also includes a bonding metal layer and a conductive substrate, the bonding metal layer is located on the surface of the dielectric layer away from the barrier layer and is electrically connected to the drain electrode through a through hole, the conductive substrate is located on the surface of the bonding metal layer away from the dielectric layer, and the drain solder joint is located on the surface of the conductive substrate away from the dielectric layer.

[0011] Optionally, the transistor also includes a substrate, a source solder joint and a gate solder joint, the substrate is located on a surface of the channel layer away from the barrier layer, and the surface of the substrate has a third via and a fourth via exposing the invalid area; the source solder joint and the gate solder joint are both located on the surface of the substrate away from the channel layer, the source solder joint is connected to the source electrode through the third via and the first via in sequence, and the gate solder joint is connected to the gate electrode through the fourth via and the second via in sequence.

[0012] Optionally, the epitaxial wafer also includes a p-type layer, which is located on the surface of the barrier layer away from the channel layer, the source electrode and the drain electrode are both spaced apart from the p-type layer, and the gate electrode is located on the surface of the p-type layer away from the barrier layer; in the active area, the orthographic projection of the gate electrode on the surface of the barrier layer is located within the orthographic projection of the p-type layer on the surface of the barrier layer.

[0013] Optionally, the first part of the source electrode is in a strip shape, the second part of the source electrode is in a block shape, and one end of the first part of the source electrode is connected to the second part of the source electrode; the second through hole is in a strip shape, and the orthographic projection of the second through hole on the surface of the barrier layer is located within the orthographic projection of the first part of the source electrode on the surface of the barrier layer; the first part of the gate electrode is in a strip shape, the second part of the gate electrode is in a block shape, and one end of the first part of the gate electrode is connected to the second part of the gate electrode.

[0014] Optionally, the drain electrode is in a strip shape, the first through hole is in a strip shape, and an orthographic projection of the first through hole on the surface of the barrier layer is located within an orthographic projection of the first part of the drain electrode on the surface of the barrier layer.

[0015] On the other hand, an embodiment of the present disclosure provides a method for preparing a transistor, the method comprising: forming an epitaxial wafer on a substrate, the epitaxial wafer comprising a channel layer and a barrier layer stacked in sequence on the substrate, the barrier layer having a first through hole and a second through hole exposing the channel layer, the epitaxial wafer having an active area and an ineffective area, the active area and the ineffective area being insulated, and the ineffective area having a first via hole and a second via hole penetrating the epitaxial wafer; forming a drain electrode, a source electrode and a gate electrode on a surface of the barrier layer away from the channel layer, the drain electrode being located in the active area, the drain electrode being electrically connected to the channel layer through the first through hole, a first part of the source electrode being located in the active area, a second part of the source electrode being located in the ineffective area, the first part of the source electrode being electrically connected to the channel layer through the second through hole, and the second part of the source electrode extending to a side of the channel layer away from the barrier layer through the first via hole.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] In the transistor provided by the embodiment of the present disclosure, the drain electrode, source electrode and gate electrode are all arranged on the surface of the barrier layer away from the channel layer. Among them, the source electrode and the gate electrode both span the active area and the ineffective area of ​​the epitaxial wafer, the source electrode is located in the first part of the active area and is electrically connected to the channel layer through the second through hole, and the source electrode is located in the second part of the ineffective area and extends to the side of the channel layer away from the barrier layer through the first via hole, so that the drain electrode and the source electrode are distributed on opposite sides of the epitaxial wafer; at the same time, the gate electrode is located in the first part of the active area and is connected to the barrier layer, and the gate electrode is located in the second part of the ineffective area and the second via hole extends to the side of the channel layer away from the barrier layer, so that the drain electrode and the gate electrode are distributed on opposite sides of the epitaxial wafer. That is, the source electrode and the gate electrode are arranged on the side of the channel layer away from the barrier layer, and the drain electrode is arranged on the side of the barrier layer away from the channel layer, so as to form a transistor with a vertical structure.

[0018] At the same time, when the external power source energizes the source electrode and the gate electrode, the current will cross the channel layer from the ineffective area of ​​the active layer, so that the current injected from the source electrode or the gate electrode will not enter the channel layer on the side of the channel layer away from the barrier layer, but will enter the channel layer from the side of the channel layer close to the barrier layer through the source electrode or the gate electrode after crossing from the ineffective area to the active area. The drain electrode is located on the surface of the barrier layer away from the channel layer, and the drain electrode can be electrically connected to the channel layer through the first through hole, so that the current injected by the drain electrode can also enter the channel layer from the side of the channel layer close to the barrier layer. Since the source electrode and the drain electrode are injected from the same surface of the channel layer, rather than from the opposite sides of the channel layer, a high-concentration two-dimensional electron gas channel can be formed at the heterojunction interface of the channel layer and the barrier layer, allowing the transistor to take advantage of the two-dimensional electron gas channel. In this way, the transistor not only takes advantage of the two-dimensional electron gas channel, but also forms a transistor with a vertical structure to reduce the difficulty of transistor application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 is a top view of a transistor provided by an embodiment of the present disclosure;

[0021] Figure 2 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;

[0022] Figure 3 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;

[0023] Figure 4 It is a flow chart of a method for preparing a transistor provided in an embodiment of the present disclosure.

[0024] The descriptions of the marks in the figure are as follows:

[0025] 10. substrate; 11. third via hole; 12. fourth via hole;

[0026] 20, epitaxial wafer; 210, active region; 220, isolation channel region; 230, inactive region;

[0027] 201, first via hole; 202, second via hole;

[0028] 21. channel layer; 22. barrier layer; 221. first through hole; 222. second through hole; 23. p-type layer;

[0029] 31. Source electrode; 32. Drain electrode; 33. Gate electrode;

[0030] 40. Dielectric layer;

[0031] 51. Source solder joint; 52. Drain solder joint; 53. Gate solder joint;

[0032] 61. Bonding metal layer; 62. Conductive substrate. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0034] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0035] Figure 1 is a top view of a transistor provided by an embodiment of the present disclosure. Figure 2 It is a schematic diagram of the structure of a transistor provided in an embodiment of the present disclosure. Figure 3 It is a schematic diagram of the structure of a transistor provided in an embodiment of the present disclosure. Figure 2 is along Figure 1 The cross-section diagram obtained by cutting along the AA section line. Figure 3 is along Figure 1 Cross-sectional view obtained by cutting along section line BB.

[0036] like Figure 1 , 2 As shown, the transistor includes: an epitaxial wafer 20, a source electrode 31, a drain electrode 32, and a gate electrode 33; the epitaxial wafer 20 includes a channel layer 21 and a barrier layer 22 stacked in sequence, the epitaxial wafer 20 has an active area 210 and an ineffective area 230, the active area 210 and the ineffective area 230 are insulated, and the ineffective area 230 has a first via 201 and a second via 202 that pass through the epitaxial wafer 20.

[0037] like Figure 2 As shown, the drain electrode 32 is located on the surface of the barrier layer 22 away from the channel layer 21 , and the drain electrode 32 is located in the active area 210 . The barrier layer 22 has a first through hole 221 exposing the channel layer 21 , and the drain electrode 32 is electrically connected to the channel layer 21 through the first through hole 221 .

[0038] like Figures 1 to 3As shown, the source electrode 31 and the gate electrode 33 are both located on the surface of the barrier layer 22 away from the channel layer 21, the first part of the source electrode 31 is located in the active area 210, and the second part of the source electrode 31 is located in the inactive area 230. The barrier layer 22 also has a second through hole 222 exposing the channel layer 21. The first part of the source electrode 31 is electrically connected to the channel layer 21 through the second through hole 222, and the second part of the source electrode 31 extends to the side of the channel layer 21 away from the barrier layer 22 through the first via 201.

[0039] like Figures 1 to 3 As shown, the first part of the gate electrode 33 is located in the active area 210, the second part of the gate electrode 33 is located in the inactive area 230, the first part of the gate electrode 33 is connected to the barrier layer 22, and the second part of the gate electrode 33 extends to the side of the channel layer 21 away from the barrier layer 22 through the second via 202.

[0040] In the transistor provided by the embodiment of the present disclosure, the drain electrode 32, the source electrode 31 and the gate electrode 33 are all arranged on the surface of the barrier layer 22 away from the channel layer 21. The source electrode 31 and the gate electrode 33 both span the active area 210 and the inactive area 230 of the epitaxial wafer 20. The first part of the source electrode 31 located in the active area 210 is electrically connected to the channel layer 21 through the second through hole 222, and the second part of the source electrode 31 located in the inactive area 230 is extended to the side of the channel layer 21 away from the barrier layer 22 through the first via 201, so that the drain electrode 32 and the source electrode 31 are distributed on opposite sides of the epitaxial wafer 20; at the same time, the first part of the gate electrode 33 located in the active area 210 is connected to the barrier layer 22, and the second part of the gate electrode 33 located in the inactive area 230 is extended to the side of the channel layer 21 away from the barrier layer 22 through the second via 202, so that the drain electrode 32 and the gate electrode 33 are distributed on opposite sides of the epitaxial wafer 20. That is, the source electrode 31 and the gate electrode 33 are arranged on the side of the channel layer 21 away from the barrier layer 22 , and the drain electrode 32 is arranged on the side of the barrier layer 22 away from the channel layer 21 , so as to form a vertical transistor.

[0041] At the same time, when the external power source energizes the source electrode 31 and the gate electrode 33, the current will cross the channel layer 21 from the ineffective area 230 of the active layer, so that the current injected from the source electrode 31 or the gate electrode 33 will not enter the channel layer 21 on the side of the channel layer 21 away from the barrier layer 22, but will cross from the ineffective area 230 to the active area 210, and then enter the channel layer 21 from the side of the channel layer 21 close to the barrier layer 22 through the source electrode 31 or the gate electrode 33. The drain electrode 32 is located on the surface of the barrier layer 22 away from the channel layer 21, and the drain electrode 32 can be electrically connected to the channel layer 21 through the first through hole 221, so that the current injected by the drain electrode 32 can also enter the channel layer 21 from the side of the channel layer 21 close to the barrier layer 22. Since the source electrode 31 and the drain electrode 32 are both injected from the same surface of the channel layer 21, rather than from the opposite sides of the channel layer 21, a high-concentration two-dimensional electron gas channel can be formed at the heterojunction interface between the channel layer 21 and the barrier layer 22, allowing the transistor to take advantage of the two-dimensional electron gas channel. In this way, the transistor not only takes advantage of the two-dimensional electron gas channel, but also forms a vertically structured transistor to reduce the difficulty of transistor application.

[0042] Exemplarily, the channel layer 21 is a GaN layer, and the barrier layer 22 is an AlGaN layer.

[0043] Alternatively, if Figure 1 As shown, the epitaxial wafer 20 further has an isolation channel region 220 . The isolation channel region 220 surrounds the active region 210 , and the isolation channel region 220 is located between the active region 210 and the inactive region 230 .

[0044] In the disclosed embodiment, the active region 210 is the functional region of the transistor, and the ineffective region 230 is a redundant region. The active region 210 and the ineffective region 230 are isolated by setting an isolation channel region 220. In this way, the redundant ineffective region 230 is used to allow the source electrode 31 to extend to the side of the channel layer 21 away from the barrier layer 22, so that the drain electrode 32 and the source electrode 31 are distributed on opposite sides of the epitaxial wafer 20, and the source electrode 31 is prevented from being electrically connected to the channel layer 21 when penetrating the epitaxial wafer 20; similarly, the drain electrode 32 and the gate electrode 33 can be distributed on opposite sides of the epitaxial wafer 20, and the source electrode 31 is prevented from being electrically connected to the channel layer 21 when penetrating the epitaxial wafer 20, so as to finally form a transistor with a vertical structure.

[0045] Optionally, N+ ions are implanted into the isolation channel region 220. By implanting N+ ions into the isolation channel region 220, the active region 210 and the inactive region 230 can be isolated, so that a five-effect region insulated from the active region 210 can be formed.

[0046] For example, the concentration of N+ ions implanted into the isolation channel region 220 may be greater than or equal to 5×10 14cm -3 .

[0047] Alternatively, if Figure 2 As shown, the transistor also includes a dielectric layer 40 and a drain solder joint 52. The dielectric layer 40 is located on the surface of the barrier layer 22 away from the channel layer 21, and the dielectric layer 40 covers the drain electrode 32, the source electrode 31 and the gate electrode 33. The surface of the dielectric layer 40 away from the barrier layer 22 has a through hole exposing the drain electrode 32, and the drain solder joint 52 is electrically connected to the drain electrode 32 through the through hole.

[0048] Exemplarily, the dielectric layer 40 is a silicon oxide layer. The silicon oxide layer covers the drain electrode 32, the source electrode 31 and the gate electrode 33 to protect the drain electrode 32, the source electrode 31 and the gate electrode 33, and the silicon oxide layer also has an insulating function to prevent the drain electrode 32, the source electrode 31 and the gate electrode 33 from shorting.

[0049] In the above implementation, the drain pad 52 is disposed above the dielectric layer 40 to prevent the drain pad 52 from being short-circuited with the gate electrode 33 or the source electrode 31 , thereby improving the reliability of the transistor.

[0050] Exemplarily, the drain pad 52 includes at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

[0051] The above metal material has good heat dissipation performance. Therefore, the drain solder joint 52 made of the above material also has good heat dissipation performance, which can improve the heat dissipation effect of the transistor.

[0052] Optionally, the drain pad 52 includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked in sequence.

[0053] Alternatively, if Figure 2 As shown, the transistor also includes a bonding metal layer 61 and a conductive substrate 62. The bonding metal layer 61 is located on the surface of the dielectric layer 40 away from the barrier layer 22 and is electrically connected to the drain electrode 32 through a through hole. The conductive substrate 62 is located on the surface of the bonding metal layer 61 away from the dielectric layer 40, and the drain solder joint 52 is located on the surface of the conductive substrate 62 away from the dielectric layer 40.

[0054] Exemplarily, the conductive substrate 62 may be a silicon substrate 10 .

[0055] The silicon substrate 10 is a conductive substrate 10 , the bonding metal is used to connect the silicon substrate 10 and the drain electrode 32 , and the drain solder joint 52 is arranged on the surface of the silicon substrate 10 , so that the drain solder joint 52 can be electrically connected to the drain electrode 32 through the silicon substrate 10 .

[0056] By providing bonding metal and allowing the bonding metal to be electrically connected to the drain electrode 32 through the through hole on the dielectric layer 40, the conductive substrate 62 can be directly electrically connected to the drain electrode 32 through the bonding metal. When preparing the drain solder joint 52, it only needs to be laid flat on the conductive substrate 62 to achieve the electrical connection between the drain solder joint 52 and the drain electrode 32, thereby reducing the difficulty of preparing the drain solder joint 52.

[0057] Alternatively, if Figure 3 As shown, the transistor further includes a substrate 10 , a source pad 51 and a gate pad 53 . The substrate 10 is located on a surface of the channel layer 21 away from the barrier layer 22 . The surface of the substrate 10 has a third via hole 11 and a fourth via hole 12 exposing the ineffective area 230 .

[0058] like Figure 3 As shown, the source solder joint 51 and the gate solder joint 53 are both located on the surface of the substrate 10 away from the channel layer 21. The source solder joint 51 is connected to the source electrode 31 through the third via 11 and the first via 201 in sequence, and the gate solder joint 53 is connected to the gate electrode 33 through the fourth via 12 and the second via 202 in sequence.

[0059] By way of example, the substrate 10 may be a substrate 10 having an insulating effect, such as a sapphire substrate 10 .

[0060] The substrate 10 is disposed on the surface of the channel layer 21 away from the barrier layer 22 to isolate the channel layer 21 from the source solder joint 51 and the gate solder joint 53. The source solder joint 51 and the gate solder joint 53 are prevented from being directly electrically connected to the channel layer 21 on the surface of the channel layer 21 away from the barrier layer 22.

[0061] At the same time, by providing the substrate 10 on the surface of the channel layer 21 , dangling bonds generated after the GaN channel layer 21 is broken can be prevented.

[0062] In the above implementation, a third via hole 11 and a fourth via hole 12 penetrating the substrate 10 may be provided on the surface of the substrate 10 so that the source pad 51 and the gate pad 53 provided on the substrate 10 can be connected to the corresponding electrodes through the via holes.

[0063] Alternatively, if Figure 2 As shown, the epitaxial wafer 20 also includes a p-type layer 23, which is located on the surface of the barrier layer 22 away from the channel layer 21, the source electrode 31 and the drain electrode 32 are arranged at intervals from the p-type layer 23, and the gate electrode 33 is located on the surface of the p-type layer 23 away from the barrier layer 22.

[0064] By forming the p-type layer 23 between the gate electrode 33 and the barrier layer 22 , the gate electrode 33 and the p-type layer 23 form a Schottky contact.

[0065] Exemplarily, the p-type layer 23 is a p-type GaN layer.

[0066] like Figure 1 , 2 As shown, in the active region 210 , the orthographic projection of the gate electrode 33 on the surface of the barrier layer 22 is located within the orthographic projection of the p-type layer 23 on the surface of the barrier layer 22 .

[0067] The gate electrode 33 in the active region 210 is completely in the p-type layer 23 , which can prevent the gate electrode 33 from crossing the peripheral edge of the p-type layer 23 and contacting the barrier layer 22 , thereby preventing the gate electrode 33 from being directly electrically connected to the barrier layer 22 or the channel layer 21 .

[0068] For example, Figure 3 As shown, the p-type layer 23 is in a strip shape and extends from the active area 210 to the inactive area 230 , which ensures that the gate electrode 33 always covers the p-type layer 23 in the inactive area 230 .

[0069] Alternatively, if Figure 1 As shown, the first portion of the source electrode 31 is in a strip shape, the second portion of the source electrode 31 is in a block shape, and one end of the first portion of the source electrode 31 is connected to the second portion of the source electrode 31. The second through hole 222 is in a strip shape, and the orthographic projection of the second through hole 222 on the surface of the barrier layer 22 is located within the orthographic projection of the first portion of the source electrode 31 on the surface of the barrier layer 22.

[0070] The strip-shaped source electrode 31 is arranged in the active area 210, so that the current can pass through the strip-shaped source electrode 31 across the epitaxial wafer 20, making the current transmission more uniform. The block-shaped source electrode 31 is arranged in the inactive area 230, so that the area of ​​the source electrode 31 receiving current can be increased, which is convenient for current injection.

[0071] Alternatively, if Figure 1 As shown, the first portion of the gate electrode 33 is in a strip shape, the second portion of the gate electrode 33 is in a block shape, and one end of the first portion of the gate electrode 33 is connected to the second portion of the gate electrode 33 .

[0072] The strip-shaped gate electrode 33 is arranged in the active area 210, so that the current can pass through the strip-shaped gate electrode 33 across the epitaxial wafer 20, making the current transmission more uniform. The block-shaped gate electrode 33 is arranged in the inactive area 230, so that the area of ​​the gate electrode 33 receiving current is increased, which is convenient for current injection.

[0073] Alternatively, if Figure 1 As shown, the drain electrode 32 is in a strip shape, the first through hole 221 is in a strip shape, and the orthographic projection of the first through hole 221 on the surface of the barrier layer 22 is located within the orthographic projection of the first part of the drain electrode 32 on the surface of the barrier layer 22 .

[0074] A strip-shaped drain electrode 32 is disposed in the active region 210 , so that current can pass through the strip-shaped drain electrode 32 across the epitaxial wafer 20 , making current transmission more uniform.

[0075] Figure 4 1 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure. Figure 4 As shown, the preparation method comprises:

[0076] S11: forming an epitaxial wafer on a substrate.

[0077] Exemplarily, the substrate is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the transistor has good stability.

[0078] The epitaxial wafer includes a channel layer and a barrier layer stacked on a substrate in sequence, the barrier layer has a first through hole and a second through hole exposing the channel layer, the epitaxial wafer has an active area and an inactive area, the active area and the inactive area are insulated, and the inactive area has a first through hole and a second through hole penetrating the epitaxial wafer

[0079] S12: forming a drain electrode, a source electrode, and a gate electrode on a surface of the barrier layer away from the channel layer.

[0080] Among them, the drain electrode is located in the active area, the drain electrode is electrically connected to the channel layer through the first through hole, the first part of the source electrode is located in the active area, the second part of the source electrode is located in the invalid area, the first part of the source electrode is electrically connected to the channel layer through the second through hole, and the second part of the source electrode extends to the side of the channel layer away from the barrier layer through the first via hole.

[0081] In the transistor prepared by the preparation method, the drain electrode, source electrode and gate electrode are all arranged on the surface of the barrier layer away from the channel layer. Among them, the source electrode and the gate electrode both span the active area and the ineffective area of ​​the epitaxial wafer, the source electrode is located in the first part of the active area and is electrically connected to the channel layer through the second through hole, and the source electrode is located in the second part of the ineffective area and extends to the side of the channel layer away from the barrier layer through the first via hole, so that the drain electrode and the source electrode are distributed on opposite sides of the epitaxial wafer; at the same time, the gate electrode is located in the first part of the active area and is connected to the barrier layer, and the gate electrode is located in the second part of the ineffective area and the second via hole extends to the side of the channel layer away from the barrier layer, so that the drain electrode and the gate electrode are distributed on opposite sides of the epitaxial wafer. That is, the source electrode and the gate electrode are arranged on the side of the channel layer away from the barrier layer, and the drain electrode is arranged on the side of the barrier layer away from the channel layer, so as to form a transistor with a vertical structure.

[0082] At the same time, when the external power source energizes the source electrode and the gate electrode, the current will cross the channel layer from the ineffective area of ​​the active layer, so that the current injected from the source electrode or the gate electrode will not enter the channel layer on the side of the channel layer away from the barrier layer, but will enter the channel layer from the side of the channel layer close to the barrier layer through the source electrode or the gate electrode after crossing from the ineffective area to the active area. The drain electrode is located on the surface of the barrier layer away from the channel layer, and the drain electrode can be electrically connected to the channel layer through the first through hole, so that the current injected by the drain electrode can also enter the channel layer from the side of the channel layer close to the barrier layer. Since the source electrode and the drain electrode are injected from the same surface of the channel layer, rather than from the opposite sides of the channel layer, a high-concentration two-dimensional electron gas channel can be formed at the heterojunction interface of the channel layer and the barrier layer, allowing the transistor to take advantage of the two-dimensional electron gas channel. In this way, the transistor not only takes advantage of the two-dimensional electron gas channel, but also forms a transistor with a vertical structure to reduce the difficulty of transistor application.

[0083] The specific process of the method for preparing a transistor in the embodiment of the present disclosure may include the following steps:

[0084] In the first step, a GaN channel layer, an AlGaN barrier layer and a p-type layer are grown on a sapphire substrate using a MOCVD (Metal-organic Chemical Vapor Deposition) process to form an epitaxial wafer.

[0085] The p-type layer may be a p-type GaN layer.

[0086] In the second step, the p-type layer is removed through photolithography and etching processes except for the part below the gate electrode to expose the AlGaN barrier layer.

[0087] The third step is to deposit a TiW layer on the surface of the barrier layer of the epitaxial wafer, etch the TiW metal after photolithography, and retain the TiW layer on the surface of the p-type GaN layer to obtain a gate electrode.

[0088] Exemplarily, the thickness of the TiW layer may be 200 nm.

[0089] The fourth step is to locate the source electrode and drain electrode through photolithography, and use dry etching technology to etch the epitaxial wafer to remove the AlGaN barrier layer at the source electrode and drain electrode positions to form the first through hole and the second through hole. Both the first through hole and the second through hole completely penetrate the AlGaN barrier layer and leak out the GaN channel layer.

[0090] Step 5: After photolithography, the source electrode and drain electrode are deposited. The drain electrode covers the first through hole, and the source electrode covers the second through hole. After high-temperature annealing, the source electrode and the drain electrode form an ohmic contact with the epitaxial wafer. The gate electrode forms a Schottky contact with the P-type layer.

[0091] Step 6: Use ion implantation technology to implant N+ ions into the isolation channel region of the epitaxial wafer to isolate the active and inactive regions of the device.

[0092] In the seventh step, a dielectric layer is deposited, and a through hole is formed above the drain electrode to penetrate the dielectric layer and leak out of the surface of the drain electrode.

[0093] By way of example, the dielectric layer may be a silicon oxide layer.

[0094] In the eighth step, a bonding metal layer is evaporated on the surface of the dielectric layer, and the bonding metal layer is connected to the drain electrode through a via.

[0095] In the ninth step, the bonding metal layer is bonded to the conductive substrate.

[0096] Exemplarily, the conductive substrate may be a silicon substrate.

[0097] The tenth step is to thin the substrate to a desired thickness by grinding and thinning.

[0098] In the eleventh step, photolithography positioning is performed on the back side of the thinned substrate, and the third and fourth via holes of the substrate are etched in the invalid area of ​​the epitaxial wafer through etching technology, and the GaN channel layer and the AlGaN barrier layer are further etched to form a first via hole connected to the third via hole and a second via hole connected to the fourth via hole.

[0099] Step 12: Make gate solder joints and source solder joints on the back of the substrate through an evaporation process. The gate solder joints are connected to the gate electrode through the fourth via hole and the second via hole in sequence. The source solder joints are connected to the source electrode through the third via hole and the first via hole in sequence.

[0100] Step 13: Thinning the conductive substrate.

[0101] In the fourteenth step, metal is deposited on the back side of the conductive substrate to form a drain solder joint.

[0102] In the fifteenth step, the surface can be grown with a medium through the PECVD (Plasma Enhanced Chemical Vapor Deposition) process to protect the device structure and balance the stress, so that the stress of the final transistor is equivalent to that of the epitaxial wafer.

[0103] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A transistor, characterized in that: The transistor comprises: an epitaxial wafer (20), a source electrode (31), a drain electrode (32), and a gate electrode (33); The epitaxial wafer (20) comprises a channel layer (21) and a barrier layer (22) stacked in sequence, the epitaxial wafer (20) has an active region (210) and an inactive region (230), the active region (210) and the inactive region (230) are insulated, and the inactive region (230) has a first via hole (201) and a second via hole (202) penetrating the epitaxial wafer (20); The drain electrode (32) is located on a surface of the barrier layer (22) away from the channel layer (21), and the drain electrode (32) is located in the active area (210); the barrier layer (22) has a first through hole (221) exposing the channel layer (21); and the drain electrode (32) is electrically connected to the channel layer (21) through the first through hole (221); The source electrode (31) and the gate electrode (33) are both located on a surface of the barrier layer (22) away from the channel layer (21); a first portion of the source electrode (31) is located in the active region (210), and a second portion of the source electrode (31) is located in the inactive region (230); the barrier layer (22) further comprises a second through hole (222) exposing the channel layer (21); a first portion of the source electrode (31) is electrically connected to the channel layer (21) through the second through hole (222); and a second portion of the source electrode (31) extends through the first through hole (201) to a side of the channel layer (21) away from the barrier layer (22); A first portion of the gate electrode (33) is located in the active region (210), a second portion of the gate electrode (33) is located in the inactive region (230), the first portion of the gate electrode (33) is connected to the barrier layer (22), and the second portion of the gate electrode (33) extends through the second via hole (202) to a side of the channel layer (21) away from the barrier layer (22).

2. The transistor according to claim 1, characterized in that The epitaxial wafer (20) also has an isolation channel region (220), the isolation channel region (220) surrounds the active region (210), and the isolation channel region (220) is located between the active region (210) and the ineffective region (230).

3. The transistor according to claim 2, characterized in that The isolation channel region (220) is implanted with N+ ions.

4. The transistor according to any one of claims 1 to 3, characterized in that: The transistor further comprises a dielectric layer (40) and a drain solder joint (52); the dielectric layer (40) is located on a surface of the barrier layer (22) away from the channel layer (21), and the dielectric layer (40) covers the drain electrode (32), the source electrode (31) and the gate electrode (33); the surface of the dielectric layer (40) away from the barrier layer (22) has a through hole exposing the drain electrode (32); and the drain solder joint (52) is electrically connected to the drain electrode (32) through the through hole.

5. The transistor according to claim 4, characterized in that The transistor further comprises a bonding metal layer (61) and a conductive substrate (62); the bonding metal layer (61) is located on a surface of the dielectric layer (40) away from the barrier layer (22) and is electrically connected to the drain electrode (32) via a through hole; the conductive substrate (62) is located on a surface of the bonding metal layer (61) away from the dielectric layer (40); and the drain electrode solder joint (52) is located on a surface of the conductive substrate (62) away from the dielectric layer (40).

6. The transistor according to any one of claims 1 to 3, characterized in that: The transistor further comprises a substrate (10), a source solder joint (51) and a gate solder joint (53); the substrate (10) is located on a surface of the channel layer (21) away from the barrier layer (22); the surface of the substrate (10) has a third via hole (11) and a fourth via hole (12) exposing the ineffective area (230); The source electrode solder joint (51) and the gate electrode solder joint (53) are both located on a surface of the substrate (10) away from the channel layer (21); the source electrode solder joint (51) is connected to the source electrode (31) through the third via hole (11) and the first via hole (201) in sequence; and the gate electrode solder joint (53) is connected to the gate electrode (33) through the fourth via hole (12) and the second via hole (202) in sequence.

7. The transistor according to any one of claims 1 to 3, characterized in that: The epitaxial wafer (20) further comprises a p-type layer (23), the p-type layer (23) being located on a surface of the barrier layer (22) away from the channel layer (21), the source electrode (31) and the drain electrode (32) being arranged at intervals from the p-type layer (23), and the gate electrode (33) being located on a surface of the p-type layer (23) away from the barrier layer (22); In the active region (210), an orthographic projection of the gate electrode (33) on the surface of the barrier layer (22) is located within an orthographic projection of the p-type layer (23) on the surface of the barrier layer (22).

8. The transistor according to any one of claims 1 to 3, characterized in that: The first part of the source electrode (31) is in a strip shape, the second part of the source electrode (31) is in a block shape, and one end of the first part of the source electrode (31) is connected to the second part of the source electrode (31); The second through hole (222) is in a strip shape, and an orthographic projection of the second through hole (222) on the surface of the barrier layer (22) is located within an orthographic projection of the first part of the source electrode (31) on the surface of the barrier layer (22); The first part of the gate electrode (33) is in a strip shape, the second part of the gate electrode (33) is in a block shape, and one end of the first part of the gate electrode (33) is connected to the second part of the gate electrode (33).

9. The transistor according to any one of claims 1 to 3, characterized in that: The drain electrode (32) is in a strip shape, the first through hole (221) is in a strip shape, and the orthographic projection of the first through hole (221) on the surface of the barrier layer (22) is located within the orthographic projection of the first part of the drain electrode (32) on the surface of the barrier layer (22).

10. A method for preparing a transistor, characterized in that: The preparation method comprises: An epitaxial wafer is formed on a substrate, wherein the epitaxial wafer comprises a channel layer and a barrier layer sequentially stacked on the substrate, wherein the barrier layer has a first through hole and a second through hole exposing the channel layer, wherein the epitaxial wafer has an active region and an inactive region, wherein the active region and the inactive region are insulated, and wherein the inactive region has a first through hole and a second through hole penetrating the epitaxial wafer; A drain electrode, a source electrode and a gate electrode are formed on a surface of the barrier layer away from the channel layer, the drain electrode is located in the active area, the drain electrode is electrically connected to the channel layer through the first through hole, a first part of the source electrode is located in the active area, a second part of the source electrode is located in the inactive area, the first part of the source electrode is electrically connected to the channel layer through the second through hole, and the second part of the source electrode extends to a side of the channel layer away from the barrier layer through the first via hole.

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