Method for reducing gate voltage burrs of silicon carbide MOSFET

Abstract

Aspects of the present disclosure relate to a circuit for providing an off-state circuit path having a programmable impedance and a negative gate-source voltage Vgs for a power transistor in an inverter configuration to prevent gate voltage glitches and a method of operation thereof. During a fast voltage transient dV / dt when another complementary power transistor is turned on or off, a gate voltage burr may occur due to generation of a Miller current across a gate path of a power transistor in an off state. According to one aspect, using a negative gate-source voltage to turn off a power transistor may mitigate a gate voltage spike caused by large voltage transients when a complementary power transistor is turned on, thereby preventing parasitic turn-on of the power transistor. According to another aspect, an off-state circuit path having a programmable impedance is provided that is controllably in a low-impedance state prior to a complementary power transistor being turned on such that the low-impedance off-state circuit path prevents gate voltage spurs of the power transistor.

Description

Technical Field

[0001] The present application generally relates to a test equipment for a power transistor, and more particularly to a driving circuit for a power transistor as a device under test. Background Art

[0002] Electronic components such as semiconductor devices, circuits, and printed circuit board (PCB) assemblies are frequently tested during and after their manufacture using test systems such as automated test equipment (ATE). Testing allows defective devices to be removed from manufacturing batches, further eliminating unnecessary processing and packaging. In addition, test results can be used to identify faulty manufacturing equipment, thereby increasing device yield. Test results can also allow binning of devices with different performance and operating specifications due to process variations. To perform these tests, ATE (also known as a tester) may include instruments that generate input signals to a specific device under test (DUT) and / or measure output signals from the device under test, so that a range of operating conditions can be tested on the DUT.

[0003] The DUT may include one or more power semiconductor devices. A power semiconductor device may also be referred to as a power device, a power transistor, or a power switch. Examples of power transistors include power metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs). To test a DUT having power transistors, the tester may include a driver circuit or a control circuit for controlling the power transistors.

[0004] Power transistors are sometimes used to switch current supplied to a load such as an industrial motor drive on and off. During operation, the power transistor may be switched on in response to a gate voltage applied by a control circuit at a gate terminal of the power transistor. In the on state, the power transistor has a low resistance between the collector terminal (or drain terminal) and the emitter terminal (or source terminal), and current may flow through the power transistor. In the off state, the power transistor has a high resistance, and little current may flow through the power transistor.

[0005] In an inverter configuration, power transistors are typically used in pairs, with an upper transistor and a lower transistor connected in series between a supply voltage and a reference voltage, and an output node between the two power transistors. In typical operation, the upper transistor and the lower transistor are typically turned on and off in a complementary manner, with one of the upper transistor / lower transistor being driven to turn on and the other of the upper / lower transistor being driven to turn off. A known problem associated with such operation using power transistors in an inverter topology is the gate voltage glitch phenomenon, sometimes also referred to as the parasitic turn-on phenomenon. The gate voltage glitch is caused by the Miller current generation across the gate path impedance of the first power transistor in the off state during a rapid change in the drain (or collector) to gate voltage transient dV / dt, which may be caused by the turn-on of the second complementary power transistor. The voltage drop from the Miller current can cause a gate voltage spike at the power transistor in the off state, which can sometimes cause the transistor to accidentally turn on, creating an undesirable breakdown condition in the power transistor, which in some cases can damage the power transistor and / or related equipment. Gate voltage glitches may also occur during negative dV / dt when the second complementary power transistor is turned off. For example, when the complementary power transistor is turned off, a negative gate voltage spike may occur in the first power transistor as a result of the Miller current generation. It is desirable to avoid excessive negative gate voltage spikes to prevent gate oxide damage of the complementary power transistor. Summary of the invention

[0006] Various aspects of the present disclosure relate to a circuit and method of operating the same for providing an off-state circuit path with a programmable impedance and a negative gate-source voltage Vgs for a power transistor in an inverter configuration to prevent gate voltage glitches. Gate voltage glitches may occur during fast voltage transients dV / dt when another complementary power transistor is turned on or off due to the generation of Miller current across the gate path of the power transistor in the off state. According to one aspect, using a negative gate-source voltage to turn off a power transistor can mitigate gate voltage spikes caused by large voltage transients when the complementary power transistor is turned on, thereby preventing parasitic turn-on of the power transistor. According to another aspect, an off-state circuit path with programmable impedance is provided, which is controllably in a low impedance state before the complementary power transistor is turned on, so that the low impedance off-state circuit path prevents gate voltage glitches of the power transistor.

[0007] Some embodiments relate to an automated test equipment (ATE) for testing a device under test (DUT). The DUT includes a first transistor having a gate terminal and a source terminal. The ATE includes a first control circuit configured to drive the first transistor; a second control circuit configured to drive a second transistor having a gate terminal and a source terminal, the second transistor being coupled to the first transistor in an inverter configuration. Each control circuit includes: a gate line configured to be connected to a gate terminal of a corresponding transistor; a source line configured to be connected to a source terminal of a corresponding transistor; a first circuit path and a second circuit path, the first circuit path and the second circuit path being connected in parallel between the gate line and the source line. The first circuit path is configured to switchably bias the gate line with a positive voltage relative to the source line, the second circuit path is configured to switchably bias the gate line with a negative voltage relative to the source line, and includes a programmable resistor.

[0008] Some embodiments relate to a method for driving a first power transistor and a second power transistor coupled in an inverter configuration using a first control circuit and a second control circuit. Each control circuit includes a first circuit path and a second circuit path connected in parallel. The method includes driving the first power transistor with the first control circuit by the following steps: using the first circuit path, the gate terminal of the first power transistor is switchably coupled to a first power supply having a positive voltage relative to the source terminal of the first power transistor; using the second circuit path, the gate terminal of the first power transistor is switchably coupled to a second power supply having a negative voltage relative to the source terminal of the first power transistor via a first programmable resistor; and driving the second power transistor with the second control circuit by the following steps: using the first circuit path, the gate terminal of the second power transistor is switchably coupled to a third power supply having a positive voltage relative to the source terminal of the second power transistor; using the second circuit path, the gate terminal of the second power transistor is switchably coupled to a fourth power supply having a negative voltage relative to the source terminal of the second power transistor via a second programmable resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various aspects and embodiments will be described in conjunction with the following drawings. It should be understood that the drawings are not necessarily drawn to scale. In the drawings, each identical or nearly identical component shown in different figures is represented by the same reference numeral. For clarity, not every component in each drawing is labeled.

[0010] Figure 1 is a schematic diagram illustrating a circuit for testing a DUT including a power transistor, according to some embodiments.

[0011] Figure 2is a diagram showing a method for operating a Figure 1 A schematic timing diagram of an exemplary timing sequence for the circuit shown.

[0012] Figure 3 is a schematic diagram of an exemplary embodiment of an automatic test system in which circuits according to aspects of the present application may be applied.

[0013] Figure 4 According to some embodiments, a device interface board is used Figure 3 Schematic diagram of a variation of the automated test system in . DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to a circuit and method of operating the same for providing an off-state circuit path with programmable impedance and negative gate-source voltage Vgs for a power transistor in an inverter configuration to prevent gate voltage glitches.

[0015] The inventors have recognized and appreciated that using a negative gate-source voltage to turn off a power transistor can mitigate gate voltage spikes caused by large voltage transients when a complementary power transistor is turned on, thereby preventing parasitic turn-on of the power transistor. In some embodiments, the power transistor is configured to turn on and off a large amount of load current, such as greater than 40 A, and the negative gate-source voltage can be sufficient to prevent parasitic turn-on caused by large perturbations in the gate voltage of the power transistor.

[0016] The inventor further recognizes that even in the case of a negative gate-source voltage, the finite impedance of the circuit path from the gate terminal of the off-state power transistor to the reference voltage may still cause a large voltage drop due to the Miller current during the voltage transient at the complementary power transistor. To solve this problem, in some embodiments, an off-state circuit path with programmable impedance is provided. The off-state circuit path may include a controllable switch to bias the gate terminal of the power transistor with a negative gate-source voltage via a programmable resistor. Before the complementary power transistor is turned on, the programmable resistor may be controlled to be in a low impedance state so that the low impedance off-state circuit path prevents the gate voltage burr of the power transistor. In one example, the low impedance state has a resistance close to zero, such as less than 0.1 ohms. When the power transistor is no longer in the off state, the programmable resistor in the off-state circuit path may be controlled to be in a high impedance state to meet other operating requirements of the power transistor during the on state or the transition from the on state to the off state.

[0017] In some embodiments, an on-state circuit path is also provided for the power transistor. The on-state circuit path is connected in parallel with the off-state circuit path and includes a switch that is controllable to bias the gate terminal of the power transistor with a positive gate-source voltage during an on-cycle of the power transistor.

[0018] The on-state circuit path and the off-state circuit path may be part of a control circuit for driving a power transistor. For a pair of power transistors in an inverter configuration, a circuit having two such control circuits may be provided to drive the respective upper and lower transistors. Each of the two control circuits may include the same on-state circuit path and off-state circuit path as disclosed herein, so that during voltage transients at the complementary switches, each of the upper / lower transistors is prevented from experiencing gate voltage glitches.

[0019] The components in the two control circuits may be implemented in any suitable manner, such as integrated on a semiconductor chip, or by discrete components, or a combination thereof. In some embodiments, a controller may be provided to generate control signals for switches and programmable resistors in the control circuits based on a timing pattern to prevent gate voltage glitches in the driven power transistor.

[0020] Some aspects relate to an ATE that uses an inverter configuration to test a DUT that includes a power transistor. For example, the DUT may include a pair of power transistors, both of which may be connected to the ATE in the inverter configuration for testing. In another example, the DUT may be a single-transistor device that includes only one power transistor. In such an example, the single-transistor DUT may be connected in combination with an auxiliary transistor in the inverter configuration. For example, the DUT may be connected as an upper transistor, and the auxiliary transistor may be connected as a lower transistor. In some embodiments, the ATE includes a first control circuit and a second control circuit as described above to drive the upper transistor and the lower transistor, respectively, so that gate voltage glitches in the two transistors can be prevented.

[0021] The above aspects and embodiments, as well as additional aspects and embodiments, are further described below. These aspects and / or embodiments may be used alone, together or in any combination of two or more, as this patent application is not limited in this regard.

[0022] Figure 1 is a schematic diagram illustrating a circuit 10 for testing a DUT 20 including a power transistor, according to some embodiments.

[0023] like Figure 1As shown, the upper power transistor Q1_upp and the lower transistor Q1_low are connected in an inverter configuration, and the sources Q1_upp and Q1_low are connected in series between the power supply voltage +Udc and the reference voltage GND. Specifically, the circuit 10 has a power supply terminal 12 that can be connected to the drain terminal of Q1_upp, and a ground terminal 14 that can be connected to the source terminal of Q1_low. The source terminal of Q1_upp is connected together with the drain terminal of Q1_low at node A as an output.

[0024] It should be understood that the DUT 20 may include only the upper transistor Q1_upp, only the lower transistor Q1_low, or both Q1_upp and Q1_low, as aspects of the present invention are not so limited. For example, the circuit 10 may be used to test a single power device DUT as the upper transistor position Q1_upp, while the auxiliary transistor may be connected as Q1_low for testing of Q1_upp. Similarly, the same circuit 10 may be used to test a single power device DUT in the Q1_low position, with the auxiliary transistor connected as Q1_upp. In other examples, the circuit 10 may be used to test a DUT having two or more power transistors by connecting the corresponding power transistors in the DUT as Q1_upp and Q1_low, respectively.

[0025] Q1_low and Q1_high can be configured in an inverter geometry, such as a phase leg, and are continuously turned on and off. Q1_low and Q1_high can be MOSFETs or IGBTs, as aspects of circuit 10 are not limited thereto. In one example, Q1_low and Q1_high can be SiC MOSFETs. It should be understood that the collector terminal / emitter terminal of the IGBT can be connected to the circuit 10 in a manner similar to the drain terminal / source terminal of the MOSFET. For example, the terminal of the circuit 10 for driving the drain of the MOSFET can also be used to drive the collector terminal of the IGBT instead of the MOSFET, and the terminal of the circuit 10 for driving the source of the MOSFET can also be used to drive the emitter terminal of the IGBT instead of the MOSFET.

[0026] The circuit 10 has an upper control circuit 100 for driving an upper transistor Q1_upp, and a lower control circuit 200 for driving a lower transistor Q1_low. The upper control circuit 100 has a gate line Ug_upp that can be connected to the gate terminal of Q1_upp, and a source line Us_upp that can be connected to the source terminal of Q1_upp. The lower control circuit 200 has a gate line Ug_low that can be connected to the gate terminal of Q1_low, and a source line Us_low that can be connected to the source terminal of Q1_low. As described in the previous paragraph, the term "source line" used herein is not meant to be limited to applications involving only MOSFETs.

[0027] The upper control circuit 100 can use an on-state circuit path 110 and an off-state circuit path 120 connected in parallel between the gate line Ug_upp and the source line Us_upp to provide a dual voltage power supply to control Q1_upp. The on-state circuit path 110 has a power supply 112, which can bias Ug_upp with a positive Vgs voltage UGS_upp relative to Us_upp via a switch S_on_upp and an impedance Rg_on_upp. The off-state circuit path 120 has a power supply 122, which can bias Ug_upp with a negative Vgs voltage -UGS_upp relative to Us_upp via a switch S_off_upp and a programmable resistor Rg_off_upp.

[0028] Still reference Figure 1 , the lower control circuit 200 is similar to the upper control circuit 100 and has an on-state circuit path 210 and an off-state circuit path 220 connected in parallel between the gate line Ug_low and the source line Us_low. The on-state circuit path 210 has a power supply 212, which can bias Ug_low with a positive Vgs voltage UGS_low relative to Us_low via a switch S_on_low and an impedance Rg_on_low. The off-state circuit path 220 has a power supply 222, which can bias Ug_low with a negative Vgs voltage -UGS_low relative to Us_low via a switch S_off_low and a programmable resistor Rg_off_low.

[0029] In the upper control circuit 100, switches S_on_upp and S_off_upp are controlled by the pattern of control signals from a controller (not shown) to connect the gate terminal of Q1_upp to the positive voltage source 112 or the negative voltage source 122, thereby controlling the turning on of Q1_upp. Switches S_on_low and S_off_low in the lower control circuit 200 operate in a similar manner with respect to Q1_low.

[0030] Turning to the lower control circuit 200, when Q1_low is in the off state from being connected to the negative power supply 222 via the off state circuit path 220, turning on Q1_upp can result in a large positive dV / dt transient across the drain / source terminals of Q1_upp, which can result in a voltage spike at the gate terminal of Q1_low due to the Miller current. Due to the negative voltage -UGS_low at its gate terminal, the parasitic turn-on of Q1_low can be prevented. In some embodiments, -UGS_low can be between -10 V and 0 V, between -8 V and -1 V, -5 V, or any suitable voltage value that can be selected based on the threshold voltage of Q1_low to provide protection against parasitic turn-on due to gate voltage glitches.

[0031] Still when Q1_low is in the off state, turning off Q1_upp may result in a large negative dV / dt transient across the drain / source terminals of Q1_upp, which may result in a negative voltage spike at the gate terminal of Q1_low due to the Miller current. The programmable resistance Rg_off_low may be controlled to be in a low impedance state so that the voltage drop from the Miller current from Ug_low to Us_low may be minimized and excessive Vgs in Q1_low may be prevented during the shutdown of Q1_upp. In some embodiments, the low impedance state of Rg_off_low may be approximately zero, such as less than 0.1 ohms. When Q1_low is no longer in the off state, Rg_off_low may be controlled to be in a high impedance state to meet the operating requirements of Q1_low during the on state and / or transition from the on state to the off state. In some embodiments, the high impedance state can be between 0.1 ohms and 10 ohms, between 1 ohm and 8 ohms, 5 ohms, or any suitable resistance value for operating Q1_low. For example, the high impedance state resistance can be selected so that Q1_low has a desired dynamic behavior during on or off. The programmable resistor Rg_off_low can be implemented in any suitable manner now known or developed in the future to provide at least two settable resistance values, and a control signal from a controller can be provided to change Rg_off_low between a low impedance state and a high impedance state, or any other suitable resistance value.

[0032] Still focusing on the lower control circuit 200, the on-state circuit path 210 has a resistance Rg_on_low that provides a resistance between 0.1 ohms and 10 ohms, between 1 ohm and 8 ohms, such as 5 ohms. For example, Rg_on_low may be selected so that Q1_low has a desired dynamic behavior during on or off.

[0033] In the upper control circuit 100, the switches S_off_upp, S_on_upp, and the programmable resistor Rg_off_upp may operate in a similar manner to their counterparts in the lower control circuit 200 as described above.

[0034] One aspect of the present disclosure relates to the timing of operating switches and programmable resistors in circuit 10 . Figure 2 is a diagram showing a method for operating a Figure 1 A schematic timing diagram of an exemplary timing sequence of circuit 10 is shown.

[0035] exist Figure 2 In FIG. 1 , during a time period between t0 and t10 , the upper transistor Q1_upp is turned on and then turned off, and the lower transistor Q1_low is turned on and then turned off during a time period between t10 and t20 .

[0036] At time t1, Rg_off_upp and Rg_off_low are set to specific states. As shown, Rg_off_upp is set to a high impedance state, while Rg_off_low is set to a low impedance state. It should be understood that the exact timing of t1 is not important, nor is it required that Rg_off_upp and Rg_off_low be set at the same time, as long as their states are both before time t2.

[0037] At time t2, S_off_upp opens, and after a certain waiting time, S_on_upp closes at time t3, causing the gate-source voltage upper limit to increase and approach +UGS_upp at time t4. Thus, Q1_upp is turned on to a conducting state.

[0038] Around time t4, the voltage (A) at the output node A starts to increase until it reaches +Udc at time t5. This positive voltage transient dV / dt between time t4 and t5 causes a Miller current to flow and affects the gate-source voltage of Q1_low. The Miller current is caused by the Miller capacitance at the gate of Q1_low and the voltage transient at node A when Q1_upp is turned on. The Miller current is directed through Rg_off_low to the lower control circuit 200, which has been set to a low impedance state with a very low voltage drop before time t2. Therefore, the gate voltage glitch phenomenon in Q1_low during the turn-on of Q1_upp is prevented.

[0039] At time t6, S_on_upp turns off, causing the gate-source voltage on Q1_upp to decrease at time t7, and Q1_upp transitions from an on state to an off or blocking state at time t8. Figure 3As shown in the last trace in Figure 1, during this transition and around time t7, the voltage at the output node A (A) starts to decrease until it reaches 0 V at time t8. This negative voltage transient dV / dt causes the Miller current at the gate of Q1_off to flow in the opposite direction compared to the period between t4 and t5 when Q1_upp is turned on. Since Rg_off_low has a low resistance at this time, the gate voltage glitch phenomenon in Q1_low is prevented.

[0040] From time t10 to t20 , circuit 10 operates in a similar manner, but Q1_low is switched to an on state and the gate voltage glitch phenomenon in Q1_upp is mitigated due to the Miller current generated at the gate of Q1_upp.

[0041] It should be understood that Figure 2 The timing shown in is merely one example of how to operate circuit 10 to test a DUT containing a power transistor, and aspects of the present disclosure are not limited thereto. As a variation, although Figure 2 The lower transistor Q1_low is shown to be turned on during the time period t10 to t20, but the sequence from t10 to t20 is optional because Q1_low is not required to be turned on when only Q1_upp is tested. In some embodiments, Q1_low can be a passive auxiliary transistor for testing the power transistor connected as Q1_upp. In such embodiments, the gate terminal of Q1_off can be connected to a constant negative gate voltage -UGS_low while effectively turning the upper transistor on and off using the first control circuit 100. As another variation, in some embodiments, the test sequence can alternatively be used to test a power transistor connected only as Q1_low instead of Q1_upp. In such embodiments, a passive auxiliary transistor can be connected as Q1_upp.

[0042] Figure 3 is a schematic diagram of an exemplary embodiment of an automatic test system in which circuits according to aspects of the present application may be applied. Figure 3 A test system 50 is shown that includes a test computer 52 that controls a tester 56 to perform tests on a device under test (DUT) 20 according to the methods disclosed in the present application. In some cases, the tester 56 can be an automated test equipment (ATE) constructed using techniques known in the art. The DUT 20 can be any suitable device for testing. The DUT 20 can be a semiconductor device, and in some embodiments can include one or more power transistors.

[0043] exist Figure 3In the embodiment of the present invention, the ATE 56 may include circuits that generate and / or measure a plurality of test signals 54 for the DUT 20. For example, the ATE 56 may include circuits 10 configured to generate and drive one or more power transistors in the DUT 20. The ATE 56 may additionally include a controller 62 having one or more timing generators and / or pulse generators configured to synchronize the generation of a plurality of control signals 64 to control the timing of switches and programmable resistors in the circuit 10. In some embodiments, the controller may include a software controlled pulse generator, but any suitable pulse generator may be used.

[0044] It should be understood that Figure 3 is a greatly simplified representation of an automated test system. For example, although not shown, the test system 50 may include control circuitry to control the operation of instruments within the ATE 56. Additionally, the test system 50 may include processing circuitry to process the measurement results and determine whether the DUT 20 is operating properly. Furthermore, although Figure 3 A scenario is shown where a single DUT 20 is being tested, but the test system 50 can be configured to test multiple devices. Regardless of the number of instruments or other components that generate or measure test signals and the number of devices under test, the test system 10 can include a signal delivery component that routes signals between the DUT 20 and the instruments within the ATE 56.

[0045] In addition, it should be understood that the other components shown in the figure are exemplary and not limiting. For example, although the test computer 52 is Figure 3 5. The test computer 52 is shown as a personal computer (PC) in the figure, but it should be understood that any suitable computing device can be used to implement the test computer, such as a mobile device or a computer workstation. The test computer 52 can be connected to a network and can access resources through the network and / or communicate with one or more other computers connected to the network.

[0046] Figure 4 According to some embodiments, a device interface board is used Figure 3 Schematic diagram of a variant of the automated test system in FIG. Figure 4As shown, the ATE 56 is connected to a device interface board (DIB) 430, and the DIB 430 is connected to a DUT 420 having a plurality of power transistors to route a signal 454 from the ATE 56 as a test signal 456 to a selected power transistor on the DUT 420. The DIB 430 includes a plurality of contact points for connecting to respective gate terminals and source terminals of the power transistors in the DUT 420, and routing circuitry for connecting to gate lines and source lines in the circuit 10 of the ATE 56. The routing circuitry in the DIB 430 is configured to interconnect the gate lines and source lines of the control circuitry in the circuit 10 to the respective contact points, such that the gate lines in the control circuitry are connected to respective gate terminals of the transistors in the DUT, and the source lines in the control circuitry are connected to respective source terminals of the transistors in the DUT. The routing circuitry may be implemented in any suitable manner, and may include a multiplexer.

[0047] Having described several aspects of at least one embodiment of the present invention, it should be appreciated that various alterations, modifications, and improvements may be readily made by those skilled in the art.

[0048] Such changes, modifications and improvements are intended to be part of this disclosure and are considered to fall within the spirit and scope of the present invention. In addition, although the advantages of the present invention are indicated, it should be understood that not every embodiment of the technology described herein will include each of the advantages. Some embodiments may not implement any of the features advantageously described herein, and in some cases, one or more of the features may be implemented to implement additional embodiments. Therefore, the above description and drawings are only by way of example.

[0049] Various aspects of the present invention may be used individually, in combination or in various configurations not specifically discussed in the above embodiments, and therefore their application is not limited to the details and configurations of the components described in the above description or shown in the accompanying drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

[0050] In addition, the present invention can be implemented as a method, and examples thereof have been provided. The operations performed as part of the method can be ordered in any suitable manner. Therefore, embodiments can be constructed that perform operations in a different order than shown, which can include performing certain operations simultaneously, even though these operations are shown as sequential operations in each exemplary embodiment.

[0051] Such changes, modifications and improvements are intended to be part of this disclosure and are considered to fall within the spirit and scope of the present invention. In addition, although the advantages of the present invention are indicated, it should be understood that not every embodiment of the present invention will include each of the advantages. Some embodiments may not implement any of the features described herein and in some cases that are advantageous. Therefore, the above description and accompanying drawings are only used as examples.

[0052] The use of ordinal terms such as "first", "second", "third" and the like in the claims to modify claim elements does not in itself imply any priority, precedence or sequence of one claim element over another or a temporal order of performing method operations, but is merely used as a label to distinguish one claim element with a certain name from another element with the same name (except for the ordinal term used) to identify the claim elements.

[0053] In addition, the phrases and terms used herein are for illustrative purposes and should not be considered as limiting. "Including," "comprising," or "having," "containing," "involving," and variations thereof used herein are meant to include the items listed thereafter and their equivalents as well as additional items.

Claims

1. An automated test equipment (ATE) for testing a device under test (DUT), the DUT comprising a first transistor having a gate terminal and a source terminal, the ATE comprising: a first control circuit configured to drive the first transistor; a second control circuit configured to drive a second transistor, the second transistor having a gate terminal and a source terminal, the second transistor being coupled to the first transistor in an inverter configuration, each control circuit comprising: a gate line configured to be connected to the gate terminal of a corresponding transistor; a source line configured to be connected to the source terminal of a corresponding transistor; a first circuit path and a second circuit path, wherein the first circuit path and the second circuit path are connected in parallel between the gate line and the source line, wherein the first circuit path being configured to switchably bias the gate line with a positive voltage relative to the source line, The second circuit path is configured to switchably bias the gate line with a negative voltage relative to the source line and includes a programmable resistance.

2. The ATE of claim 1, wherein the DUT comprises the second transistor.

3. The ATE of claim 1 , wherein in each of the first control circuit and the second control circuit: The first circuit path includes a first power source coupled to the source line via a first switch, and The second circuit path includes a second power source coupled to the source line via a second switch.

4. The ATE according to claim 3, wherein The second switch in the second circuit path of the first control circuit is configured to switch from a closed state to an open state at a first moment, and The programmable resistance in the second circuit path of the second control circuit is configured to change from a high impedance state to a low impedance state before the first time.

5. The ATE of claim 4, wherein The first switch in the first circuit path of the first control circuit is configured to close at a second time after the first time to bias the gate line in the first control circuit.

6. The ATE of claim 4, wherein The second switch in the second circuit path of the second control circuit is configured to close before the first time.

7. The ATE of claim 4, wherein The programmable resistance in the second circuit path of the first control circuit is configured to change from a low impedance state to a high impedance state before the first time.

8. The ATE of claim 5, wherein The first switch in the first circuit path of the first control circuit is configured to be opened at a third time after the second time, and The second switch in the second circuit path of the first control circuit is configured to switch from an open state to a closed state at a fourth time after the third time.

9. The ATE of claim 8, wherein The programmable resistor in the second circuit path of the second control circuit is configured to change from the low impedance state to the high impedance state after the fourth time instant, and The programmable resistance in the second circuit path of the first control circuit is configured to change from a high impedance state to a low impedance state after the fourth time.

10. The ATE of claim 1, wherein The first transistor in the DUT is an insulated gate bipolar transistor (IGBT), and the source terminal of the first transistor is an emitter terminal of the IGBT.

11. The ATE of claim 1, wherein The first transistor in the DUT is a metal oxide semiconductor field effect transistor (MOSFET).

12. The ATE of claim 1, wherein The programmable resistor has a resistance programmable from about 0 ohms to about 10 ohms.

13. The ATE of claim 12, wherein The programmable resistor has a high impedance state with a resistance between 1 ohm and 10 ohms, and a low impedance state with a resistance less than 0.1 ohms.

14. The ATE of claim 1, further comprising a controller operable to control timing of switches and the programmable resistors in the first and second circuit paths of the first and second control circuits.

15. The ATE of claim 1 , wherein the DUT comprises a plurality of transistors, and the ATE further comprises: Device Interface Board (DIB), the DIB comprising: a plurality of contacts configured to couple to the gate terminal and the source terminal of the transistor in the DUT, and a routing circuit coupled to the gate lines and the source lines in the first control circuit and the second control circuit and configured to interconnect the gate lines and the source lines to respective contacts such that the gate lines in the first control circuit and the second control circuit are connected to respective gate terminals of the transistor in the DUT and the source lines in the first control circuit and the second control circuit are connected to respective source terminals of the transistor in the DUT.

16. A method for driving first and second power transistors coupled in an inverter configuration using first and second control circuits, each control circuit comprising a first circuit path and a second circuit path connected in parallel, the method comprising: The first power transistor is driven by the first control circuit by the following steps: switchably coupling a gate terminal of the first power transistor to a first power supply having a positive voltage relative to a source terminal of the first power transistor using the first circuit path; switchably coupling the gate terminal of the first power transistor to a second power supply having a negative voltage via a first programmable resistor relative to the source terminal of the first power transistor using the second circuit path; as well as The second power transistor is driven by the second control circuit by the following steps: switchably coupling a gate terminal of the second power transistor relative to a source terminal of the second power transistor to a third power supply having a positive voltage using the first circuit path; The gate terminal of the second power transistor is switchably coupled to a fourth power supply having a negative voltage via a second programmable resistor relative to the source terminal of the second power transistor using the second circuit path.

17. The method according to claim 16, wherein driving the first power transistor comprises switchably coupling the gate terminal of the first power transistor to the second power supply at a first moment, and Driving the second power transistor includes changing the second programmable resistor from a high impedance state to a low impedance state before the first time.

18. The method of claim 17, wherein driving the first power transistor further comprises: A first switch in the first circuit path of the first control circuit is closed at a second time after the first time to bias the gate terminal of the first power transistor.

19. The method of claim 18, wherein driving the second power transistor further comprises: A second switch in the second circuit path of the second control circuit is closed before the first time.

20. The method of claim 17, wherein driving the first power transistor further comprises: Before the first time, the first programmable resistor in the second circuit path of the first control circuit is changed from a low impedance state to a high impedance state.

21. The method of claim 18, wherein driving the first power transistor further comprises: At a third time after the second time, the first switch in the first circuit path of the first control circuit is turned off, and At a fourth time after the third time, a second switch in the second circuit path of the first control circuit is closed to disconnect the second power source from the source terminal of the first power transistor.

22. The method of claim 21 , wherein driving the second power transistor further comprises: After the fourth time, changing the second programmable resistor in the second circuit path of the second control circuit from the low impedance state to the high impedance state, and Driving the first power transistor further includes: After the fourth time, the first programmable resistor in the second circuit path of the first control circuit is changed from a high impedance state to a low impedance state.

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