Semiconductor module and method for manufacturing the same
By adopting multi-layer overlapping configuration and electrical connection technology in semiconductor modules, the problem of difficulty in thinning is solved, and a thinner and cheaper semiconductor module design is achieved, which improves the electrical connection efficiency and manufacturing efficiency of the module.
Patent Information
- Application Number
- CN202280095341.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-18
- Publication Date
- 2025-01-17
AI Technical Summary
In the process of achieving large capacity and high speed, the thickness of existing semiconductor modules is difficult to further thin, resulting in increased chip area and noise vulnerability problems, limiting their further optimization.
By adopting a multi-layer overlapping configuration in a semiconductor module, the rewiring layer sandwiches the memory portion and the logic chip, and through the electrical connection between the column and the substrate, the thickness of the semiconductor module is thinned, and combined with the use of the molded portion Optimize the structure.
It realizes a thinner semiconductor module design, reduces manufacturing costs, and improves the thinness and electrical connection efficiency of the module, and has the characteristics of inexpensive and efficient manufacturing.
Smart Images
Figure CN119325642A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor module and a method for manufacturing the same. Background Art
[0002] In the past, volatile memories (RAM) such as DRAM (Dynamin Random Access Memory) were known as storage devices. DRAM is required to have a larger capacity to withstand the high performance of computing devices (hereinafter referred to as logic chips or logic wafers) and the increase in data volume. Therefore, the larger capacity is achieved by miniaturizing the memory (memory cell array, memory chip) and increasing the planar size of the cells. On the other hand, this larger capacity has reached its limit due to the vulnerability to noise caused by miniaturization and the increase in chip area.
[0003] Therefore, a technology has recently been developed to stack multiple planar memories to achieve three-dimensionalization (3D) and thus large capacity. In addition, as the amount of data increases, data communication between chips (logic chips and memory chips) is accelerated. For example, a semiconductor module in which a logic chip and a DRAM are stacked is known (for example, see non-patent document 1).
[0004] Prior art literature
[0005] Non-patent literature
[0006] Non-patent literature 1: Taiwan Semiconductor Manufacturing Company R&D, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC). Summary of the invention
[0007] Problem that the invention aims to solve
[0008] In the semiconductor module of Patent Document 1, SOC (System-on-a-chip) and LPDDR (Low Power DDR) are stacked in two layers. In addition, no bumps for flip chips are used for SOC. Thus, a thin semiconductor module is realized. Therefore, it is more preferable if the semiconductor module can be made thinner.
[0009] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor module capable of being reduced in thickness and a method for manufacturing the same.
[0010] Solutions for solving problems
[0011] The present invention relates to a method for manufacturing a semiconductor module, wherein the semiconductor module includes multiple chips, and the method for manufacturing the semiconductor module comprises: a first chip configuration step, configuring a first chip; a redistribution layer forming step, forming a redistribution layer configured on one side of the first chip and electrically connected to a second chip; a second chip configuration step, configuring the second chip at a position overlapping with the first chip in a facing direction on the other side of the redistribution layer opposite to the facing side of the first chip; a column forming step, forming a column extending from the other side of the redistribution layer; and a substrate configuration step, configuring a substrate electrically connected to the column and the second chip.
[0012] Furthermore, it is preferred that the first chip placement step is performed after the redistribution layer forming step, and the second chip placement step, the pillar forming step, and the substrate placement step are performed after the first chip placement step.
[0013] Furthermore, it is preferred that the second chip placement step and the pillar formation step are performed after the substrate placement step, and the redistribution layer formation step and the first chip placement step are performed after the second chip placement step and the pillar formation step.
[0014] Furthermore, it is preferred that the second chip placement step and the pillar formation step are performed after the redistribution layer formation step, and the first chip placement step and the substrate placement step are performed after the second chip placement step and the pillar formation step.
[0015] Furthermore, preferably, the first chip disposing step further includes: a connecting step of electrically connecting the first chip and the redistribution layer.
[0016] Furthermore, it is preferable that the connection step is a wire bonding step.
[0017] In addition, the present invention relates to a semiconductor module, which includes multiple chips and has: a substrate; a second chip, which is arranged on one side of the substrate; a column, which extends from one side of the substrate; a redistribution layer, which is arranged between the substrate and the second chip and is electrically connected to the column; a first chip, which is arranged on the side of the redistribution layer opposite to the surface facing the second chip; and a connecting terminal, which electrically connects one side of the redistribution layer and the first chip.
[0018] Furthermore, preferably, the connection terminal includes a bonding wire and a pad.
[0019] Effects of the Invention
[0020] According to the present invention, it is possible to provide a semiconductor module capable of being thinned and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 It is a cross-sectional view showing a semiconductor module according to a first embodiment of the present invention.
[0022] Figure 2 It is a cross-sectional view showing one process of manufacturing the semiconductor module according to the first embodiment.
[0023] Figure 3 It is a cross-sectional view showing one process of manufacturing the semiconductor module according to the first embodiment.
[0024] Figure 4 It is a cross-sectional view showing one process of manufacturing the semiconductor module according to the first embodiment.
[0025] Figure 5 It is a cross-sectional view showing one process of manufacturing the semiconductor module according to the first embodiment.
[0026] Figure 6 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the second embodiment of the present invention.
[0027] Figure 7 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the second embodiment.
[0028] Figure 8 It is a cross-sectional view showing a process of manufacturing a semiconductor module according to the third embodiment of the present invention.
[0029] Fig. 9 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the third embodiment.
[0030] Fig.10 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the third embodiment.
[0031] Fig.11 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the third embodiment.
[0032] Fig.12 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the third embodiment.
[0033] Fig.13 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the third embodiment.
[0034] Fig.14 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the third embodiment.
[0035] Fig.15It is a cross-sectional view showing a process of manufacturing a semiconductor module according to the fourth embodiment of the present invention.
[0036] Fig.16 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the fourth embodiment.
[0037] Fig.17 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the fourth embodiment.
[0038] Fig.18 It is a cross-sectional view showing a process of manufacturing the semiconductor module according to the fourth embodiment. DETAILED DESCRIPTION
[0039] Below, refer to Figures 1 to 18 A semiconductor module 1 and a method for manufacturing the same according to each embodiment of the present invention will be described.
[0040] First, the outline of the semiconductor module 1 according to each embodiment will be described.
[0041] The semiconductor module 1 of each embodiment is, for example, formed by overlapping a storage unit including a plurality of stacked memories and a logic chip (for example, SOC). Specifically, the semiconductor module 1 is formed by overlapping a storage unit and a logic chip in the stacking direction of the stacked memories. The semiconductor module 1 is, for example, formed by overlapping a storage unit and a logic chip with a redistribution layer sandwiched therebetween. In the following embodiments, the storage unit and the logic chip are configured with a redistribution layer sandwiched therebetween, thereby attempting to make the semiconductor module 1 thinner. In addition, by manufacturing the storage unit and the logic chip at the wafer level, the semiconductor module 1 is attempted to be manufactured inexpensively. In addition, in the following embodiments, the storage unit and the logic chip are described as the first chip and the second chip. In addition, in the following embodiments, Figure 1 The description is performed by setting the upper side of the paper as one side and the lower side of the paper as the other side.
[0042] [First embodiment]
[0043] Next, refer to Figures 1 to 5 A semiconductor module 1 and a method for manufacturing the same according to a first embodiment of the present invention will be described.
[0044] The semiconductor module 1 includes a plurality of chips. Figure 1 As shown, the semiconductor module 1 includes a substrate 11 , a second chip 12 , pillars 13 , a second molding portion 14 , a redistribution layer 15 , a first chip 16 , connection terminals 17 , and a first molding portion 18 .
[0045] The substrate 11 is, for example, an organic substrate. The substrate 11 may also be, for example, a redistribution layer. The substrate 11 is, for example, a rectangular plate-shaped body when viewed from above. The substrate 11 has, for example, an electronic circuit 111 inside. The substrate 11 has solder balls 112 on the other side opposite to the one side for electrical connection with other electronic circuits (not shown).
[0046] The second chip 12 is, for example, arranged on one side of the substrate 11. In the present embodiment, the second chip 12 is, for example, a logic chip (SOC). The second chip 12 is, for example, arranged in a state of being electrically connected to one side of the substrate 11. The second chip 12 is, for example, surface mounted on one side of the substrate 11. The second chip 12 is, for example, surface mounted on one side of the substrate 11 by fan-out wafer-level packaging (FOWLP). The second chip 12 has a terminal portion 121 on the other side for electrically connecting to the substrate 11.
[0047] The column 13 is made of a conductive material (e.g., copper). The column 13 extends from one side of the substrate 11. The column 13, for example, extends from one side of the substrate 11 toward the out-of-plane direction. The column 13 has a length, for example, that is the same as or greater than the thickness of the second chip 12. The column 13 is, for example, arranged around the second chip 12. In the present embodiment, the column 13 is arranged along the in-plane direction of one side of the substrate 11 to sandwich the second chip 12. The column 13 is arranged in a state where one end side thereof is electrically connected to one side of the substrate 11.
[0048] The second molded part 14 is formed using, for example, a molded resin. The second molded part 14 is disposed on one side of the substrate 11. The second molded part 14 is formed so that, for example, its thickness is consistent with the height (length) of the pillar 13. The second molded part 14 covers the second chip 12 and the pillar 13 on one side of the substrate 11. The second molded part 14 is formed so that its outer shape is consistent with the shape of the rectangular substrate 11 in a plan view.
[0049] The redistribution layer 15 may also be composed of, for example, an organic substrate. The redistribution layer 15 has an electronic circuit 151 inside. The redistribution layer 15 is arranged with the second chip 12 sandwiched between the substrate 11, and is electrically connected to the pillar 13. The redistribution layer 15 is, for example, arranged on one side of the substrate 11. The redistribution layer 15 is arranged across the second chip 12 and the pillar 13 in the in-plane direction of one side of the substrate 11. In the present embodiment, the redistribution layer 15 is, for example, configured in a rectangular shape similar to the substrate 11 when viewed from above. In addition, the redistribution layer 15 is configured so that its outer shape is the same as or substantially the same size as the outer shape of the substrate 11 and the second molded part 14 when viewed from above. The redistribution layer 15 is configured in a state of being electrically connected to the other end side of the pillar 13. In addition, in the present embodiment, the redistribution layer 15 is configured in a state of being in contact with one side of the second chip 12 on its other side. The redistribution layer 15 is configured in a rectangular shape consistent with the outer shape of the rectangular substrate 11 when viewed from above.
[0050] The first chip 16 is arranged on the side of the redistribution layer 15 opposite to the side facing the second chip 12. In the present embodiment, the first chip 16 is a storage unit having, for example, a plurality of stacked memories 161. The first chip 16 has, for example, a plurality of stacked memories 161 stacked with the out-of-plane direction of one side of the redistribution layer 15 as the stacking direction. In addition, the first chip 16 has a plurality of stacked memories 161 whose configuration positions are offset in the in-plane direction (direction intersecting the stacking direction) of one side of the redistribution layer 15. The first chip 16 has, for example, a plurality of stacked memories 161 arranged adjacent to each other and offset in the in-plane direction of one side of the redistribution layer 15. In the present embodiment, the first chip 16 has, for example, a plurality of stacked memories 161 stacked in sequence with their positions offset from each other in one direction of the in-plane direction of the redistribution layer 15.
[0051] The connection terminal 17 is made of, for example, a conductive material (e.g., copper, gold, or aluminum). The connection terminal 17 is, for example, a wire and a pad. The connection terminal 17 electrically connects one side of the redistribution layer 15 to the first chip 16. The connection terminal 17 electrically connects the redistribution layer 15 to the first chip 16, for example, by wire bonding. The connection terminal 17 is, for example, provided for each stacked memory 161 of the first chip 16. The connection terminal 17 electrically connects, for example, one stacked memory to the redistribution layer 15. In the present embodiment, the connection terminal 17 electrically connects one side of the stacked memory 161 to one side of the redistribution layer 15.
[0052] The first molded portion 18 is formed using, for example, a molded resin. The first molded portion 18 is disposed on one side of the redistribution layer 15. The first molded portion 18 is formed, for example, on one side of the redistribution layer 15, with a thickness exceeding the height (thickness) of the first chip 16 and the connection terminal 17. The first molded portion 18 covers the first chip 16 and the connection terminal 17 on one side of the redistribution layer 15. The first molded portion 18 is formed, for example, in a rectangular shape in accordance with the outer shape of the rectangular substrate 11 in a plan view.
[0053] Next, the operation of the semiconductor module 1 will be described.
[0054] The semiconductor module 1 is electrically connected between the substrate 11 and an external electronic circuit through the solder balls 112. The second chip 12 is electrically connected to the external electronic circuit by being electrically connected to the substrate 11. The first chip 16 is electrically connected to the substrate 11 via the connection terminals 17, the redistribution layer 15, and the pillars 13, thereby being electrically connected to the external electronic circuit.
[0055] Next, a method for manufacturing the semiconductor module 1 according to the present embodiment will be described.
[0056] The method for manufacturing the semiconductor module 1 includes a first chip placement step, a connection terminal forming step, a first mold portion forming step, a redistribution layer forming step, a second chip placement step, a pillar forming step, a second mold portion forming step, and a substrate placement step.
[0057] In the first chip configuration process, Figure 2 As shown, the first chip 16 is arranged. Specifically, in the first chip arrangement process, the first chip 16 is arranged by stacking a stacked memory on the carrier substrate 100 .
[0058] In the connection terminal forming step, connection terminals 17 are formed to be electrically connected to the first chip 16. In the connection terminal forming step, pads are arranged on the carrier substrate 100. In the connection terminal forming step, the pads are connected to one side of each stacked memory with a wire.
[0059] In the first molding part forming step, Figure 3 As shown, the first mold part 18 is formed to cover the connection terminals 17 and the first chip 16. In the first mold part forming process, for example, after the first chip placement process and the connection terminal forming process, the first mold part 18 is formed using a molding resin. Next, the carrier substrate 100 is removed.
[0060] like Figure 4 As shown, in the redistribution layer forming step, a redistribution layer 15 is formed which is arranged on one surface side of the first chip 16 and is electrically connected to the second chip 12. In the redistribution layer forming step, for example, a redistribution layer 15 electrically connected to the connection terminal 17 is formed.
[0061] In the second chip arrangement step, the second chip 12 is arranged at a position overlapping with the first chip 16 in the facing direction on the other side of the redistribution layer 15 opposite to the facing surface of the first chip 16. In the second chip arrangement step, the second chip 12 is arranged on the other side of the redistribution layer 15, and the terminal portion 121 of the second chip 12 is located on the side (the other side) opposite to the other side of the redistribution layer 15. In the second chip arrangement step, the second chip 12 is arranged at a position overlapping with the first chip 16 in the out-of-plane direction of the redistribution layer 15.
[0062] In the column forming step, the column 13 extending from the other surface of the redistribution layer 15 is formed. In the column forming step, the column 13 is formed at a position around the second chip 12 in the in-plane direction of the redistribution layer 15. In the present embodiment, in the column forming step, a pair of columns 13 sandwiching the second chip 12 are formed around the second chip 12 in the in-plane direction of the redistribution layer 15.
[0063] like Figure 5As shown, in the second molded part forming step, the second molded part 14 covering the second chip 12 and the pillar 13 is formed. In the second molded part forming step, after the second chip configuration step and the pillar forming step, the second molded part 14 is formed using a molded resin. Next, the molded resin of the second molded part 14 is ground to expose the top end portion of the terminal portion 121 of the second chip 12 and the top end portion of the pillar 13.
[0064] In the substrate configuration step, the substrate 11 electrically connected to the pillar 13 and the second chip 12 is configured. The substrate 11 may also be formed using a redistribution layer. In addition, in the substrate configuration step, the solder ball 112 is configured on the other side of the substrate 11. In the substrate configuration step, the terminal portion 121 of the second chip 12 and the pillar 13 are electrically connected on one side of the substrate 11.
[0065] Next, the flow of a method for manufacturing the semiconductor module 1 will be described.
[0066] First, if Figure 2 As shown, the first chip configuration step is performed. Next, the connection terminal forming step is performed. Next, the first molded part forming step is performed. Next, as shown Figure 3 As shown, the carrier substrate 100 is removed.
[0067] Next, if Figure 4 As shown, the other surface side of the first chip 16 and the exposed portion (pad) of the connection terminal 17 are arranged face up to perform the redistribution layer forming step. Next, the second chip arrangement step is performed. Next, the pillar forming step is performed.
[0068] Next, if Figure 5 As shown, the second mold portion forming step is performed. Next, the substrate disposing step is performed. Thus, the semiconductor module 1 is manufactured.
[0069] According to the semiconductor module 1 and the manufacturing method thereof according to the first embodiment as described above, the following effects are obtained.
[0070] (1) A method for manufacturing a semiconductor module 1, the semiconductor module 1 including a plurality of chips, the method comprising: a first chip configuration step of configuring a first chip 16; a redistribution layer forming step of forming a redistribution layer 15 configured on one side of the first chip 16 and electrically connected to a second chip 12; a second chip configuration step of configuring the second chip 12 at a position overlapping with the first chip 16 in a facing direction on the other side of the redistribution layer 15 opposite to the facing side of the first chip 16; a column forming step of forming a column 13 extending from the other side of the redistribution layer 15; and a substrate configuration step of configuring a substrate 11 electrically connected to the column 13 and the second chip 12. Thus, compared with a case where either the first chip 16 or the second chip 12 is manufactured by packaging, a semiconductor module 1 of thin size specifications can be provided. In addition, since it can be manufactured at a wafer level, it can be manufactured inexpensively.
[0071] [Second embodiment]
[0072] Next, refer to Figure 6 and Figure 7 , a semiconductor module 1 and a manufacturing method thereof according to a second embodiment of the present invention will be described. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be simplified or omitted.
[0073] The manufacturing method of the semiconductor module 1 of the second embodiment is different from that of the first embodiment in that the first chip configuration step is performed after the redistribution layer formation step. In addition, the manufacturing method of the semiconductor module 1 of the second embodiment is different from that of the first embodiment in that the second chip configuration step, the column formation step, and the substrate configuration step are performed after the first chip configuration step.
[0074] First, if Figure 6 As shown, the redistribution layer forming step is performed on the carrier substrate 100. Next, the first chip placement step and the connection terminal forming step are performed on one side of the redistribution layer 15. Next, the first molded portion forming step is performed.
[0075] Next, if Figure 7 As shown, the carrier substrate 100 is removed. Next, the second chip placement step, the pillar forming step, the second mold portion forming step, and the substrate placement step are performed in the same manner as in the first embodiment.
[0076] According to the semiconductor module 1 and the manufacturing method thereof according to the second embodiment as described above, the following effects are obtained.
[0077] (2) The first chip placement step is performed after the redistribution layer forming step, and the second chip placement step, the pillar forming step, and the substrate placement step are performed after the first chip placement step. Thus, the semiconductor module 1 can be easily manufactured.
[0078] [Third Embodiment]
[0079] Next, refer to Figures 8 to 14 A semiconductor module 1 and a method for manufacturing the same according to a third embodiment of the present invention will be described. In the third embodiment, the same components as those in the first and second embodiments are denoted by the same reference numerals, and description thereof will be simplified or omitted.
[0080] The manufacturing method of the semiconductor module 1 of the third embodiment is different from the first embodiment and the second embodiment in that the second chip configuration step and the column formation step are performed after the substrate configuration step. In addition, the manufacturing method of the semiconductor module 1 of the third embodiment is different from the first embodiment and the second embodiment in that the redistribution layer formation step and the first chip configuration step are performed after the second chip configuration step and the column formation step.
[0081] First, if Figure 8 As shown in FIG. 1 , a substrate configuration step is performed on the carrier substrate 100. The substrate 11 may also be formed using a redistribution layer. Fig. 9 As shown in FIG. 1 , the second chip placement step and the column formation step are performed on one side of the substrate 11. Fig.10 Next, the molding resin of the second molding part 14 is ground to expose the tip end portions of the terminal portions 121 of the second chip 12 and the tip end portions of the pillars 13 .
[0082] Next, if Fig.11 As shown, on one side of the substrate 11, a redistribution layer forming step is performed to form the redistribution layer 15 in a manner of sandwiching the pillars 13 and the second chip 12 between the substrate 11. Fig.12 As shown in FIG. 1 , the first chip placement step and the connection terminal formation step are performed on one side of the redistribution layer 15. Fig.13 As shown in FIG. 1 , the first molding portion forming step is performed. Fig.14 As shown, the carrier substrate 100 is removed, and the solder balls 112 are arranged on the other surface side of the substrate 11. In this way, the semiconductor module 1 is manufactured.
[0083] According to the semiconductor module 1 and the manufacturing method thereof according to the third embodiment as described above, the following effects are obtained.
[0084] (3) The second chip placement step and the pillar formation step are performed after the substrate placement step, and the redistribution layer formation step and the first chip placement step are performed after the second chip placement step and the pillar formation step. Thus, the semiconductor module 1 can be easily manufactured.
[0085] [Fourth Embodiment]
[0086] Next, refer to Figures 15 to 18 A semiconductor module 1 and a method for manufacturing the same according to a fourth embodiment of the present invention will be described. In the fourth embodiment, the same components as those in the first to third embodiments are denoted by the same reference numerals, and descriptions thereof will be simplified or omitted.
[0087] The semiconductor module 1 and the manufacturing method thereof of the fourth embodiment are different from the first to third embodiments in that the second chip arrangement process and the pillar formation process are performed after the redistribution layer formation process. In addition, the semiconductor module 1 and the manufacturing method thereof of the fourth embodiment are different from the first to third embodiments in that the first chip 16 formation and the substrate arrangement process are performed after the second chip arrangement process and the pillar formation process.
[0088] First, if Fig.15 As shown in FIG. 1 , a redistribution layer forming process is performed on the carrier substrate 100. Next, a second chip placement process and a pillar forming process are performed on the redistribution layer 15. Next, as shown in FIG. Fig.16 As shown in FIG. 1 , the second molding part forming step is performed. Next, the molding resin of the second molding part 14 is ground to expose the top end of the terminal part 121 of the second chip 12 and the top end of the pillar 13. Next, the carrier substrate 100 is removed. Next, as shown in FIG. Fig.17 As shown in FIG. 1 , the redistribution layer 15 is placed with one side surface facing upward, and the first chip placement step and the connection terminal formation step are performed on the redistribution layer 15. Fig.18 As shown, the first mold portion forming step is performed. Next, the substrate disposing step is performed with the other side surface of the second chip 12 facing upward. Thus, the semiconductor module 1 is manufactured.
[0089] According to the semiconductor module 1 and the manufacturing method thereof according to the fourth embodiment as described above, the following effects are obtained.
[0090] (4) The second chip placement step and the pillar formation step are performed after the redistribution layer formation step, and the first chip 16 formation and substrate placement step are performed after the second chip placement step and the pillar formation step. Thus, the semiconductor module 1 can be easily manufactured.
[0091] As mentioned above, although the preferred embodiments of the semiconductor module and the manufacturing method thereof of the present invention have been described, the present invention is not limited to the above-mentioned embodiments and can be modified as appropriate.
[0092] For example, in the above-mentioned embodiment, the method for manufacturing the semiconductor module 1 may also include a singulation step of singulating the plurality of semiconductor modules 1. The method for manufacturing the semiconductor module 1 may singulate the plurality of semiconductor modules 1 after forming the plurality of semiconductor modules 1 at the wafer level. The method for manufacturing the semiconductor module 1 may also singulate the plurality of semiconductor modules 1 after forming the plurality of semiconductor modules 1 at the panel level. Thus, the plurality of semiconductor modules 1 can be manufactured efficiently.
[0093] In addition, in the above-mentioned embodiment, the first chip 16 is used as a storage unit, but it is not limited to this. In addition, the second chip 12 is used as a logic chip, but it is not limited to this. The first chip 16 can also be a logic chip and the second chip 12 can be a storage unit. In addition, multiple stacked memories 161 can also be electrically connected through TSV (Through-Silicon Via). In this case, the multiple stacked memories 161 can be electrically connected to the substrate 11 or the redistribution layer 15 using micro bumps.
[0094] Description of Reference Numerals
[0095] 1: Semiconductor module;
[0096] 11: Substrate;
[0097] 12: second chip;
[0098] 13: column;
[0099] 14: second molding part;
[0100] 15: redistribution layer;
[0101] 16: First chip;
[0102] 17: Connecting terminal;
[0103] 18: first molding part;
[0104] 112: Solder ball.
Claims
1. A method for manufacturing a semiconductor module, wherein the semiconductor module comprises a plurality of chips, and the method for manufacturing the semiconductor module comprises: A first chip configuration step of configuring a first chip; a redistribution layer forming step of forming a redistribution layer disposed on one side of the first chip and electrically connected to the second chip; a second chip placement step of placing the second chip at a position overlapping with the first chip in a facing direction on the other surface side of the redistribution layer opposite to the surface facing the first chip; a pillar forming step of forming a pillar extending from the other side of the redistribution layer; and The substrate disposing step is to dispose a substrate electrically connected to the pillar and the second chip.
2. The method for manufacturing a semiconductor module according to claim 1, wherein: The first chip configuration step is performed after the redistribution layer formation step. The second chip placement step, the pillar forming step, and the substrate placement step are performed after the first chip placement step.
3. The method for manufacturing a semiconductor module according to claim 1, wherein: The second chip arrangement step and the pillar formation step are performed after the substrate arrangement step. The redistribution layer forming step and the first chip arranging step are performed after the second chip arranging step and the pillar forming step.
4. The method for manufacturing a semiconductor module according to claim 1, wherein: The second chip arrangement step and the pillar formation step are performed after the redistribution layer formation step. The first chip placement step and the substrate placement step are performed after the second chip placement step and the pillar formation step.
5. The method for manufacturing a semiconductor module according to any one of claims 1 to 4, wherein: Then the first chip configuration step further includes: a connection step of electrically connecting the first chip and the redistribution layer.
6. The method for manufacturing a semiconductor module according to claim 5, wherein: The connection process is a wire bonding process.
7. A semiconductor module comprising a plurality of chips, wherein the semiconductor module has: substrate; A second chip is disposed on one side of the substrate; a column extending from one side of the substrate; a redistribution layer, which is disposed between the substrate and the second chip and is electrically connected to the pillar; A first chip is disposed on a side of the redistribution layer opposite to a side facing the second chip and has a stacked memory; as well as A connection terminal electrically connects one side of the redistribution layer and the first chip.
8. The semiconductor module according to claim 7, wherein: The connection terminal includes a bonding wire and a pad.