Semiconductor test structure and semiconductor test method

Abstract

The present disclosure relates to a semiconductor test structure and a semiconductor test method, and relates to the field of semiconductor technology. The semiconductor test structure includes: at least one group of semiconductor devices, a first test circuit, and a second test circuit. The first test circuit is connected to the semiconductor devices of the corresponding group, and is used to measure the off-state current of the semiconductor devices in normal mode. The second test circuit is connected to the semiconductor devices of the corresponding group, and is used to measure and amplify the leakage current of the semiconductor devices in debug mode. Among them, the debug mode is started when the measurement result of the first test circuit is abnormal. The present disclosure can accurately locate the leakage position of the semiconductor device in the test pattern.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor test structure and a semiconductor test method. Background Art

[0002] Excessive leakage current directly affects the improvement of device performance and reduces the reliability of semiconductor devices. At present, test patterns are often used to monitor leakage current in the semiconductor device manufacturing process, and the leakage position of semiconductor devices in the test patterns is located through conventional failure analysis methods.

[0003] However, when the leakage current is small (below nanoamperes), it is difficult to monitor with conventional failure analysis methods. As a result, the subsequent semiconductor device process is continuously affected by the leakage, which brings great difficulties to the subsequent process failure analysis. Therefore, how to further accurately locate the leakage position of semiconductor devices in the test pattern is an urgent problem to be solved. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor test structure and a semiconductor test method to accurately locate the leakage position of the semiconductor device in the test pattern.

[0005] In order to achieve the above-mentioned purpose, on the one hand, an embodiment of the present disclosure provides a semiconductor test structure, including: at least one group of semiconductor devices, a first test circuit and a second test circuit. The first test circuit is connected to the semiconductor devices of the corresponding group, and is used to measure the off-state current of the semiconductor devices in the normal mode. The second test circuit is connected to the semiconductor devices of the corresponding group, and is used to measure and amplify the leakage current of the semiconductor devices in the debug mode. Wherein, the debug mode is started when the measurement result of the first test circuit is abnormal.

[0006] In the embodiment of the present disclosure, in the normal mode, the off-state current of the semiconductor devices of the corresponding group is measured by the first test circuit. When the measurement result is abnormal, the debug mode is started. In the debug mode, the leakage current of the semiconductor devices of the corresponding group is measured and amplified by the second test circuit. The unexpected technical effect is that the embodiment of the present disclosure amplifies the leakage current of the semiconductor devices of the corresponding group in the debug mode by using the second test circuit without changing the original test pattern (i.e., at least one group of semiconductor devices 1) at all, and generates an amplified current. In this way, the amplified current can be monitored by conventional failure analysis, so as to accurately locate the leakage position on the semiconductor device and shorten the failure analysis time.

[0007] In addition, if the leakage position still cannot be detected using conventional failure analysis in the embodiments of the present disclosure, it can be indirectly explained that the leakage current comes evenly from all semiconductor devices.

[0008] In some embodiments of the present disclosure, a group of semiconductor devices includes at least two transistor devices arranged in parallel. The first end of the first test circuit is connected to the first signal line, the second end is connected to the first pole of each transistor in the corresponding group, and the second pole of each transistor is connected to the second signal line. The first end of the second test circuit is connected to the first signal line, the second end is connected to the first pole of each transistor in the corresponding group, and the third end is connected to the second signal line. The first signal line is configured to provide a first power supply voltage in normal mode and a second power supply voltage in debug mode; the second signal line is configured to provide a second power supply voltage in normal mode and a first power supply voltage in debug mode.

[0009] In the embodiment of the present disclosure, the first signal line provides a first power supply voltage in the normal mode. When the measurement result is abnormal, the debug mode is started, and in the debug mode, the second signal line provides a second power supply voltage. In this way, the second test circuit is driven by the second power supply voltage to amplify the leakage current of the corresponding group of semiconductor devices to generate an amplified current, which can be monitored by conventional failure analysis, thereby further accurately locating the leakage position on the semiconductor device and further shortening the failure analysis time.

[0010] In some embodiments of the present disclosure, the first test circuit includes a first diode; an anode of the first diode is connected to the first signal line, and a cathode of the first diode is connected to the first electrode of each transistor in the corresponding group.

[0011] In the embodiment of the present disclosure, the unidirectional conductivity of the first diode can be used to provide the first power supply voltage to the semiconductor device in the normal mode, thereby measuring the off-state current of the semiconductor device of the corresponding group.

[0012] In some embodiments of the present disclosure, the second test circuit includes: a first amplifying transistor, a second amplifying transistor, a second diode and a third diode. Among them, the first electrode of the first amplifying transistor and the first electrode of the second amplifying transistor are connected to the first signal line. The gate and the second electrode of the first amplifying transistor are both connected to the gate of the second amplifying transistor. The second electrode of the first amplifying transistor is also connected to the cathode of the second diode, and the anode of the second diode is connected to the first electrode of each transistor in the corresponding group. The second electrode of the second amplifying transistor is also connected to the cathode of the third diode, and the anode of the second diode is connected to the second signal line.

[0013] In the disclosed embodiment, the unidirectional conductivity of the second diode and the third diode can be used to provide a second power supply voltage to the semiconductor device in the debugging mode, and the first amplifying transistor and the second amplifying transistor are driven by the second power supply voltage to generate an amplified current, which can be monitored by conventional failure analysis. For example, the leakage position on the semiconductor device can be determined by detecting the luminous transistor through an emission microscope, thereby further accurately locating the leakage position on the semiconductor device and further shortening the failure analysis time.

[0014] In addition, the magnitude of the amplified current can be controlled by selecting the amplifying transistor, and the sensitivity to current cannot be achieved by designs such as current mirrors.

[0015] In some embodiments of the present disclosure, the first test circuit and the second test circuit are arranged side by side on the same side of a corresponding group of semiconductor devices.

[0016] In some embodiments of the present disclosure, the current measurement magnitude of the second test circuit is less than or equal to 10 -8 A.

[0017] On the other hand, the present disclosure also provides a semiconductor testing method, comprising the following steps:

[0018] In a normal mode, a first test circuit is used to measure the off-state current of a corresponding group of semiconductor devices;

[0019] When the measurement result of the first test circuit is abnormal, starting the debugging mode;

[0020] In the debug mode, the leakage current of the corresponding group of semiconductor devices is measured and amplified using the second test circuit.

[0021] In the embodiment of the present disclosure, the semiconductor testing method adopts the above method. The technical effect that can be achieved by this method is the same as the technical effect that can be achieved by the semiconductor testing structure in the aforementioned embodiment, and will not be described in detail here.

[0022] In some embodiments of the present disclosure, the semiconductor testing method further includes:

[0023] In a normal mode, a first power supply voltage is provided to a first signal line connected to the first test circuit and the second test circuit, and a second power supply voltage is provided to a second signal line connected to a corresponding group of semiconductor devices and the second test circuit;

[0024] In the debug mode, the second power supply voltage is provided to the first signal line, and the first power supply voltage is provided to the second signal line.

[0025] In some embodiments of the present disclosure, the first power supply voltage is a maximum power supply voltage; and the second power supply voltage is a ground voltage.

[0026] In some embodiments of the present disclosure, the current measurement magnitude of the second test circuit is less than or equal to 10 -8 A.

[0027] The semiconductor structure and the method for manufacturing the same provided by the embodiments of the present disclosure may have / at least have the following advantages:

[0028] In the embodiment of the present disclosure, in the normal mode, the off-state current of the semiconductor devices of the corresponding group is measured by the first test circuit. When the measurement result is abnormal, the debug mode is started. In the debug mode, the leakage current of the semiconductor devices of the corresponding group is measured and amplified by the second test circuit. The unexpected technical effect is that the embodiment of the present disclosure amplifies the leakage current of the semiconductor devices of the corresponding group in the debug mode by using the second test circuit without changing the original test pattern (i.e., at least one group of semiconductor devices) to generate an amplified current. In this way, the amplified current can be monitored by conventional failure analysis, thereby accurately locating the leakage position on the semiconductor device and shortening the failure analysis time.

[0029] In addition, if conventional failure analysis is used in the disclosed embodiments and the leakage position still cannot be detected, it can be indirectly explained that the leakage current comes uniformly from all semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of a semiconductor test structure provided in an embodiment of the present disclosure;

[0032] Figure 2 A schematic structural diagram of another semiconductor test structure provided in an embodiment of the present disclosure;

[0033] Figure 3 A schematic structural diagram of another semiconductor test structure provided in an embodiment of the present disclosure;

[0034] Figure 4 A schematic structural diagram of another semiconductor test structure provided in an embodiment of the present disclosure;

[0035] Figure 5 A schematic diagram of a process of a semiconductor testing method provided in an embodiment of the present disclosure.

[0036] Description of reference numerals:

[0037] 1-semiconductor device, 11-transistor device, 111-first electrode of transistor, 112-second electrode of transistor;

[0038] 2-first test circuit, 21-first end of the first test circuit, 22-second end of the first test circuit, 23-first diode, 231-anode of the first diode, 232-cathode of the first diode;

[0039] 3-second test circuit, 31-first end of the second test circuit, 32-second end of the second test circuit, 33-third end of the second test circuit, 34-first amplifier transistor, 341-first electrode of the first amplifier transistor, 342-second electrode of the first amplifier transistor, 343-third electrode of the first amplifier transistor, 35-second amplifier transistor, 351-first electrode of the second amplifier transistor, 352-second electrode of the second amplifier transistor; 353-third electrode of the second amplifier transistor, 36-second diode, 361-anode of the second diode, 362-cathode of the second diode, 37-third diode, 371-anode of the third diode, 372-cathode of the third diode;

[0040] s1-first signal line, s2-second signal line. DETAILED DESCRIPTION

[0041] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0043] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0044] It is understood that the terms "first", "second", "third", "fourth", etc. used in the present disclosure may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of the present disclosure, a first transistor may be referred to as a second transistor, and similarly, a second transistor may be referred to as a first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.

[0045] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0046] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0047] Excessive leakage current directly affects the improvement of device performance and reduces the reliability of the device. At present, test patterns are often used to monitor leakage current in device manufacturing processes, and the leakage position in the test pattern is located by conventional failure analysis methods. At present, there are two types of test patterns used to monitor leakage current in the process: the first type of test pattern includes 1 semiconductor device, which can only monitor the basic process and cannot respond to some special process problems in time. The second type of test pattern includes 266 semiconductor devices. Taking the rapid heating oxidation process as an example, the test pattern of 266 semiconductor devices detected the leakage at the nanoampere level caused by the process change, but the first type of test pattern could not detect the leakage. The second type of test pattern monitors the total leakage current of 266 semiconductor devices. However. Even the failure test pattern with large leakage is at the nanoampere level. When the leakage current is small (below nanoampere), it is difficult to monitor by conventional failure analysis methods. As a result, the subsequent device process is continuously affected by the leakage, which brings great difficulties to the failure analysis of the subsequent process.

[0048] Based on this, it is necessary to provide a semiconductor test structure and a semiconductor test method to accurately locate the leakage position of the semiconductor device in the test pattern.

[0049] See also Figure 1 The embodiment of the present disclosure provides a semiconductor test structure, including: at least one group of semiconductor devices 1, a first test circuit 2, and a second test circuit 3. The first test circuit 2 is connected to the corresponding group of semiconductor devices 1, and is used to measure the off-state current of the semiconductor device 1 in the normal mode. The second test circuit 3 is connected to the corresponding group of semiconductor devices 1, and is used to measure and amplify the leakage current of the semiconductor device 1 in the debug mode. The debug mode is started when the measurement result of the first test circuit 2 is abnormal.

[0050] In the embodiment of the present disclosure, in the normal mode, the off-state current of the semiconductor device 1 of the corresponding group is measured by the first test circuit 2. When the measurement result is abnormal, the debug mode is started. In the debug mode, the leakage current of the semiconductor device 1 of the corresponding group is measured and amplified by the second test circuit 3. The unexpected technical effect is that the embodiment of the present disclosure amplifies the leakage current of the semiconductor device 1 of the corresponding group in the debug mode by using the second test circuit 3 without changing the original test pattern (i.e., at least one group of semiconductor devices 1) at all, and generates an amplified current. In this way, the amplified current can be monitored by conventional failure analysis, so as to accurately locate the leakage position on the semiconductor device 1 and shorten the failure analysis time.

[0051] In addition, if the leakage position still cannot be detected by conventional failure analysis in the embodiment of the present disclosure, it can be indirectly explained that the leakage current comes uniformly from all semiconductor devices 1.

[0052] In some examples, the failure analysis includes emission microscopy (EMMI) analysis.

[0053] In some embodiments, see Figure 2 , a group of semiconductor devices 1 includes at least two transistor devices 11 arranged in parallel. Among them, the first end 21 of the first test circuit 2 is connected to the first signal line s1, the second end 22 is connected to the first electrode 111 of each transistor 11 in the corresponding group, and the second electrode 112 of each transistor 11 is connected to the second signal line s2. The first end 31 of the second test circuit 3 is connected to the first signal line s1, the second end 32 is connected to the first electrode 111 of each transistor 11 in the corresponding group, and the third end 33 is connected to the second signal line s2. Among them, the first signal line s1 is configured to provide a first power supply voltage V1 in normal mode and a second power supply voltage V2 in debug mode. The second signal line s2 is configured to provide a second power supply voltage V2 in normal mode and a first power supply voltage V1 in debug mode.

[0054] In some examples, the first power supply voltage V1 is a maximum power supply voltage. The second power supply voltage V2 is a ground voltage.

[0055] In the embodiment of the present disclosure, the first signal line s1 provides the first power supply voltage V1 in the normal mode. When the measurement result is abnormal, the debug mode is started. In the debug mode, the second signal line s2 provides the second power supply voltage V2. In this way, the second test circuit 3 is driven by the second power supply voltage V2 to amplify the leakage current of the corresponding group of semiconductor devices 1, generating an amplified current, which can be monitored by conventional failure analysis, thereby further accurately locating the leakage position on the semiconductor device 1 and further shortening the failure analysis time.

[0056] In some embodiments, see Figure 3The first test circuit 2 includes a first diode 23. An anode 231 of the first diode 23 is connected to the first signal line s1, and a cathode 232 of the first diode 23 is connected to the first electrode 111 of each transistor 11 in the corresponding group.

[0057] In the embodiment of the present disclosure, by utilizing the unidirectional conductivity of the first diode 23 , the first power supply voltage V1 can be provided to the semiconductor device 1 in the normal mode, thereby measuring the off-state current of the semiconductor device 1 of the corresponding group.

[0058] In some embodiments, see Figure 4 , the second test circuit 3 includes: a first amplifying transistor 34, a second amplifying transistor 35, a second diode 36 and a third diode 37. Among them, the first electrode 341 of the first amplifying transistor 34 and the first electrode 351 of the second amplifying transistor 35 are connected to the first signal line s1. The gate 343 of the first amplifying transistor 34 and the second electrode 342 of the first amplifying transistor 34 are both connected to the gate 353 of the second amplifying transistor 35. The second electrode 342 of the first amplifying transistor 34 is also connected to the cathode 362 of the second diode 36, and the anode 361 of the second diode 36 is connected to the first electrode 111 of each transistor 11 in the corresponding group. The second electrode 352 of the second amplifying transistor 35 is also connected to the cathode 372 of the third diode 37, and the anode 371 of the second diode 37 is connected to the second signal line s2.

[0059] In the disclosed embodiment, the unidirectional conductivity of the second diode 36 and the third diode 37 can be used to provide the second power supply voltage V2 to the semiconductor device 1 in the debugging mode, and the first amplifying transistor 34 and the second amplifying transistor 35 are driven by the second power supply voltage V2 to generate an amplified current, which can be monitored by conventional failure analysis. For example, the leakage position on the semiconductor device 1 can be determined by detecting the luminous transistor through EMMI, thereby further accurately locating the leakage position on the semiconductor device 1 and further shortening the failure analysis time.

[0060] In addition, the magnitude of the amplified current can be controlled by selecting the amplifying transistor, and the sensitivity to current cannot be achieved by designs such as current mirrors.

[0061] In some embodiments, the first test circuit 2 and the second test circuit 3 are arranged side by side on the same side of the corresponding group of semiconductor devices 1 .

[0062] In some embodiments, the current measurement magnitude of the second test circuit 3 is less than or equal to 10 -8 A.

[0063] See also Figure 5 The embodiment of the present disclosure also provides a semiconductor testing method, including steps S100~S300.

[0064] S100 , in a normal mode, using a first test circuit to measure off-state currents of a corresponding group of semiconductor devices.

[0065] S200, when the measurement result of the first test circuit is abnormal, starting the debugging mode.

[0066] S300 , in a debugging mode, using a second test circuit to measure and amplify leakage current of a corresponding group of semiconductor devices.

[0067] In the embodiment of the present disclosure, the semiconductor testing method adopts the above method. The technical effect that can be achieved by this method is the same as the technical effect that can be achieved by the semiconductor testing structure in the aforementioned embodiment, and will not be described in detail here.

[0068] In some embodiments, the semiconductor test structure provided in the aforementioned embodiments may be used to implement the semiconductor test method.

[0069] In some embodiments, step S100 further includes: in a normal mode, providing a first power supply voltage to a first signal line connected to the first test circuit and the second test circuit, and providing a second power supply voltage to a second signal line connected to a corresponding group of semiconductor devices and the second test circuit;

[0070] In some embodiments, step S300 further includes: in the debug mode, providing the second power supply voltage to the first signal line, and providing the first power supply voltage to the second signal line.

[0071] In the embodiment of the present disclosure, the first signal line provides a first power supply voltage in the normal mode. When the measurement result is abnormal, the debug mode is started, and in the debug mode, the second signal line provides a second power supply voltage. In this way, the second test circuit is driven by the second power supply voltage to amplify the leakage current of the corresponding group of semiconductor devices to generate an amplified current, which can be monitored by conventional failure analysis, thereby further accurately locating the leakage position on the semiconductor device and further shortening the failure analysis time.

[0072] In some embodiments, the first power supply voltage is a maximum power supply voltage; and the second power supply voltage is a ground voltage.

[0073] In some embodiments, the current measurement magnitude of the second test circuit is less than or equal to 10 -8 A.

[0074] As described above, in the embodiment of the present disclosure, in the normal mode, the off-state current of the semiconductor devices of the corresponding group is measured by the first test circuit. When the measurement result is abnormal, the debug mode is started. In the debug mode, the leakage current of the semiconductor devices of the corresponding group is measured and amplified by the second test circuit. The unexpected technical effect is that the embodiment of the present disclosure amplifies the leakage current of the semiconductor devices of the corresponding group in the debug mode by using the second test circuit without changing the original test pattern (i.e., at least one group of semiconductor devices 1) at all, and generates an amplified current. In this way, the amplified current can be monitored by conventional failure analysis, so as to accurately locate the leakage position on the semiconductor device and shorten the failure analysis time.

[0075] In addition, if the leakage position still cannot be detected using conventional failure analysis in the embodiments of the present disclosure, it can be indirectly explained that the leakage current comes evenly from all semiconductor devices.

[0076] In the description of this specification, the technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A semiconductor test structure, characterized in that: include: at least one set of semiconductor devices; A first test circuit, connected to the semiconductor devices of the corresponding group, for measuring the off-state current of the semiconductor devices in a normal mode; A second test circuit, connected to the semiconductor devices of the corresponding group, for measuring and amplifying the leakage current of the semiconductor devices in a debugging mode; Wherein, the debugging mode is started when the measurement result of the first test circuit is abnormal; A group of the semiconductor devices comprises at least two transistor devices arranged in parallel; wherein, The first end of the first test circuit is connected to the first signal line, the second end is connected to the first electrode of each transistor in the corresponding group, and the second electrode of each transistor is connected to the second signal line; A first end of the second test circuit is connected to the first signal line, a second end is connected to the first electrode of each transistor in the corresponding group, and a third end is connected to the second signal line; The first signal line is configured to provide a first power supply voltage in the normal mode and a second power supply voltage in the debug mode; the second signal line is configured to provide the second power supply voltage in the normal mode and the first power supply voltage in the debug mode.

2. The semiconductor test structure according to claim 1, wherein: The first test circuit includes a first diode; an anode of the first diode is connected to the first signal line, and a cathode of the first diode is connected to the first electrode of each transistor in the corresponding group.

3. The semiconductor test structure according to claim 1, wherein: The second test circuit includes: a first amplifying transistor, a second amplifying transistor, a second diode and a third diode; wherein, The first electrode of the first amplifying transistor and the first electrode of the second amplifying transistor are connected to the first signal line; The gate and the second electrode of the first amplifying transistor are both connected to the gate of the second amplifying transistor; The second electrode of the first amplifying transistor is also connected to the cathode of the second diode, and the anode of the second diode is connected to the first electrode of each transistor in the corresponding group; The second electrode of the second amplifying transistor is also connected to the cathode of the third diode, and the anode of the second diode is connected to the second signal line.

4. The semiconductor test structure according to claim 1, wherein: The first test circuit and the second test circuit are arranged side by side on the same side of the corresponding group of semiconductor devices.

5. The semiconductor test structure according to any one of claims 1 to 4, characterized in that: The current measurement magnitude of the second test circuit is less than or equal to 10 -8 A.

6. A semiconductor testing method, characterized in that: include: In a normal mode, a first test circuit is used to measure the off-state current of a corresponding group of semiconductor devices; When the measurement result of the first test circuit is abnormal, starting the debugging mode; In the debugging mode, the leakage current of the corresponding group of semiconductor devices is measured and amplified using the second test circuit; In a normal mode, a first power supply voltage is provided to a first signal line connected to the first test circuit and the second test circuit, and a second power supply voltage is provided to a second signal line connected to a corresponding group of semiconductor devices and the second test circuit; In the debug mode, the second power supply voltage is provided to the first signal line, and the first power supply voltage is provided to the second signal line.

7. The semiconductor testing method according to claim 6, wherein: The first power supply voltage is a maximum power supply voltage; the second power supply voltage is a ground voltage.

8. The semiconductor testing method according to claim 6 or 7, characterized in that: The current measurement magnitude of the second test circuit is less than or equal to 10 -8 A.

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