Method and device for testing packaging level of MOS (Metal Oxide Semiconductor) transistor

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) transistors, and discloses a method and a device for testing a packaging level of an MOS transistor. The method comprises the following steps: applying a multi-frequency pulse signal to a packaged MOS transistor to obtain MOS transistor response data under different frequencies; performing parameter synchronous acquisition on the MOS transistor response data to obtain original test data; performing packaging parasitic effect compensation processing on the original test data to obtain corrected test data; performing signal characteristic decomposition on the correction test data to obtain a characteristic parameter set of the MOS transistor; and packaging defect analysis is carried out based on the characteristic parameter set, and a defect identification report is obtained. According to the invention, hidden dangers causing device failure can be identified in advance, and the safety of high-power application is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS transistors, and in particular to a packaging-level testing method and device for MOS transistors. Background Art

[0002] Traditional MOS transistor package-level test frameworks test device performance at a single frequency point, failing to fully reflect device characteristics in complex operating environments. This is particularly limited for high-frequency, low-power applications. Furthermore, traditional methods typically test electrical and thermal parameters separately, ignoring their mutual influence, leading to discrepancies between test results and actual operating conditions.

[0003] Another key issue with traditional package-level testing is low test efficiency. Multiple test cycles are required to separately acquire key parameters such as threshold voltage, on-resistance, and gate charge, increasing test time and reducing test data consistency. Furthermore, package parasitics can significantly impact test results, but traditional methods lack effective compensation techniques, limiting parameter extraction accuracy. This is especially true at high frequencies, where the impact of parasitic parameters such as lead inductance, lead resistance, and mutual capacitance becomes more pronounced. Summary of the Invention

[0004] The main purpose of the present invention is to provide a packaging-level testing method and device for MOS transistors. The present invention can identify hidden dangers that lead to device failure in advance, greatly improving the safety of high-power applications.

[0005] To achieve the above object, the present invention provides a package-level testing method for a MOS transistor, comprising the following steps: Apply multi-frequency pulse signals to the packaged MOS transistor to obtain MOS transistor response data at different frequencies; Performing parameter synchronous acquisition on the MOS transistor response data to obtain original test data; Performing package parasitic effect compensation processing on the original test data to obtain corrected test data; Performing signal feature decomposition on the correction test data to obtain a feature parameter set of the MOS transistor; A packaging defect analysis is performed based on the characteristic parameter set to obtain a defect identification report.

[0006] The present invention also provides a package-level testing device for a MOS transistor, comprising: A response module is used to apply a multi-frequency pulse signal to the packaged MOS transistor to obtain MOS transistor response data at different frequencies; A synchronous acquisition module, used for synchronously acquiring parameters of the MOS transistor response data to obtain original test data; a compensation processing module, configured to perform package parasitic effect compensation processing on the original test data to obtain corrected test data; A feature decomposition module, configured to perform signal feature decomposition on the calibration test data to obtain a feature parameter set of the MOS transistor; The defect analysis module is used to perform packaging defect analysis based on the characteristic parameter set to obtain a defect identification report.

[0007] In summary, the technical solution provided by the present invention adopts a multi-frequency injection pulse test method to simultaneously obtain multiple key parameters such as threshold voltage, on-resistance and gate charge in a single test cycle, greatly shortening the test time and improving the test throughput of the production line. Through the identification and compensation technology of package-level parasitic effects, accurate modeling is achieved and the influence of lead inductance, lead resistance, mutual capacitance and package thermal resistance on the test results is eliminated, making parameter extraction more accurate. The intelligent recognition system based on wavelet entropy decomposition and deep convolutional neural network can simultaneously detect various packaging defects such as bond breakage, chip cracks, gate floating and source-drain short circuits, especially with ultra-high sensitivity to tiny bond defects. The present invention is particularly suitable for the test scenarios of high-frequency, low-power MOS transistors. Through temperature-frequency joint test domain analysis and pulse modulation thermal resistance test method, the synchronous measurement of electrical parameters and thermal parameters is realized, and an electric-thermal joint parameter extraction model is established to provide a more accurate basis for device reliability assessment. It can detect potential thermal failure risks in advance, especially for power MOS transistors, and can identify hidden dangers that lead to device failure in advance, greatly improving the safety of high-power applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 1 is a schematic diagram of the steps of a package-level testing method for a MOS transistor in one embodiment of the present invention; Figure 2 It is a structural block diagram of a package-level test device for MOS transistors in one embodiment of the present invention.

[0009] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0011] Reference Figure 1 This embodiment provides a package-level testing method for a MOS transistor, comprising the following steps: S1, applying a multi-frequency pulse signal to the packaged MOS transistor to obtain the MOS transistor response data at different frequencies; The digital signal processor (DSP) serves as the core of the test system. The required frequency sequence is pre-programmed and, utilizing a high-precision clock reference, a set of multi-frequency test reference signals is generated within the processor. These signals cover a wide frequency range from 100kHz to 10MHz and are logarithmically spaced to enable more detailed analysis of the device's dynamic response at low, medium, and high frequencies. The DSP directly digitally synthesizes the multi-frequency reference signals, ensuring frequency accuracy and enabling highly controllable modulation of the pulse signal waveform. For example, the rise and fall times and duty cycle of the pulses are strictly limited, thus meeting the high-frequency and high-speed excitation signal requirements of MOS transistors. The resulting multi-frequency pulse signals are precisely routed to the gate port of the MOS transistor under test via a specially designed high-speed switch matrix. This switch matrix seamlessly switches between different frequency signals between test channels with extremely low latency and high switching speed, ensuring that the pulse signal at each frequency point stably and accurately acts on the device gate, generating a high-fidelity gate excitation signal. The voltage amplitude of the gate excitation signal is gradually adjusted, increasing from a low of 0.5V to a maximum of 10V, simulating the various driving conditions encountered by the device in actual applications, so that the test data is fully representative and discriminative at different voltage operating points. At the same time, in the test configuration, a high-precision source meter measurement unit is connected to the drain, source, and base of the MOS transistor respectively, and the source is directly grounded and the base is grounded through a high-stability resistor, while a specific voltage is constantly applied to the drain end to ensure that the device operates in a controlled working environment. Through the above-mentioned multi-frequency and multi-voltage excitation method, the response signal of the MOS transistor is collected in real time at each set frequency and voltage point, including the voltage and current of the gate input, the drain current, and other key electrical parameters, forming a multi-dimensional response data matrix.

[0012] S2, synchronously collect the parameters of the MOS transistor response data to obtain the original test data; Specifically, MOS transistor response data is collected to generate raw response waveform data, covering the device's complete transient and steady-state responses under various stimulus conditions. Precise synchronous triggering is achieved based on a master clock signal, and each set of raw response waveform data is time-synchronized with the master clock as a reference. This ensures that the sampling times of different channels for the same physical event are strictly consistent, thereby reducing correlation errors caused by sampling delays or inter-channel time differences. The test system utilizes four parallel high-speed measurement channels to classify and collect the time-synchronized response data. These four channels provide real-time acquisition of four key parameters: gate voltage, drain current, gate charge and discharge current, and device junction temperature. The gate voltage channel captures the fluctuation characteristics of the stimulus signal at the MOS transistor gate, while the drain current channel utilizes precision current shunting and automatic range switching to measure the full range of drain current, from microamperes to 10 amperes. For the high-speed transient gate charge and discharge current, an integral sampling technique is employed, with ultra-high-speed sampling performed at key time points, such as the rising and falling edges of the pulse signal. The charge changes during the gate charge and discharge process are directly extracted through integration, yielding physically meaningful gate charge data. At the same time, the junction temperature of MOS devices is measured in real time using the temperature-sensitive parameter method to capture the potential impact of temperature rise on device characteristics. Gate voltage data, gate charge data, full-scale drain current data, and device junction temperature data are digitally filtered using targeted structures such as band-stop or low-pass filters to effectively suppress main frequency noise and high-frequency interference in the test environment, improve the signal-to-noise ratio, and eliminate invalid glitches to obtain the original test data.

[0013] S3, performing package parasitic effect compensation processing on the original test data to obtain corrected test data; It should be noted that, based on the raw test data and combined with the actual package structure and thermal characteristics, target parameters, including the thermal resistance between the chip and the package substrate, were constructed. A complete MOS transistor package equivalent circuit model was also established. This model incorporates electrical parasitics such as lead resistance, lead inductance, and mutual capacitance between leads. Thermal characteristics such as the thermal resistance between the chip and the substrate were also incorporated into the modeling, reflecting the comprehensive impact of the package structure on electrical and thermal responses under actual operating conditions. After the model was constructed, a targeted response characteristic analysis was performed based on the model parameters and the raw test data. The raw data was divided into multiple response segments by frequency, and the key features at low, medium, and high frequencies were extracted. This segmented frequency response data was generated to reflect the dominant role of various parasitic effects in different frequency ranges. By interpreting the segmented frequency response data, the dominant control region of each parasitic parameter was identified. For example, the low-frequency band is mainly affected by lead resistance, the medium-frequency band is mainly affected by lead inductance, and the high-frequency band is dominated by mutual capacitance. Based on the dominant control relationship between the frequency bands, the influencing factors of each parasitic parameter were correlated to establish a set of mathematical equations for the parasitic parameters. Matrix operations are used to solve this set of equations to obtain a set of actual values ​​for parasitic parameters, including specific parameters such as lead resistance, lead inductance, mutual capacitance, and package thermal resistance. Based on the actual value set of parasitic parameters, the original test data is compensated in the frequency domain, and the electrical response and thermal response data are corrected in sections to obtain balanced and consistent compensation effect data across the entire frequency band. By compensating for lead inductance, the accuracy of gate charge and discharge current measurements is effectively improved, thereby improving the accuracy of gate charge extraction. Compensating for lead resistance eliminates its voltage drop effect on threshold voltage measurement results, minimizing threshold voltage measurement errors. Compensating for thermal resistance helps correct the impact of the package structure on junction temperature measurement. After the above-mentioned section-by-section compensation and full-band consistency processing, corrected test data is obtained.

[0014] In this embodiment, the package topology structure analysis is performed based on the electrical response characteristics of the MOS transistor at different frequencies in the original test data. By collecting and arranging the response curves of the device at various excitation frequencies, the actual layout of the leads inside the package and the positional relationship of each key interconnection node are analyzed, and the physical structure characterization data used to describe the spatial distribution of the package are extracted. These characterization data reflect the geometric shape of the package and also include structural deviations and process changes introduced during the actual manufacturing process. Based on these physical structure characterization data, combined with empirical formulas and industry databases, the initial value set of each parasitic parameter is quickly obtained using the preliminary estimation method of electromagnetic compatibility design. These initial values ​​include key parameters such as lead resistance, lead inductance, and distributed capacitance between interconnections. The initial value set of parasitic parameters is specifically compared and analyzed with the response characteristics of the low-frequency band in the original test data. Under low-frequency conditions, the dominant role of lead resistance in the overall electrical response is more significant. By minimizing the difference between the measured response and the simulation results, the target value of the lead resistance is inferred. At the same time, the response characteristics of the original test data in the mid-frequency band are combined with three-dimensional finite element magnetic field simulation technology to analyze the loop induced magnetic field and its dynamic response generated when the signal flows between the leads. By comparing the inverse simulation and test data, a more accurate lead inductance target value is obtained. For the electrical response data in the high-frequency band, the potential distribution and field intensity changes of the pulse signal between the leads are simulated with the help of a high-precision electric field distribution calculation method to deduce the mutual capacitance target value between the leads. The lead resistance target value, lead inductance target value, mutual capacitance target value between the leads and the temperature-power consumption relationship curve in the original test data are subjected to heat flow analysis to obtain the thermal resistance target value between the chip and the package substrate, which reflects the conduction efficiency of the heat flow from the chip to the external environment. The lead resistance target value, lead inductance target value, mutual capacitance target value and thermal resistance target value are integrated to form a complete MOS transistor package equivalent circuit model.

[0015] In this embodiment, the parasitic parameter association data is processed in frequency interval segments. Based on the dominant role of various parasitic effects in different frequency bands, the overall test frequency range is divided into several sub-intervals. In each frequency interval, the focus is on the parameter association corresponding to its physical dominant mechanism. For example, the low-frequency region mainly considers the influence of lead resistance, the mid-frequency region focuses on lead inductance, and the high-frequency region focuses on mutual capacitance, while the thermal resistance effect across frequency bands runs through the whole. Through segmented processing, parameter cross-interference is eliminated to the greatest extent, and accurate extraction within the main control area of ​​different parasitic parameters is achieved. For each sub-band parameter association data, a function model between the device response and the parasitic parameter is constructed, and a set of relationship functions between the measured response and the lead inductance, lead resistance, mutual capacitance and package thermal resistance is established for each frequency point. These function models are based on equivalent circuits and describe the influence of each parameter on the actual output of the device through a series of coupled response equations, forming a multi-variable, multi-equation parameter network. A linear transformation is performed on the parameter function model set. Through methods such as Taylor expansion or small perturbation approximation, the originally nonlinear physical response function is converted into a system of linear equations for parasitic parameters. The resulting parasitic parameter equation system is expressed in the standard matrix form of A·x=b, where A is the coefficient matrix, x is the parameter vector to be determined, and b is the measured response vector. To solve the system of equations, the coefficient matrix A is decomposed using the singular value decomposition method to obtain a robust least squares solution matrix. The singular value decomposition method has excellent numerical stability and can avoid divergence and non-uniqueness of the solution even when there is strong correlation or partial redundancy between parameters. The least squares solution matrix and the response vector are multiplied by a matrix to obtain the initial parasitic parameter vector, which preliminarily reflects the actual physical value of each parasitic element. Residual analysis and iterative optimization are performed on the initial parameter vector. The initial solution is introduced into the original model, and the residual distribution between the theoretical output and the measured response is calculated. Optimization algorithms such as gradient descent or Newton iteration are then used to gradually modify the parameter values ​​until the residual converges to a preset threshold or the model output closely matches the measured data. Through numerical calculations and optimization iterations, the actual values ​​of the parasitic parameters are ultimately obtained.

[0016] S4, performing signal feature decomposition on the calibration test data to obtain a feature parameter set of the MOS transistor; Specifically, the correction test data is subjected to wavelet decomposition and multi-scale decomposition processing. High-order wavelet basis functions such as Daubechies8 are selected to expand each correction signal - including parameters such as gate voltage, drain current, gate charge and discharge current, and junction temperature - into detail coefficients and approximate coefficients of different resolutions in the time domain. Through wavelet decomposition, the signal that originally mixed transient and steady-state responses can be reconstructed in a multi-level and multi-band form. Each layer of decomposition reflects the response characteristics of the device under different dynamic processes. Based on the wavelet decomposition coefficient set, entropy-type features are calculated, including indicators such as Shannon entropy and Tsallis entropy, to measure the complexity and nonlinearity of the signal. These entropy features can reveal the internal dynamic changes and abnormal states of the device at specific frequencies and temperatures. Simultaneously, based on the calibration data, statistical analysis is performed on parameter sequences such as gate voltage, drain current, gate charge / discharge current, and junction temperature. This includes calculating statistical features such as the mean, standard deviation, maximum, minimum, skewness, kurtosis, peak occurrence time, rise / fall time, and stability interval for each data set. This set of features reveals the average performance and dispersion of the device under typical operating conditions and reflects its response behavior under extreme operating conditions or at sudden changes. Furthermore, based on the calibration test data, a parameter correlation analysis matrix is ​​constructed to systematically calculate correlation coefficients for the transconductance between gate voltage and drain current, the capacitance change between gate charge and gate voltage, and the thermal resistance between junction temperature and device power consumption. Through correlation analysis of these parameters, the coupling effect between the device's electrical and thermal performance is quantified, assisting in identifying the inherent impact of process defects, parasitic interference, and material variations on device performance. The entropy feature data, statistical feature data, and parameter correlation feature data are combined to form a full feature dataset covering the static, dynamic, electrical, thermal, and coupled physical characteristics of the MOS transistor. In order to avoid the interference of invalid or redundant information in the high-dimensional feature space and improve the efficiency and accuracy of subsequent intelligent recognition and classification models, algorithms such as recursive feature elimination are used to automatically screen the entire feature data set. By recursively eliminating features with low contribution, the most discriminative and representative feature vectors are finally retained to form the MOS transistor feature parameter set.

[0017] S5, performing packaging defect analysis based on the feature parameter set to obtain a defect identification report.

[0018] The high-dimensional feature parameter set is input into a pre-trained deep convolutional neural network model. Through the network's multi-layer convolutional feature extraction and fully connected layer mapping, complex features are abstracted and integrated layer by layer. The network performs forward propagation calculations on each set of input feature data, outputting preliminary identification results for device package defects and the corresponding category probability distribution. A Focal Loss function is introduced to weight the confidence scores of all output categories after obtaining the preliminary identification results. This loss function automatically focuses on defect types that are difficult for the model to distinguish, have uneven sample distribution, or have low probability, improving the network's sensitivity and accuracy for small, hidden, and diverse defects. The resulting defect identification results are annotated with confidence levels. High-confidence identification results are directly accepted, while low-confidence results or those close to the threshold are marked as "pending review." This enables automatic early warning and screening, effectively reducing the risk of misidentification or missed detections. These confidence-based defect identification results are then used for comparative analysis in a higher-dimensional temperature-frequency joint test domain. MOS transistor samples are repeatedly tested under different temperature and frequency excitation conditions. For each temperature-frequency point, the corresponding characteristic parameter set is input into the neural network to obtain the defect recognition probability under the test conditions. All test results are summarized on a two-dimensional temperature-frequency matrix to construct a normalized defect feature map. In order to improve the objectivity and micro-area resolution of defect analysis, a distributed thermoelectric sampling point array is arranged on the package surface, and the actual temperature distribution characteristics are synchronously collected at D key temperature sensing points to reflect physical phenomena such as intensive power consumption, heat dissipation bottlenecks and local abnormal temperature rise. The collected temperature distribution characteristics are combined with the above-mentioned defect recognition results with confidence for joint analysis, including evaluating the correlation between thermal distribution and defect probability, the overlap between hot spot areas and high-incidence defect areas, and the impact of temperature changes on recognition confidence. All results are integrated to form a defect recognition report, which covers the defect type, distribution, severity, probability of occurrence, corresponding test conditions and physical feature descriptions.

[0019] In one example, a multi-frequency pulse signal is applied to a packaged MOS transistor to obtain MOS transistor response data at different frequencies, including: Generate a multi-frequency test reference signal through a digital signal processor, and digitally synthesize the multi-frequency test reference signal to obtain a multi-frequency pulse signal; The multi-frequency pulse signal is routed to the gate terminal of the packaged MOS transistor through a high-speed switch matrix to obtain a gate excitation signal; The voltage amplitude of the gate excitation signal is gradually adjusted to obtain a multi-voltage amplitude gate excitation signal; Based on the multi-voltage amplitude gate excitation signal, the source meter measurement unit is connected to the drain, source and base of the packaged MOS transistor. At the same time, under the conditions of grounding the source and base and applying a constant voltage to the drain, the MOS transistor response data at different frequencies is obtained.

[0020] In this example, a multi-frequency test reference signal is generated using a digital signal processor (DSP). The DSP integrates a high-precision numerically controlled oscillator and phase accumulator module. By setting the frequency control word and phase update step size, the frequency value can be rapidly switched while maintaining frequency stability. During the test, a predefined frequency sequence, covering the low- to high-frequency range, is distributed logarithmically to ensure sufficient frequency sampling density within each frequency band to fully characterize the frequency response characteristics of MOS transistors. Based on these frequency points, the DSP uses direct digital synthesis techniques to convert the reference sinusoidal signal at each frequency point into a pulse waveform. The waveform shape is controlled during the process to ensure that the generated pulse has extremely short rise and fall times. The duty cycle is fixed at 30% to enhance the transient driving capability and dynamic change perception of the excitation signal. This signal structure improves the accuracy of capturing the edge behavior of the MOS device and minimizes response tailing caused by slow driving. This step results in a multi-frequency pulse signal. Multi-frequency pulse signals are routed to the gate terminals of packaged MOS transistors via a high-speed switch matrix. The high-speed switch matrix utilizes high-bandwidth, high-isolation solid-state electronic switches, switching the excitation channels between different paths with extremely low channel latency and microsecond switching times. During the routing process, the pulse signals are precisely directed to the gate pins of the packaged MOS transistors, forming gate excitation signals. To ensure signal integrity during transmission, a 50Ω impedance matching network is installed at the excitation output, and shielded RF-grade transmission cables are used to prevent interference effects such as reflections, crosstalk, and signal distortion during high-speed switching. Furthermore, to enhance analysis of the MOS device's response behavior under varying drive strengths, the gate excitation signal's voltage amplitude is gradually adjusted from 0.5V to 10V. A full frequency sequence is applied at each voltage level to construct a two-dimensional frequency-voltage test matrix. A source-meter measurement unit is set up based on the multi-voltage gate excitation signals and connected to the drain, source, and base terminals of the MOS transistors. The source is directly grounded to establish a reference potential, and the base is grounded via a precision 1kΩ resistor. This configuration prevents direct current from interfering with the test results while providing natural isolation of the gate-drain coupling capacitance. A high-precision source-meter measurement unit applies a constant voltage to the drain terminal, set to 5V. This voltage level provides both sufficient turn-on voltage and safety, enabling the device to switch between on, off, and subthreshold states, and facilitating observation of the dynamic response of the drain current to gate excitation. After the entire signal drive and voltage application system is constructed, testing is performed. In each test cycle, the system sequentially applies excitation signals to the MOS device at different frequency points and gate voltage amplitudes, triggering the device's dynamic behavior response. The high-precision source-meter measurement unit simultaneously records key electrical parameter data during the response process.The amplitude and variation characteristics of the drain current are collected, and the gate voltage changes are monitored. The gate charge and discharge currents are recorded for subsequent extraction of gate charge indicators. Simultaneously, the junction temperature of the device is measured based on temperature-sensitive voltage parameters, establishing a data sequence of the electrothermal response of the MOS transistor under a given operating state. All response data at each frequency point and each gate voltage level is collected and stored, forming a multi-dimensional, comprehensive test data set.

[0021] In one example, parameter synchronization is performed on MOS transistor response data to obtain raw test data, including: Collecting MOS transistor response data to obtain original response waveform data; Perform synchronous triggering processing on the original response waveform data based on the master clock signal to obtain timing-synchronized response data; The time-synchronized response data is collected through four parallel measurement channels, which collect multi-parameter synchronous data including gate voltage data, drain current, gate charge and discharge current, and device junction temperature data. Integrate and sample the gate charge and discharge current in the multi-parameter synchronous acquisition data, perform high-speed sampling at the pulse edge instant, and obtain gate charge data; Automatically switch the range of the drain current in the multi-parameter synchronous acquisition data to obtain the full-scale drain current data; The gate voltage data, gate charge data, full-scale drain current data and device junction temperature data are digitally filtered to obtain the original test data.

[0022] In this example, a multi-channel data acquisition system with high sampling accuracy and high bandwidth was built. Once the test began, as gate excitation signals with multiple frequencies and voltage amplitudes were gradually applied, the MOS transistors exhibited corresponding dynamic responses under different operating conditions. The analog signals acquired from the device were continuously digitized by a high-speed analog-to-digital conversion module, recording the response waveform data. This process required the acquisition module to possess extremely high temporal and amplitude resolution to capture transient details such as pulse rise and fall edges, as well as subtle responses in low-level regions. Using a master clock signal as a global reference, the raw response waveform data was synchronously triggered. Each excitation signal generation and acquisition start point was based on the same high-precision master clock pulse, ensuring that the response data points closely matched the actual occurrence of the physical event. Timing synchronization prevented correlation distortion caused by inter-channel trigger drift and timebase errors. With data synchronization guaranteed, four independent parallel measurement channels were used to classify and acquire the time-synchronized response data in real time, each channel performing a different measurement task. The first channel focuses on collecting gate voltage data, recording the voltage variations at the gate end under different excitation amplitudes and frequencies. The second channel collects drain current, utilizing a precision shunt resistor and current sampling amplifier to achieve wide-range, high-dynamic range monitoring, covering the entire operating range from microampere leakage to 10A high-power operation. The third channel, equipped with a high-bandwidth sampling circuit to address the rapid changes in gate charge and discharge currents, records the gate current waveform at key nodes such as the rising and falling edges of the excitation signal. The fourth channel, equipped with a temperature sensor or leveraging the voltage-temperature sensitivity, continuously measures the device's junction temperature, capturing the instantaneous temperature rise and heat diffusion caused by current surges or frequent switching. An integral sampling algorithm is employed for the gate charge and discharge current sequence within the collected multi-parameter synchronous data. Specifically, at each pulse edge, high-speed sampling is used to capture the short-term gate current waveform and perform real-time numerical integration to calculate the physically meaningful gate charge. This data reflects the dynamic drive capability and speed limit of the MOS device and serves as a key indicator for evaluating gate oxide quality and failure risk. When collecting drain current data, the acquisition channel is equipped with an intelligent range switching function, automatically selecting the optimal range based on the current intensity, achieving full coverage from minimal leakage to high-power current, avoiding saturation distortion caused by over-range or measurement blind spots due to low signal resolution. Gate voltage data, gate charge data, full-scale drain current data, and device junction temperature data are digitally filtered, using algorithms such as band-stop filtering and low-pass filtering to effectively suppress power frequency, electromagnetic, and high-frequency interference noise, improve the signal-to-noise ratio of the effective signal, and obtain the original test data.

[0023] In one example, performing package parasitic effect compensation on original test data to obtain corrected test data includes: Build the target thermal resistance between the chip and the package substrate and the MOS transistor package equivalent circuit model based on the original test data; The response characteristics of the original test data are analyzed based on the target value of the thermal resistance between the chip and the package substrate and the MOS transistor package equivalent circuit model to obtain segmented frequency response data; Based on the segmented frequency response data, determine the parasitic parameter correlation data of the low frequency band affected by lead resistance, the mid-frequency band affected by lead inductance, and the high frequency band affected by mutual capacitance; Establish a parasitic parameter equation group based on parasitic parameter correlation data, and solve the actual value set of parasitic parameters through matrix operations; Perform frequency domain compensation on the original test data based on the actual value set of parasitic parameters to obtain consistent compensation effect data across the entire frequency band; Based on the full-band consistent compensation effect data, the effects of lead inductance on gate charge measurement, lead resistance on threshold voltage measurement, and package thermal resistance on junction temperature measurement are compensated respectively to obtain corrected test data.

[0024] In this example, a target value for the thermal resistance between the chip and the package substrate, as well as an equivalent circuit model for the MOS transistor package, are constructed based on the raw test data. Multi-physics collaborative modeling, based on the raw test data, quantitatively describes the thermal and electrical coupling phenomena during device operation. The package equivalent circuit model incorporates intrinsic chip parameters such as drain-source channel resistance and gate oxide capacitance, and describes external package parasitic parameters such as lead resistance, lead inductance, mutual capacitance between leads, and thermal resistance between the chip and substrate. By performing a normalized fit on the device's steady-state and transient temperature rise responses under standard excitation, the target thermal resistance is derived. This target value reflects the thermal conductivity of the device's materials and structure, and identifies the heat flow bottlenecks along the entire package path. Based on these thermal resistance target values ​​and the equivalent circuit model, the raw test data is analyzed for response characteristics. The test frequency range is divided into three main segments: low, mid, and high. Each frequency segment corresponds to the dominant role of different types of parasitic parameters on the device's electrical response. At low frequencies, the test response characteristics are primarily affected by lead resistance, as inductive and capacitive reactances are weak compared to resistance in this range, making conduction loss and voltage drop characteristics clearly visible. In the mid-frequency range, as the frequency increases, the magnetic flux generated by the signal in the lead structure changes significantly, and the lead inductance dominates the amplitude attenuation and phase lag of the response signal. At this point, the mid-frequency response characteristics of the test data are highly sensitive to the inductance parameters. At high frequencies, the mutual capacitance effect between the leads gradually becomes dominant, and the amplitude degradation and waveform distortion of the high-frequency components in the device response signal directly reflect the actual magnitude of the mutual capacitance. By segmenting the data to analyze the response characteristics at different frequency bands, we extract parasitic parameter correlation data closely related to lead resistance, lead inductance, mutual capacitance, and thermal resistance. This data reveals the primary physical manifestations of different parasitic effects in different operating ranges. A set of parasitic parameter equations is established based on the parasitic parameter correlation data. Based on the functional relationship between the physical parameters in the equivalent circuit model and the device response data, a response equation is established for each frequency point. By segmenting the frequency band, parasitic parameters (such as lead resistance, lead inductance, mutual capacitance, and thermal resistance) are used as variables for each test response segment to construct coupled parameter relationships. These relationships are linearized into a matrix form of A·x=b, where A is the coefficient matrix, x is the parameter vector to be solved, and b is the measured response vector. To obtain a stable and reliable parameter solution, numerical linear algebra methods such as singular value decomposition or QR decomposition are used to decompose the coefficient matrix A and perform a least-squares optimization solution to obtain a set of actual parasitic parameter values. This set reflects the key parasitic electrical and thermal parameters of each MOS transistor device under the current packaging process, structural design, and material system. Frequency-domain compensation is performed on the original test data based on this set of actual parasitic parameter values. The influence mechanism of each parasitic parameter in its primary control frequency band is reversed and the data is corrected.Low-frequency compensation focuses on eliminating the additional voltage loss caused by lead resistance, thereby improving threshold voltage measurement accuracy. Mid-frequency compensation primarily targets the impact of lead inductance on gate charge and discharge current measurements, improving gate charge extraction accuracy through compensation. High-frequency compensation corrects for current leakage and response amplitude distortion caused by mutual capacitance between leads, restoring the device's true signal response during high-speed switching. The compensation algorithm utilizes segmented frequency domain correction, applying different weighting coefficients to each segment of test data based on the actual values ​​of parasitic parameters to achieve consistent compensation across the entire frequency band. Furthermore, combining the thermal resistance target value with the actual temperature rise curve, it automatically compensates for junction temperature measurement deviations caused by package thermal resistance, correcting the impact of power consumption variations on temperature sensing accuracy, and ensuring a reliable representation of the device's thermal response under various operating conditions. Through this parameter identification and frequency domain compensation process, all original test data is corrected to produce corrected test data.

[0025] In one example, a target thermal resistance value between a chip and a package substrate and an equivalent circuit model of a MOS transistor package are constructed based on original test data, including: Based on the electrical response characteristics of MOS transistors at different frequencies in the original test data, the package topology structure is analyzed to determine the lead layout and interconnection position, and obtain the package physical structure characterization data; Perform initial estimation of electrical parameters on the package physical structure characterization data to obtain an initial set of parasitic parameter values; Compare and analyze the initial value set of parasitic parameters with the low-frequency response characteristics in the original test data to obtain the target value of lead resistance; Perform magnetic field simulation on the mid-frequency response characteristics of the original test data to obtain the target value of the lead inductance, and calculate the electric field distribution based on the high-frequency response characteristics in the original test data to obtain the target value of the mutual capacitance between the leads; The target values ​​of lead resistance, lead inductance, mutual capacitance between leads, and the temperature-power consumption relationship curve in the original test data are subjected to heat flow analysis to obtain the target value of thermal resistance between the chip and the package substrate and the equivalent circuit model of the MOS transistor package.

[0026] In this example, based on raw test data, a systematic analysis of the electrical response characteristics of MOS transistors under different frequency conditions was performed. Dynamic response testing under multi-frequency excitation recorded multiple physical parameters, including drain current, gate current, gate voltage, and junction temperature, at each frequency point. Through detailed comparison and morphological analysis of the response curves, the physical constraints imposed on the signal during transmission within the package were inferred. The switching loss, delay, and waveform distortion of the MOS transistor at different frequencies are attributed to the internal lead layout and interconnect paths of the package. Therefore, by combining multiple sets of frequency response data with theoretical equivalent circuit models, and leveraging information such as amplitude attenuation, phase lag, and harmonic distribution across different operating ranges, and employing techniques such as signal propagation time-domain and frequency-domain inversion, the geometric relationships and spatial layout of the leads were gradually identified. The actual routing path of each lead and the physical location of the interconnect points were inferred, thereby obtaining data representing the physical structure of the package. This data includes lead length, cross-sectional area, orientation, and spatial location, as well as the shortest distance between leads, intersection distribution, and positional offset of key nodes. Initial estimates of electrical parameters were generated from this package physical structure characterization data. Leveraging industry-standard electromagnetic field theory and material databases, and employing parametric formulas or finite element methods, preliminary electrical parameters corresponding to the package's physical structural characterization data are calculated. These include the distributed resistance and inductance of each lead, as well as the mutual capacitance between leads. This process requires input of key parameters such as material resistivity, dielectric constant, conductor cross-sectional area, insulation distance, and spatial relationships between leads. Using classical physics formulas or 3D field simulations, initial values ​​for lead resistance, lead inductance, and mutual capacitance are obtained. The initial lead resistance values ​​are then compared with the low-frequency response characteristics of the original test data. Under low-frequency excitation, the device's current signal is primarily affected by the voltage drop across the lead resistance. By comparing the measured voltage-current curve with the theoretical model output, optimization algorithms such as least-squares fitting and residual minimization are employed to refine and accurately extract the target lead resistance value, ensuring that it best reflects the device's actual power loss and electrical impedance. A magnetic field simulation is then performed on the original test data's mid-frequency response characteristics. During this stage, the increased frequency enhances magnetic field coupling between leads, significantly increasing the test data's sensitivity to lead inductance. By inputting physical structure characterization parameters into the simulation environment and combining them with the measured signal amplitude and phase variation patterns, electromagnetic field finite element simulation and network parameter fitting are used to iteratively obtain the target lead inductance value that is highly consistent with the actual dynamic response. At the same time, the analysis of high-frequency response characteristics requires the calculation of electric field distribution. Under high-frequency excitation conditions, the spatial distribution of signals between leads can easily induce stray capacitance, which manifests as amplitude degradation and coupling leakage of the high-frequency components of the signal. By performing frequency domain analysis on the bandwidth, harmonic distortion, amplitude attenuation and other characteristics of the high-frequency test waveform, and combining it with the spatial structure model, the target mutual capacitance value between the leads is quantified using electrostatic field simulation or equivalent capacitance array derivation method.The entire parameter extraction process repeatedly undergoes error feedback and model correction to ensure that all parameters achieve optimal consistency between actual measurements and the physical model. Thermal flow analysis is performed on the target values ​​for lead resistance, lead inductance, mutual capacitance between leads, and the temperature-power consumption relationship curve in the original test data. By fitting the temperature rise curve during the dynamic test process, a linear or nonlinear relationship model between junction temperature and total device power consumption is established. With the help of thermal flow simulation software, combined with physical parameters such as thermal conductivity, heat diffusion path, and package volume, the target thermal resistance between the chip and the package substrate is calculated. This thermal resistance value can reflect the thermal management level of the package structure and the temperature rise limit of the device under actual use conditions. The target values ​​for lead resistance, lead inductance, mutual capacitance between leads, and thermal resistance are globally integrated. Within a unified multi-physics field equivalent circuit model framework, each parameter is mapped to standard circuit elements and thermal circuit networks to form a high-precision package equivalent circuit model for MOS transistors.

[0027] In one example, a parasitic parameter equation group is established based on parasitic parameter correlation data, and a set of actual parasitic parameter values ​​is solved through matrix operations, including: Performing frequency interval segmentation processing on the parasitic parameter correlation data to obtain frequency band parameter correlation data; A function model of the relationship between device response and parasitic parameters is constructed based on the frequency band parameter correlation data. A parameter function model set between the measured response and lead inductance, lead resistance, mutual capacitance, and package thermal resistance is established for each frequency point. Performing linear transformation on the parameter function model set to obtain the parasitic parameter equation group, and performing singular value decomposition on the coefficient matrix in the parasitic parameter equation group to obtain the least squares solution matrix; The least squares solution matrix and the response vector are subjected to matrix multiplication to obtain an initial parameter vector, and the initial parameter vector is subjected to residual analysis and iterative optimization processing to obtain a set of actual values ​​of the parasitic parameters.

[0028] In this example, the frequency-dependent effects reflected in the test data are managed and systematically analyzed in segments. By comparing and analyzing the distribution characteristics of parasitic parameter correlation data in different frequency intervals, a frequency segmentation strategy is adopted to divide the entire test frequency range into several sub-intervals: low frequency, medium frequency, and high frequency. The device response in different frequency intervals is influenced differently by the dominant physical mechanisms controlling various parasitic effects. The parasitic parameter effects are minimized to their respective frequency bands to minimize coupling errors and computational complexity between parameters. The low-frequency region focuses on the voltage drop effect of lead resistance on the current response, the medium-frequency region focuses on the magnetic field effect of lead inductance, and the high-frequency region focuses on the high-frequency leakage and distortion of electrical signals caused by mutual capacitance. The thermal impact of package thermal resistance runs through all frequency bands and requires global consideration. A functional model of the relationship between device response and parasitic parameters is constructed based on the frequency segmentation parameter correlation data. Taking the low-frequency band as an example, Ohm's law or classical circuit equivalents are used to construct a direct linear function model that responds to current and lead resistance. In the mid-frequency region, the induction law is combined to expand the current or voltage response model into a differential or delayed response equation related to lead inductance. In the high-frequency band, capacitance distribution and current phase shift are the physical core, mapping the high-frequency response characteristics into a function model of signal coupling or bandwidth degradation related to mutual capacitance. Furthermore, the relationship between package thermal resistance, device temperature rise, and power consumption is considered across the entire frequency band to establish a nonlinear function relationship for thermal-electrical coupling. The system establishes a corresponding parametric function model for each frequency point and each key parasitic parameter, forming a multi-dimensional, multi-equation, and tightly coupled parametric function model set. This parametric function model set is then linearized. The linearization process uses Taylor series expansion, small perturbation analysis, or piecewise approximation to expand the nonlinear model into a linear relationship near a specific operating point, making it suitable for efficient processing using linear algebraic methods. The physical functional relationship between each set of responses and parasitic parameters is expressed as a set of linear equations. All equations are combined and summarized into a standard matrix-vector product form: A·x=b, where A is the coefficient matrix containing the first-order partial derivatives or coefficients of each functional model, x is the actual value vector of the parasitic parameters to be determined, and b is the response vector consisting of the measured responses at multiple frequency points. The coefficient matrix of the parasitic parameter equations is subjected to singular value decomposition (SWD), decomposing the arbitrary real matrix A into the product of three orthogonal matrices, which contain important information such as the rank, condition number, and principal directions of the system equations. This SWD effectively detects potential strong correlations or redundancies between parameters, avoiding the numerical instabilities caused by ill-conditioned matrices in traditional Gaussian elimination or direct matrix inversion methods. It also yields the optimal solution matrix in the least-squares sense. Matrix multiplication of the least-squares solution matrix and the response vector yields a set of initial parameter vectors, which serve as preliminary quantitative estimates of all parasitic parameters based on the current model and observed data. Taking into account the existence of systematic errors, noise interference and model approximation in actual data, residual analysis and iterative optimization are performed on the initial parameter solution.The initial solution is then applied back to the original nonlinear physical function model, and the difference between the theoretical prediction and the measured response is compared to calculate the residual distribution. If the residual is large or exhibits systematic deviations at certain frequencies, the parameter solution is corrected multiple times using optimization algorithms (such as gradient descent, Newton method, quasi-Newton method, etc.). Each iteration fine-tunes the parameter vector based on the latest residual distribution until the residual converges to the engineering tolerance or the model output is highly consistent with the actual observed data. Through these steps, the actual values ​​of the parasitic parameters are obtained.

[0029] In one example, signal feature decomposition is performed on the calibration test data to obtain a feature parameter set of the MOS transistor, including: Performing wavelet decomposition on the calibration test data to obtain a multi-scale wavelet decomposition coefficient set, and calculating entropy feature data based on the multi-scale wavelet decomposition coefficient set; Performing statistical analysis on the gate voltage, drain current, gate charge and discharge current, and junction temperature parameters in the correction test data to obtain statistical characteristic data; Based on the calibrated test data, a parameter correlation analysis matrix is ​​constructed to calculate the cross-correlation coefficients corresponding to the transconductance characteristics of gate voltage and drain current, the capacitance characteristics of gate charge and gate voltage, and the thermal resistance characteristics of junction temperature and power consumption, thereby obtaining parameter correlation characteristic data. The entropy feature data, statistical feature data and parameter association feature data are combined to obtain a full feature data set, and recursive feature elimination is performed on the full feature data set to obtain a feature parameter set of the MOS transistor.

[0030] In this example, wavelet decomposition is performed on the calibration test data. Because MOS devices exhibit significant transient edges, voltage fluctuations, and high-frequency jitter under different operating frequencies and excitation conditions, mathematical tools with time-frequency localization properties are used to analyze the signals. The wavelet transform can simultaneously capture both abrupt changes in the time domain and smooth variations in the frequency domain. In practice, the db8 wavelet from the Daubechies family is selected as the basis function. Multiscale wavelet decomposition is performed on the gate voltage, drain current, gate current, and junction temperature response data, with five layers, covering the full scale range from the original signal to the coarsest scale. After wavelet decomposition, a set of multiscale detail coefficients and approximation coefficients is obtained. These coefficients reflect the oscillation strength and energy distribution characteristics of the signal at different scales. Based on these decomposition coefficients, by defining probability distribution functions, entropy features such as Shannon entropy and Tsallis entropy are calculated to characterize the complexity and nonlinearity of the signal at different scales. Shannon entropy is used to assess the overall level of signal chaos, while Tsallis entropy is suitable for characterizing non-Gaussian and long-memory dependent multi-scale characteristics. Combining these two can describe the entropy structure of MOS devices during package-level dynamic response. These entropy features have clear physical implications. For example, changes in the entropy of high-frequency wavelet coefficients can reflect microscopic failures such as changes in device drive capability, early signs of breakdown, or charge retention. After entropy feature extraction, traditional statistical feature analysis is performed on the time series of each parameter in the calibration data. For each signal group, statistical metrics such as mean, standard deviation, extreme value, kurtosis, skewness, rise time, fall time, and steady-state interval length are calculated. These features, based on the data's central tendency, dispersion, symmetry, sharpness, and dynamic characteristics, provide indicators for analyzing device volatility, responsiveness, and stability under standard or extreme conditions. For example, the standard deviation of drain current reflects resistance instability during turn-on, the rise time of junction temperature corresponds to the efficiency of the chip's thermal response path, and the peak time of gate voltage indicates phase alignment during the drive phase. These statistical indicators numerically quantify the key device behaviors and provide standardized time series feature vectors for model input. Correlation analysis is performed between parameters. By combining parameters such as gate voltage, drain current, gate charge (obtained by current integration), and junction temperature to construct a parameter correlation analysis matrix, and calculating the mutual correlation coefficients between them, the coupling characteristics between the device's electrical and thermal behaviors are extracted. Among them, the cross-correlation between gate voltage and drain current describes the device's transconductance behavior and is a typical indicator of gate control efficiency and current drive capability; the relationship between gate charge and gate voltage reflects the device's charge accumulation rate under unit drive voltage, that is, the dynamic characteristics of capacitance; and the correlation between junction temperature and power consumption represents the package thermal resistance and the efficiency of the heat conduction path. These mutual correlation coefficients retain the coupling laws between the original physical fields and have the ability to quantify and discriminate.The entropy feature data, statistical feature data, and parameter-related feature data are combined to form a full feature dataset. This dataset is then subjected to supervised compression and screening using a recursive feature elimination algorithm. Based on a target classifier (such as a support vector machine (SVM), RF, or dense neural network), recursive feature elimination gradually eliminates the least contributing features based on their importance. The model is repeatedly trained and evaluated for accuracy until the optimal subset is retained. The set of feature vectors output after recursive feature elimination represents the filtered and optimized set of MOS transistor feature parameters.

[0031] In one example, a package defect analysis is performed based on a feature parameter set to obtain a defect identification report, including: Input the feature parameter set into the deep convolutional neural network to perform forward propagation calculation to obtain preliminary recognition results; The Focal Loss function is used to perform confidence scoring on the preliminary recognition results to obtain defect recognition results with confidence; Based on the defect recognition results with confidence, a temperature-frequency joint test domain analysis matrix is ​​constructed, and a comparative analysis of the temperature-frequency joint test domain analysis matrix is ​​performed to obtain a normalized defect feature map; Perform distributed thermoelectric sampling point array measurement based on the normalized defect feature map, and collect temperature distribution characteristic data at D temperature sensing points on the package surface; The temperature distribution characteristic data and the defect identification results with confidence are jointly analyzed to obtain a defect identification report.

[0032] In this example, a set of feature parameters is input into a deep convolutional neural network for forward propagation. The network architecture comprises multiple convolutional, pooling, and fully connected layers, automatically extracting spatial distribution, temporal variations, and complex nonlinear coupling features from the input data. During the forward propagation process, each set of feature samples is processed through a convolution kernel to extract signal features such as edges, dynamics, and transitions. Pooling is then used to reduce dimensionality and enhance feature stability. The fully connected layers then output probability distributions or confidence vectors for multiple defect categories. A Focal Loss function is used to assign confidence scores to the preliminary recognition results. Focal Loss effectively mitigates class imbalance by assigning higher loss weights to difficult-to-classify and low-confidence samples, allowing the network to focus on learning and distinguishing hidden defects such as extreme, low-probability, and fuzzy-bounded defects. Focal Loss is calculated for each preliminary recognition result, and the confidence score output for each defect category is adjusted accordingly, resulting in a confident defect discrimination result for each sample. A temperature-frequency joint test domain analysis matrix is ​​constructed based on these confident defect recognition results. The characteristic parameters at each temperature and excitation frequency are fed into a deep convolutional neural network. The probability or confidence level of each defect type under all conditions is recorded, constructing a three-dimensional matrix with the dimensions of temperature point, frequency point, and defect category. Normalizing the matrix eliminates scale effects across different samples and operating conditions, making the defect probability distribution comparable. Slicing, heatmap rendering, and boundary analysis are performed on this matrix to intuitively reveal which defects are most prevalent at specific temperatures and frequencies, and which are globally stable or susceptible at extreme boundaries. To achieve deep coupling between test data and physical reality, D high-precision thermoelectric temperature sensors are distributed across the surface of the MOS package, synchronously collecting temperature distribution data on the device surface and key structural nodes in real time. This data reflects the overall heat flow distribution of the sample during static and dynamic test cycles, and captures local overheating, temperature distortion, and abnormal temperature rise within the package caused by parasitic defects, process variations, or heat dissipation bottlenecks. For scenarios with extremely high reliability requirements, thermal imaging or micro-area infrared scanning can be used to obtain thermal distribution maps with higher spatial resolution. The normalized defect feature map and temperature distribution feature data are cross-analyzed to analyze the physical coupling and statistical correlation between "defect probability-thermal anomaly". By calculating the spatial overlap, covariance and interaction trend between the temperature field and the high-incidence area of ​​defects, the "high-risk hot spots" and "critical areas prone to defects" are located, and the relationship between different defect categories and local or global temperature changes is analyzed separately, thereby achieving closed-loop verification from statistical inference to physical evidence. On this basis, the system automatically integrates all criteria, probabilities, thermal fields and frequency domain features to generate a structured and traceable defect identification report. The report includes the defect type, confidence level, occurrence conditions, and distribution location of each device, and outputs the failure risk range, thermal distribution characteristics, reliability evaluation indicators and recommended process adjustment suggestions in the temperature-frequency process window.

[0033] Reference Figure 2 This embodiment provides a package-level testing device for a MOS transistor, comprising: Response module 1, used to apply multi-frequency pulse signals to the packaged MOS transistor to obtain MOS transistor response data at different frequencies; Synchronous acquisition module 2, used for synchronously acquiring parameters of MOS transistor response data to obtain original test data; Compensation processing module 3, used to perform package parasitic effect compensation processing on the original test data to obtain corrected test data; The feature decomposition module 4 is used to perform signal feature decomposition on the calibration test data to obtain a feature parameter set of the MOS transistor; The defect analysis module 5 is used to perform packaging defect analysis based on the characteristic parameter set and obtain a defect identification report.

[0034] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to the above method embodiment, which will not be repeated here.

[0035] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, apparatus, article, or method comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, apparatus, article, or method. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, apparatus, article, or method comprising the element.

[0036] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A package-level testing method for MOS transistors, characterized in that: include: Apply multi-frequency pulse signals to the packaged MOS transistor to obtain MOS transistor response data at different frequencies; Performing parameter synchronous acquisition on the MOS transistor response data to obtain original test data; Performing package parasitic effect compensation processing on the original test data to obtain corrected test data; Performing signal feature decomposition on the correction test data to obtain a feature parameter set of the MOS transistor; A packaging defect analysis is performed based on the characteristic parameter set to obtain a defect identification report.

2. The package-level testing method for MOS transistors according to claim 1, wherein: Applying a multi-frequency pulse signal to the packaged MOS transistor to obtain MOS transistor response data at different frequencies includes: Generate a multi-frequency test reference signal by a digital signal processor, and digitally synthesize the multi-frequency test reference signal to obtain a multi-frequency pulse signal; Routing the multi-frequency pulse signal to the gate terminal of the packaged MOS transistor through a high-speed switch matrix to obtain a gate excitation signal; Stepwise adjusting the voltage amplitude of the gate excitation signal to obtain a multi-voltage amplitude gate excitation signal; Based on the multi-voltage amplitude gate excitation signal, a source meter measurement unit is set to be connected to the drain, source and base of the packaged MOS transistor, and under the conditions of the source being grounded, the base being grounded and a constant voltage being applied to the drain, the MOS transistor response data at different frequencies is obtained.

3. The package-level testing method for MOS transistors according to claim 1, wherein: The step of synchronously collecting parameters of the MOS transistor response data to obtain original test data includes: Collecting the MOS transistor response data to obtain original response waveform data; Performing synchronous triggering processing on the original response waveform data based on a master clock signal to obtain timing-synchronized response data; Classifying and collecting the timing synchronized response data through four parallel measurement channels, respectively collecting multi-parameter synchronous acquisition data including gate voltage data, drain current, gate charge and discharge current, and device junction temperature data; Integrating and sampling the gate charge and discharge current in the multi-parameter synchronously collected data, and performing high-speed sampling at the pulse edge to obtain gate charge data; Automatically switching the range of the drain current in the multi-parameter synchronously collected data to obtain full-range drain current data; The gate voltage data, the gate charge data, the full-scale drain current data and the device junction temperature data are digitally filtered to obtain original test data.

4. The package-level testing method for MOS transistors according to claim 1, wherein: The performing package parasitic effect compensation processing on the original test data to obtain corrected test data includes: Constructing a target thermal resistance value between the chip and the package substrate and an equivalent circuit model of the MOS transistor package based on the original test data; Performing response characteristic analysis on the original test data based on the target thermal resistance between the chip and the package substrate and the MOS transistor package equivalent circuit model to obtain segmented frequency response data; Determine, based on the segmented frequency response data, parasitic parameter correlation data of the low frequency band affected by lead resistance, the mid-frequency band affected by lead inductance, and the high frequency band affected by mutual capacitance; Establishing a parasitic parameter equation group according to the parasitic parameter correlation data, and solving a set of actual parasitic parameter values ​​through matrix operations; Performing frequency domain compensation on the original test data based on the actual value set of the parasitic parameters to obtain full-band consistent compensation effect data; According to the full-band consistent compensation effect data, the effects of lead inductance on gate charge measurement, lead resistance on threshold voltage measurement, and package thermal resistance on junction temperature measurement are compensated respectively to obtain corrected test data.

5. The package-level testing method for MOS transistors according to claim 4, wherein: The step of constructing a target thermal resistance value between the chip and the package substrate and an equivalent circuit model of a MOS transistor package based on the original test data includes: Performing package topology analysis based on electrical response characteristics of the MOS transistor at different frequencies in the original test data, determining lead layout and interconnection positions, and obtaining package physical structure characterization data; Performing initial electrical parameter estimation on the package physical structure characterization data to obtain an initial value set of parasitic parameters; Comparing and analyzing the initial value set of parasitic parameters with the low-frequency response characteristics in the original test data to obtain a target value of lead resistance; Performing magnetic field simulation on the intermediate frequency response characteristics of the original test data to obtain a target value of lead inductance, and performing electric field distribution calculation based on the high frequency response characteristics in the original test data to obtain a target value of mutual capacitance between leads; The target value of lead resistance, the target value of lead inductance, the target value of mutual capacitance between the leads, and the temperature-power consumption relationship curve in the original test data are subjected to a heat flow analysis to obtain the target value of thermal resistance between the chip and the packaging substrate and the equivalent circuit model of the MOS transistor package.

6. The package-level testing method for MOS transistors according to claim 4, wherein: The step of establishing a parasitic parameter equation group according to the parasitic parameter association data and solving a set of actual parasitic parameter values ​​through matrix operations includes: Performing frequency interval segmentation processing on the parasitic parameter association data to obtain frequency band parameter association data; Constructing a function model of the relationship between device response and parasitic parameters based on the frequency band parameter association data, and establishing a parameter function model set between the measured response and lead inductance, lead resistance, mutual capacitance and package thermal resistance for each frequency point; Performing a linear transformation on the parameter function model set to obtain a parasitic parameter equation group, and performing a singular value decomposition on the coefficient matrix in the parasitic parameter equation group to obtain a least squares solution matrix; A matrix multiplication operation is performed on the least squares solution matrix and the response vector to obtain an initial parameter vector, and residual analysis and iterative optimization processing are performed on the initial parameter vector to obtain the actual value set of the parasitic parameters.

7. The package-level testing method for MOS transistors according to claim 1, wherein: The performing signal feature decomposition on the correction test data to obtain a feature parameter set of the MOS transistor includes: Performing wavelet decomposition on the correction test data to obtain a multi-scale wavelet decomposition coefficient set, and calculating entropy feature data based on the multi-scale wavelet decomposition coefficient set; Performing statistical analysis on gate voltage, drain current, gate charge and discharge current, and junction temperature parameters in the correction test data to obtain statistical characteristic data; Constructing a parameter correlation analysis matrix based on the calibration test data, calculating the correlation coefficients corresponding to the transconductance characteristics of gate voltage and drain current, the capacitance characteristics of gate charge and gate voltage, and the thermal resistance characteristics of junction temperature and power consumption, to obtain parameter correlation characteristic data; The entropy feature data, the statistical feature data and the parameter association feature data are combined to obtain a full feature data set, and recursive feature elimination is performed on the full feature data set to obtain a feature parameter set of the MOS transistor.

8. The package-level testing method for MOS transistors according to claim 1, wherein: The performing of packaging defect analysis based on the characteristic parameter set to obtain a defect identification report includes: Inputting the feature parameter set into a deep convolutional neural network to perform forward propagation calculation to obtain a preliminary recognition result; A Focal Loss function is used to perform confidence scoring on the preliminary recognition result to obtain a defect recognition result with confidence; Constructing a temperature-frequency joint test domain analysis matrix based on the defect recognition result with confidence, and performing comparative analysis on the temperature-frequency joint test domain analysis matrix to obtain a normalized defect feature map; Performing distributed thermoelectric sampling point array measurement based on the normalized defect feature map to collect temperature distribution characteristic data at D temperature sensing points on the package surface; The temperature distribution characteristic data and the defect identification result with confidence are jointly analyzed to obtain a defect identification report.

9. A package-level test device for a MOS transistor, characterized in that: The steps for implementing the package-level testing method of the MOS transistor according to any one of claims 1 to 8, wherein the package-level testing device of the MOS transistor comprises: A response module is used to apply a multi-frequency pulse signal to the packaged MOS transistor to obtain MOS transistor response data at different frequencies; A synchronous acquisition module, used for synchronously acquiring parameters of the MOS transistor response data to obtain original test data; a compensation processing module, configured to perform package parasitic effect compensation processing on the original test data to obtain corrected test data; A feature decomposition module, configured to perform signal feature decomposition on the calibration test data to obtain a feature parameter set of the MOS transistor; The defect analysis module is used to perform packaging defect analysis based on the characteristic parameter set to obtain a defect identification report.

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